KR101752599B1 - Frequency Synthesizer - Google Patents

Abstract

The frequency synthesizer according to the present embodiment includes: an oscillation unit that provides a reference signal; and a voltage-controlled oscillator (not shown) that provides a signal corresponding to the control signal and outputs a signal having a frequency belonging to one of a plurality of predetermined bands A voltage controlled oscillator (VCO), a divider for receiving and outputting a signal output from the voltage controlled oscillator, and a divider for receiving a signal output from the divider and a reference signal, A phase frequency detector for providing an error signal and a charge pump and a phase frequency detector for forming a control signal for controlling the voltage controlled oscillator so as to correspond to the error signal, A phase locked loop including a loop filter for outputting a signal provided by the voltage controlled oscillator as an output signal, The frequency bands and the frequency division ratio of the output signal of the minute dividing and outputting an output signal frequency division ratio preset housewife and a phase locked loop of the loop including a controller for controlling any one or more than one.

Description

{Frequency Synthesizer}

The present invention relates to a frequency synthesizer.

A conventional phase locked loop synthesizer (PLL) includes a phase frequency detector (PFD), a divider, a charge pump, and a voltage controlled oscillator (VCO). do. The frequency divider divides the frequency of the output signal provided by the voltage controlled oscillator and provides it to the phase frequency detector. The phase frequency detector provides the error signal according to the phase difference and frequency difference between the divided signal and the reference signal to the charge pump. The charge pump provides a voltage signal corresponding to the error signal to the voltage controlled oscillator to control the phase and frequency of the output signal.

Korean Patent Registration No. 10-1228867 Japanese Patent Publication No. 3833824 Korean Patent Publication No. 10-2007-0005136

When changing the frequency of the conventional frequency synthesizer output signal, the divide ratio of the frequency divider should be adjusted to fix the loop again. In the case of changing the frequency division ratio, a fixed time is required until the phase locked loop is fixed in phase and frequency according to the changed frequency division ratio, and further, there may arise a problem of system stability. In addition, although the frequency can be changed only within the frequency range in which the voltage-controlled oscillator can output, when the oscillator has a wide range of frequencies and the oscillator gain is large, the phase noise is adversely affected.

The present embodiment solves the disadvantages of the conventional frequency synthesizer described above and provides a frequency synthesizer that does not require a fixed time even when the output frequency is to be changed, has good phase noise characteristics, and provides a wide range of frequencies Is one of the main objects of the present embodiment.

The frequency synthesizer according to the present embodiment includes: an oscillation unit that provides a reference signal; and a voltage-controlled oscillator (not shown) that provides a signal corresponding to the control signal and outputs a signal having a frequency belonging to one of a plurality of predetermined bands A voltage controlled oscillator (VCO), a divider for receiving and outputting a signal output from the voltage controlled oscillator, and a divider for receiving a signal output from the divider and a reference signal, A phase frequency detector for providing an error signal and a charge pump and a phase frequency detector for forming a control signal for controlling the voltage controlled oscillator so as to correspond to the error signal, A phase locked loop including a loop filter for outputting a signal provided by the voltage controlled oscillator as an output signal, The frequency bands and the frequency division ratio of the output signal of the minute dividing and outputting an output signal frequency division ratio preset housewife and a phase locked loop of the loop including a controller for controlling any one or more than one.

The frequency synthesizer according to the present embodiment provides an advantage that the phase noise characteristic is improved even when a signal is output over a wideband frequency. Further, according to the frequency synthesizer according to the present embodiment, a locking time in the phase locked loop is not required, and the output frequency can be changed quickly, except when the control unit selects an oscillator providing a reference signal Advantages are provided.

1 is a schematic block diagram showing an outline of a frequency synthesizer according to the present embodiment.
2 is a diagram showing an outline of an oscillation section.
Figs. 3 (a) to 3 (e) are diagrams showing the openings of the output signal formed in accordance with the frequency of the reference signal and the division ratio of the dividing portion.
4 (a) shows an oscillator phase noise at 1.485 GHz, and FIG. 4 (b) shows an oscillator phase noise at 540 MHz.
5 shows the tuning range of the voltage-controlled oscillator of this embodiment.

The description of the present invention is merely an example for structural or functional explanation, and the scope of the present invention should not be construed as being limited by the embodiments described in the text. That is, the embodiments are to be construed as being variously embodied and having various forms, so that the scope of the present invention should be understood to include equivalents capable of realizing technical ideas.

Meanwhile, the meaning of the terms described in the present application should be understood as follows.

The terms "first "," second ", and the like are used to distinguish one element from another and should not be limited by these terms. For example, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "on" or "on" another element, it may be directly on top of the other element, but other elements may be present in between. On the other hand, when an element is referred to as being "in contact" with another element, it should be understood that there are no other elements in between. On the other hand, other expressions that describe the relationship between components, such as "intervening" and "intervening", between "between" and "immediately" or "neighboring" Direct neighbors "should be interpreted similarly.

It should be understood that the singular " include "or" have "are to be construed as including a stated feature, number, step, operation, component, It is to be understood that the combination is intended to specify that it is present and not to preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

Each step may take place differently from the stated order unless explicitly stated in a specific order in the context. That is, each step may occur in the same order as described, may be performed substantially concurrently, or may be performed in reverse order.

The drawings referred to for explaining embodiments of the present disclosure are exaggerated in size, height, thickness, and the like intentionally for convenience of explanation and understanding, and are not enlarged or reduced in proportion. In addition, any of the components shown in the drawings may be intentionally reduced, and other components may be intentionally enlarged.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. Terms such as those defined in commonly used dictionaries should be interpreted to be consistent with the meanings in the context of the relevant art and can not be construed as having ideal or overly formal meaning unless explicitly defined in the present application .

Hereinafter, a frequency synthesizer according to an embodiment of the present invention will be described with reference to the accompanying drawings. 1 is a schematic block diagram showing an outline of a frequency synthesizer according to the present embodiment. 1, the frequency synthesizer 1 according to the present embodiment includes an oscillation unit XO 100 for providing a reference signal and an output _PLL corresponding to the control signal con, A VCO (Voltage Controlled Oscillator) 500 for outputting a signal having a frequency belonging to one of a plurality of bands, a frequency divider for dividing and outputting a signal output from the voltage controlled oscillator, A phase frequency detector 200 receiving a signal output from the frequency divider 600 and a reference signal ref and providing an error signal corresponding to a phase difference and a frequency difference; A charge pump (300) for forming a control signal for controlling the voltage controlled oscillator to correspond to the error signal, and a loop filter (400) for removing noise provided by the phase frequency detector (200) Group phase-locked loop 10 and the output signal (out _PLL), the minute dividing the output ratio of a preset frequency division periphery of the phase-locked loop 10, which 500 is provided outputting a signal to the output signal (out _PLL) (20) and a control unit (800) for controlling at least one of a frequency band and a frequency division ratio of an output signal of the phase locked loop.

A voltage controlled oscillator (VCO) 500 forms and outputs an output signal out _PLL corresponding to the provided control signal con. For example, the voltage controlled oscillator (VCO) 500 may be formed using a ring oscillator, an LC oscillator, or the like. The voltage-controlled oscillator (VCO) 500 according to this embodiment outputs a signal having a frequency belonging to any one of a plurality of predetermined bands.

The frequency divider 600 receives the output signal out _PLL provided by the voltage controlled oscillator (VCO) 500 and divides the frequency of the output signal out of the frequency divider to provide the divided frequency to the phase frequency detector (PFD) 200. In one embodiment, the frequency divider 600 may provide the output signal out _{PLL in a} fixed dividing ratio as shown in FIG. According to another exemplary embodiment of the present invention, the control unit 800 may provide a control signal to the frequency divider 600 to control the frequency division ratio of the frequency divider 600. The frequency divider 600 may include, for example, a pre-scaler and a divider.

The phase frequency detector 200 receives the reference signal ref and the signal output from the frequency divider 600 and outputs error signals UP and DN obtained by detecting the phase difference and the frequency difference. For example, the error signals UP and DN can be obtained by multiplying the frequency of the divided output signal by the pump up signal provided when the phase is later than the frequency and phase of the reference signal ref, And a pump-down (DN) signal provided when the frequency and phase of the reference signal ref are later than the frequency and phase of the reference signal ref.

The charge pump 300 receives the error signals UP and DN provided by the phase frequency detector 200 and pumps the charges corresponding to the error signals. In one example, the charge pump pumps the charge to the charge accumulating means so as to correspond to the pulse width of the pump up signal UP or the pump down (DN) signal, or flushes the charge accumulated in the charge accumulating means, The voltage formed in the accumulating means is raised or decreased corresponding to the error signal.

The loop filter 400 may have a low pass filter configuration and remove the spurious noise included in the signal provided by the phase frequency detector 200. The loop filter 400 also includes charge storage means (not shown) for accumulating or discharging charge in accordance with the pumping or flushing operation of the charge pump. The amount of charge accumulated in the charge accumulating means changes in accordance with the pumping or flushing operation of the charge pump 300, and the voltage formed in the charge accumulating means also changes. As a result, the voltage of the control signal con supplied to the voltage controlled oscillator (VCO) 500 changes to correspond to the error signal. The control signal con thus formed may be provided to a voltage controlled oscillator (VCO) 500 to form an output _PLL having a desired frequency and phase.

2 is a diagram showing an outline of the oscillation unit XO (100). Referring to FIG. 2, the oscillation unit 100 according to the present embodiment may include a plurality of oscillators 100a, 100b,..., 100n each outputting a signal having one frequency. The control unit 800 may control the frequency of the signal provided by the oscillation unit 100 by controlling the switches with a control signal.

The oscillation unit (XO, 100) provides a reference signal ref having a reference frequency. In one embodiment, the oscillation unit XO 100 may be implemented by any one of a crystal oscillator, a temperature compensated crystal oscillator (TCXO), and a voltage compensated crystal oscillator (VCXO).

The divider (DIV) 600 divides the frequency of the input signal and outputs it. The frequency of the phase locked loop output signal varies as the dividing ratio of the frequency divider (DIV) 600 is set. According to the embodiment of the frequency synthesizer 1 illustrated in FIG. 1, the frequency division ratio of the frequency divider 600 is fixed, but the control unit 800 includes a plurality of oscillators 100a, 100b, ..., 100n May control the oscillation section 100 to adjust the frequency of the phase locked loop output signal (out _PLL ) to provide one of the signals having different frequencies provided by the oscillator 100 as a reference signal ref.

According to another embodiment of the frequency synthesizer 1 according to the present embodiment, which is not shown, the oscillator 100 may include one oscillator for providing one reference signal ref, The frequency of the phase locked loop output signal out _PLL can be adjusted by controlling the division ratio of the period 600. [

The frequency divider 20 receives the output signal out _PLL of the phase locked loop 10 and divides the output frequency of the frequency divider 20 to a desired frequency. In one embodiment, the divider 20 includes a first path R1 providing the output signal outPLL of the phase locked loop 10, a divider 20 providing the output signal outPLL of the phase locked loop 10, And a third path R3 for dividing the output signal out _PLL of the phase locked loop 10 by a second dividing ratio to provide the second path R2 and the third path R3. For example, the third path R3 may be a path that receives the signal divided by the first division ratio in the second path and provides the divided signal to the second division ratio again. As another example, the third path R3 may be provided with a phase process loop output signal (out _PLL ) to provide an output signal by dividing to a second division ratio.

In one embodiment, the frequency dividers 712 and 722 included in the branching section 20 have a pre-set frequency division ratio. For example, the frequency dividers 712 and 722 may be implemented with delay elements such as a delay flip-flop, a toggle flip-flop, and a JK flip-flop. In another embodiment, the frequency dividers 712 and 722 included in the dividing section 20 may be implemented in a frequency divider in which the frequency division ratio is controlled by the control section 800.

In one embodiment, the multiplexer 900 is controlled by the control unit 800 and outputs either the output signal of the first path R1, the output signal of the second path R2, or the output signal of the third path R3 As an output signal OUT. The multiplexer 900 is controlled by the control unit 800 and outputs either the output signal of the first path R1 or the output signal of the second path R2 or the output signal of the third path R3 Or more as an output signal OUT.

The control unit 800 controls the frequency synthesizer 1 so that the frequency synthesizer 1 according to the present embodiment outputs a signal having a desired frequency among a plurality of frequency bands. For example, the controller 800 may be implemented as a master device of I ² C (Inter-Integrated Circuit), and may include an oscillator 100, a divider 20, or a frequency divider 600 controlled by a controller 800, Etc. may be implemented as a slave device of I ² C (Inter-Integrated Circuit).

Hereinafter, the operation of the frequency synthesizer 1 according to the present embodiment will be described. However, the frequency dividers 712 and 722 will be described by way of example in which frequency of a signal provided as an input is divided and outputted. The oscillator 100 includes two oscillators, each providing a reference signal having a frequency of 27 MHz and a reference signal having a frequency of 74.25 MHz. The control unit 800 controls the oscillation unit 100 to provide the phase frequency detector 200 with one of a plurality of signals as a reference signal ref.

The phase frequency detector 200 receives and receives the reference signal ref and the output signal out _PLL of the phase locked loop in which the frequency divider 600 is divided and receives the error signal UP , DN) are formed and provided to the charge pump 300. The charge pump 300 pumps or flushes the charge to the charge accumulating means so as to correspond to the provided error signal to form the control signal con. The loop filter 400 removes noise other than the error signal among the signals provided by the phase frequency detector 200 and provides the control signal con formed in the charge accumulating means to the voltage controlled oscillator 500, And forms an output signal out _{PLL of the PLL} having a frequency.

In one embodiment, the frequency division ratio of the frequency divider 600 is set such that the frequency of the output signal out _PLL of the phase locked loop is 540 MHz when the frequency of the reference signal ref is 27 MHz. The division ratio of the frequency divider 600 is set such that the frequency of the output signal out _PLL of the phase locked loop is 1.485 GHz when the reference clock frequency ref is 74.25 MHz. In another embodiment, when one oscillator is used, the controller 800 controls the division ratio of the frequency divider 600 so that the frequency of the phase locked loop output signal out _PLL is either 540 MHz or 1.485 GHz do.

The control unit 800 controls the switches S1, S2, S3 and the multiplexer 900 so that the frequency synthesizer 1 outputs the desired frequency. For example, when it is desired to output the output signal OUT having the same frequency as the output _PLL frequency of the phase locked loop, the control unit 800 turns on the switch S1, And controls the multiplexer 900 so that an output signal is output.

As another example, when outputting a signal having a frequency that is one-half the frequency of the output _PLL of the phase locked loop, the control unit 800 turns on the switch S2 and outputs the output signal of the second path R2 And controls the multiplexer 900 so as to output the output signal. If the frequency of the output _PLL of the phase locked loop provided as an input is 540 MHz, the frequency of the output signal OUT has this frequency of 270 MHz and the frequency of the output _PLL of the _PLL If it is 1.485 GHz, the frequency of the output signal (OUT) is 742.5 MHz.

As another example, when it is desired to output a signal having a frequency that is 1/4 of the output _PLL frequency of the phase locked loop, the control unit 800 turns on the S2 switch and the S3 switch, R3 of the multiplexer 900 are outputted. If the frequency of the output _PLL of the phase locked loop provided as an input is 540 MHz, the frequency of the output signal OUT has a quadrant of 135 MHz and the frequency of the output _PLL of the _PLL provided as the input is 1.485 GHz, the frequency of the output signal OUT is 371.25 MHz.

imitation Experimental Example

Hereinafter, a frequency synthesizer simulation example according to the present embodiment will be described with reference to FIG. 3 to FIG. 3 (a) is a view showing an open form of a signal output through a first path in response to a phase locked loop output signal (out _PLL ) of 1.485 GHz, and FIG. 3 (b) And a signal having a frequency of 742.5 MHz formed by dividing the second path by receiving an out _PLL signal. 3C is a diagram showing an open form of a signal output through the first path in response to a 540MHz phase locked loop output signal out _PLL . FIG. 3D shows a phase locked loop output signal of 540MHz receiving provide out _PLL) is a view showing the ever-open type of signal having a 270MHz? F frequency formed by the frequency divider via a second path, and Fig. 3 (e) are received provides a phase-locked loop output signal (out _PLL) of 540MHz And a signal having a frequency of 135 MHz formed by dividing into a third path is shown. It can be confirmed that the target frequency is output as shown in Figs. 3 (a) to 3 (e).

4 (a) shows an oscillator phase noise at 1.485 GHz, and FIG. 4 (b) shows an oscillator phase noise at 540 MHz. Referring to FIGS. 4 (a) and 4 (b), it can be seen that the phase noise is -101 dBc / Hz and -105 dBc / Hz at 1 MHz. It can be seen that the phase noise characteristic of approximately 10 dBc / Hz to 20 dBc / Hz is improved compared with that of the ring-VCO (phase noise of general ring VCO) of about -80 to -90 dBc / Hz at 1 MHz.

5 shows the tuning range of the voltage-controlled oscillator of this embodiment. As shown in FIG. 5A, when the control voltage con provided to the voltage-controlled oscillator is 0.7833V, the frequency of the output signal is 1.485GHz. As shown in FIG. 5B, When the control voltage con supplied to the control oscillator is 0.703V, it can be confirmed that the frequency of the output signal is 540M. Unlike a conventional broadband voltage controlled oscillator, outputs a signal having a frequency belonging to one of a plurality of predetermined bands.

The conventional broadband voltage controlled oscillator has a problem that the gain (kVCO) of the voltage controlled oscillator is increased due to the characteristics of the wide band, so that the phase noise characteristic is degraded when a signal having a wide frequency band from 135 MHz to 1.485 GHz is obtained. However, according to the frequency synthesizer of this embodiment, even when a signal having a wide band frequency of 135 MHz to 1.485 GHz is output, the phase noise characteristic of 10 dBc / Hz to 20 dBc / Hz is improved compared with the conventional art .

Further, according to the frequency synthesizer of this embodiment, the locking time in the phase locked loop is not consumed, and the output frequency can be changed quickly, except when the control unit selects the oscillator providing the reference signal Advantages are provided.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It will be appreciated that other embodiments are possible. Accordingly, the true scope of the present invention should be determined by the appended claims.

10: phase locked loop 20:
100: oscillation unit 200: phase frequency detector
300: charge pump 400: loop filter
500: voltage controlled oscillator 600: frequency divider
712, 722: frequency divider 800:
900: Multiplexer

Claims (7)

A voltage controlled oscillator (VCO) for providing a signal corresponding to the control signal and outputting a signal having a frequency belonging to one of a plurality of predetermined bands, A frequency divider for receiving and outputting a signal output from the voltage controlled oscillator and an error signal corresponding to a phase difference and a frequency difference by receiving the reference signal and the signal output from the frequency divider, A charge pump for forming the control signal for controlling the voltage controlled oscillator to correspond to the error signal, and a loop filter for removing noise provided by the phase frequency detector. A phase locked loop for outputting a signal provided by the voltage controlled oscillator as an output signal;
A divider for dividing the output signal of the phase locked loop by a predetermined division factor and outputting the divided signal;
And a control unit for controlling at least one of a frequency band of the output signal of the phase locked loop and the frequency division ratio. The method according to claim 1,
Wherein the oscillator comprises a plurality of oscillators providing a plurality of reference signals having different frequencies, respectively. 3. The method of claim 2,
Wherein a predetermined plurality of bands to which a signal output by the voltage controlled oscillator belongs are different according to the reference signals. The method according to claim 1,
Wherein the oscillator includes an oscillator providing a reference signal having a single frequency. 5. The method of claim 4,
And the control unit controls the frequency of the signal output from the voltage controlled oscillator by controlling the frequency division ratio of the frequency divider. The method according to claim 1,
Wherein,
A first path for providing an output signal of the phase locked loop,
A second path for dividing an output signal frequency of the phase locked loop and
And a third path for dividing the frequency of the output signal of the phase locked loop. The method according to claim 6,
And the second path and the third path perform frequency division using delay elements, respectively.

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