KR101698812B1 - Semiconductor device - Google Patents

Abstract

One of the problems is to suppress the drop of the potential of the gate of the pull-up transistor.
The first transistor included in the driving circuit has a first terminal electrically connected to the second wiring, a second terminal electrically connected to the first wiring, and a gate electrically connected to the first terminal of the second circuit and the third transistor The second terminal of the second transistor is electrically connected to the first wiring, the second terminal of the second transistor is electrically connected to the sixth wiring, and the gate is electrically connected to the gates of the first circuit and the third transistor , The third transistor is electrically connected to the sixth wiring, the first circuit is electrically connected to the third wiring, the fourth wiring, the fifth wiring, and the sixth wiring, and the second circuit is electrically connected to the sixth wiring , The first wiring, the second wiring, and the sixth wiring.

Description

Technical Field [0001] The present invention relates to a semiconductor device,

A semiconductor device, a display device, a liquid crystal display device, a method of driving them, or a method of manufacturing them. And more particularly to a semiconductor device, a display device, a liquid crystal display device, or a driving method thereof having a driving circuit formed on a substrate such as a pixel portion. Or the electronic device having the semiconductor device, the display device, or the liquid crystal display device.

BACKGROUND ART In recent years, display devices have been actively developed as the number of large-sized display devices such as liquid crystal TVs increases. Particularly, a technique of forming a driver circuit such as a gate driver on a substrate such as a pixel portion using a transistor made of a non-single crystal semiconductor contributes greatly to cost reduction and reliability improvement, It is progressing.

In a transistor formed of a non-single crystal semiconductor, deterioration such as an increase in threshold voltage or a decrease in mobility may occur. When the deterioration of the transistor progresses, the driving circuit becomes difficult to operate and an image can not be displayed. Thus, Patent Document 1 discloses a shift register capable of suppressing transistor deterioration. In particular, in Fig. 7 of Patent Document 1, two transistors are used to suppress deterioration of characteristics of a transistor. One of the transistors is connected between the output terminal of the flip-flop and the wiring to which VSS (hereinafter referred to as a negative power supply) is supplied. The other transistor is connected between the output terminal of the flip-flop and the gate of the pull-up transistor. Then, in a period in which the output signal of the flip-flop becomes the L level, these two transistors turn on alternately (ON). When one of the transistors is turned on, VSS is supplied to the output terminal of the flip-flop through one of the transistors. When the other transistor is turned on, VSS supplied to the gate of the pull-up transistor is supplied to the output terminal of the flip-flop through the other transistor. In this manner, deterioration of the transistor can be suppressed. In addition, since VSS is always supplied to the output terminal of the flip-flop, the output signal of the flip-flop can be easily maintained at the L level.

Japanese Patent Application Laid-Open No. 2005-50502

In the configuration disclosed in Patent Document 1, the gate of the pull-up transistor and the output terminal of the flip-flop are kept conductive for a while because the other transistor is turned on for a while during the period when the output signal of the flip- State. At this time, the gate potential of the pull-up transistor becomes a high potential and the potential of the output terminal of the flip-flop becomes a low potential. One aspect of the present invention is to raise the potential of the gate of the pull-up transistor.

Alternatively, when the potential of the gate of the pull-up transistor decreases, the pull-up transistor may be turned off. An aspect of the present invention is to prevent erroneous operation of a shift register.

Alternatively, even if the pull-up transistor is turned on and the shift register can operate normally, the potential of the gate of the pull-up transistor is constantly lowered. An aspect of the present invention is to increase a potential difference (Vgs) between a gate and a source of a pull-up transistor.

Alternatively, when the Vgs of the pull-up transistor is reduced, the ON resistance of the pull-up transistor is increased. An aspect of the present invention is to reduce a display device. According to an aspect of the present invention, there is provided a display device having a high resolution.

Alternatively, when Vgs of the pull-up transistor becomes small, the rise time or fall time of the output signal of the flip-flop becomes long. An aspect of the present invention is to prevent the recording of an incorrect signal (for example, a video signal to a pixel belonging to another row) in a pixel, thereby increasing the display quality.

Alternatively, when the Vgs of the pull-up transistor becomes small, it is necessary to increase the channel width of the pull-up transistor. If the channel width of the pull-up transistor is increased, the channel width of the other transistor must also be increased. An aspect of the present invention is to reduce the layout area. Alternatively, one aspect of the present invention is to narrow the frame of the display device.

Alternatively, when the channel width of the transistor is large, the gate and source or drain of the transistor are apt to short-circuit. One aspect of the present invention is to improve the yield. Alternatively, one aspect of the present invention is to reduce costs.

Alternatively, when the channel width of the transistor is increased, the parasitic capacitance of the shift register is increased. An aspect of the present invention is to reduce distortion or delay of a signal input to a shift register. Alternatively, one aspect of the present invention is to reduce power consumption. In order to improve this, it is necessary to use a circuit having a large current capability as a circuit for supplying a signal or a voltage to the shift register. One aspect of the present invention is to reduce an external circuit. Alternatively, one aspect of the present invention is to reduce the size of the display device.

Further, the description of the above-described problems does not hinder the existence of other problems.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising a driving circuit having a first transistor, a second transistor, a third transistor, a first circuit, and a second circuit and a pixel having a liquid crystal element, Or a second wiring having a function as a clock signal line and the second terminal is electrically connected to a first wiring having a function as a signal line, a gate line, a scanning line, or an output signal line, and the gate is electrically connected to the second circuit and The second transistor is electrically connected to the first terminal of the third transistor and the second terminal is electrically connected to the first wiring and the second terminal is electrically connected to the power line or the sixth wiring having a function as a ground line The gate of the third transistor is electrically connected to the gates of the first circuit and the third transistor, the second terminal of the third transistor is electrically connected to the sixth wiring, Two circuits are electrically connected to a signal line, a third wiring having a function as a clock signal line, a fourth wiring having a function as a signal line, a fifth wiring having a function as a signal line, and a sixth wiring, The second wiring, and the sixth wiring in the liquid crystal display device.

In one aspect of the present invention, the first transistor may function as a bootstrap transistor for controlling the timing of supplying the signal of the second wiring to the first wiring in accordance with the potential of the gate of the first transistor.

In one aspect of the present invention, the second transistor may function as a switch for controlling the conduction state between the sixth wiring and the first wiring in accordance with the output signal of the first circuit or the potential of the gate of the second transistor .

In one aspect of the present invention, the third transistor may function as a switch for controlling the conduction state of the sixth wiring and the gate of the first transistor in accordance with the output signal of the first circuit.

In one aspect of the present invention, the first circuit controls the timing of supplying the voltage of the sixth wiring to the gate of the second transistor in accordance with the signal of the first wiring or the signal of the second wiring, A function of raising, lowering or holding the potential, or a function of controlling the gate of the second transistor in a floating state.

In one aspect of the present invention, the second circuit is connected to the gate of the first transistor and the fourth wiring to the signal supplied to the third wiring, the signal supplied to the fourth wiring, or the signal supplied to the fifth wiring A function of raising, lowering, or holding the gate potential of the first transistor by controlling the timing of supplying a supplied signal or the voltage of the sixth wiring or functioning as a control circuit for putting the potential of the gate of the first transistor in a floating state It may be good.

In one aspect of the present invention, the first circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, the fourth transistor has a first terminal electrically connected to the second wiring, The first terminal is electrically connected to the sixth wiring, the second terminal is electrically connected to the gate of the second transistor, and the gate is electrically connected to the first The first terminal of the sixth transistor is electrically connected to the second wiring, the second terminal of the sixth transistor is electrically connected to the gate of the fourth transistor, the gate of the sixth transistor is electrically connected to the second wiring, The seventh transistor has a first terminal electrically connected to the sixth wiring, a second terminal electrically connected to the gate of the fourth transistor, a gate electrically connected to the first wiring, Or it may be connected to.

In one aspect of the present invention, the second circuit has the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor, and the eighth transistor has the first terminal electrically connected to the fourth wiring The first terminal is electrically connected to the gate of the first transistor, the second terminal is electrically connected to the gate of the first transistor, the gate is electrically connected to the third wiring, The second terminal is electrically connected to the fourth wiring, the gate is electrically connected to the fourth wiring, the first transistor is electrically connected to the gate of the first transistor, and the second terminal is electrically connected to the sixth wiring The gate is electrically connected to the fifth wiring, the first transistor is electrically connected to the first wiring, and the second terminal is electrically connected to the sixth wiring The first terminal is electrically connected to the first wiring, the second terminal is electrically connected to the sixth wiring, and the gate is electrically connected to the fifth wiring. In the twelfth transistor, the first terminal is electrically connected to the first wiring, Or may be electrically connected to the three wirings.

In one aspect of the present invention, the driving circuit may be formed on a substrate such as a pixel.

In one aspect of the present invention, the channel width of the first transistor may be larger than the channel width of the second transistor and the third transistor.

In addition, the switch can use various types of switches. For example, there are electrical switches or mechanical switches. That is, the switch may be a switch capable of controlling the flow of current, and is not limited to a specific switch. For example, as a switch, a transistor (for example, a bipolar transistor, a MOS transistor, etc.), a diode (for example, a PN diode, a PIN diode, a Schottky diode, a Metal Insulator Metal (MIM) ) Diode, and a diode-connected transistor). Alternatively, a logic circuit combining these can be used as a switch.

An example of a mechanical switch is a switch using a MEMS (Micro electro mechanical system) technology, such as a digital micromirror device (DMD).

It is also possible to use a CMOS-type switch as a switch by using both the N-channel transistor and the P-channel transistor.

In the case where A and B are explicitly stated to be connected, the case where A and B are electrically connected, the case where A and B are functionally connected and the case where A and B are directly connected . Here, A and B are objects (e.g., devices, elements, circuits, wires, electrodes, terminals, conductive films, layers, etc.). Therefore, the present invention is not limited to a predetermined connection relationship, for example, a connection relationship shown in a drawing or a sentence, and includes connections other than those shown in the drawings or sentences.

(For example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, or the like) that enables electrical connection between A and B is A and B, B may be connected. (For example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, or the like), a signal conversion circuit (a DA conversion circuit A voltage source, a current source, a switching circuit, and an amplifying circuit (for example, an A / D conversion circuit, a gamma correction circuit and the like), a potential level conversion circuit A signal amplifier, a differential amplifier circuit, a source follower circuit, a buffer circuit, etc.), a signal generating circuit, a memory circuit, a control circuit, etc.) can be provided between A and B More than one may be connected. For example, in the case where a signal output from A is transmitted to B even when another circuit is inserted between A and B, A and B are functionally connected.

In the case where A and B are explicitly stated to be electrically connected, when A and B are electrically connected (that is, when A and B are connected by interposing another element or another circuit between them) and A And B are functionally connected (that is, when they are functionally connected by interposing another circuit between A and B), and when A and B are directly connected (that is, In the case where they are connected without interposing a circuit). That is, the case where the connection is explicitly stated to be electrically connected is the same as the case where the connection is explicitly stated to be simply connected.

Further, the light-emitting device which is a display device, a display device which is a device having a display element, a light-emitting element, and a device having a light-emitting element can be variously used or can have various devices. For example, EL (electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red (LED), a green LED, a blue LED, and the like), a transistor (a transistor that emits light according to current), an electron emitting device, a liquid crystal device, an electronic ink, an electrophoretic device, a grating light valve (GLV) It is possible to have a display medium in which contrast, brightness, reflectance, transmittance, and the like are changed by an electromagnetism action such as a device (DMD), a piezoelectric ceramic display, or a carbon nanotube.

A liquid crystal element is an element that controls the transmission or non-transmission of light by the optical modulation function of a liquid crystal, and is composed of a pair of electrodes and a liquid crystal. Further, the optical modulation function of the liquid crystal is controlled by an electric field applied to the liquid crystal (including an electric field in the transverse direction, an electric field in the longitudinal direction or an electric field in the oblique direction). Examples of the liquid crystal element include nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, A liquid crystal, a main chain type liquid crystal, a side chain type polymer liquid crystal, a plasma address liquid crystal (PALC), a banana type liquid crystal and the like. In addition, as a driving method of the liquid crystal, a twisted nematic (TN) mode, a super twisted nematic (STN) mode, an in-plane switching (IPS) mode, a fringe field switching (FFS) mode, a multi-domain vertical alignment (PVA) mode, an ASV (Advanced Super View) mode, an ASM (Axially Symmetric Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an ECB (Electrically Controlled Birefringence) Mode, an anti-ferroelectric liquid crystal (AFLC) mode, a polymer dispersed liquid crystal (PDLC) mode, a guest host mode, and a blue phase mode. However, the present invention is not limited to this, and various liquid crystal devices and their driving methods can be used.

Electro luminescence, a cold cathode tube, a hot cathode tube, an LED, a laser light source, and a mercury lamp can be used as the light source. However, the present invention is not limited to this, and various light sources can be used.

Further, the configuration of the transistor can be various forms, and is not limited to a specific configuration. For example, the gate electrode may have two or more multi-gate structures. In the case of a multi-gate structure, since the channel regions are connected in series, a plurality of transistors are connected in series.

As another example, a structure in which the gate electrode is disposed above and below the channel can be applied.

A structure in which a gate electrode is disposed on a channel region, a structure in which a gate electrode is disposed under a channel region, a structure in which a positive stagger structure, a reverse stagger structure, a structure in which a channel region is divided into a plurality of regions, A connected structure, or a structure in which channel regions are connected in series can be applied. Further, a structure in which a source electrode or a drain electrode is superimposed on a channel region (or a part thereof) is also applicable. Alternatively, a structure in which an LDD region is formed can be applied.

Further, in the case where "B is formed on A" is explicitly stated, it is not limited to that B is directly formed on A. But also includes cases in which other objects are interposed between A and B, i.e., Here, A and B are objects (e.g., devices, elements, circuits, wires, electrodes, terminals, conductive films, layers, etc.).

Thus, for example, in the case where "layer B is formed on layer A" is explicitly described, the case where layer B is formed directly on layer A and the case where layer B is formed directly on layer A (for example, (For example, the layer C or the layer D) may be formed as a single layer, and even a plurality of layers may be used good.

This also applies to the case where "B is formed above A" is explicitly stated, and the case where B is directly in contact with A is not limited to the case where B is directly in contact with A, and the case where another object is interposed between A and B is also included. Therefore, for example, when "the layer B is formed above the layer A", a case where the layer B is formed directly on the layer A and a case where the layer B is formed directly on the layer A (for example, a layer C Layer or the like) is formed on the substrate, and the layer B is formed directly on the layer. The other layer (for example, layer C or layer D) may be a single layer or a plurality of layers.

Also, in the case of explicitly describing "B is formed on A ", or" B is formed above A, "

This also applies to the case where "B is formed under A ", or" B is formed under A ".

In addition, it is preferable that the singular number is explicitly stated as singular value. However, the present invention is not limited to this, and a plurality can be used. Likewise, it is preferable that a plural number is explicitly described as plural. However, the present invention is not limited to this, and it is possible to use a single number.

Further, in the drawings, the size, the layer thickness, or the area may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale.

The drawings are schematic illustrations of ideal examples and are not limited to shapes or values shown in the drawings. For example, a deviation of a shape due to a manufacturing technique, a deviation of a shape due to an error, a deviation of a signal, a voltage, or a current due to noise, or a deviation of a signal, a voltage, It is possible to include.

Also, the terminology is often used for the purpose of explaining a specific embodiment, an example, and the like, and is not limited thereto.

Also, undefined text (including technical and technical terms such as terminology or academic terms) can be used as a generic meaning understood by those of ordinary skill in the art. Quot ;, " dictionary ", etc. should preferably be construed in a meaning that does not contradict the background of the related art.

Also, the terms "first", "second", "third" and the like are used to describe various elements, members, regions, layers, and regions separately from others. Thus, the words "first," " second, "" third," etc. do not limit the number of elements, members, regions, layers, Also, for example, it is possible to replace words such as "first," " second, "and " third. &Quot;

According to one aspect of the present invention, the potential of the gate of the transistor can be increased. Alternatively, one mode of the present invention can prevent a malfunction. Alternatively, in an aspect of the present invention, the Vgs of the transistor can be increased. Alternatively, one aspect of the present invention can reduce the on-resistance of the transistor. Alternatively, one aspect of the present invention can reduce the channel width of the transistor. Alternatively, one mode of the present invention can suppress or alleviate deterioration of the transistor. Alternatively, one form of the present invention can reduce the layout area. Alternatively, one form of the present invention can shorten the fall time or the rise time of the output signal of a drive circuit such as a flip-flop, a shift register, or a scan line driver circuit. In an embodiment of the present invention, the display device can be enlarged. Alternatively, one form of the present invention can fix the display device vertically. Alternatively, one form of the present invention can narrow the frame of the display device. Alternatively, an aspect of the present invention can record an accurate signal to a pixel. Alternatively, one form of the present invention can increase the display quality. Alternatively, one aspect of the present invention can increase the yield. Alternatively, one form of the invention can reduce costs. Alternatively, one form of the present invention can reduce the distortion or delay of the signal input to the shift register. Alternatively, one mode of the present invention can reduce power consumption. Alternatively, one form of the present invention can reduce the current capability of the external circuit. Alternatively, one form of the present invention can reduce the size of the external circuit or the size of the display device having the external circuit.

1A and 1B are a circuit diagram of a semiconductor device and a timing chart for explaining a driving method thereof.
2A to 2C are schematic diagrams illustrating a method of driving a semiconductor device.
3A and 3B are schematic diagrams illustrating a method of driving a semiconductor device.
4A and 4B are timing charts illustrating a method of driving a semiconductor device.
5A and 5B are circuit diagrams of a semiconductor device.
6A to 6C are circuit diagrams of a semiconductor device.
7A to 7C are circuit diagrams of a semiconductor device.
8A and 8B are a circuit diagram of a semiconductor device and a timing chart for explaining a driving method thereof.
9A to 9F are schematic diagrams illustrating a method of driving a semiconductor device.
10A to 10F are circuit diagrams of a semiconductor device.
11 is a circuit diagram of a semiconductor device.
12A to 12C are schematic diagrams illustrating a circuit diagram of a semiconductor device and a driving method thereof.
13A to 13C are schematic diagrams illustrating a method of driving a semiconductor device.
14A to 14C are circuit diagrams of a semiconductor device.
15A and 15B are circuit diagrams of a semiconductor device.
16A and 16B are circuit diagrams of a semiconductor device.
17A to 17C are circuit diagrams of a semiconductor device.
18A and 18B are circuit diagrams of a semiconductor device.
19 is a circuit diagram of a shift register.
20 is a timing chart illustrating a method of driving a shift register;
21A and 21B are timing charts illustrating a method of driving a shift register.
22 is a circuit diagram of a shift register;
23A and 23B are system block diagrams of a display device.
24A to 24E are diagrams for explaining the configuration of a display device;
25A and 25B are a circuit diagram of a signal line driver circuit and a timing chart for explaining a driving method thereof.
26A to 26C are timing charts illustrating a circuit diagram of a pixel and a driving method thereof.
27A to 27C are circuit diagrams of pixels.
28A and 28B are circuit diagrams of a semiconductor device.
29A to 29C are top views and sectional views of the display device;
30A to 30C are cross-sectional views of a transistor.
31 is a layout diagram of a shift register.
32 is a layout diagram of a shift register;
33A to 33H are diagrams for explaining an electronic apparatus;
34A to 34H are diagrams for explaining an electronic apparatus;

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. It will be apparent to those skilled in the art, however, that the embodiments can be practiced in many different forms and that various changes in form and detail may be made therein without departing from the spirit and scope thereof. Therefore, the present invention is not limited to the content of the present embodiment. In the following description, the same reference numerals will be used to denote the same components throughout the different drawings, and detailed descriptions of the same portions or portions having the same functions will be omitted.

In addition, contents (some contents may be) described in any one embodiment are not limited to the contents described in the embodiments (some contents may be used) and / or one or a plurality of other embodiments It is possible to apply, combine, substitute, or the like to the contents (some contents may be used).

The contents described in the embodiments are contents to be described using various drawings in the embodiments, or contents to be described using the sentences described in the specification.

The drawings (any part may be) described in any one of the embodiments may be applied to other portions of the drawings, other drawings (some of which may be a part) described in the embodiment, and / By combining the drawings (some of which may be described) in the form, more drawings can be formed.

(Embodiment 1)

In this embodiment, an example of a semiconductor device will be described. The semiconductor device of the present embodiment can be used as, for example, a shift register, a gate driver, a source driver, or a display device. Further, the semiconductor device can be presented as a flip-flop or a drive circuit.

First, an example of the semiconductor device of this embodiment will be described with reference to Fig. 1A. Figure 1 (a) shows a circuit 100. Also, the circuit 100 can be presented as a semiconductor device, a driving circuit, or a flip-flop.

The circuit 100 includes a transistor 101 (also referred to as a first transistor), a transistor 102 (also referred to as a second transistor), a transistor 103 (also referred to as a third transistor), a circuit 104 ), And a circuit 105 (also referred to as a second circuit). The circuit 104 has a plurality of terminals which are a terminal 104a, a terminal 104b, a terminal 104c, and a terminal 104d. The circuit 105 has a plurality of terminals which are a terminal 105a, a terminal 105b, a terminal 105c, and a terminal 105d, a terminal 105e, and a terminal 105f. However, the present invention is not limited to this, and any one of these transistors or any of these circuits may be omitted, or various devices such as a capacitive element, a resistance element, or a diode, or a circuit combining any of these elements may be used. Substitution can be performed. Alternatively, various devices such as transistors, capacitors, resistors, or diodes, or circuits combining any of these devices, can be newly added. Depending on the configuration of the circuit 104 and the circuit 105, it is possible to add a terminal or to omit a terminal.

As an example, the transistors 101 to 103 are of the N channel type. The N-channel transistor is turned on when the potential difference (Vgs) between the gate and the source exceeds the threshold voltage (Vth). However, the present invention is not limited to this, and the transistors 101 to 103 can be of the P-channel type. The P-channel transistor is turned on when the potential difference (Vgs) between the gate and the source is lower than the threshold voltage (Vth).

As an example, as shown in Fig. 28A, the circuit 104 is a logic circuit that combines AND and NOT of two inputs. This combinational logic circuit is a logical product of the inverted signal of one input signal (for example, the signal of the wiring 113) and the inverted signal of the other input signal (for example, the signal of the wiring 111) . However, the present invention is not limited to this, and as the circuit 104, as shown in Fig. 28B, NOR of two inputs can be used. In addition, as the circuit 104, various circuits can be used.

Also by way of example, the circuit 104 and the circuit 105 have one or more transistors. The polarity of these transistors is the same as that of the transistors 101 to 103. By setting the polarity of the transistor to have the same polarity, the manufacturing process can be reduced, the yield can be improved, reliability can be improved, or cost can be reduced. However, the present invention is not limited to this, and the circuit 104 and the circuit 105 can have an N-channel transistor and a P-channel transistor. That is, the circuit 104 and the circuit 105 can be CMOS circuits.

As an example, the terminals 104a to 104c function as an input terminal, and the terminal 104d functions as an output terminal. As an example, the terminals 105a to 105d function as input terminals, and the terminals 105e and 105f function as output terminals. However, the present invention is not limited to this.

Also, circuit 104, and / or circuit 105 may have more terminals. Alternatively, the circuit 104 and / or the circuit 105 may omit some of the terminals.

Next, an example of the connection relationship of the circuit 100 will be described. The first terminal of the transistor 101 is connected to the wiring 112 and the second terminal of the transistor 101 is connected to the wiring 111. [ The first terminal of the transistor 102 is connected to the wiring 116 and the second terminal of the transistor 102 is connected to the wiring 111. [ The first terminal of the transistor 103 is connected to the wiring 116. The second terminal of the transistor 103 is connected to the gate of the transistor 101. The gate of the transistor 103 is connected to the gate of the transistor 102. [ Respectively. The terminal 104a of the circuit 104 is connected to the wiring 112 and the terminal 104b of the circuit 104 is connected to the wiring 111. The terminal 104c of the circuit 104 is connected to the wiring 116, And the terminal 104d of the circuit 104 is connected to the gate of the transistor 102. [ The terminal 105a of the circuit 105 is connected to the wiring 113 and the terminal 105b of the circuit 105 is connected to the wiring 114. The terminal 105c of the circuit 105 is connected to the wiring 115, The terminal 105d of the circuit 105 is connected to the wiring 116 and the terminal 105e of the circuit 105 is connected to the gate of the transistor 101 and the terminal 105d of the circuit 105 Is connected to the wiring 111. [ However, the present invention is not limited to this, and various other connection configurations can be used.

The connection point of the gate of the transistor 101, the second terminal of the transistor 103, or the terminal 105e of the circuit 105 is referred to as a node A. The connection point of the gate of the transistor 102, the terminal 104d of the circuit 104, or the gate of the transistor 103 is referred to as a node B. Further, the node A and the node B can be referred to as a wiring or a terminal.

The wirings 111, 112, 113, 114, 115, and 116 may be referred to as terminals.

Also, as already described, a new terminal can be added to the circuit 104 and / or the circuit 105. In this case, the terminal can be connected to various wirings or various devices.

Further, it is possible to omit any of the wirings 111 to 116 and / or to add new wirings.

Next, examples of signals or voltages input to or output from the wirings 111 to 116 will be described. A signal OUT is outputted from the wiring 111 as an example. The signal OUT is often a digital signal having a high level and a low level and functions as an output signal, a selection signal, a transfer signal, a start signal, a reset signal, a gate signal, can do. A signal IN1 is input to the wiring 112 as an example. The signal IN1 is often a digital signal and can function as a clock signal. The signal IN2 is input to the wiring 113 as an example. The signal IN2 is often an inverted signal of the signal IN1 or a signal whose phase is shifted by 180 DEG from the signal IN1 and can function as an inverted clock signal. The signal IN3 is input to the wiring 114 as an example. The signal IN3 is often a digital signal and can function as a start signal or a vertical synchronizing signal. Alternatively, when the circuit 100 is used in a shift register or a display device, the signal IN3 may be a transmission signal from another stage (e.g., the previous stage) (Preceding row), for example). A signal IN4 is inputted to the wiring 115 as an example. The signal IN4 is often a digital signal and can function as a reset signal. Alternatively, when the circuit 100 is used in a shift register or display device, the signal IN4 may function as a signal for selecting another row (e.g., the next row). To the wiring 116, a voltage V1 is inputted as an example. The voltage V1 is often substantially the same value as the signal OUT of the L level, the signal IN1, the signal IN2, the signal IN3, or the signal IN4, and may be a ground voltage, a power supply voltage, Function. However, the present invention is not limited to this, and various signals, various currents, or various voltages may be input to the wirings 111 to 116. [ A voltage such as a voltage V1 or a voltage V2 may be supplied to the wiring 112, the wiring 113, the wiring 114, and / or the wiring 115, for example. Signals such as a signal OUT, a signal IN1, a signal IN2, a signal IN3, or a signal IN4 may be input to the wiring 116. [ Alternatively, signals or voltages may not be input to the wiring 111, the wiring 112, the wiring 113, the wiring 114, the wiring 115, and / or the wiring 116, .

Incidentally, "roughly" includes various errors such as errors due to noise, errors due to process deviations, deviations caused by deviations in manufacturing steps of devices, and / or measurement errors.

The wiring 111 (also referred to as a first wiring) can function as a signal line, a gate line, a scanning line, or an output signal line. The wiring 112 (also referred to as a second wiring) can function as a signal line or a clock signal line. The wiring 113 (also referred to as a third wiring) can function as a signal line or a clock signal line. The wiring 114 (also referred to as a fourth wiring) can function as a signal line. The wiring 115 (also referred to as a fifth wiring) can function as a signal line. The wiring 116 (also referred to as a sixth wiring) can function as a power supply line or a ground line. However, the present invention is not limited to this, and the wirings 111 to 116 can function as various wirings. For example, when a voltage is supplied to the wiring 112, the wiring 113, the wiring 114, and / or the wiring 115, these wirings can function as a power supply line. Alternatively, when a signal is input to the wiring 116, the wiring 116 can function as a signal line. Alternatively, the wiring 114 and / or the wiring 115 may function as a signal line, a gate line, a scanning line, or an output signal line in the same manner as the wiring 111.

Also, the circuit 100 can input a multi-phase clock signal. For example, when n-phase (n is a natural number) clock signal is presented, the n-phase clock signal refers to n clock signals whose cycles are shifted by 1 / n cycles, respectively. Alternatively, any two of the multi-phase clock signals may be input to the wiring 112 and the wiring 113, respectively.

As the signal IN1 or the signal IN2, a balanced clock signal can be used, and a clock signal of an unbalanced type (also called an unbalance) can be used. The equilibrium refers to a period in which the H level is equal to a period in which the L level is the same in one cycle. The non-parallel type indicates that the period of the H level is different from the period of the L level in one cycle.

Further, as an example, the potential of the L-level signal is V1 and the potential of the H-level signal is V2. V2 > V1. When the voltage V2 is presented, the voltage V2 is substantially equal to the H level of the signal. However, the present invention is not limited to this, and the potential of the L level signal may be lower than V1, or higher than V1. Alternatively, the potential of the H level signal may be lower than V2, or higher than V2.

Next, an example of the functions of the transistor 101 to the transistor 103 and the circuit 104 and the circuit 105 will be described.

The transistor 101 has a function of controlling the timing at which the signal OUT becomes the H level by controlling the timing of supplying the signal IN1 of the H level to the wiring 111 in accordance with the potential of the node A, A pull-up transistor, or a bootstrap transistor. The transistor 102 controls the conduction state between the wiring 116 and the wiring 111 in accordance with the output signal of the circuit 104 or the potential of the node B so that the timing of supplying the voltage V1 to the wiring 111 is set to And can function as a switch. The transistor 103 has a function of controlling the timing of supplying the voltage V1 to the node A by controlling the conduction state of the wiring 116 and the node A in accordance with the output signal of the circuit 104 or the potential of the node B , And can function as a switch.

The circuit 104 has a function of raising, lowering, or holding the potential of the node B by controlling the timing of supplying the signal IN3 or the voltage V1 to the node B in accordance with the signal OUT or the signal IN1, Has a function of putting the node B in a floating state, and can function as a control circuit. The circuit 104 may have a function of controlling the conduction state of the transistor 102 and the transistor 103 by controlling the potential of the node B. [ For example, the circuit 104 has a function of reducing the potential of the node B by supplying the voltage V1 or the signal IN2 of the L level to the node B when the signal IN2 becomes the L level. As another example, the circuit 104 has a function of reducing the potential of the node B by supplying a signal of the voltage V1 or the L level to the node B when the signal OUT becomes the H level. As another example, when the signal IN2 becomes H level when the signal OUT is at the L level, the function of raising the potential of the node B by supplying the voltage V2 or the signal IN2 of the H level to the node B .

The circuit 105 controls the timing of supplying the signal IN3 or the voltage V1 to the node A in accordance with the signal IN2, the signal IN3 or the signal IN4 so that the potential of the node A can be raised, Or a function of holding node A in a floating state, and can function as a control circuit. Alternatively, the circuit 105 may control the timing of supplying the voltage V1 to the wiring 111 in accordance with the signal IN2, the signal IN3, or the signal IN4 to reduce or maintain the potential of the wiring 111 Function or the wiring 111 in a floating state. For example, when the signal IN2 or the signal IN3 becomes the H level, the circuit 105 supplies the node IN with the H level signal IN3 or the voltage V2 to raise the potential of the node A Respectively. As another example, when the signal IN2 or the signal IN4 becomes the H level, the circuit 105 supplies the node A or the wiring 111 with the voltage V1 or the signal of the L level, Quot;).

However, the present invention is not limited to this, and the transistor 101 to the transistor 103, the circuit 104 and the circuit 105 may have various other functions. Alternatively, these elements or circuits may not have the above-described functions.

Next, the operation of the semiconductor device of FIG. 1A will be described with reference to FIGS. 1B, 2A to 2C, 3A, and 3B. 1B is an example of a timing chart for explaining the operation of the semiconductor device. 1B shows an example of the signal IN1, signal IN2, signal IN3, signal IN4, potential Va of node A, potential Vb of node B, and signal OUT in one operation period do. 1B includes a period T1, a period T2, a period T3, a period T4, and a period T5. FIG. 2A is an example of a schematic diagram of the operation of the semiconductor device of FIG. 1A during the period T1. Fig. 2B is an example of a schematic diagram of the operation of the semiconductor device of Fig. 1A in the period T2. FIG. 2C is an example of a schematic diagram of the operation of the semiconductor device of FIG. 1A during the period T3. FIG. 3A is an example of a schematic diagram of the operation of the semiconductor device of FIG. 1A during the period T4. Fig. 3B is an example of a schematic diagram of the operation of the semiconductor device of Fig. 1A in the period T5.

As an example, when the signal IN3 becomes H level, the semiconductor device of FIG. 1A sequentially performs the operation in the period T1, the operation in the period T2, and the operation in the period T3. Then, the semiconductor device of FIG. 1A sequentially repeats the operation in the period T4 and the operation in the period T5 until the signal IN3 becomes the H level again. However, the present invention is not limited to this, and the semiconductor device of FIG. 1A can perform the operations in the periods T1 to T5 in various stages.

First, in the period T1, the signal IN1 is at the L level, the signal IN2 is at the H level, the signal IN3 is at the H level, and the signal IN4 is at the L level. Since the signal IN3 becomes the H level, the circuit 105 starts to raise the potential of the node A. [ At this time, since the signal IN1 becomes the L level, the circuit 104 starts to decrease so that the potential of the node B becomes V1. Therefore, since the transistor 102 and the transistor 103 are turned off, the wiring 116 and the wiring 111 become non-conductive, and the wiring 116 and the node A become non-conductive. Then, when the potential of the node A becomes the sum (V1 + Vth101) of the potential V1 of the wiring 112 and the threshold voltage Vth101 of the transistor 101, the transistor 101 is turned on. Then, since the wiring 112 and the wiring 111 become conductive, the signal IN1 of the L level is supplied from the wiring 112 to the wiring 111 through the transistor 101. Then, Therefore, since the potential of the wiring 111 becomes V1, the signal OUT becomes L level. Thereafter, the circuit 105 further raises the potential of the node A further. Then, the circuit 105 raises the potential of the node A to a certain value (at least V1 + Vth101 or more) and stops the supply of the signal or the voltage to the node A. Therefore, the node A is in the floating state while maintaining the potential (for example, V1 + Vth101 or more) at this time.

In addition, in the period T1, the circuit 105 often supplies the voltage V1 or the signal of the L level to the wiring 111. [ However, the present invention is not limited to this, and the circuit 105 can make the circuit 105 and the wiring 111 non-conductive by not supplying a voltage or a signal to the wiring 111. [

Next, in the period T2, the signal IN1 becomes the H level, the signal IN2 becomes the L level, the signal IN3 becomes the L level, and the signal IN4 becomes the L level. Since the circuit 105 often does not supply a voltage or a signal to the node A, the node A is in a floating state while maintaining the potential (V1 + Vth101 or more) in the period T1. Therefore, since the transistor 101 continues to be in an ON state, the wiring 112 and the wiring 111 continue to be conductive. At this time, since the signal IN1 rises from the L level to the H level, the potential of the wiring 111 starts to rise from V1. Then, since the node A becomes a floating state, the potential of the node A rises in accordance with the parasitic capacitance between the gate of the transistor 101 and the second terminal. Called bootstrap operation. Thus, the potential of the node A rises to V2 + Vth101 + alpha (where a is a positive number). Then, since the potential of the wiring 111 rises to the potential of the H level signal IN2, that is, V2, the signal OUT becomes H level. At this time, since the signal OUT becomes the H level, the circuit 104 supplies the voltage V1 or the L level signal to the node B, thereby maintaining the potential of the node B at V1. Therefore, the wiring 116 and the wiring 111 continue to be in a non-conductive state, and the wiring 116 and the node A continue to be in a non-conductive state since the transistor 102 and the transistor 103 are continuously turned off. The conductive state is established.

In addition, in the period T2, the circuit 104 can turn off the circuit 104 and the node B by not supplying the node B with a signal, a voltage, or the like. Then, the circuit 104 can put the node B in a floating state. In this case also, since the node B is in the floating state, the potential of the node B is often maintained at V1.

In the period T2, the circuit 105 does not supply a signal or a voltage to the wiring 111, thereby making the circuit 105 and the wiring 111 non-conductive. However, the present invention is not limited to this, and the circuit 105 can supply a voltage V2 or H level signal or the like to the wiring 111. [

Next, in the period T3, the signal IN1 becomes the L level, the signal IN2 becomes the H level, the signal IN3 continues to be the L level, and the signal IN4 becomes the H level. Since the signal IN4 becomes the H level, the circuit 105 reduces the potential of the node A to V1. Therefore, since the transistor 101 is turned off, the wiring 112 and the wiring 111 become non-conductive. Here, since the potential of the node A is controlled by the voltage or the signal supplied through the circuit 105, the timing at which the transistor 101 is turned off is often later than the timing at which the signal IN1 is at the L level. In other words, when the transistor 101 is turned on, the signal IN1 may become L level. In this case, an L level signal IN1 is supplied from the wiring 112 to the wiring 111 through the transistor 101. [ Therefore, since the potential of the wiring 111 becomes V1, the signal OUT becomes L level. At this time, since the signal IN1 is at the L level, the circuit 104 supplies the signal IN2 or the voltage V1 of L level to the node B, thereby maintaining the potential of the node B at V1. Therefore, since the transistor 102 and the transistor 103 are continuously turned off, the wiring 116 and the wiring 111 continue to be non-conductive, and the wiring 116 and the node A continue to be non-conductive State.

Further, in the period T3, the circuit 104 does not supply a signal or a voltage to the node B, thereby making the circuit 104 and the node B nonconductive. Then, the circuit 104 can put the node B in a floating state. Even in this case, since the node B is in the floating state, the potential of the node B is often maintained at V1.

Further, in the period T2, the circuit 105 can supply the voltage V1 or the signal of the L level to the wiring 111. [ Alternatively, the circuit 105 does not supply a voltage or a signal to the wiring 111, thereby making the circuit 105 and the wiring 111 non-conductive.

Next, in the period T4, the signal IN1 becomes the H level, the signal IN2 becomes the L level, the signal IN3 becomes the L level continuously, and the signal IN4 becomes the L level. Since the signal OUT continues to be at the L level and the signal IN1 becomes the H level, the circuit 104 supplies the signal IN1 or the voltage V2 at the H level to the node B, V2. Then, since the transistor 102 and the transistor 103 are turned on, the wiring 116 and the wiring 111 become conductive, and the wiring 116 and the node A become conductive. Therefore, since the voltage V1 is supplied from the wiring 116 to the wiring 111 through the transistor 102, the potential of the wiring 111 is held at V1. Since the voltage V1 is supplied from the wiring 116 to the node A via the transistor 103, the potential of the node A is maintained at V1. Thus, the signal OUT continues to be at the L level.

Further, the circuit 105 can supply a voltage V1 or an L level signal or the like to the wiring 111 or the node A. [ Alternatively, the circuit 105 does not supply a voltage or a signal to the wiring 111 or the node A, thereby making the circuit 105 and the node A non-conductive, and the circuit 105 and the wiring 111, Can be brought into a non-conduction state.

Next, in the period T5, the signal IN1 becomes the L level, the signal IN2 becomes the H level, the signal IN3 continues to be L level, and the signal IN4 continues to be L level do. Since the signal IN1 becomes the L level, the circuit 104 reduces the potential of the node B to V1 by supplying the signal IN1 or the voltage V1 to the node B. Therefore, since the transistor 102 and the transistor 103 are turned off, the wiring 116 and the wiring 111 become non-conductive, and the wiring 116 and the node A become non-conductive. Here, when the circuit 105 supplies a voltage V1 or a signal of L level to the wiring 111 or the node A, the potential of the wiring 111 or the node A is held at V1. However, even when the circuit 105 does not supply a voltage or a signal to the wiring 111 or the node A, the potential of the wiring 111 or the node A is held at V1. This is because the wiring 111 and the node A are in the floating state and thus maintain the potential V1 in the period T4. In this way, the signal OUT continues to be at the L level.

The operation of the semiconductor device of FIG. 1A has been described above. In the semiconductor device of FIG. 1A, it is possible to prevent the potential of the node A from decreasing in the period T2. In the conventional technique, the node A and the wiring 111 become conductive until the potential of the wiring 111 rises to a certain value in the period T2. Therefore, the potential of the node A is decreased. However, in the semiconductor device of Fig. 1A, the node A and the wiring 111 do not become conductive in the period T2. Therefore, it is possible to prevent the potential of the node A from decreasing. As a result, a decrease in Vgs of the transistor 101 can be prevented. Alternatively, the Vgs of the transistor 101 can be increased. Or, it is possible to prevent a malfunction caused by excessive reduction of the potential of the node A. Alternatively, since the Vgs of the transistor 101 can be prevented from decreasing, the channel width W of the transistor 101 can be reduced. Therefore, it is possible to reduce the layout area. Alternatively, since the Vgs of the transistor 101 can be increased, the ON resistance of the transistor 101 can be reduced. Therefore, the fall time or rise time of the signal OUT or the delay of the signal OUT can be reduced.

Alternatively, in the semiconductor device of FIG. 1A, the polarity of all the transistors can be N-channel type or P-channel type. Therefore, it is possible to reduce the number of processes, improve the yield, improve the reliability, or reduce the cost. In particular, when all the transistors are of the N-channel type, a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used as the semiconductor layer of the transistor. Therefore, it is possible to reduce the number of processes, improve the yield, improve the reliability, or reduce the cost. However, the present invention is not limited to this, and the semiconductor device of FIG. 1A may have a CMOS circuit composed of a P-channel transistor and an N-channel transistor. Alternatively, a single crystal semiconductor or a polycrystalline semiconductor can be used as the semiconductor layer of the transistor.

Alternatively, in the semiconductor device of FIG. 1A, the transistor 101 to the transistor 103 are turned off in at least one of the period T4 and the period T5. Therefore, since the transistor is not turned on during one operation period, deterioration of characteristics of the transistor, such as a rise in threshold voltage or a decrease in mobility, can be suppressed. Particularly, when a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used as a semiconductor layer of a transistor, characteristic deterioration of the transistor is often remarkable. However, in the semiconductor device of FIG. 1A, deterioration of characteristics of the transistor can be suppressed, so that it becomes easy to use a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor as a semiconductor layer of a transistor. However, the present invention is not limited to this, and a polycrystalline semiconductor or a single crystal semiconductor can be used as the semiconductor layer.

In addition, the period T2 is referred to as a selection period, and the other periods (the period T1, the period T3, the period T4, and the period T5) may be referred to as a non-selection period. Alternatively, the period T1, the period T2, the period T3, the period T4, and the period T5 may be referred to as a set period, an output period, a reset period, a first non-selection period, and a second non-selection period, respectively.

In the example of the timing chart of Fig. 1B, the case where the signal IN1 and the signal IN2 are balanced is shown, but the present invention is not limited to this. As described above, the signal IN1 and the signal IN2 can be non-balanced. Alternatively, in the timing chart of Fig. 1B, when the time when the signal IN1 (or the signal IN2) becomes the H level and the time when the signal IN1 (or the signal IN2) becomes the L level are substantially equal to each other , And the duty ratio of the signal IN1 and the signal IN2 is approximately 50%, the present invention is not limited to this. The duty ratio of the signal IN1 and the signal IN2 can be 50% or more, and 50% or less. 4A shows a timing chart when the signal IN1 and the signal IN2 are non-balanced and the duty ratio of the signal IN1 and the signal IN2 is not 50%. In the timing chart of Fig. 4A, in the period T2, when the signal IN1 becomes the H level, the potential of the node A rises by the bootstrap operation and the signal OUT becomes the H level. Thereafter, the signal IN1 becomes L level. In the timing chart of Fig. 1B, the potential of the node A is decreased to V1 simultaneously or slightly later. That is, the transistor 101 is turned off at the same time as or when the signal IN1 becomes L level. However, in the timing chart of Fig. 4A, the potential of the node A continues to be high until the signal IN4 becomes the H level or the signal IN2 becomes the H level. That is, even after the signal IN1 becomes L level, the transistor 101 continues to be in the ON state. Therefore, the signal IN1 of the L level is supplied from the wiring 112 to the wiring 111 through the transistor 101 since the wiring 112 and the wiring 111 continue to be in a conductive state. Then, since the channel width W of the transistor 101 is often large, the potential of the wiring 111 is reduced to V1 immediately. Therefore, the fall time of the signal OUT can be shortened.

In Fig. 4A, one period of the signal IN1 is denoted by a period Tck. A period Tck (H) represents a period during which the signal IN1 becomes H level in one cycle, and a period Tck (L) represents a period during which the signal IN1 becomes L level during one cycle. Likewise, one period of the signal IN2 is denoted by a period Tckb. The period Tckb (H) is referred to as a period in which the signal IN2 becomes H level in one cycle, and the period Tckb (L) is presented as a period in which the signal IN2 becomes L level in one cycle. The relationship between the period Tck and the period Tckb, the relationship between the period Tck (H) and the period Tckb (H) and the relationship between the period Tck (L) and the period Tckb (L) are Tck? Tckb and Tck ) And Tck (L)? Tckb (L). However, the present invention is not limited to this.

In FIG. 4A, the relationship between the period Tck (H) and the period Tck (L) is preferably Tck (H) < Tck (L). Similarly, the relationship between the period Tckb (H) and the period Tckb (L) is preferably Tckb (H) < Tckb (L). As described above, the fall time of the signal OUT can be shortened. However, the present invention is not limited to this and Tck (H) > Tck (L) is also possible, and Tckb (H) > Tckb (L) is possible.

Further, as shown in the timing chart of FIG. 4A, it is possible to bring the signal OUT to the L level midway through the period T2. In order to realize this, the signal IN4 is set to H level in the middle of the period T2. Then, the circuit 100 of FIG. 1A forcibly starts the operation of the period T3 or the operation corresponding thereto. The circuit 105 supplies the voltage V1 or the L level signal to the node A and the wiring 111 so that the potential of the node A and the wiring 111 is V1 . Therefore, the signal OUT becomes L level. Since the signal OUT becomes the L level and the signal IN1 continues to be at the H level, the circuit 104 supplies the signal IN1 of the H level to the node B similarly to the period T4, Let the potential be V2. Then, since the transistor 102 and the transistor 103 are turned on, the wiring 116 and the wiring 111 become conductive, and the wiring 116 and the node A become conductive. Therefore, since the voltage V1 is supplied from the wiring 116 to the wiring 111 through the transistor 102, the potential of the wiring 111 is held at V1. On the other hand, since the voltage V1 is supplied from the wiring 116 to the node A through the transistor 103, the potential of the node A is held at V1. At this time, since the potential of the node A becomes V1, the transistor 101 is turned off. Therefore, the wiring 112 and the wiring 111 become non-conductive. Thus, the period during which the signal OUT becomes H level is shorter than the period during which the signal IN1 is at the H level. As a result, the driving frequency is delayed as compared with the case where the signal IN1 is at the H level and the signal OUT is at the H level. Therefore, the power consumption can be reduced.

As an example, it is preferable that the channel width of the transistor 101 is the largest among the transistors 101 to 103 or among the transistors of the semiconductor device of Fig. 1A. By doing this, since the ON resistance of the transistor 101 becomes small, the rise time or the fall time of the signal OUT can be shortened. However, the present invention is not limited to this, and the channel width of the transistor 101 can be smaller than any of the transistors of the semiconductor device of Fig. 1A.

When the channel width of a transistor is referred to, it can be said that the ratio is W / L (W: channel width, L: channel length) ratio of the transistor.

In addition, as an example, it is preferable that the channel width of the transistor 102 is larger than the channel width of the transistor 103. [ This is because the wiring 111 is often connected to a gate line or a pixel or the like and therefore the load of the wiring 111 is often larger than the load of the node A. [ This is because the transistor 102 has a function of supplying the voltage V1 to the wiring 111 and the transistor 103 has a function of supplying the voltage V1 to the node A. [ However, the present invention is not limited to this, and the channel width of the transistor 102 may be smaller than the channel width of the transistor 103. [

As an example, it is preferable that, in the transistor 101, the parasitic capacitance between the gate and the second terminal is larger than the parasitic capacitance between the gate and the first terminal. This is because, in the period T2, the potential of the node A tends to become higher by the bootstrap operation. Therefore, it is preferable that the area where the conductive layer functioning as a gate overlaps with the conductive layer functioning as a source or drain is larger than that of the first terminal side on the second terminal side. However, the present invention is not limited to this.

Further, the wiring can be divided into a plurality of wirings. The same signal or voltage can be input to the plurality of wirings, and different signals or voltages can be input, respectively. Alternatively, the plurality of wirings may be connected to the same wiring or the same element, and the plurality of wirings may be connected to different wirings or different elements, respectively. 5A shows a configuration in which the wiring 112 is divided into a plurality of wirings of the wirings 112A and 112B and the wirings 116 are divided into a plurality of wirings of the wirings 116A to 116D. The first terminal of the transistor 101 is connected to the wiring 112A and the terminal 104a of the circuit 104 is connected to the wiring 112B. The first terminal of the transistor 102 is connected to the wiring 116A and the first terminal of the transistor 103 is connected to the wiring 116B and the terminal 104c of the circuit 104 is connected to the wiring 116C And the terminal 105d of the circuit 105 is connected to the wiring 116D. However, the present invention is not limited to this, and the wiring 111, the wiring 113, the wiring 114, and / or the wiring 115 can be divided into a plurality of wirings. Alternatively, only one of the wiring 112 and the wiring 116 can be divided into a plurality of wirings.

In Fig. 5A, the wirings 112A and 112B correspond to the wirings 112 in Fig. 1A. Therefore, the signal IN1 can be input to the wirings 112A and 112B, and the wirings 112A and 112B can function as a signal line or a clock signal line. However, the present invention is not limited to this, and a voltage such as a voltage V1 or a voltage V2 may be supplied to the wirings 112A and 112B, and the wirings 112A and 112B may function as a power supply line. Alternatively, different signals or different voltages may be input to the wirings 112A and 112B, respectively. Alternatively, various signals, various voltages, or various currents may be input to the wirings 112A and 112B.

In Fig. 5A, the wirings 116A to 116D correspond to the wirings 116 in Fig. 1A. Therefore, the voltage V1 can be supplied to the wirings 116A to 116D, and the wirings 116A to 116D can function as a power supply line. However, the present invention is not limited to this, and signals OUT, or signals such as signals IN1 to IN4 may be input to the wirings 116A to 116D, and the wirings 116A to 116D may be signal lines Function. Alternatively, different voltages or different signals may be input to the wirings 116A to 116D, respectively. Alternatively, various signals, various voltages, or various currents may be input to the wirings 116A to 116D.

In Fig. 5A, a signal that becomes L level in the period T4 can be input to the wiring 116A and the wiring 116B. For example, the signal IN2 can be input to the wiring 116A and the wiring 116B. In this case, the first terminal of the transistor 102 and the first terminal of the transistor 103 can be connected to the wiring 113, as shown in Fig. 5B. As described above, reverse bias can be applied to the transistor 102 and the transistor 103, so that deterioration of the characteristics of the transistor 102 and the transistor 103 can be mitigated. The signal IN2 may be input to one of the wiring 116A and the wiring 116B and only one of the wiring 116A and the wiring 116B may be connected to the wiring 113 . Alternatively, the signal OUT, the signal IN3, the signal IN4, or other signals can be input to the wiring 116A and / or the wiring 116B. In this case, the first terminal of the transistor 103 and / or the first terminal of the transistor 102 may be connected to the wiring 111, the wiring 114, or the wiring 115. Alternatively, the signal OUT, the signal IN2, the signal IN3, the signal IN4, or other signals can be input to the wiring 116C and / or the wiring 116D. In this case, the terminal 104c of the circuit 104 and / or the terminal 105d of the circuit 105 can be connected to the wiring 111, the wiring 113, the wiring 114, or the wiring 115 have.

Further, as shown in Fig. 6A, the capacitor 121 can be newly connected between the gate of the transistor 101 and the second terminal. By doing so, the potential of the node A can be made high during the bootstrap operation in the period T2. Therefore, since the Vgs of the transistor 101 becomes large, the fall time or rise time of the signal OUT can be shortened. However, the present invention is not limited to this, and a transistor may be used as the MOS capacitor as the capacitor 121. [ In this case, it is preferable that the gate of the transistor is connected to the node A and the first terminal or the second terminal of the transistor is connected to the wiring 111 in order to increase the capacitance value of the transistor used as the MOS capacitor.

5A and 5B, the capacitance element 121 can be newly connected between the gate of the transistor 101 and the second terminal. Alternatively, a transistor in which the first terminal and the second terminal are connected to the wiring 111 and the gate is connected to the node A can be newly added.

6B, it is possible to newly add the transistor 122 in which the first terminal is connected to the wiring 111, the second terminal is connected to the node A, and the gate is connected to the wiring 112 have. The polarity of the transistor 122 is preferably the same as the polarity of the transistor 101 to the transistor 103, and is often an N-channel type. However, the present invention is not limited to this, and the polarity of the transistor 122 can be of the P-channel type. The transistor 122 has a function of controlling the timing at which the node A and the wiring 111 become conductive in accordance with the signal IN2 and can function as a switch. The transistor 122 is turned on in the period T4 to bring the node A and the wiring 111 into conduction.

5A to 6A, the transistor 122 in which the first terminal is connected to the wiring 111, the second terminal is connected to the node A, and the gate is connected to the wiring 112 is shown in Fig. Newly added.

Further, as shown in Fig. 6C, the transistor 103 can be omitted. In this case, in a period T4, the node A often becomes a floating state. However, the present invention is not limited to this, and the transistor 102 may be omitted. In this case, in a period T4, the wiring 111 often becomes a floating state. By omitting either the transistor 102 or the transistor 103, the number of transistors can be reduced. Therefore, the area of the layout can be reduced, or the yield can be improved.

5A to 6B, the transistor 102 or the transistor 103 can be omitted as in the case of Fig. 6C. In particular, in Fig. 6B, it is preferable to omit either the transistor 102 or the transistor 103. Fig. This is because in FIG. 6B, the node A and the wiring 111 become conductive in the period T4, so that the node A or the wiring 111 does not become a floating state.

7A, one terminal (hereinafter also referred to as an anode) of the transistor 102 is connected to the wiring 111, and the other terminal (hereinafter also referred to as a cathode) is connected to the node B The diode 102a may be replaced by a diode 102a. Alternatively, the transistor 103 can be replaced with a diode 103a connected to the node A at one terminal (hereinafter, also referred to as an anode) and the other terminal (hereinafter also referred to as a cathode) connected to the node B . In this case, the circuit 104 can reduce the potential of the node B to V1 in the period T4, and raise the potential of the node B to V2 in the period T1, the period T2, and the period T5. However, the present invention is not limited to this, and only one of the transistor 102 and the transistor 103 can be replaced with a diode. Alternatively, a diode 102a and / or a diode 103a may be newly added.

5A to 6C, the transistor 102 can be replaced with a diode 102a in which one terminal is connected to the wiring 111 and the other terminal is connected to the node B . Alternatively, the transistor 103 can be replaced with a diode 103a having one terminal connected to the node A and the other terminal connected to the node B. Alternatively, a diode 102a and / or a diode 103a may be newly added.

1A and FIG. 5A to FIG. 7A, the transistor 102 or the transistor 103 can be connected to a diode. In this case, the first terminal of the transistor 102 is connected to the node B, the second terminal of the transistor 102 is connected to the wiring 111, the gate of the transistor 102 is connected to the node B or the wiring 111 Respectively. The first terminal of the transistor 103 is connected to the node B, the second terminal of the transistor 103 is connected to the node A, and the gate of the transistor 103 is connected to the node A or the node B. [ However, the present invention is not limited to this, and only one of the transistor 102 and the transistor 103 can be diode-connected.

Further, as shown in Fig. 7B, the terminal 104b of the circuit 104 can be connected to the node A. Fig. By doing so, since it is possible to prevent the input of the L level signal to the terminal 104b of the circuit 104 in the period T2, it becomes easy to maintain the potential of the node B at V1. Therefore, the potential of the node B instantaneously rises, and the transistor 102 and the transistor 103 can be prevented from being turned on.

Also in Fig. 5A to Fig. 7A as in Fig. 7B, the terminal 104b of the circuit 104 can be connected to the node A. Fig.

In addition, as shown in Fig. 7C, the circuit 105 can be omitted.

Similar to Fig. 7C, the circuit 105 can also be omitted in Figs. 5A to 7B.

28 (b), the terminal 104a of the circuit 104 can be connected to the wiring 113. In addition, as shown in Fig. However, the present invention is not limited to this, and the terminal 104a of the circuit 104 may be connected to various wirings, terminals, or nodes. Similarly to Fig. 28B, the terminal 104a of the circuit 104 can also be connected to the wiring 113 in Figs. 5A to 7B.

8A, a P-channel type transistor can be used as the transistor 101 to the transistor 103. In addition, The transistor 101p, the transistor 102p and the transistor 103p are of the P-channel type corresponding to the transistor 101, the transistor 102, and the transistor 103, respectively. 8B, when the polarity of the transistor is of the P-channel type, the voltage V2 is supplied to the wiring 116 so that the signal OUT, the signal IN1, the signal IN2, the signal IN3, The signal IN4, the potential of the node A, and the potential of the node B are inverted in comparison with the timing chart of Fig. 1B.

In Fig. 8A, it is preferable that the polarity of the transistor included in the circuit 104 and the circuit 105 is P-channel type. However, the present invention is not limited to this, and the polarity of the transistor included in the circuit 104 and the circuit 105 can be of the N-channel type.

5A to 7C, a P-channel transistor can be used as the transistor 101 to the transistor 103, as in FIGS. 8A and 8B.

(Embodiment 2)

In the present embodiment, a concrete example of the circuit 104 described in the first embodiment will be described. Further, the circuit 104 may be referred to as a semiconductor device, a driver circuit, or a gate driver. The description of the first embodiment will not be repeated. The contents described in Embodiment 1 can be freely combined with the contents described in this embodiment.

First, an example of the circuit 104 will be described with reference to Fig. 9A. 9A, the circuit 104 includes a transistor 201 (also referred to as a fourth transistor), a transistor 202 (also referred to as a fifth transistor), a transistor 203 (also referred to as a sixth transistor) (Also referred to as a seventh transistor). However, the present invention is not limited to this, and any of these transistors can be omitted. Alternatively, any of these transistors may be replaced with various elements such as a capacitor, a resistance element, or a diode, or a circuit combining any of these elements. Alternatively, various devices such as transistors, capacitors, resistors, or diodes, or circuits combining any of these devices, can be newly added.

As an example, the transistors 201 to 204 are of the N-channel type. In particular, when the transistors 101 to 103 described in Embodiment Mode 1 are of the N-channel type, the transistors 201 to 204 are preferably of the N-channel type. Thus, all the transistors can be of the N-channel type. However, the present invention is not limited to this, and the transistors 201 to 204 may be of the P-channel type.

Next, an example of the connection relationship of the circuit 104 will be described. The first terminal of the transistor 201 is connected to the wiring 112 and the second terminal of the transistor 201 is connected to the node B. [ The first terminal of the transistor 202 is connected to the wiring 116. The second terminal of the transistor 202 is connected to the node B and the gate of the transistor 202 is connected to the wiring 111. [ The first terminal of the transistor 203 is connected to the wiring 112. The second terminal of the transistor 203 is connected to the gate of the transistor 201. The gate of the transistor 203 is connected to the wiring 112 do. The first terminal of the transistor 204 is connected to the wiring 116 and the second terminal of the transistor 204 is connected to the gate of the transistor 201. The gate of the transistor 204 is connected to the wiring 111 Respectively. However, the present invention is not limited to this, and various other connection configurations can be used.

The connection point of the gate of the transistor 201, the second terminal of the transistor 203, or the second terminal of the transistor 204 is referred to as a node C. Further, the node C may be referred to as a wiring or a terminal.

Various signals, various voltages, or various currents can be input to the wiring 111, the wiring 112, or the wiring 116 as described in the first embodiment. Here, as an example, the signal OUT described in the first embodiment is input to the wiring 111. [ The signal IN1 described in the first embodiment is inputted to the wiring 112 as an example. The wiring 116 is supplied with the voltage V1 described in the first embodiment as an example. However, the present invention is not limited to this.

Next, an example of the functions of the transistors 201 to 204 will be described. The transistor 201 has a function of controlling the timing of supplying the signal IN2 to the node B in accordance with the potential of the node C, and can function as a bootstrap transistor or a switch. The transistor 202 has a function of controlling the timing of supplying the voltage V1 to the node B by controlling the conduction state of the wiring 116 and the node B in accordance with the potential (signal OUT) of the wiring 111, As shown in Fig. The transistor 203 has a function of putting the node C in a floating state after raising the potential of the node C, and can function as a diode. The transistor 204 has a function of controlling the timing of supplying the voltage V1 to the node C by controlling the conduction state of the wiring 116 and the node C in accordance with the potential (signal OUT) of the wiring 111 , And can function as a switch. However, the present invention is not limited to this, and the transistor 201 to the transistor 204 may have various other functions. Alternatively, these elements or circuits may not have the above-described functions.

Next, the operation of the circuit 104 will be described with reference to Figs. 1B, 9B, 9C, 9D, 9E, and 9F. 9B is an example of a schematic diagram of the operation of the circuit 104 in the period T1. 9C is an example of a schematic diagram of the operation of the circuit 104 in the period T2. FIG. 9D is an example of a schematic diagram of the operation of the circuit 104 in the period T3. FIG. 9E is an example of a schematic diagram of the operation of the circuit 104 in the period T4. 9F is an example of a schematic diagram of the operation of the circuit 104 in the period T5.

First, the operation will be described sequentially from the operation in the period T2 for the sake of convenience. In the period T2, the signal IN2 becomes the H level, and the signal OUT becomes the H level. Since the signal OUT becomes the H level, the transistor 202 and the transistor 204 are turned on. Then, the wiring 116 and the node B become conductive, and the wiring 116 and the node C become conductive. Therefore, since the voltage V1 is supplied from the wiring 116 to the node B through the transistor 202, the potential of the node B decreases to V1. Then, since the voltage V1 is supplied from the wiring 116 via the transistor 204 to the node C, the potential of the node C decreases. The potential of the node C at this time is determined according to the operating point of the transistor 203 and the transistor 204. [ Here, the potential of the node C is lower than the sum (V1 + Vth201) of the voltage V1 and the threshold voltage (Vth201) of the transistor 201 as an example. Therefore, since the transistor 201 is turned off, the wiring 112 and the node B become non-conductive.

Next, in the period T3, the signal IN1 becomes the L level, and the signal OUT becomes the L level. Since the signal OUT becomes the L level, the transistor 202 and the transistor 203 are turned off. Thus, the wiring 116 and the node B become non-conductive, and the wiring 116 and the node C become non-conductive. Since the signal IN1 is at the L level, the transistor 203 is turned off. Then, since the node C becomes a floating state, the potential in the period T2 is maintained. Therefore, the transistor 201 is continuously turned off.

Next, in the period T4, the signal IN1 becomes the H level, and the signal OUT becomes the L level continuously. Since the signal OUT continues to be at the L level, the transistor 202 and the transistor 203 are continuously turned off. Therefore, the wiring 116 and the node B continue to be non-conductive, and the wiring 116 and the node C continue to be non-conductive. At this time, the signal IN1 becomes the H level. Then, since the transistor 203 is turned on, the wiring 112 and the node C become conductive. Therefore, since the H level signal IN1 is supplied from the wiring 112 to the node C through the transistor 203, the potential of the node C starts to rise. Thereafter, when the potential of the node C becomes V1 + Vth201, the transistor 201 is turned on. Then, the wiring 112 and the node B become conductive. Therefore, since the H level signal IN1 is supplied from the wiring 112 to the node B through the transistor 201, the potential of the node B starts to rise. Thereafter, when the potential of the node C becomes a value (V2-Vth203) obtained by subtracting the threshold voltage Vth203 of the transistor 203 from the potential V2 of the signal IN1 of the H level, the transistor 203 is turned off do. Therefore, the wiring 112 and the node C become non-conductive. Then, since the node C is in the floating state, the potential of the node C continues to rise by the capacitive coupling of the parasitic capacitance between the gate of the transistor 201 and the second terminal, that is, the bootstrap operation. If it is assumed that the potential of the node C becomes higher than V2 + Vth201, the potential of the node B rises to V2.

Next, in the period T5 or the period T1, the signal IN1 becomes the L level, and the signal OUT becomes the L level continuously. Since the signal OUT continues to be at the L level, the transistor 202 and the transistor 203 are continuously turned off. Therefore, the wiring 116 and the node B continue to be non-conductive, and the wiring 116 and the node C become non-conductive. Then, the signal IN1 becomes L level. Then, since the transistor 203 is turned off, the wiring 112 and the node C continue to be non-conductive. Therefore, since the node C becomes a floating state, the node C maintains a potential higher than V2 + Vth201. As a result, since the transistor 201 continues to be in the ON state, the wiring 112 and the node B continue to conduct. Therefore, since the signal IN1 of the L level is supplied from the wiring 112 through the transistor 201 to the node B, the potential of the node B decreases to V1. At this time, since the node C is in the floating state, the potential is often reduced by capacitive coupling of the parasitic capacitance between the gate of the transistor 201 and the second terminal. In the period T4, the potential of the node C is often decreased by the amount of the rise caused by the bootstrap operation.

The circuit 104 of FIG. 9A has been described above. The circuit 104 of Fig. 9A can use the bootstrap operation to raise the potential of the node B to V2. Therefore, the Vgs of the transistor 102 and the transistor 103 described in the first embodiment can be increased. As a result, since the channel width of the transistor 102 and the transistor 103 can be reduced, the layout area can be reduced. Alternatively, even if the threshold voltage of the transistor 102 and the transistor 103 rises, the transistor can easily turn on. Alternatively, since the ON resistance of the transistor 102 and the transistor 103 becomes small, the potential of the node A and the potential of the wiring 111 can be easily maintained at V1.

Alternatively, in the circuit 104 shown in Fig. 9A, the polarity of all the transistors can be N-channel type or P-channel type. Therefore, it is possible to reduce the number of processes, improve the yield, improve the reliability, or reduce the cost. In particular, when all the transistors are of the N-channel type, a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used as the semiconductor layer of the transistor. Therefore, it is possible to reduce the number of processes, improve the yield, improve the reliability, or reduce the cost. However, the present invention is not limited to this, and the circuit 104 of Fig. 9A may have a CMOS circuit composed of a p-channel type transistor and an n-channel type transistor. Alternatively, a single crystal semiconductor or a polycrystalline semiconductor can be used as the semiconductor layer of the transistor.

Alternatively, in the circuit 104 of FIG. 9A, the transistors 202 to 204 are turned off in at least one of the periods T4 and T5. Therefore, since the transistor does not always stay in an ON state during one operation period, it is possible to suppress deterioration of characteristics of the transistor such as a rise in threshold voltage or a decrease in mobility. Alternatively, in the period T4 and the period T5, the node C repeats the rise of the potential and the decrease of the potential. Therefore, since the pulse is inputted to the transistor 201, it is possible to suppress deterioration of characteristics of the transistor, such as a rise in threshold voltage or a decrease in mobility. Particularly, when a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used as a semiconductor layer of a transistor, characteristic deterioration of the transistor is often remarkable. However, in the semiconductor device of Fig. 9A, deterioration of characteristics of the transistor can be suppressed, so that a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor or the like can be easily used as a semiconductor layer of the transistor. However, the present invention is not limited to this, and a polycrystalline semiconductor or a single crystal semiconductor can be used as the semiconductor layer.

Further, as an example, it is preferable that the channel width of the transistor 203 is smaller than the channel width of the transistor 204. [ This is because, in the period T2, the potential of the node C is lowered when the transistor 203 and the transistor 204 are turned on. For the same reason, it is preferable that the channel length of the transistor 203 is shorter than the channel length of the transistor 204 as an example. However, the present invention is not limited to this, and the channel width of the transistor 203 can be larger than the channel width of the transistor 204. [ Alternatively, the channel length of the transistor 203 may be smaller than the channel length of the transistor 204.

Further, as an example, it is preferable that the channel width of the transistor 204 is smaller than the channel width of the transistor 202. [ This is because the load of the node B is larger than the load of the node C in many cases. For the same reason, it is preferable that the channel width of the transistor 203 is smaller than the channel width of the transistor 201. [ However, the present invention is not limited to this, and the channel width of the transistor 204 can be larger than the channel width of the transistor 202. [ Alternatively, it is possible that the channel width of the transistor 203 is larger than the channel width of the transistor 201.

As an example, it is preferable that the channel width of the transistor 201 and the channel width of the transistor 202 are substantially equal. This is because both the transistor 201 and the transistor 202 control the potential of the node C and are transistors of the same polarity. However, the present invention is not limited to this, and the channel width of the transistor 201 may be larger than the channel width of the transistor 202, and it may be smaller.

The channel widths of the transistor 201, the transistor 202, the transistor 203, or the transistor 204 are set to be the same as those of the transistor 101, the transistor 102, Is smaller than the channel width. However, the present invention is not limited to this, and the channel width of any one of the transistors 201 to 204 can be larger than the channel width of the transistor 101, the transistor 102, or the transistor 103 in Fig. 1A .

As an example, as in the transistor 101 described in Embodiment 1, in the transistor 201, the parasitic capacitance between the gate and the second terminal is larger than the parasitic capacitance between the gate and the first terminal desirable. This is because, in the period T4, the potential of the node C tends to become higher by the bootstrap operation. Therefore, it is preferable that the overlapping area of the conductive layer functioning as a gate and the conductive layer functioning as a source or drain is larger on the second terminal side than on the first terminal side. However, the present invention is not limited to this.

It is also possible to input to the terminal 104b a signal whose L level potential is lower than V1. As described above, reverse bias can be applied to the transistor 202 and the transistor 204, so that deterioration of characteristics of the transistor 202 and the transistor 204 can be mitigated. Alternatively, a signal having a potential at the H level lower than V2 can be input to the terminal 104b. As described above, since the Vgs when the transistor 202 and the transistor 204 are in the ON state can be reduced, deterioration of the characteristics of the transistor 202 and the transistor 204 can be suppressed. In this case, a signal having an L level potential lower than V1, a signal having a H level potential lower than V2, a signal having a L level potential lower than V1 and a H level potential lower than V2, Alternatively, a signal whose L level potential is lower than V1 and whose H level potential is lower than V2 can be input. However, the present invention is not limited to this, and the terminal 104b may be connected to a wiring different from the wiring 111. A signal having an L level potential lower than V1, a signal having a H level potential lower than V2, A signal whose level is lower than V1 and whose potential of H level is lower than V2 can be input.

Further, as in Embodiment 1, the wiring can be divided into a plurality of wirings. The same signal or voltage may be input to the plurality of wirings, and different signals or voltages may be input to the plurality of wirings. Alternatively, the plurality of wirings may be connected to the same wiring or the same element, and the plurality of wirings may be connected to different wirings or elements, respectively. 10A, the wiring 111 is divided into a plurality of wirings such as a wiring 111A and a wiring 111B, a wiring 112 is divided into a plurality of wirings such as a wiring 112C and a wiring 112D, And the wiring 116 is divided into a plurality of wirings such as a wiring 116E and a wiring 116F. The gate of the transistor 204 is connected to the wiring 111A and the gate of the transistor 202 is connected to the wiring 111B. The first terminal of the transistor 201 is connected to the wiring 112C and the first terminal and the gate of the transistor 203 are connected to the wiring 112D. The first terminal of the transistor 202 is connected to the wiring 116E and the first terminal of the transistor 204 is connected to the wiring 116F. However, the present invention is not limited to this, and only one or two of the wiring 111, the wiring 112, and the wiring 116 can be divided into a plurality of wirings. Alternatively, different signals or voltages may be input to the gate and the first terminal of the transistor 203, respectively. In this case, the gate and the first terminal of the transistor 203 can be connected to different wirings, respectively.

In Fig. 10A, the wiring 111A and the wiring 111B correspond to the wiring 111 in Fig. 9A. Therefore, like the wiring 111, the signal OUT can be input to the wiring 111A and the wiring 111B, and the wiring 111A and the wiring 111B can function as a signal line. However, the present invention is not limited to this, and a voltage such as a voltage V1 or a voltage V2 can be supplied to the wiring 111A and the wiring 111B, and the wiring 111A and the wiring 111B can function as a power source line . Alternatively, different signals or different voltages may be input to the wiring 111A and the wiring 111B, respectively. Alternatively, various signals, various voltages, or various currents may be input to the wiring 111A and the wiring 111B.

In Fig. 10A, the wiring 112C and the wiring 112D correspond to the wiring 112 in Fig. 9A. Therefore, like the wiring 112, the signal IN1 can be input to the wiring 112C and the wiring 112D, and the wiring 112C and the wiring 112D can function as a signal line. However, the present invention is not limited to this, and a voltage such as a voltage V1 or a voltage V2 can be supplied to the wiring 112C and the wiring 112D, and the wiring 112C and the wiring 112D can function as a power source line . Alternatively, different signals or voltages can be input to the wiring 112C and the wiring 112D, respectively. Alternatively, various signals, various voltages, or various currents may be input to the wiring 112C and the wiring 112D.

In Fig. 10A, the wiring 116E and the wiring 116F correspond to the wiring 116 in Fig. 9A. Therefore, similarly to the wiring 116, the voltage V1 can be supplied to the wiring 116E and the wiring 116F, and the wiring 116E and the wiring 116F can function as a power source line. However, the present invention is not limited to this, and the wiring 116E and the wiring 116F may be formed by inputting a signal OUT or a signal such as the signal IN1 to the signal IN4, Can function as a signal line. Alternatively, different signals or voltages can be supplied to the wiring 116E and the wiring 116F, respectively. Alternatively, various signals, various voltages, or various currents may be input to the wiring 116E and the wiring 116F.

In Fig. 10A, a signal that becomes L level can be input to the wiring 116E and the wiring 116F in the period T2. For example, the signal IN2 can be input to the wiring 116E and the wiring 116F. In this case, the wiring 116E and the wiring 116F can be connected to the wiring 113 described in the first embodiment. By doing so, since the reverse bias is applied to the transistor 202 and the transistor 204, degradation of characteristics of the transistor 202 and the transistor 204 can be mitigated. However, the present invention is not limited to this, and the signal IN2 can be input to only one of the wiring 116E and the wiring 116F. In this case, only one of the wiring 116E and the wiring 116F can be connected to the wiring 113. [ Alternatively, the signal IN3 or the signal IN4 may be input to the wiring 116E and / or the wiring 116F. In this case, the wiring 116E and / or the wiring 116F can be connected to the wiring 114 or the wiring 115 described in the first embodiment.

In Fig. 10A, the signal IN2 can be input to the wiring 112D. In this case, the gate and the first terminal of the period transistor 203 can be connected to the wiring 113. Thus, in the period T3, the potential of the node C becomes a value (V2-Vth203) obtained by subtracting the threshold voltage Vth203 of the transistor 203 from the potential V2 of the signal IN2 of the H level. Thereafter, in the period T4, since the signal IN1 becomes the H level, the potential of the node C rises more than V2-Vth203 by the bootstrap operation. Therefore, since the potential of the node C is high, the Vgs of the transistor 201 can be increased. As a result, the fall time and rise time of the output signal (the potential of the node B) of the circuit 104 can be shortened. Alternatively, the delay of the output signal of the circuit 104 can be reduced. However, the present invention is not limited to this, and the voltage V2 can be supplied to the wiring 112D.

Further, as shown in Fig. 10B, the capacitor element 221 can be newly connected between the gate of the transistor 201 and the second terminal. By doing so, the potential of the node C can be increased, as in the case of FIG. 6A. However, the present invention is not limited thereto. As in the case of Fig. 6A, the first terminal and the second terminal of the capacitor 221 can be connected to the node B, and the transistor whose gate is connected to the node C can be used as the MOS capacitor.

10A, the capacitance element 221 can be newly connected between the gate of the transistor 201 and the second terminal. Alternatively, the first terminal and the second terminal may be connected to the node B, and the transistor whose gate is connected to the node C may be newly connected.

Further, as shown in Fig. 10C, the transistor 204 can be omitted. Alternatively, as shown in Fig. 10D, the transistor 202 may be omitted. By doing so, the number of transistors can be reduced. Therefore, the layout area can be reduced, or the yield can be improved. However, the present invention is not limited to this, and both the transistor 202 and the transistor 204 can be omitted.

10A and 10B, the transistor 202 and / or the transistor 204 may be omitted in FIGS. 10A and 10B.

10E, one terminal (hereinafter also referred to as an anode) of the transistor 202 is connected to the node B, and the other terminal (hereinafter also referred to as a cathode) is connected to the wiring 111 Can be replaced by a diode 202a. Alternatively, the transistor 203 may be replaced with a diode 203a connected to one terminal (hereinafter also referred to as an anode) connected to the node C and the other terminal (hereinafter also referred to as a cathode) connected to the wiring 111 . In this case, it is possible to input the inverted signal of the signal OUT or the inverted signal of the potential of the node A to the terminal 104b of the circuit 104. The wiring 111 or the node A is connected to the terminal 104b of the circuit 104 through a circuit having a function of inverting and outputting an input signal such as an inverter circuit, a NAND circuit, or a NOR circuit It is possible. However, the present invention is not limited to this, and one of the transistor 202 and the transistor 204 can be replaced with a diode. Alternatively, a diode 202a and / or a diode 203a may be newly added.

10A to 10D, the transistor 202 can be replaced with a diode 202a in which one terminal is connected to the node B and the other terminal is connected to the wiring 111 . Alternatively, the transistor 203 may be replaced with a diode 203a having one terminal connected to the node C and the other terminal connected to the wiring 111. [ Alternatively, a diode 202a and / or a diode 203a may be newly added.

10A to 10E, the first terminal of the transistor 202 is connected to the wiring 111, the second terminal of the transistor 202 is connected to the node B, the transistor 202 is connected to the second terminal, The gate of the transistor 202 can be connected to the wiring 111 or the node B so that the transistor 202 can be diode-connected. Alternatively, the first terminal of the transistor 204 is connected to the wiring 111, the second terminal of the transistor 204 is connected to the node C, and the gate of the transistor 204 is connected to the wiring 111 or the node C The transistor 204 can be diode-connected. However, the present invention is not limited to this, and only one of the transistor 202 and the transistor 204 can be diode-connected.

Further, as shown in FIG. 10F, a P-channel transistor can be used as the transistor 201 to the transistor 204. FIG. In particular, when a p-channel transistor is used as the transistor 101 to the transistor 103 in Fig. 1A, it is preferable to use a p-channel transistor as the transistor 201 to the transistor 204. [ The transistor 201p, the transistor 202p, the transistor 203p, and the transistor 204p correspond to the transistor 201, the transistor 202, the transistor 203, and the transistor 204, respectively, .

10A to 10E, a P-channel type transistor can be used as the transistor 201 to the transistor 204. In this case,

As described above, the circuit 104 described in the first embodiment can be used for the circuit 104 included in the circuit 100 described in the first embodiment. 11 shows a configuration in which an example of the circuit 104 shown in Fig. 9A is used as the circuit 104 included in the circuit 100 shown in Fig. 7C. However, the present invention is not limited to this, and the circuit 104 in the case of FIG. 9A, FIG. 10A to FIG. 10F, or a combination thereof may be illustrated in FIGS. 1A, 5A, 5B, 6A, 6B, 6C, 7b, 8a, or the circuit 104 of the circuit 100 when these are combined.

(Embodiment 3)

In the present embodiment, a concrete example of the circuit 105 will be described. Further, the circuit 105 may be referred to as a semiconductor device, a driver circuit, or a gate driver. In addition, the description in the first embodiment and the second embodiment is omitted. The contents described in Embodiment 1 and Embodiment 2 can be freely combined with the contents described in this embodiment.

First, an example of the circuit 105 will be described with reference to Fig. 12A. 9A, the circuit 105 includes a transistor 301 (also referred to as an eighth transistor), a transistor 302 (also referred to as a ninth transistor), a transistor 303 (also referred to as a tenth transistor), a transistor 304 (also referred to as an eleventh transistor), and a transistor 305 (also referred to as a twelfth transistor). However, the present invention is not limited to this, and any of these transistors can be omitted. Alternatively, any of these transistors may be replaced with various elements such as a capacitor, a resistance element, or a diode, or a circuit combining any of these elements. Alternatively, various devices such as transistors, capacitors, resistors, or diodes, or circuits combining any of these devices, can be newly added.

As an example, the transistors 301 to 305 are of the N-channel type. Particularly, when the transistor 101 to the transistor 103 described in Embodiment 1 and the transistor 201 to the transistor 204 described in Embodiment Mode 2 are of the N channel type, Is preferably of the N channel type. Thus, all the transistors can have the same polarity. However, the present invention is not limited to this, and the transistor 301 to the transistor 305 may be of the P-channel type.

Next, an example of the connection relationship of the circuit 105 in Fig. 12A will be described. The first terminal of the transistor 301 is connected to the wiring 114. The second terminal of the transistor 301 is connected to the node A and the gate of the transistor 301 is connected to the wiring 114. [ The first terminal of the transistor 302 is connected to the wiring 114. The second terminal of the transistor 302 is connected to the node A and the gate of the transistor 302 is connected to the wiring 113. [ The first terminal of the transistor 303 is connected to the wiring 116. The second terminal of the transistor 303 is connected to the node A and the gate of the transistor 303 is connected to the wiring 115. [ The first terminal of the transistor 304 is connected to the wiring 116. The second terminal of the transistor 304 is connected to the wiring 111. The gate of the transistor 304 is connected to the wiring 115. [ The first terminal of the transistor 305 is connected to the wiring 116. The second terminal of the transistor 305 is connected to the wiring 111. The gate of the transistor 305 is connected to the wiring 113. [ However, the present invention is not limited to this, and various other connection configurations can be used.

Various signals, various voltages, or various voltages can be input to the wiring 113, the wiring 114, the wiring 115, or the wiring 116 as described in the first embodiment. Here, as an example, the signal IN2 described in Embodiment 1 is input to the wiring 113. [ The signal IN3 described in the first embodiment is input to the wiring 114 as an example. As an example, the signal IN4 shown in Fig. 1B or Fig. 3A is inputted to the wiring 115. Fig. A voltage V1 is supplied to the wiring 116 as an example. However, the present invention is not limited to this.

Next, an example of the functions of the transistors 301 to 305 will be described. The transistor 301 can function as a diode by controlling the timing of supplying the signal IN2 of the H level to the node A in accordance with the signal IN3. Alternatively, the transistor 301 has a function of controlling the timing of supplying the signal IN3 to the node A by controlling the conduction state of the wiring 114 and the node A in accordance with the potential of the node A. [ The transistor 302 has a function of controlling the timing of supplying the signal IN3 to the node A by controlling the conduction state of the wiring 114 and the node A in accordance with the signal IN2 and can function as a switch . The transistor 303 has a function of supplying the voltage V1 to the node A by controlling the conduction state of the wiring 116 and the node A in accordance with the signal IN4 and can function as a switch. The transistor 304 has a function of supplying the voltage V1 to the wiring 111 by controlling the conduction state of the wiring 116 and the wiring 111 in accordance with the signal IN4 and can function as a switch. The transistor 305 has a function of supplying the voltage V1 to the wiring 111 by controlling the conduction state of the wiring 116 and the wiring 111 in accordance with the signal IN2 and can function as a switch. However, the present invention is not limited to this, and the transistor 301 to the transistor 305 may have various other functions. Alternatively, these elements or circuits may not have the above-described functions.

Next, the operation of the circuit 105 will be described with reference to Figs. 1B and 12B to 13C. 12B is an example of a schematic diagram of the operation of the circuit 105 in the period T1. 12C is an example of a schematic diagram of the operation of the circuit 105 in the period T2. 13A is an example of a schematic diagram of the operation of the circuit 105 in the period T3. 13B is an example of a schematic diagram of the operation of the circuit 105 in the period T4. 13C is an example of a schematic diagram of the operation of the circuit 105 in the period T5.

First, in the period T1, the signal IN2 becomes the H level, the signal IN3 becomes the H level, and the signal IN4 becomes a L level. Since the signal IN3 becomes the H level, the transistor 301 is turned on. At the same time, since the signal IN2 becomes H level, the transistor 302 and the transistor 305 are turned on. The signal IN3 is supplied from the wiring 114 to the node A through the transistor 301 and the transistor 302 because the wiring 114 and the node A are rendered conductive. Therefore, the potential of the node A starts to rise. Similarly, since the wiring 116 and the wiring 111 become conductive, the voltage V1 is supplied from the wiring 116 to the wiring 111 through the transistor 305. [ Therefore, the potential of the wiring 111 becomes V1. At this time, since the signal IN4 is at the L level, the transistor 303 and the transistor 304 are turned off. Therefore, the wiring 116 and the node A become non-conductive, and the wiring 116 and the wiring 111 become non-conductive. Thereafter, when the potential of the node A becomes equal to the potential V2 of the wiring 114 (V2-Vth301) obtained by subtracting the threshold voltage Vth301 of the transistor 301, the transistor 301 is turned off. Likewise, when the potential of the node A becomes equal to the potential (V2-Vth302) of the potential V2 of the wiring 113 minus the threshold voltage Vth302 of the transistor 302, the transistor 302 is turned off. Therefore, the wiring 114 and the node A become non-conductive. Here, as an example, when the potential of the node A becomes V2-Vth301, the transistor 301 and the transistor 302 are turned off. Therefore, the node A is in the floating state while maintaining the potential at V2-Vth301.

Next, in the period T2, the signal IN3 becomes the L level, the signal IN4 becomes the L level, and the signal IN5 becomes the L level continuously. Since the signal IN3 becomes the L level, the transistor 301 is continuously turned off. At the same time, since the signal IN2 becomes L level, the transistor 302 is continuously turned off and the transistor 303 is turned off. Therefore, the wiring 114 and the node A continue to be non-conductive, and the wiring 116 and the wiring 111 become non-conductive. At this time, since the signal IN4 continues to be at the L level, the transistor 303 and the transistor 304 are continuously turned off. Therefore, the wiring 116 and the node A continue to be non-conductive, and the wiring 116 and the wiring 111 continue to be non-conductive.

Next, in the period T3, the signal IN2 becomes the H level, the signal IN3 continues to be the L level, and the signal IN4 becomes the H level. Since the signal IN3 continues to be at the L level, the transistor 301 is continuously turned off. Since the signal IN2 becomes H level, the transistor 302 and the transistor 304 are turned on. Then, since the wiring 114 and the node A become conductive, the signal IN3 of the L level is supplied from the wiring 114 to the node A through the transistor 302. Then, Similarly, since the wiring 116 and the wiring 111 become conductive, the voltage V1 is supplied from the wiring 116 to the wiring 111 through the transistor 305. [ At this time, since the signal IN4 becomes H level, the transistor 303 and the transistor 304 are turned on. Then, since the wiring 116 and the node A become conductive, the voltage V1 is supplied from the wiring 116 via the transistor 303 to the node A. Similarly, since the wiring 116 and the wiring 111 become conductive, the voltage V1 is supplied from the wiring 116 to the wiring 111 through the transistor 304. [ Therefore, the potential of the node A decreases to become V1, and the potential of the wiring 111 decreases to become V1.

Next, in the period T4, the signal IN2 becomes the L level, the signal IN3 continues to be the L level, and the signal IN4 becomes the L level. Since the signal IN3 continues to be at the L level, the transistor 301 is continuously turned off. Since the signal IN2 becomes L level, the transistor 302 and the transistor 305 are turned off. Thus, the wiring 114 and the node A become non-conductive, and the wiring 116 and the wiring 111 become non-conductive. At the same time, since the signal IN4 becomes the L level, the transistor 303 and the transistor 304 are turned off. Therefore, the wiring 116 and the node A become non-conductive, and the wiring 116 and the wiring 111 become non-conductive. As described above, in the period T4, there are many cases in which no signal or voltage is supplied from the circuit 105 to the node A or the wiring 111. [

Next, in the period T5, the signal IN2 becomes the H level, the signal IN3 continues to be the L level, and the signal IN4 becomes the L level continuously. Since the signal IN4 continues to be at the L level, the transistor 303 and the transistor 304 are turned off. Therefore, the wiring 116 and the node A become non-conductive, and the wiring 116 and the wiring 111 become non-conductive. Likewise, since the signal IN3 continues to be at the L level, the transistor 301 is continuously turned off. At this time, since the signal IN2 becomes the H level, the transistor 302 and the transistor 305 are turned on. Then, since the wiring 114 and the node A become conductive, the signal IN3 of the L level is supplied from the wiring 114 to the node A through the transistor 302. Then, Therefore, the potential of the node A is maintained at V1. Similarly, since the wiring 116 and the wiring 111 become conductive, the voltage V1 is supplied from the wiring 116 to the wiring 111 through the transistor 305. [ Therefore, the potential of the wiring 111 is held at V1.

The circuit 105 of Fig. 12A has been described above. In the circuit 105 of Fig. 12A, the polarity of all the transistors can be N-channel type or P-channel type. Therefore, it is possible to reduce the number of processes, improve the yield, improve the reliability, or reduce the cost. In particular, when all the transistors are of the N-channel type, a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used as the semiconductor layer of the transistor. Therefore, it is possible to reduce the number of processes, improve the yield, improve the reliability, or reduce the cost. However, the present invention is not limited to this, and the circuit 105 in Fig. 12A may have a CMOS circuit composed of a p-channel transistor and an n-channel transistor. Alternatively, a single crystal semiconductor or a polycrystalline semiconductor can be used as the semiconductor layer of the transistor.

Alternatively, in the circuit 105 of Fig. 12A, the transistor 301 to the transistor 305 are turned off in at least one of the period T4 and the period T5. Therefore, since the transistor does not always stay in an ON state during one operation period, it is possible to suppress deterioration of characteristics of the transistor such as a rise in threshold voltage or a decrease in mobility. Particularly, when a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used as a semiconductor layer of a transistor, characteristic deterioration of the transistor is often remarkable. However, in the circuit 105 shown in Fig. 12A, it is possible to suppress deterioration of characteristics of the transistor, so that it becomes easy to use a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor or the like as the semiconductor layer of the transistor. However, the present invention is not limited to this, and a polycrystalline semiconductor or a single crystal semiconductor can be used as the semiconductor layer.

As an example, it is preferable that the channel width of the transistor 305 is larger than the channel width of the transistor 302. [ Alternatively, the channel width of the transistor 304 is preferably larger than the channel width of the transistor 303 as an example. Since the load of the wiring 111 is often larger than the load of the node A, the driving ability of the transistor for supplying the signal or the voltage to the wiring 111 is controlled by the drive of the transistor supplying the signal or the voltage to the node A This is because it is often larger than the ability. The transistor 305 and the transistor 304 have a function of supplying a signal or a voltage to the wiring 111. The transistor 302 and the transistor 303 have functions . However, the present invention is not limited to this, and the channel width of the transistor 305 can be smaller than the channel width of the transistor 302. [ Alternatively, the channel width of the transistor 304 may be smaller than the channel width of the transistor 303 as an example. This is because noise is apt to occur at the node A due to the parasitic capacitance between the first terminal and the gate of the transistor 101 described in the first embodiment. This is because there is a case where the transistor 101 is turned on by the noise and the potential of the wiring 111 rises.

In addition, as an example, it is preferable that the channel width of the transistor 303 is larger than the channel width of the transistor 302. [ Alternatively, the channel width of the transistor 304 is preferably larger than the channel width of the transistor 305 as an example. By doing so, the influence of noise generated in the node A and the wiring 111 can be reduced. However, the present invention is not limited to this, and the channel width of the transistor 303 may be smaller than the channel width of the transistor 302. [ Alternatively, the channel width of the transistor 304 may be smaller than the channel width of the transistor 305.

Further, a signal whose L level potential is lower than V1 can be input to the terminal 105a and the terminal 105c. As described above, since the reverse bias can be applied to the transistors 302 to 305, characteristic deterioration of the transistors 302 to 305 can be mitigated. Alternatively, a signal having a potential at the H level lower than V2 can be input to the terminal 105a and the terminal 105c. As described above, since the Vgs when the transistors 302 to 305 are turned on can be reduced, characteristic deterioration of the transistors 302 to 305 can be suppressed. In this case, a signal whose L level potential is lower than V1, a signal whose H level potential is lower than V2, or a L level potential is lower than V1 and a H level potential is supplied to the wiring 113 and the wiring 115 by V2 A lower signal can be input. However, the present invention is not limited to this, and a signal having an L level potential lower than V1, a signal having a H level potential lower than V2, or a low level potential is lower than V1 in one of the terminal 105a and the terminal 105c, And a signal having a potential of the H level lower than V2 can be input. In this case, a signal having an L level potential lower than V1, a signal having a H level potential lower than V2, or a signal having an L level is lower than V1 and a H level potential Can input a signal lower than V2. Alternatively, the terminal 105a is connected to a wiring different from the wiring 113, and a signal having a low level potential lower than V1, a signal having a high level potential lower than V2, And the potential of the H level is lower than V2. Alternatively, the terminal 105c is connected to a wiring different from the wiring 115. A signal having an L level potential lower than V1, a signal having a H level potential lower than V2, or a signal having an L level potential higher than V1 And the potential of the H level is lower than V2.

Further, the terminal 105d can be supplied with a signal at the L level in the periods T1, T3, and T4. For example, the signal IN2 may be input to the terminal 105d. In this case, the terminal 105d can be connected to the wiring 113. [ By doing so, reverse bias can be applied to the transistor 303, the transistor 304, or the transistor 305, so that deterioration of characteristics of the transistor 303, the transistor 304, or the transistor 305 can be mitigated have.

Further, as in Embodiment 1 or Embodiment 2, the wiring can be divided into a plurality of wirings. The same signal or voltage can be input to the plurality of wirings, and different signals or voltages can be input, respectively. Alternatively, the plurality of wirings may be connected to the same wiring or the same element, and the plurality of wirings may be connected to different wirings or elements, respectively. 14A, the wiring 113 is divided into a plurality of wirings, that is, the wirings 113A and 113B, the wirings 114 are divided into a plurality of wirings, that is, the wirings 114A and 114B, The wiring 115 is divided into a plurality of wirings 115A and 115B and the wirings 116 are divided into a plurality of wirings 116G to 116I. The gate of the transistor 302 is connected to the wiring 113A and the gate of the transistor 305 is connected to the wiring 113B. The first terminal of the transistor 302 is connected to the wiring 114A and the first terminal and the gate of the transistor 301 are connected to the wiring 114B. The gate of the transistor 303 is connected to the wiring 115A and the gate of the transistor 304 is connected to the wiring 115B. The first terminal of the transistor 303 is connected to the wiring 116G and the first terminal of the transistor 304 is connected to the wiring 116H and the first terminal of the transistor 305 is connected to the wiring 116I . However, the present invention is not limited to this, and only one, two, or three of the wirings 113, the wirings 114, the wirings 115, and the wirings 116 may be divided into a plurality of wirings.

In Fig. 14A, the wiring 113A and the wiring 113B correspond to the wiring 113 in Fig. 12A. The signal IN2 can be input to the wirings 113A and 113B and the wirings 113A and 113B can function as signal lines similarly to the wirings 113. [ However, the present invention is not limited to this, and a voltage such as a voltage V1 or a voltage V2 can be supplied to the wiring 113A and the wiring 113B, and the wiring 113A and the wiring 113B can function as a power supply line. Alternatively, different signals or different voltages may be input to the wiring 113A and the wiring 113B, respectively. Alternatively, various signals, various voltages, or various currents can be input to the wiring 113A and the wiring 113B.

In Fig. 14A, the wiring 114A and the wiring 114B correspond to the wiring 114 in Fig. 12A. Therefore, similarly to the wiring 114, the signal IN3 can be input to the wiring 114A and the wiring 114B, and the wiring 114A and the wiring 114B can function as a signal line. However, the present invention is not limited to this, and a voltage such as a voltage V1 or a voltage V2 can be supplied to the wiring 114A and the wiring 114B, and the wiring 114A and the wiring 114B can function as a power supply line. Alternatively, different signals or different voltages may be input to the wiring 114A and the wiring 114B, respectively. Alternatively, various signals, various voltages, or various currents can be input to the wiring 114A and the wiring 114B.

In Fig. 14A, the wiring 115A and the wiring 115B correspond to the wiring 115 in Fig. 12A. The signal IN4 can be input to the wirings 115A and 115B and the wirings 115A and 115B can function as signal lines similarly to the wirings 115. [ However, the present invention is not limited to this, and a voltage such as a voltage V1 or a voltage V2 can be supplied to the wiring 115A and the wiring 115B, and the wiring 115A and the wiring 115B can function as a power supply line. Alternatively, different signals or different voltages may be input to the wiring 115A and the wiring 115B, respectively. Alternatively, various signals, various voltages, or various currents may be input to the wiring 115A and the wiring 115B.

In Fig. 14A, the wirings 116G to 116I correspond to the wirings 116 in Fig. 12A. Therefore, similarly to the wiring 116, the voltage V1 can be supplied to the wiring 116G to the wiring 116I, and the wiring 116G to the wiring 116I can function as a power source line. However, the present invention is not limited to this, and the signals OUT, or signals such as the signals IN1 to IN4 may be input to the wirings 116G to 116I so that the wirings 116G to 116I And can function as a signal line. Alternatively, different voltages or different signals may be supplied to the wirings 116G to 116I, respectively. Alternatively, various signals, various voltages, or various currents may be input to the wirings 116G to 116I.

In Fig. 14A, a signal that becomes the L level can be input to the wiring 116G and the wiring 116H in the period T3. For example, the signal IN2 can be input to the wiring 116G and the wiring 116H. In this case, the wiring 116G and the wiring 116H can be connected to the wiring 112 described in the first and second embodiments. By doing so, reverse bias can be applied to the transistor 303 and the transistor 304, so that deterioration of characteristics of the transistor 303 and the transistor 304 can be suppressed. However, the present invention is not limited to this, and the signal IN2 can be input to only one of the wiring 116G and the wiring 116H. Alternatively, the signal OUT or the signal IN3 can be input to the wiring 116G and / or the wiring 116H. In this case, the wiring 116G and / or the wiring 116H can be connected to the wiring 111 or the wiring 114 described in the first and second embodiments.

In Fig. 14A, a signal that becomes L level can be input to the wiring 116I in the period T1, the period T3, and the period T5. For example, the signal IN2 may be input to the wiring 116I. In this case, the wiring 116I can be connected to the wiring 112 described in the first embodiment and the second embodiment. By doing so, reverse bias can be applied to the transistor 305, so that degradation of the characteristics of the transistor 305 can be suppressed. However, the present invention is not limited to this.

Further, as shown in Fig. 14B, the transistor 303 and the transistor 304 can be omitted. Thus, the number of transistors can be reduced. Therefore, the area of the layout can be reduced, or the yield can be improved. However, the present invention is not limited to this, and only one of the transistor 303 and the transistor 304 can be omitted.

14A, the transistor 303 and / or the transistor 304 may be omitted in Fig. 14A.

Further, as shown in Fig. 14C, the transistor 305 can be omitted. Thus, the number of transistors can be reduced. Therefore, the layout area can be reduced, or the yield can be improved. However, the present invention is not limited to this.

14A and 14B, the transistor 305 can be omitted.

Further, as shown in Fig. 15A, the transistor 302 can be omitted. Thus, the number of transistors can be reduced. Therefore, the layout area can be reduced, or the yield can be improved. However, it is not limited to this.

Also in the same manner as in Fig. 15A, the transistor 302 can be omitted also in Figs. 14A to 14C.

Further, as shown in Fig. 15B, the transistor 301 can be omitted. Thus, the number of transistors can be reduced. Therefore, the layout area can be reduced, or the yield can be improved. However, the present invention is not limited to this.

Also in the same manner as in Fig. 15B, the transistor 301 can be omitted also in Figs. 14A to 15A.

16A, the transistor 303 is connected to one terminal (hereinafter also referred to as an anode) with the node A, and the other terminal (hereinafter also referred to as a cathode) is connected to the wiring 115 The diode 303a may be replaced by a diode 303a. Alternatively, the transistor 304 may be connected to a diode 304a to which one terminal (hereinafter also referred to as an anode) is connected to the wiring 111 and the other terminal (hereinafter also referred to as a cathode) is connected to the wiring 115 Can be substituted. However, the present invention is not limited to this, and one of the transistor 303 and the transistor 304 may be replaced with a diode. Alternatively, a diode 303a and / or a diode 304a may be newly added.

14A to 15B, the transistor 303 can be replaced with a diode 303a, in which one terminal is connected to the node A and the other terminal is connected to the wiring 115 have. Alternatively, the transistor 304 can be replaced with a diode 304a, one terminal of which is connected to the wiring 111, and the other terminal of which is connected to the wiring 115. [ Alternatively, a diode 303a and / or a diode 304a may be newly added.

14A to 16A, the first terminal of the transistor 303 is connected to the wiring 115, the second terminal of the transistor 303 is connected to the node A, and the transistor 303 is connected to the second terminal of the transistor 303. Further, although not shown, The gate of the transistor 303 is connected to the node A, so that the transistor 303 can be diode-connected. Alternatively, the first terminal of the transistor 304 is connected to the wiring 115, the second terminal of the transistor 304 is connected to the wiring 111, and the gate of the transistor 304 is connected to the wiring 111 , The transistor 304 can be diode-connected. However, the present invention is not limited to this, and one of the transistor 303 and the transistor 304 can be diode-connected.

16B, one terminal (hereinafter, also referred to as an anode) of the transistor 305 is connected to the wiring 111 and the other terminal (hereinafter also referred to as a cathode) is connected to the wiring 113 It can be replaced with a diode 305a to be connected. However, the present invention is not limited to this, and a diode 305a can be newly added.

14A to 16A, the transistor 305 is connected to one terminal (hereinafter also referred to as an anode) with the wiring 111, and the other terminal (hereinafter also referred to as a cathode) ) Can be replaced with a diode 305a connected to the wiring 113. [ However, a diode 305a can be newly added.

14A to 16B, a first terminal of the transistor 305 is connected to the wiring 113, a second terminal of the transistor 305 is connected to the wiring 111, and a transistor (not shown) 305 are connected to the wiring 111, the transistor 305 can be diode-connected. However, the present invention is not limited to this.

Further, as shown in Fig. 17A, the gate of the transistor 301 can be connected to the wiring 117. Fig. Thus, the circuit 105 can have a new terminal 105g. The wiring 117 is connected to the gate of the transistor 301 through the terminal 105g. The voltage V2 is supplied to the wiring 117, and the wiring 117 can function as a power supply line. The first terminal of the transistor 301 may be connected to the wiring 117 and the gate of the transistor 301 may be connected to the wiring 114. [ Alternatively, a signal which becomes H level in the period T2 can be inputted to the wiring 117, and the wiring 117 can function as a signal line. For example, the signal IN2 may be input to the wiring 117, and the wiring 117 may be connected to the wiring 113. [ Alternatively, various signals, various voltages, or various currents may be input to the wiring 117.

14A to 16B, the gate of the transistor 301 or the first terminal of the transistor 301 may be connected to the wiring 117, as in Fig. 17A.

Further, as shown in Fig. 17B, the transistor 306 and the transistor 307 can be newly added. As an example, the transistor 306 and the transistor 307 are often of the same polarity as the transistor 301 to the transistor 305, and are of the N-channel type. The first terminal of the transistor 306 is connected to the wiring 116. The second terminal of the transistor 306 is connected to the node A and the gate of the transistor 306 is connected to the wiring 118. [ The first terminal of the transistor 307 is connected to the wiring 116. The second terminal of the transistor 307 is connected to the wiring 111. The gate of the transistor 307 is connected to the wiring 118. [ The signal IN5 is inputted as an example to the wiring 118, and the wiring 118 can function as a signal line. The transistor 306 has a function of controlling the timing at which the voltage V1 is supplied to the node A by controlling the conduction state of the wiring 116 and the node A in accordance with the signal IN5 or the potential of the wiring 115, It can function as a switch. The transistor 307 controls the conduction state between the wiring 116 and the wiring 111 in accordance with the signal IN5 or the potential of the wiring 115 to thereby control the timing at which the voltage V1 is supplied to the wiring 111 And can function as a switch. The signal IN5 often functions as a front-end reset signal as an example. However, the present invention is not limited to this, and only one of the transistor 306 and the transistor 307 can be newly added.

14A to FIG. 17A, the transistor 306 and / or the transistor 307 can be newly added as in FIG. 17B. The first terminal of the transistor 306 is connected to the wiring 116. The second terminal of the transistor 306 is connected to the node A and the gate of the transistor 306 is connected to the wiring 118. [ The first terminal of the transistor 307 is connected to the wiring 116. The second terminal of the transistor 307 is connected to the wiring 111. The gate of the transistor 307 is connected to the wiring 118. [

Further, as shown in Fig. 17C, a P-channel transistor can be used as the transistor 301 to the transistor 305. Fig. Particularly, when a P-channel transistor is used as the transistor 101 to the transistor 103 described in Embodiment Mode 1 and the transistor 201 to the transistor 204 described in Embodiment Mode 2, It is preferable to use a P-channel transistor as the transistor 305. [ The transistor 301p, the transistor 302p, the transistor 303p, the transistor 304p and the transistor 305p are connected to the transistor 301, the transistor 302, the transistor 303, the transistor 304, 305).

14A to FIG. 17B, a P-channel transistor can be used as the transistor 301 to the transistor 305. As shown in FIG.

Further, as already described, the circuit 105 described in the present embodiment can be used for the circuit 105 included in the circuit 100 described in the first embodiment. Fig. 18A shows a configuration in which an example of the circuit 105 shown in Fig. 12A is used as the circuit 105 included in the circuit 100 shown in Fig. 1A as an example. 12A is used as the circuit 105 included in the circuit 100 shown in Fig. 1A and the circuit 104 included in the circuit 100 shown in Fig. 1A is used as an example, FIG. 9A shows a configuration in which an example of the circuit 104 of FIG. 9A is used. However, the present invention is not limited to this, and the circuit 100 in the case of Fig. 12A, Fig. 14A to Fig. 17C, or the circuit 105 in the case of combining them is shown in Figs. 1A, 5A to 7B, The circuit 105 can be used.

(Fourth Embodiment)

In the present embodiment, an example of a shift register will be described. The shift register of the present embodiment can have the semiconductor devices of the first to third embodiments. The shift register may be a semiconductor device or a gate driver. In addition, the description of the first to third embodiments will not be repeated. The contents described in Embodiment Modes 1 to 3 can be freely combined with the contents described in this embodiment mode.

First, an example of a shift register will be described with reference to Fig. The shift register 400 has a plurality of flip-flops called flip-flops 401_1 to 401_N (N is a natural number).

The flip-flops 401_1 to 401_N correspond to the semiconductor devices described in Embodiments 1 to 3, respectively. One example of Fig. 19 shows a case where the semiconductor device of Fig. 1A is used as the flip-flops 401_1 to 401_N. However, the present invention is not limited thereto. As the flip-flops 401_1 to 401_N, semiconductor devices described in Embodiment Modes 1 to 3, or various other semiconductor devices or circuits other than the semiconductor device shown in Fig. 1A can be used.

Next, the connection relationship of the shift registers will be described. The shift register 400 is connected to the wirings 411_1 to 411_N, the wirings 412, 413, 414, and 415. The wiring 111 is connected to the wiring 411_i and the wiring 112 is connected to one of the wiring 412 and the wiring 413 The wiring 113 is connected to the other of the wiring 412 and the wiring 413 and the wiring 114 is connected to the wiring 411_i-1 and the wiring 115 is connected to the wiring 411_i + 1, And the wiring 116 is connected to the wiring 416. [ Here, when the flip-flops of the odd-numbered stages and the flip-flops of the even-numbered stages are compared, the places where the wirings 112 and the wirings 113 are connected are often opposite. For example, when the wiring 112 is connected to the wiring 412 and the wiring 113 is connected to the wiring 413 in the odd-numbered flip-flop, in the even-numbered flip-flop, Is connected to the wiring 413 and the wiring 113 is connected to the wiring 412 in many cases. On the other hand, in the even-numbered stage flip-flop, when the wiring 112 is connected to the wiring 413 and the wiring 113 is connected to the wiring 412, It is often connected to the wiring 412, and the wiring 113 is connected to the wiring 413 in many cases. However, the present invention is not limited to this, and various other connection configurations can be used.

Further, in the flip-flop 401_1, the wiring 114 is often connected to the wiring 414. In the flip-flop 401_N, the wiring 115 is often connected to the wiring 415 in many cases.

The wirings 411_1 to 411_N correspond to the wirings 111 described in Embodiments 1 to 3, respectively. The wiring 412 corresponds to the wiring 112 or the wiring 113 described in the first to third embodiments. The wiring 413 corresponds to the wiring 112 or the wiring 113 described in the first to third embodiments. The wiring 414 corresponds to the wiring 114 described in the first to third embodiments. The wiring 415 corresponds to the wiring 115 described in the first to third embodiments. The wiring 416 corresponds to the wiring 116 described in the first to third embodiments.

Next, examples of signals or voltages input to or output from the wirings 411_1 to 411_N, the wirings 412, 413, 414, 415 and 416 will be described. As an example, the signals GOUT_1 to GOUT_N are output from the wirings 411_1 to 411_N, respectively. The signals GOUT_1 to GOUT_N are output signals of the flip-flops 401_1 to 401_N, respectively. The signals GOUT_1 to GOUT_N correspond to the signals OUT described in Embodiments 1 to 3 and serve as an output signal, a selection signal, a transmission signal, a start signal, a reset signal, a gate signal, can do. The signal GCK is inputted to the wiring 412 as an example. The signal GCK can function as a clock signal corresponding to the signal IN1 or the signal IN2 described in the first to third embodiments. The signal GCKB is input to the wiring 413 as an example. The signal GCKB corresponds to the signal IN1 or the signal IN2 described in the first to third embodiments and can function as an inverted clock signal. A signal GSP is inputted to the wiring 414 as an example. The signal GSP corresponds to the signal IN3 described in the first to third embodiments and can function as a start signal or a vertical synchronizing signal. The signal GRE is input to the wiring 415 as an example. The signal GRE can function as a reset signal in response to the signal IN4 described in the first to third embodiments. The voltage V1 is inputted to the wiring 416 as an example. However, the present invention is not limited to this, and various signals, various currents, and the like may be added to the wirings 411_1 to 411_N, the wirings 412, 413, 414, 415 and / , Various voltages can be input. A voltage such as a voltage V1 or a voltage V2 may be supplied to the wiring 412, the wiring 413, the wiring 414, and / or the wiring 415, for example. Alternatively, a signal such as signals GOUT_1 to GOUT_N, a signal GCK, a signal GCKB, a signal GSP, or a signal GRE may be input to the wiring 416. [ Alternatively, signals or voltages may not be input to the wirings 411_1 to 411_N, wirings 412, 413, 414, 415 and / or 416, It can be put in a floating state.

Further, the wirings 411_1 to 411_N can function as a signal line, a gate line, a scanning line, or an output signal line. The wiring 412 can function as a signal line or a clock signal line. The wiring 413 can function as a signal line or a clock signal line. The wiring 414 can function as a signal line. The wiring 415 can function as a signal line. The wiring 416 can function as a power supply line or a ground line. The wirings 411_1 to 411_N, the wirings 412, the wirings 413, the wirings 414, the wirings 415 and / or the wirings 416 function as various wirings in addition to the wirings 411_1 to 411_N, can do. For example, when a voltage is supplied to the wiring 412, the wiring 413, the wiring 414, and / or the wiring 415, these wirings can function as a power source line. Alternatively, when a signal is input to the wiring 416, the wiring 416 can function as a signal line.

As described above, a multi-phase clock signal or an unbalanced clock signal can be input to the shift register.

A signal or a voltage is input to the wiring 412, the wiring 413, the wiring 414, the wiring 415, and the wiring 416 from the circuit 420. The circuit 420 has a function of controlling the shift register 400 by supplying a signal or a voltage to the shift register 400 and can function as a control circuit or a controller. In the present embodiment, as an example, the circuit 420 is provided with a signal GCK, a signal GCKB, and a signal GCK to the wiring 412, the wiring 413, the wiring 414, the wiring 415, and the wiring 416, (GSP), a signal (GRE), and a voltage V1. However, the present invention is not limited to this, and the circuit 420 may supply a signal or a voltage to various circuits (for example, a signal line driver circuit, a scanning line driver circuit, and / or a pixel) in addition to the shift register 400 So that these circuits can be controlled.

In addition, the circuit 420 has a circuit 421 and a circuit 422 as an example. The circuit 421 has a function of generating a power supply voltage such as a constant voltage, a non-voltage, a ground voltage, and a reference voltage, and can function as a power supply circuit or a regulator. The circuit 422 has a function of generating various signals such as a clock signal, an inverted clock signal, a start signal, a reset signal, and / or a video signal, and can function as a timing generator. However, the present invention is not limited to this, and the circuit 420 may have various circuits or various elements in addition to the circuit 421 and the circuit 422. [ For example, the circuit 420 may be an oscillator, a level shift circuit, an inverter circuit, a buffer circuit, a DA conversion circuit, an AD conversion circuit, an OP amplifier, a shift register, a look up table, A capacitor, a resistance element, and / or a frequency divider.

Next, the operation of the shift register of Fig. 19 will be described with reference to the timing chart of Fig. 20 is an example of a timing chart for explaining the operation of the shift register. 20 shows a signal (GSP), a signal GRE, a signal GCK, a signal GCKB, a signal GOUT_1, a signal GOUT_i-1, a signal GOUT_i, a signal GOUT_i + GOUT_N). The same reference numerals as those of the semiconductor device according to the first embodiment through the third embodiment are not described.

The operation of the flip-flop 401_i will be described. First, the signal GOUT_i-1 becomes H level. Then, the flip-flop 401_i starts the operation in the period T1 and the signal GOUT_i becomes L level. Thereafter, the signal GCK and the signal GCKB are inverted. Then, the flip-flop 401_i starts the operation in the period T2 and the signal GOUT_i becomes the H level. The signal GOUT_i is input to the flip-flop 401_i-1 as a reset signal and is also input to the flip-flop 401_i + 1 as a start signal. Therefore, the flip-flop 401_i-1 starts the operation in the period T3, and the flip-flop 401_i + 1 starts the operation in the period T1. Thereafter, the signal GCK and the signal GCKB are inverted again. Then, the flip-flop 401_i + 1 starts the operation in the period T2 and the signal GOUT_i + 1 becomes the H level. The signal GOUT_i + 1 is input to the flip-flop 401_i as a reset signal. Therefore, since the flip-flop 401_i starts the operation in the period T3, the signal GOUT_i becomes the L level. Thereafter, until the signal GOUT_i-1 returns to the H level, the flip-flop 401_i performs the operation in the period T4 every time the signal GCK and the signal GCKB are inverted, Repeat the operation.

Further, in the flip-flop 401_1, the signal GSP is input from the circuit 420 via the wiring 414 instead of the output signal of the flip-flop at the preceding stage. Therefore, when the signal GSP becomes H level, the flip-flop 401_1 starts the operation in the period T1.

Further, in the flip-flop 401_N, the signal GRE is input from the circuit 420 via the wiring 415 instead of the output signal of the flip-flop at the next stage. Therefore, when the signal GRE becomes the H level, the flip-flop 401_N starts the operation in the period T3.

The operation of the shift register of the present embodiment has been described above. The shift register of the present embodiment can obtain the same advantages as the semiconductor device described above by using the semiconductor devices of the first to third embodiments.

Further, as described in Embodiments 1 to 3, the relationship between the signal GCK and the signal GCKB can be non-equilibrium. For example, as shown in the timing chart of Fig. 21A, the period of the signal GCK and the period of the signal GCKB may be shorter than the period of the L level. By doing so, it is possible to prevent a period in which the signals GOUT_1 to GOUT_N become H level even if delay or distortion occurs in the signals GOUT_1 to GOUT_N. Therefore, when the shift register of the present embodiment is used in a display device, it prevents a plurality of rows from being selected at the same time. However, the present invention is not limited to this, and it is possible to make the period of the signal GCK and / or the signal GCKB higher than the period of the L level.

Further, as described in Embodiments 1 to 3, a multi-phase clock signal can be used. For example, as shown in the timing chart of Fig. 21B, a clock signal of M phase (M is a natural number) can be used. In this case, the period in which the signals GOUT_1 to GOUT_N are at the H level at any stage can be overlapped with the period at which the signals GOUT_1 to GOUT_N are at the H level at the stages before and after the signal. Therefore, when the present embodiment is used in a display device, a plurality of rows are simultaneously selected. This makes it possible to use the video signal to the pixels of the other row as the pre-charge voltage.

In Fig. 21B, M? 8 is preferable. More preferably, M? 6. More preferably, M? 4. This is because, when the shift register is used in the scanning line driving circuit of the display device, if M is excessively large, a plurality of kinds of video signals are recorded in the pixel. This is because the period during which an erroneous video signal is input to the pixel becomes longer, and the display quality may decrease.

Also in the timing chart of Fig. 21A, as in Fig. 21B, a multi-phase clock signal can be used.

Further, the wiring 415 may be shared with other wiring or may be omitted. For example, the wiring 415 can be shared with the wiring 412, the wiring 413, the wiring 414, or the wiring 416. In this case, the wiring 415 is omitted, and the wiring 115 can be connected to the wiring 412, the wiring 413, the wiring 414, or the wiring 416 in the flip-flop 401_N. As another example, the wiring 415 can be omitted. In this case, in the flip-flop 401_N, the transistor 303 and the transistor 304 included in the circuit 105 can be omitted as in Fig. 14B.

Depending on the configuration of the flip-flops 401_1 to 401_N, a new wiring can be added. For example, as shown in Fig. 17A or 17B, when a voltage V2 or a signal capable of functioning as a full-stage reset signal is required, a new wiring can be added. A signal, a voltage, or the like can be supplied from the circuit 420 to the newly added wiring.

It is also possible to add transistors 431 to the flip-flops 401_1 to 401_N, respectively, as shown in Fig. The polarity of the transistor 431 is preferably the same as the polarity of the transistor 101, and is often of the N-channel type. However, the present invention is not limited to this, and the transistor 431 may be of the P-channel type. In the flip-flop 401_i, the first terminal of the transistor 431 is connected to the wiring 112, the second terminal of the transistor 431 is connected to the wiring 417_i, A. In the flip-flop 401_i, the wiring 111 is connected to the wiring 411_i, the wiring 112 is connected to one of the wiring 412 and the wiring 413, and the wiring 113 is connected to the wiring 411_i. The wiring 114 is connected to the wiring 417_i-1; the wiring 115 is connected to the wiring 411_i + 1; the wiring 116 is connected to the wiring 417_i-1; (416). Thus, even when a load such as a pixel or a gate line is connected to the wirings 411_1 to 411_N, no distortion or delay occurs in the transmission signal for driving the flip-flop at the next stage. Therefore, the influence of the delay of the shift register can be reduced. However, the present invention is not limited to this, and the wiring 114 may be connected to the wiring 411_i-1. Alternatively, the wiring 115 may be connected to the wiring 417_i + 1. Alternatively, a transistor for holding the potential of the wirings 417_1 to 417_N at V1 can be newly added.

Also in FIG. 22, the signal GCK and the signal GCKB can be made non-balanced similarly to FIG. 21A. Alternatively, as in Fig. 21B, a multi-phase clock signal can be used.

(Embodiment 5)

In the present embodiment, an example of a display device will be described.

First, an example of a system block of the liquid crystal display device will be described with reference to FIG. 23A. The liquid crystal display device has a circuit 5361, a circuit 5362, a circuit 5363_1, a circuit 5363_2, a pixel portion 5364, a circuit 5365, and a lighting device 5366. A plurality of wirings 5371 extend from the circuit 5362 and a plurality of wirings 5372 extend from the circuit 5363_1 and the circuit 5363_2 in the pixel portion 5364. [ Pixels 5367 each having a display element such as a liquid crystal element are arranged in a matrix in a crossing region of a plurality of wirings 5371 and a plurality of wirings 5372. [

The circuit 5361 has a function of supplying a signal, a voltage, a current, or the like to the circuit 5362, the circuit 5363_1, the circuit 5363_2, and the circuit 5365 in accordance with the video signal 5360, A control circuit, a timing generator, a power supply circuit, or a regulator. In the present embodiment, as an example, the circuit 5361 is connected to the circuit 5362 with a signal line driving circuit start signal SSP, a signal line driving circuit clock signal SCK, a signal line driving circuit inverting clock signal SCKB, Data (DATA), and a latch signal (LAT). Alternatively, the circuit 5361 is connected to the circuit 5363_1 and the circuit 5363_2 by way of example, the start signal GSP for the scanning line driving circuit, the clock signal GCK for the scanning line driving circuit, (GCKB). Alternatively, the circuit 5361 supplies the backlight control signal BLC to the circuit 5365. The circuit 5361 can supply various signals, various voltages, or various currents to the circuit 5362, the circuit 5363_1, the circuit 5363_2, and the circuit 5365 .

The circuit 5362 has a function of outputting a video signal to the plurality of wirings 5371 in accordance with a signal (for example, SSP, SCK, SCKB, DATA, LAT) supplied from the circuit 5361, It can function as a circuit. The circuit 5363_1 and the circuit 5363_2 have a function of outputting the scanning signal to the plurality of wirings 5372 in accordance with the signals GSP, GCK, GCKB supplied from the circuit 5361, can do. The circuit 5365 controls the luminance (or the average luminance) of the illuminator 5366 by controlling the amount of power supplied to the illuminator 5366 or the time etc. according to the signal BLC supplied from the circuit 5361. [ And can function as a power supply circuit.

When a video signal is input to the plurality of wirings 5371, the plurality of wirings 5371 can function as a signal line, a video signal line, or a source line. When a scanning signal is input to the plurality of wirings 5372, the plurality of wirings 5372 can function as a signal line, a scanning line, a gate line, or the like. However, the present invention is not limited to this.

When the same signal is inputted from the circuit 5361 to the circuit 5363_1 and the circuit 5363_2, the scanning signal outputted from the circuit 5363_1 to the plurality of wirings 5372 and the circuit 5363_2 are outputted from the wiring 5372 5372 are often at substantially the same timing. Therefore, the load on which the circuit 5363_1 and the circuit 5363_2 are driven can be reduced. Therefore, the display device can be made larger. Alternatively, the display device can be fixed and lengthwise. Alternatively, since the channel width of the transistor included in the circuit 5363_1 and the circuit 5363_2 can be reduced, a display device of a narrow frame can be obtained. However, the present invention is not limited to this, and the circuit 5361 can supply different signals to the circuit 5363_1 and the circuit 5363_2.

In addition, one of the circuit 5363_1 and the circuit 5363_2 can be omitted.

Further, wirings such as a capacitor line, a power supply line, and a scanning line can be newly arranged in the pixel portion 5364. [ Then, the circuit 5361 can output a signal, a voltage, or the like to these wirings. Alternatively, a circuit such as the circuit 5363_1 and the circuit 5363_2 is newly added, and this newly added circuit can output a signal such as a scanning signal to the newly added wiring.

Further, the pixel 5367 may have a light emitting element such as an EL element as a display element. In this case, as shown in Fig. 23B, since the display element can emit light, the circuit 5365 and the illumination device 5366 can be omitted. In order to supply power to the display element, a plurality of wirings 5373 capable of functioning as a power source line can be disposed in the pixel portion 5364. [ The circuit 5361 can supply the power supply voltage of the voltage ANO to the wiring 5373. [ These wirings 5373 can be connected for each color element of the pixel, and can be connected in common to all the pixels.

In Fig. 23B, as an example, the circuit 5361 shows an example in which different signals are supplied to the circuit 5363_1 and the circuit 5363_2. The circuit 5361 supplies the circuit 5363_1 with signals such as the scanning line driving circuit start signal GSP1, the scanning line driving circuit clock signal GCK1 and the inverted scanning line driving circuit clock signal GCKB1. The circuit 5361 supplies the circuit 5363_2 with signals such as the scanning line driving circuit start signal GSP2, the scanning line driving circuit clock signal GCK2 and the inverted scanning line driving circuit clock signal GCKB2. In this case, the circuit 5363_1 scans only the odd-numbered lines of the plurality of wirings 5372, and the circuit 5363_2 can scan only the wirings of the even-numbered lines among the plurality of wirings 5372. [ Therefore, since the driving frequency of the circuit 5363_1 and the circuit 5363_2 can be reduced, the power consumption can be reduced. Alternatively, the area in which the flip-flops for one stage can be laid out can be increased. Therefore, the display device can be fixed and lengthwise. Alternatively, the display device can be made large. However, the present invention is not limited to this, and similarly to Fig. 23A, the circuit 5361 can output the same signal to the circuit 5363_1 and the circuit 5363_2.

Similarly to Fig. 23B, in Fig. 23A, the circuit 5361 can supply different signals to the circuit 5363_1 and the circuit 5363_2.

An example of the system block of the display device has been described above.

Next, an example of the configuration of the display device will be described with reference to Figs. 24A to 24E.

24A, a circuit (e.g., circuit 5362, circuit 5363_1, and circuit 5363_2) having a function of outputting a signal to the pixel portion 5364 is connected to a substrate 5380. Then, the circuit 5361 is formed on a substrate different from the pixel portion 5364. As described above, since the number of external components is reduced, the cost can be reduced. Alternatively, since the number of signals or voltages input to the substrate 5380 is reduced, the number of connections between the substrate 5380 and external components can be reduced. Therefore, the reliability can be improved or the yield can be improved.

When a circuit is formed on a substrate other than the pixel portion 5364, the substrate may be mounted on an FPC (Flexible Printed Circuit) by a TAB (Tape Automated Bonding) method. Alternatively, the substrate may be mounted on a substrate 5380 such as a pixel portion 5364 by a COG (Chip On Glass) method.

Further, when a circuit is formed on a substrate other than the pixel portion 5364, a transistor using a single crystal semiconductor can be formed on the substrate. Therefore, the circuit formed on the substrate can obtain advantages such as improvement of the driving frequency, improvement of the driving voltage, and reduction of deviation of the output signal.

Further, in many cases, a signal, a voltage, a current, or the like is input from the external circuit through the input terminal 5381.

24B, circuits (for example, circuit 5363_1 and circuit 5363_2) having low driving frequencies are formed on a substrate 5380 such as the pixel portion 5364. [ The circuit 5361 and the circuit 5362 are formed on a substrate different from the pixel portion 5364. Thereby, a circuit formed on the substrate 5380 can be constituted by the transistor having a small mobility. Therefore, a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used as the semiconductor layer of the transistor. Therefore, it is possible to increase the size of the display device, reduce the number of process steps, reduce the cost, or improve the yield.

24C, a part (circuit 5362a) of the circuit 5362 is formed on a substrate 5380 such as the pixel portion 5364, and the remaining circuit 5362 (circuit 5362b) And may be formed on a substrate different from the pixel portion 5364. Circuit 5362a often has a circuit (e.g., a shift register, a selector, a switch, etc.) that can be configured by a transistor with low mobility. The circuit 5362b has a circuit (for example, a shift register, a latch circuit, a buffer circuit, a DA conversion circuit, an AD conversion circuit, and the like) which is preferable to be constituted by transistors having high mobility and small characteristic deviation There are many cases. By doing so, a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used as the semiconductor layer of the transistor as in FIG. 24B, and the external components can be reduced.

24D shows a circuit having a function of outputting a signal to the pixel portion 5364 (for example, a circuit 5362, a circuit 5363_1, and a circuit 5363_2), and a circuit having a function of controlling these circuits A circuit (e.g., circuit 5361) is formed on a substrate other than the pixel portion 5364. [ As a result, the pixel portion and its peripheral circuits can be formed on different substrates, thereby improving the yield.

24A to 24C, the circuit 5363_1 and the circuit 5363_2 can be formed on a substrate different from the pixel portion 5364 in the same manner as in Fig. 24D.

(Circuit 5361a) of the circuit 5361 is formed on the same substrate 5380 as the pixel portion 5364 and the remaining circuit 5361 (circuit 5361b) is formed on the pixel portion 5364 And is formed on another substrate. The circuit 5361a often has a circuit (for example, a switch, a selector, a level shift circuit, etc.) which can be configured by a transistor having a small mobility. The circuit 5361b often has a circuit (for example, a shift register, a timing generator, an oscillator, a regulator, or an analog buffer) which is desired to be constructed using a transistor having a high degree of mobility and a small deviation.

24A to 24D, the circuit 5361a may be formed on a substrate such as the pixel portion 5364, and the circuit 5361b may be formed on a substrate different from the pixel portion 5364. [

The display device of the present embodiment has been described above. As the circuit 5363_1 and the circuit 5363_2, it is possible to use the semiconductor devices or the shift registers of the first to fourth embodiments. In this case, since the circuits 5363_1 and 5363_2 and the pixel portion are formed on the same substrate, the polarity of all the transistors formed on the substrate can be N-channel type or P-channel type. Therefore, it is possible to reduce the number of processes, improve the yield, improve the reliability, or reduce the cost. Particularly, when the polarity of all the transistors is of the N-channel type, a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used as the semiconductor layer of the transistor. Therefore, it is possible to increase the size of the display device, reduce the cost, or improve the yield.

In a transistor using a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor or the like as a semiconductor layer, characteristic deterioration such as an increase in threshold voltage or a decrease in mobility often occurs. However, since the semiconductor device or the shift register according to the first to fourth embodiments can suppress deterioration of characteristics of the transistor, the lifetime of the display device can be prolonged.

As a part of the circuit 5362, the semiconductor devices of the first to fourth embodiments or the shift register can be used. For example, the circuit 5362a may have a semiconductor device or shift register according to the fourth embodiment.

(Embodiment 6)

In the present embodiment, an example of the signal line driver circuit will be described. Further, the signal line driver circuit may be referred to as a semiconductor device or a signal generator circuit.

An example of the signal line driver circuit will be described with reference to Fig. 25A. The signal line driver circuit has a plurality of circuits, that is, circuits 502_1 to 502_N (N is a natural number), a circuit 500, and a circuit 501. The circuits 502_1 to 502_N have a plurality of transistors each of which is a transistor 503_1 to 503_k (k is a natural number). The transistors 503_1 to 503_k are of the N channel type. However, the present invention is not limited to this, and the transistors 503_1 to 503_k may be P-channel type and CMOS type switches.

The connection relationship of the signal line driver circuit will be described taking the circuit 502_1 as an example. The first terminals of the transistors 503_1 to 503_k are connected to the wiring 505_1. The second terminals of the transistors 503_1 to 503_k are connected to the wirings S1 to Sk, respectively. The gates of the transistors 503_1 to 503_k are connected to the wirings 504_1 to 504_k, respectively. For example, the first terminal of the transistor 503_1 is connected to the wiring 505_1, the second terminal of the transistor 503_1 is connected to the wiring S1, and the gate of the transistor 503_1 is connected to the wiring 504_1.

The circuit 500 has a function of supplying signals to the circuits 502_1 to 502_N via the wirings 504_1 to 504_k and can function as a shift register or a decoder. The signal is often a digital signal and can function as a selection signal. The wirings 504_1 to 504_k can function as signal lines.

The circuit 501 has a function of outputting signals to the circuits 502_1 to 502_N and can function as a video signal generation circuit and the like. For example, the circuit 501 supplies a signal to the circuit 502_1 via the wiring 505_1. Simultaneously, a signal is supplied to the circuit 502_2 through the wiring 502_2. The signal is often an analog signal and can function as a video signal. The wirings 505_1 to 505_N can function as signal lines.

The circuits 502_1 to 502_N have a function of selecting to which wiring to output the output signal of the circuit 501 and can function as a selector circuit. For example, the circuit 502_1 has a function of selecting which of the wirings S1 to Sk outputs the signal that the circuit 501 outputs to the wiring 505_1.

The transistors 503_1 to 503_k each have a function of controlling the conduction state of the wiring 505_1 and the wirings S1 to Sk according to the output signal of the circuit 500 and function as a switch.

Next, the operation of the signal line driver circuit of Fig. 25A will be described with reference to the timing chart of Fig. 25B. 25B shows a signal 514_2 input to the wiring 504_1 and input to the wiring 504_2 and a signal 514_2 input to the wiring 505_1 input to the signal 514_k input to the wiring 504_k 515_1, and the signal 515_2 input to the wiring 505_2.

Further, one operation period of the signal line driver circuit corresponds to one gate selection period in the display device. One gate selection period is a period in which a pixel belonging to a certain row is selected and a video signal can be written to the pixel.

Also, one gate selection period is divided into a period T0, a period T1, and a period Tk. The period T0 is a period for simultaneously applying the pre-charge voltage to the pixels belonging to the selected row, and can function as a pre-charge period. Periods T1 to Tk are periods for recording video signals in the pixels belonging to the selected row, respectively, and can function as recording periods.

For the sake of convenience, the operation of the signal line driver circuit will be described taking the operation of the circuit 502_1 as an example.

First, in the period T0, the circuit 500 outputs a high-level signal to the wirings 504_1 to 504_k. Then, since the transistors 503_1 to 503_k are turned on, the wiring 505_1 and the wiring S1 to the wiring Sk become conductive. At this time, since the circuit 501 supplies the precharge voltage Vp to the wiring 505_1, the precharge voltage Vp is output to the wirings S1 through Sk through the transistors 503_1 through 503_k do. Since the precharge voltage Vp is written to the pixels belonging to the selected row, the pixels belonging to the selected row are precharged.

Next, in the period T1, the circuit 500 outputs a signal of H level to the wiring 504_1. Then, since the transistor 503_1 is turned on, the wiring 505_1 and the wiring S1 become conductive. Then, the wiring 505_1 and the wiring S2 and the wiring Sk become non-conductive. At this time, assuming that the circuit 501 outputs the signal Data (S1) to the wiring 505_1, the signal Data (S1) is outputted to the wiring S1 via the transistor 503_1. Thus, the signal Data (S1) is written to the pixel belonging to the selected row among the pixels connected to the wiring S1.

Next, in the period T2, the circuit 500 outputs a signal of the H level to the wiring 504_2. Then, since the transistor 503_2 is turned on, the wiring 505_2 and the wiring S2 become conductive. Then, the wiring 505_1 and the wiring S1 become non-conductive, and the wiring 505_1 and the wiring S3 and the wiring Sk continue to be non-conductive. At this time, assuming that the circuit 501 outputs the signal Data (S2) to the wiring 505_1, the signal Data (S2) is outputted to the wiring S2 via the transistor 503_2. Thus, the signal Data (S2) is written to the pixel belonging to the selected row among the pixels connected to the wiring S2.

Thereafter, the circuit 500 sequentially outputs signals of H level to the wirings 504_1 to 504_k until the period Tk, so that the circuit 500 is operated from the period T3 to the period Tk in the same manner as the periods T1 and T2. Level signals to the wiring 504_3 to the wiring 504_k in sequence. Therefore, the transistors 503_1 to 503_k sequentially turn on. Therefore, the signal output from the circuit 501 is sequentially output to the wirings S1 through Sk. Thereby, the signals can be sequentially recorded in the pixels belonging to the selected row.

An example of the signal line driver circuit has been described above. Since the signal line driver circuit of this embodiment has a circuit functioning as a selector, the number of signals or the number of wirings can be reduced. Alternatively, the voltage for precharging is written to the pixel before the video signal is written to the pixel (period T0), so that the recording time of the video signal can be shortened. Therefore, the size of the display device can be increased and the display device can be made more flexible. However, the present invention is not limited to this, and the period T0 may be omitted and the pixel may not be precharged.

In addition, if k is too large, the recording time to the pixel becomes shorter, so that there is a case where recording of the video signal in the pixel does not end in time. Therefore, it is preferable that k &amp;le; 6. More preferably, k? 3 is preferable. More preferably, k = 2 is preferable.

In particular, when the color element of a pixel is divided into n (n is a natural number), k = n can be set. For example, when a color element of a pixel is divided into three colors of red (R), green (G) and blue (B), k = 3 is possible. In this case, one gate selection period is divided into a period T0, a period T1, a period T2, and a period T3. In the periods T1, T2, and T3, video signals can be recorded in the red (R), green (G), and blue (B) pixels, respectively. However, the present invention is not limited to this, and the order of the period T1, the period T2, and the period T3 can be arbitrarily set.

In particular, when the pixel is divided into n (n is a natural number) sub-pixel (hereinafter, also referred to as a sub-pixel or a sub-pixel), k = n. For example, when a pixel is divided into two sub-pixels, it is possible that k = 2. In this case, one gate selection period is divided into a period T0, a period T1, and a period T2. In the period T1, a video signal is recorded in one of the two sub-pixels, and in the period T2, a video signal is recorded in the other of the two sub-pixels.

Since the circuit 500 and the driving frequencies of the circuits 502_1 to 502_N are often low, the circuit 500 and the circuits 502_1 to 502_N are formed on the same substrate as the pixel portion . Thereby, the number of connections between the substrate on which the pixel portion is formed and the external circuit can be reduced, so that the yield can be improved or the reliability can be improved. Further, as shown in Fig. 24C, the scanning line driving circuit is also formed on the same substrate as the pixel portion, so that the number of connections with the external circuit can be further reduced.

As the circuit 500, the semiconductor device or the shift register according to the first embodiment of the present invention can be used. In this case, the polarity of all the transistors of the circuit 500 can be N-channel type or P-channel type. Therefore, it is possible to reduce the number of steps, improve the yield, or reduce the cost.

Not only the circuit 500 but also the polarities of all the transistors of the circuits 502_1 to 502_N can be of N-channel type or P-channel type. Therefore, when the circuit 500 and the circuits 502_1 to 502_N are formed on a substrate such as a pixel portion, it is possible to reduce the number of steps, improve the yield, and reduce the cost. In particular, a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used as the semiconductor layer of the transistor by making the polarity of all the transistors be of the N channel type. This is because the driving frequencies of the circuit 500 and the circuits 502_1 to 502_N are often low.

(Seventh Embodiment)

In the present embodiment, the configuration of a pixel applicable to a liquid crystal display device and the operation of a pixel will be described.

26A shows an example of a pixel. The pixel 5420 has a transistor 5421, a liquid crystal element 5422, and a capacitor element 5423. The first terminal of the transistor 5421 is connected to the wiring 5431 and the second terminal of the transistor 5421 is connected to one electrode of the liquid crystal element 5422 and one electrode of the capacitor element 5423 And the gate of the transistor 5421 is connected to the wiring 5432. The other electrode of the liquid crystal element 5422 is connected to the electrode 5434 and the other electrode of the capacitance element 5423 is connected to the wiring 5433.

As an example, a video signal can be input to the wiring 5431. [ As an example, a scanning signal, a selection signal, or a gate signal may be input to the wiring 5432. [ The wiring 5433 can be supplied with a constant voltage as an example. As an example, a constant voltage may be supplied to the electrode 5434. However, the present invention is not limited to this, and the precharge voltage is supplied to the wiring 5431, so that the recording time of the video signal can be shortened. Alternatively, by inputting a signal to the wiring 5433, the voltage applied to the liquid crystal element 5422 can be controlled. Or, by inputting a signal to the electrode 5434, frame inversion driving can be realized.

The wiring 5431 can function as a signal line, a video signal line, or a source line. The wiring 5432 can function as a signal line, a scanning line, or a gate line. The wiring 5433 can function as a power supply line or a capacitor line. The electrode 5434 can function as a common electrode or an opposing electrode. However, the present invention is not limited to this, and when a voltage is supplied to the wiring 5431 and the wiring 5432, these wirings can function as a power source line. Alternatively, when a signal is input to the wiring 5433, the wiring 5433 can function as a signal line.

The transistor 5421 has a function of controlling the timing at which a video signal is written to the pixel by controlling the conduction state between the wiring 5431 and one electrode of the liquid crystal element 5422 and can function as a switch. The capacitance element 5423 has a function of maintaining a potential difference between one electrode of the liquid crystal element 5422 and the wiring 5433 and keeping the voltage applied to the liquid crystal element 5422 constant, . However, the present invention is not limited to this.

Fig. 26B shows an example of a timing chart for explaining the operation of the pixel in Fig. 26A. 26B shows a signal 5422_j (j is a natural number), a signal 5442_j + 1, a signal 5441_i (i is a natural number), a signal 5441_i + 1, and a voltage 5442. Fig. 26B shows a k-th frame (k is a natural number) and a (k + 1) -th frame. The signal 5422_j, the signal 5442_j + 1, the signal 5441_i, the signal 5441_i + 1, and the voltage 5442 are signals input to the wiring 5432 in the j-th row, A signal input to the wiring 5431 of the i-th column, a signal input to the wiring 5431 of the (i + 1) th column, and a voltage supplied to the wiring 5432 are examples.

The operation of the pixel 5420 belonging to the j-th row and the i-th column will be described. When the signal 5422_j becomes the H level, the transistor 5421 turns on. The signal 5441_j is input to one electrode of the liquid crystal element 5422 through the transistor 5421 since the wiring 5431 of the i-th column and one of the electrodes of the liquid crystal element 5422 become conductive. The capacitance element 5423 holds a potential difference between the potential of one electrode of the liquid crystal element 5422 and the potential of the wiring 5433 at this time. Therefore, thereafter, the voltage applied to the liquid crystal element 5422 is constant until the signal 5422_j returns to the H level again. The liquid crystal element 5422 expresses the gradation corresponding to the applied voltage.

26B shows an example in which positive and negative polarity signals are alternately input to the wiring 5431 for each row selection period. The positive signal is a signal whose potential is higher than a reference value (for example, the potential of the electrode 5434), and the negative signal is a signal whose potential is lower than a reference value (for example, the potential of the electrode 5434) Signal. However, the present invention is not limited to this, and signals input to the wiring 5431 can have the same polarity during one frame period.

26B shows an example in which the polarity of the signal 5441_i and the polarity of the signal 5441_i + 1 are different from each other. However, the present invention is not limited to this, and the polarity of the signal 5441_i and the polarity of the signal 5441_i + 1 can be the same.

26B shows an example in which the period in which the signal 5442_j becomes the H level and the period in which the signal 5442_j + 1 becomes the H level are not overlapped with each other. However, the present invention is not limited to this. As shown in Fig. 26C, the period in which the signal 5442_j becomes the H level and the period in which the signal 5442_j + 1 becomes the H level can be overlapped. In this case, it is preferable that signals of the same polarity are supplied to the wiring 5431 during one frame period. Thus, the pixel in the (j + 1) th row can be precharged using the signal 5441_j recorded in the j-th pixel. This makes it possible to shorten the time for recording the video signal in the pixel. Therefore, the display device can be fixed and lengthwise. Alternatively, the display portion of the display device can be enlarged. Alternatively, since signals of the same polarity are input to the wiring 5431 in one frame period, power consumption can be reduced.

Further, by combining the pixel configuration in Fig. 27A and the timing chart in Fig. 26C, dot inversion driving can be realized. In the pixel configuration of Fig. 27A, the pixel 5420 (i, j) is connected to the wiring 5431_i. On the other hand, the pixel 5420 (i, j + 1) is connected to the wiring 5431_i + 1. That is, the pixels belonging to the i-th column are alternately connected to the wiring 5431_i and the wiring 5431_i + 1 on a row-by-row basis. As a result, the pixels belonging to the i-th column are alternately recorded with the positive signal and the negative signal for each row, so that the dot inversion driving can be realized. However, the present invention is not limited to this, and the pixels belonging to the i-th column may be alternately connected to the wiring 5431_i and the wiring 5431_i + 1 for a plurality of rows (for example, two rows or three rows).

As the pixel structure, a subpixel structure can be used. 27B and 27C show a configuration in the case of dividing a pixel into two sub-pixels. 27B shows a subpixel structure called 1S + 2G, and FIG. 27C shows a subpixel structure called 2S + 1G. The sub-pixel 5420A and the sub-pixel 5420B correspond to the pixel 5420. [ The transistor 5421A and the transistor 5421B correspond to the transistor 5421. [ The liquid crystal element 5422A and the liquid crystal element 5422B correspond to the liquid crystal element 5422. [ The capacitor element 5423A and the capacitor element 5423B correspond to the capacitor element 5423. [ The wiring 5431A and the wiring 5431B correspond to the wiring 5431. [ The wiring 5432A and the wiring 5432B correspond to the wiring 5432. [

The pixel configuration and the pixel driving method of the present embodiment have been described above. Various advantages can be obtained by combining the pixel of the present embodiment with the semiconductor device, the shift register, the display device, or the signal line driver circuit of the first to sixth embodiments. For example, when a sub-pixel structure is used as a pixel, the number of signals required to drive the display device increases. Therefore, the number of gate lines or the number of source lines increases. As a result, the number of connections between the substrate on which the pixel portion is formed and the external circuit may increase significantly. However, as described in Embodiment 5, the scanning line driving circuit can be formed on the same substrate as the pixel portion even if the number of gate lines is increased. Therefore, a pixel of the sub-pixel structure can be used without significantly increasing the number of connections between the substrate on which the pixel portion is formed and the external circuit. Alternatively, even if the number of source lines is increased, the signal line driver circuit described in Embodiment 6 can be formed on the same substrate as the pixel portion. Therefore, it is possible to use the pixel of the sub-pixel structure without significantly increasing the number of connections between the substrate on which the pixel portion is formed and the external circuit.

Alternatively, when a signal is input to the capacitor line, the number of connections between the substrate on which the pixel portion is formed and the external circuit may increase significantly. Thus, the signal can be supplied to the capacitor line by using the semiconductor device or the shift register of the first to fourth embodiments. The semiconductor device or the shift register according to the first to fourth embodiments can be formed on a substrate such as a pixel portion. Therefore, it is possible to input a signal to the capacitor line without significantly increasing the number of connections between the substrate on which the pixel portion is formed and the external circuit.

Alternatively, when AC driving is used, the time for recording a video signal in a pixel is shortened. As a result, there is a case where the time for recording the video signal in the pixel is insufficient. Similarly, when pixels of a sub-pixel structure are used, the time for recording video signals in the pixels becomes short. As a result, there is a case where the time for recording the video signal in the pixel is insufficient. Thus, the video signal can be written to the pixel by using the signal line driver circuit of the sixth embodiment. In this case, since the precharge voltage is written to the pixel before the video signal is written to the pixel, the video signal can be written to the pixel in a short time. Alternatively, as shown in Fig. 21B, by overlapping a period in which a row is selected and a period in which another row is selected, a video signal of another row can be used as the voltage for pre-charging.

(Embodiment 8)

In the present embodiment, an example of the sectional structure of the display device will be described with reference to Figs. 29A to 29C.

29A is an example of a top view of a display device. And a driver circuit 5392 and a pixel portion 5393 are formed on the substrate 5391. [ An example of the driver circuit 5392 is a scanning line driver circuit or a signal line driver circuit.

Fig. 29B shows an example of a cross section taken along line A-B in Fig. 29A. 29B shows a conductive layer 5401 formed on the substrate 5400 and the substrate 5400 and an insulating layer 5402 formed to cover the conductive layer 5401 and a conductive layer 5401 and an insulating layer 5402 A semiconductor layer 5403b formed on the semiconductor layer 5403a and a conductive layer 5404 formed on the semiconductor layer 5403b and on the insulating layer 5402. The semiconductor layer 5403a formed on the semiconductor layer 5403b, A conductive layer 5406 formed on the insulating layer 5402 and on the conductive layer 5404 and formed on the insulating layer 5405 and the opening of the insulating layer 5405, A liquid crystal layer 5407 formed on the insulating layer 5405 and a conductive layer 5404 formed on the liquid crystal layer 5407 and the insulating layer 5408, And a substrate 5410 formed on the conductive layer 5409 and the conductive layer 5409. [

The conductive layer 5401 can function as a gate electrode. The insulating layer 5402 can function as a gate insulating film. The conductive layer 5404 can function as a wiring, an electrode of a transistor, an electrode of a capacitor, or the like. The insulating layer 5405 can function as an interlayer film or a planarizing film. The conductive layer 5406 can function as a wiring, a pixel electrode, or a reflective electrode. The insulating layer 5408 can function as a sealant. The conductive layer 5409 can function as a counter electrode or a common electrode.

Here, a parasitic capacitance may be generated between the driver circuit 5392 and the conductive layer 5409 in some cases. As a result, the output signal of the driving circuit 5392 or the potential of each node is distorted or delayed. Or, the power consumption is increased. 29B, the parasitic capacitance generated between the driver circuit 5392 and the conductive layer 5409 is reduced by forming the insulating layer 5408 capable of functioning as a sealing material on the driver circuit 5392 . This is because the dielectric constant of the seal material is often lower than the dielectric constant of the liquid crystal layer. Therefore, the output signal of the driving circuit 5392 or the distortion or delay of the potential of each node can be reduced. Alternatively, the power consumption of the driving circuit 5392 can be reduced.

Further, as shown in Fig. 29C, an insulating layer 5408 which can function as a sealant can be formed on a part of the drive circuit 5392. [ Even in such a case, since the parasitic capacitance generated between the driver circuit 5392 and the conductive layer 5409 can be reduced, the output signal of the driver circuit 5392 or the distortion or delay of the potential of each node can be reduced . However, the present invention is not limited to this, and it is possible to prevent the insulating layer 5408 functioning as a seal member from being formed on the driver circuit 5392. [

The display element is not limited to a liquid crystal element, and various display elements such as an EL element or an electrophoretic element can be used.

As described above, the present embodiment has described an example of the cross-sectional structure of the display device. This structure can be combined with the semiconductor device or the shift register according to the fourth embodiment of the present invention. For example, when a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used as a semiconductor layer of a transistor, the channel width of the transistor is often large. However, as described in the present embodiment, if the parasitic capacitance of the driving circuit can be reduced, the channel width of the transistor can be reduced. Therefore, since the layout area can be reduced, it is possible to make the display device a narrow frame. Alternatively, the display device can be fixed and lengthwise.

(Embodiment 9)

In the present embodiment, an example of the structure of the transistor will be described with reference to Figs. 30A to 30C.

30A is an example of the structure of a top gate type transistor. 30B is an example of the configuration of the bottom gate type transistor. 30C is an example of a transistor structure fabricated using a semiconductor substrate.

30A shows a substrate 5260, an insulating layer 5261 formed on the substrate 5260, and a plurality of regions 5262a, 5262b, An insulating layer 5263 formed to cover the semiconductor layer 5262 and a conductive layer 5262 formed on the semiconductor layer 5262 and the insulating layer 5263. The semiconductor layer 5262 includes a semiconductor layer 5262, A conductive layer 5264 formed on the insulating layer 5265 and in the opening of the insulating layer 5265; and an insulating layer 5264 formed on the insulating layer 5264 and the conductive layer 5264, An insulating layer 5267 formed on the conductive layer 5266 and the insulating layer 5265 and having an opening and a conductive layer (not shown) formed on the insulating layer 5267 and the opening of the insulating layer 5267 5268 formed on the insulating layer 5269 and on the conductive layer 5268 and formed on the insulating layer 5269 and in the opening of the insulating layer 5269, ), An insulating layer 5269 and a light emitting layer 5270 It shows the conductive layer (5271).

30B shows a structure in which a conductive layer 5301 formed on a substrate 5300 and a substrate 5300 and an insulating layer 5302 formed to cover the conductive layer 5301 and a conductive layer 5301 and an insulating layer 5302 A semiconductor layer 5303b formed on the semiconductor layer 5303a, a conductive layer 5304 formed over the semiconductor layer 5303b and the insulating layer 5302, A conductive layer 5306 formed on the conductive layer 5302 and on the conductive layer 5304 and formed on the insulating layer 5305 and the opening of the insulating layer 5305, A liquid crystal layer 5307 disposed on the liquid crystal layer 5305 and on the conductive layer 5306 and a conductive layer 5308 formed on the liquid crystal layer 5307. [

30C shows a semiconductor substrate 5352 having an area 5353 and an area 5355, an insulating layer 5356 formed on the semiconductor substrate 5352, an insulating layer 5354 formed on the semiconductor substrate 5352, An insulating layer 5358 formed on the insulating layer 5354, the insulating layer 5356, and the conductive layer 5357 and having an opening portion, and a conductive layer 5357 formed on the insulating layer 5356. [ And a conductive layer 5359 formed on the insulating layer 5358 and on the opening of the insulating layer 5358. [ As a result, transistors are formed in the region 5350 and the region 5351, respectively.

The insulating layer 5261 can function as a base film. The insulating layer 5354 functions as a device isolation layer (for example, a field oxide film). The insulating layer 5263, the insulating layer 5302, and the insulating layer 5356 can function as a gate insulating film. The conductive layer 5264, the conductive layer 5301, and the conductive layer 5357 can function as a gate electrode. The insulating layer 5265, the insulating layer 5267, the insulating layer 5305, and the insulating layer 5358 can function as an interlayer film, or a planarizing film. The conductive layer 5266, the conductive layer 5304, and the conductive layer 5359 can function as an electrode of a wiring, a transistor, or an electrode of a capacitor. The conductive layer 5268 and the conductive layer 5306 can function as a pixel electrode, a reflective electrode, or the like. The insulating layer 5269 can function as a bank. The conductive layer 5271 and the conductive layer 5308 can function as counter electrodes, common electrodes, or the like.

Examples of the substrate 5260 and the substrate 5300 include a glass substrate, a quartz substrate, a silicon substrate (or single crystal substrate), an SOI substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel / , A substrate having a tungsten foil, or a flexible substrate. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, and the like. As examples of the flexible substrate, there can be mentioned plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or synthetic resin having flexibility such as acrylic. In addition to this, a paper including a material in the form of a bonded film (polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, etc.), a base film (polyester, polyamide, Etc.).

As the semiconductor substrate 5352, for example, a monocrystalline Si substrate having an n-type or p-type conductivity type can be used. However, the present invention is not limited to this, and the same substrate 5260 can be used. The region 5353 is, for example, a region in which impurities are added to the semiconductor substrate 5352 and functions as a well. For example, when the semiconductor substrate 5352 has a p-type conductivity type, the region 5353 has an n-type conductivity type and functions as an n-well. On the other hand, when the semiconductor substrate 5352 has an n-type conductivity, the region 5353 has a p-type conductivity type and functions as a p-well. The region 5355 is, for example, an area in which impurities are added to the semiconductor substrate 5352 and functions as a source region and a drain region. Further, an LDD region can be formed in the semiconductor substrate 5352. [

Examples of the insulating layer 5261 include silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxynitride (SiO _x N _y ) (x> y), silicon nitride oxide (SiN _x O _y ) y) or the like, or a layered structure thereof. As an example of the case where the insulating layer 5261 is formed as a two-layer structure, a silicon nitride film can be formed as a first insulating film and a silicon oxide film can be formed as a second insulating film. As an example of the case where the insulating layer 5261 is formed in a three-layer structure, a silicon oxide film is formed as a first insulating film, a silicon nitride film is formed as a second insulating film, and a silicon oxide film can be formed as a third insulating film have.

As an example of the semiconductor layer 5262, the semiconductor layer 5303a and the semiconductor layer 5303b, a single crystal semiconductor, a compound semiconductor or an oxide semiconductor (such as a ZnO (amorphous silicon), a polycrystalline silicon, , InGaZnO, SiGe, GaAs, IZO, ITO, SnO, TiO, AlZnSnO (AZTO)), an organic semiconductor, or a carbon nanotube.

In addition, for example, the region 5262a is a true state in which no impurity is added to the semiconductor layer 5262, and functions as a channel region. However, the impurity added to the region 5262a can be added to the region 5262a, and the impurity added to the region 5262a can be added to the region 5262b, the region 5262c, the region 5262d, Is lower than the concentration of &lt; RTI ID = 0.0 &gt; The region 5262b and the region 5262d are regions doped with impurities at a low concentration and function as LDD (Lightly Doped Drain: LDD) regions. However, the area 5262b and the area 5262d can be omitted. The region 5262c and the region 5262e are regions where impurities are added to the semiconductor layer 5262 at a high concentration and function as a source region or a drain region.

The semiconductor layer 5303b is a semiconductor layer doped with phosphorus or the like as an impurity element and has an n-type conductivity type.

When an oxide semiconductor or a compound semiconductor is used as the semiconductor layer 5303a, the semiconductor layer 5303b can be omitted.

An insulating layer (5263), insulating layer 5302, and an insulating layer as an example of a (5356), silicon oxide (SiO _x), silicon nitride (SiN _x), silicon oxynitride (SiO _x N _y) (x> y) , Silicon nitride oxide (SiN _x O _y ) (x> y), or a laminated structure of these films.

The conductive layer 5264, the conductive layer 5266, the conductive layer 5268, the conductive layer 5271, the conductive layer 5301, the conductive layer 5304, the conductive layer 5306, the conductive layer 5308, The conductive layer 5357, and the conductive layer 5359 may be a single-layered conductive film, a laminated structure thereof, or the like. Examples of the conductive film include aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni) (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt (Co), niobium (Nb), silicon (Si), iron (Fe), palladium (Sc), zinc (Zn), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), oxygen (O), zirconium , And cerium (Ce), or a compound containing one or more elements selected from the above group. Examples of the compound include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide (ITSO) containing silicon oxide, zinc oxide (ZnO) ), Tin oxide (SnO), cadmium tin oxide (CTO), aluminum neodymium (Al-Nd), aluminum tungsten (Al-Ta), aluminum zirconium (Al-Zr), aluminum titanium Al-Ce), magnesium (Mg-Ag), molybdenum niobium (Mo-Nb), molybdenum tungsten (Mo-W), molybdenum tantalum (Mo- A compound of an element and nitrogen (a nitride film of titanium nitride, tantalum nitride, molybdenum nitride or the like), or a compound of silicon and one or more elements selected from the above-mentioned group (tungsten silicide, titanium silicide, nickel silicide, aluminum silicon, molybdenum silicon, Silicide film). In addition, there are nanotube materials such as carbon nanotubes, organic nanotubes, inorganic nanotubes, or metal nanotubes.

The silicon (Si) may include an n-type impurity (phosphorus or the like), or a p-type impurity (boron or the like).

When copper is used as the conductive layer, it is preferable to use a laminated structure in order to improve the adhesion.

In addition, it is preferable to use molybdenum or titanium for the oxide semiconductor or the conductive layer in contact with silicon.

Further, by using an alloy material of neodymium and aluminum as the conductive layer, it is difficult for aluminum to cause hillocks.

When a semiconductor material such as silicon is used as the conductive layer, a semiconductor material such as silicon can be formed simultaneously with the semiconductor layer having the transistor.

In addition, since ITO, IZO, ITSO, ZnO, Si, SnO, CTO, or carbon nanotubes have light transmittance, these materials can be used for a portion for transmitting light such as a pixel electrode, a counter electrode, have.

Further, by using a low resistance material (for example, aluminum or the like) to have a laminated structure, the resistance of the wiring can be reduced.

In addition, by employing a laminated structure in which a material having a low heat resistance (for example, aluminum or the like) is sandwiched by a material having a high heat resistance (for example, molybdenum, titanium, neodymium or the like) Heat resistance of wiring, electrode, etc. can be increased.

In addition, a material whose properties change in response to other materials can be sandwiched or covered with a material that is difficult to react with the other materials. For example, when ITO and aluminum are connected, a neodymium alloy, titanium, molybdenum, or the like may be sandwiched between ITO and aluminum. For example, when silicon and aluminum are connected, a neodymium alloy, titanium, or molybdenum may be sandwiched between silicon and aluminum. These materials may also be used for wirings, electrodes, conductive layers, conductive films, terminals, vias, plugs, and the like.

As an example of the insulating layer 5265, the insulating layer 5267, the insulating layer 5269, the insulating layer 5305, and the insulating layer 5358, an insulating film having a single-layer structure, or a laminated structure thereof may be used. The As an example of the insulating film, a silicon (SiO _x), silicon nitride (SiN _x), or silicon nitride _{(SiO x N y) (x} > y), silicon nitride oxide silicon (SiN _x O _y) oxide (x> y) A film containing carbon such as DLC (diamond like carbon), or a film containing carbon such as siloxane resin, epoxy, polyimide, polyamide, polyvinyl phenol, benzocyclobutene, or acrylic .

Examples of the light emitting layer 5270 include an organic EL element, an inorganic EL element, and the like. Examples of the organic EL device include a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light emitting layer made of a light emitting material, an electron transport layer made of an electron transport material, an electron injection layer made of an electron injection material, A single layer structure in which a plurality of materials are mixed, or a lamination structure thereof.

An insulating layer functioning as an alignment film, an insulating layer functioning as a projection, and the like can be formed on the insulating layer 5305 and on the conductive layer 5306.

On the conductive layer 5308, a color filter, a black matrix, or an insulating layer functioning as a protrusion can be formed. Under the conductive layer 5308, an insulating layer functioning as an alignment film can be formed.

The insulating layer 5269, the light emitting layer 5270 and the conductive layer 5271 are omitted in the sectional structure of Fig. 30A and the liquid crystal layer 5307 and the conductive layer 5308 shown in Fig. 5267 and on the conductive layer 5268.

30B, the liquid crystal layer 5307 and the conductive layer 5308 are omitted, and the insulating layer 5269, the light emitting layer 5270, and the conductive layer 5271 shown in Fig. (5305) and on the conductive layer (5306).

The insulating layer 5269, the light emitting layer 5270, and the conductive layer 5271 shown in Fig. 30A can be formed on the insulating layer 5358 and the conductive layer 5359 in the sectional structure of Fig. 30C. Alternatively, the liquid crystal layer 5307 and the conductive layer 5308 shown in Fig. 30B can be formed over the insulating layer 5267 and the conductive layer 5268. Fig.

As described above, an example of the transistor structure has been described in the present embodiment. The transistor of the present embodiment is applicable to the first to eighth embodiments. In particular, in FIG. 30B, when a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor or the like is used as the semiconductor layer, the transistor may be deteriorated. However, the semiconductor device, the shift register, or the display device according to the first to eighth embodiments is advantageous in that deterioration of the transistor can be suppressed.

(Embodiment 10)

In the present embodiment, a layout diagram of a shift register (hereinafter also referred to as a top view) will be described. In this embodiment, as an example, a layout diagram of a shift register described in Embodiment 4 will be described. The contents described in the fourth embodiment can be applied to the semiconductor devices, the shift registers, or the display devices of the first to ninth embodiments in addition to the shift registers described in the fourth embodiment . Note that the layout diagram of the present embodiment is merely an example, and it is not limited thereto.

The layout diagram of this embodiment will be described with reference to Figs. 31 and 32. Fig. FIG. 31 shows an example of a layout diagram of a part of the shift register, and FIG. 32 shows a layout diagram of the flip-flop 401_i as an example.

The transistor or the wiring shown in Figs. 31 and 32 is composed of a conductive layer 601, a semiconductor layer 602, a conductive layer 603, a conductive layer 604, and a contact hole 605. However, the present invention is not limited to this, and another conductive layer, an insulating film, or another contact hole can be newly formed. For example, a contact hole for connecting the conductive layer 601 and the conductive layer 603 can be newly added.

The conductive layer 601 may include a gate electrode or a portion functioning as a wiring. The semiconductor layer 602 may include a portion that functions as a semiconductor layer of the transistor. The conductive layer 603 may include a portion functioning as a wiring, a source, or a drain. The conductive layer 604 may include a transparent electrode, a pixel electrode, or a portion functioning as a wiring. The contact hole 605 has a function of connecting the conductive layer 601 and the conductive layer 604 or a function of connecting the conductive layer 603 and the conductive layer 604.

31, the wiring 412 has an opening 611, and the wiring 413 has an opening 612. In this example, Thus, the parasitic capacitance can be reduced by providing the openings in the wirings 412 and the wirings 413. Alternatively, breakdown of the transistor caused by electrostatic breakdown can be suppressed. However, the present invention is not limited to this, and similarly to the wiring 416, the opening 611 or the opening 612 can be omitted. Alternatively, an opening can be formed in the wiring 416 in the same manner as the wiring 412 or the wiring 413.

In the example of Fig. 31, the crossing capacity of the wiring can be reduced by forming the opening portion in the wiring 412 or the wiring 413 and a part of the intersection of the other wiring. Therefore, it is possible to reduce the noise, or reduce the delay or distortion of the signal.

31, a conductive layer 604 is formed on a part of the conductive layer 603 of the wiring 416. In the example shown in Fig. The conductive layer 604 is connected to the conductive layer 603 through a contact hole 605. [ As a result, the wiring resistance can be reduced, so that the voltage drop can be reduced, or signal delay or distortion can be reduced. However, the present invention is not limited to this, and the conductive layer 604 and the contact hole 605 can be omitted. A conductive layer 604 is formed on a part of the conductive layer 603 in the wiring 412 or the wiring 413 as in the wiring 416 and the conductive layer 604 is formed on the conductive layer 603 603, respectively.

31, the wiring width of the wiring 412, the wiring width of the wiring 413, and the wiring width of the wiring 416 are set to the wiring width 621, the wiring width 622, 623). A width 624, a length 625, a width 626 and a length 627 of the opening 611, the opening 611, the opening 612, and the opening 612, .

The signals input to the wiring 412 and the wiring 413 are often signals inverted from each other. Therefore, it is preferable that the wiring resistance or the parasitic capacitance of the wiring 412 is set to be approximately equal to the wiring resistance or the parasitic capacitance of the wiring 413. [ Therefore, it is preferable that the wiring 412 includes a portion approximately equal to the wiring width 622. Alternatively, the opening 611 preferably includes a portion approximately equal to the width 626 of the opening 612 or the length 627 of the opening 612. The width 622 of the opening 611, the width 626 of the opening 612, the length 625 of the opening 611, the width of the opening 612, Or the length 627 of the opening 612 can be set to various values. For example, the cross capacitance of the wiring 412 and another wiring is larger than the cross capacitance of the wiring 413 and the other wiring. In this case, by setting the wiring resistance of the wiring 412 to be small, it is possible to set the delay or distortion of the signals inputted to the wiring 412 and the wiring 413 to be approximately equal. As a result, the wiring 412 may include a portion larger than the wiring width 622. Alternatively, the opening 611 may include a portion that is smaller than the width 626 of the opening 612. Alternatively, the opening 611 may include a portion that is shorter than the length 627 of the opening 612. On the other hand, when the cross capacitance between the wiring 412 and the other wiring is smaller than the cross capacitance between the wiring 413 and the other wiring with respect to the wiring different from the wiring 413, the wiring 412 is wider than the wiring width 622 And may include small portions. Alternatively, the opening 611 may include a portion larger than the width 626 of the opening 612. Alternatively, the opening 611 may include a portion longer than the length 627 of the opening 612.

It is preferable that the wiring 416 includes a portion smaller than the wiring width 621 or the wiring width 622 when the wiring 416 does not have an opening. This is because the wiring 416 has no opening, and therefore the wiring resistance of the wiring 416 is small. However, the present invention is not limited to this, and the wiring 416 may include a portion larger than the wiring width 621 or the wiring width 622. [

In the example of FIG. 32, the transistor 101, the transistor 102, the transistor 103, the transistor 201, the transistor 202, the transistor 203, the transistor 204, the transistor 301, The area where the conductive layer 601 of the second terminal overlaps the conductive layer 603 in the transistor 303, the transistor 304 and / or the transistor 305 is the same as the area of the conductive layer 601 of the first terminal, And the conductive layer 603 overlap each other. Thereby, the noise of the gate of the transistor 101 or the wiring 401_i can be reduced. Alternatively, concentration of the electric field to the second terminal can be suppressed, so that deterioration of the transistor or destruction of the transistor can be suppressed.

An example of the layout diagram of the shift register has been described above. However, as described above, the layout diagram of the present embodiment is merely an example, and the present invention is not limited to this.

The semiconductor layer 602 can be formed at a portion where the conductive layer 601 and the conductive layer 603 overlap each other. Thereby, since the parasitic capacitance between the conductive layer 601 and the conductive layer 603 can be made small, the noise can be reduced. For the same reason, the semiconductor layer 602 or the semiconductor layer 603 can be formed at a portion where the conductive layer 601 and the conductive layer 604 overlap.

A conductive layer 604 may be formed on a part of the conductive layer 601 and the conductive layer 601 may be connected to the conductive layer 604 through the contact hole 605. [ As a result, the wiring resistance can be reduced. Alternatively, a conductive layer 603 and a conductive layer 604 are formed on a part of the conductive layer 601, the conductive layer 601 is connected to the conductive layer 604 through a contact hole 605, The conductive layer 603 may be connected to the conductive layer 604 through another contact hole 605. [ As a result, the wiring resistance can be further reduced.

A conductive layer 604 may be formed on a part of the conductive layer 603 and the conductive layer 603 may be connected to the conductive layer 604 through the contact hole 605. [ As a result, the wiring resistance can be reduced.

A conductive layer 601 or a conductive layer 603 is formed on a part of the conductive layer 604 and the conductive layer 604 is electrically connected to the conductive layer 601 through the contact hole 605, Layer 603 of FIG. As a result, the wiring resistance can be reduced.

Further, as described in Embodiment 1, the parasitic capacitance between the gate of the transistor 101 and the second terminal can be made larger than the parasitic capacitance between the gate of the transistor 101 and the first terminal. 32, the width of the conductive layer 603 which can function as the first electrode of the transistor 101 is shown as the width 631, and the width of the conductive layer 603 that can function as the second electrode of the transistor 101 And the width of the conductive layer 603 is shown as the width 632. [ And, the width 631 can be larger than the width 632. Thereby, the parasitic capacitance between the gate of the transistor 101 and the second junction can be made larger than the parasitic capacitance between the gate of the transistor 101 and the first terminal, as described in the first embodiment. However, the present invention is not limited to this.

(Embodiment 11)

In this embodiment, an example of an electronic apparatus will be described.

33A to 34D are diagrams showing electronic devices. These electronic devices include a case 5000, a display portion 5001, a speaker 5003, an LED lamp 5004, an operation key 5005 (including an operation switch or a power switch), a connection terminal 5006, a sensor 5007) (power, displacement, position, speed, acceleration, angular velocity, number of revolutions, distance, light, liquid, magnetic, temperature, chemical, voice, time, longitude, Humidity, hardness, vibration, odor, or infrared radiation), a microphone 5008, and the like.

33A is a mobile computer, and may have a switch 5009, an infrared port 5010, or the like in addition to the above. 33B is a portable image reproducing apparatus (for example, a DVD reproducing apparatus) having a recording medium, and may have a second display portion 5002, a recording medium reading portion 5011, and the like in addition to the above. 33C is a goggle type display, and may have a second display portion 5002, a support portion 5012, an earphone 5013, and the like in addition to the above. Fig. 33D is a portable electronic device, and may have a recording medium reading section 5011, etc. in addition to the above. 33E is a projector, and may have a light source 5033, a projection lens 5034, and the like in addition to the above. 33F is a portable type organic device and may have a second display portion 5002, a recording medium reading portion 5011, etc. in addition to the above. 33G is a television receiver, and may have a tuner, an image processing unit, and the like in addition to the above. 33H is a portable television receiver and may have a charger 5017 or the like capable of transmitting and receiving signals in addition to those described above. 34A is a display, and may have a support stand 5018 or the like other than the above. Fig. 34B is a camera and may include an external connection port 5019, a release button 5015, an image receiving portion 5016, and the like in addition to the above. 34C is a computer and may have a pointing device 5020, an external connection port 5019, a reader / writer 5021, etc. in addition to the above. 34D is a cellular phone, and may have an antenna 5014, a tuner for a one-segment partial reception service for a cellular phone or a mobile terminal, and the like, in addition to the above.

The electronic apparatuses shown in Figs. 33A to 34D may have various functions. For example, a function of displaying various information (still image, moving image, text image, etc.) on the display unit, a function of displaying a touch panel, a function of displaying a calendar, a date or time, A function of connecting various computer networks by using a wireless communication function, a function of transmitting or receiving various data by using a wireless communication function, a program or data recorded on a recording medium, And the like. Further, in an electronic apparatus having a plurality of display sections, a function of displaying image information with one display section as a main body and displaying character information mainly on the other display section, or a function of displaying parallax information on a plurality of display sections And a function of displaying a stereoscopic image by displaying the considered image. In the electronic device having the image receiving portion, a function of photographing a still image, a function of photographing a moving image, a function of automatically or manually correcting a photographed image, and a function of saving a photographed image on a recording medium A function of displaying a photographed image on a display unit, and the like. Note that the functions that the electronic apparatuses shown in Figs. 33A to 34D can have are not limited to these, and can have various functions.

The electronic apparatus described in this embodiment is characterized by having a display unit for displaying any information. By combining the electronic device of this embodiment with the semiconductor device, the shift register, or the display device of Embodiments 1 to 9, it is possible to improve the reliability, improve the yield, reduce the cost, enlarge the display portion, can do.

Next, an application example of the semiconductor device will be described.

Fig. 34E shows an example in which the semiconductor device is formed integrally with the dried material. 34E includes a case 5022, a display portion 5023, a remote control device 5024 as an operation portion, a speaker 5025, and the like. Since the semiconductor device is a wall-mounted type and integrated with the building, it can be installed without requiring a large space for installation.

Fig. 34F shows another example in which the semiconductor device is integrally formed with the dried material in the dried material. The display panel 5026 is mounted integrally with a prefabricated bath 5027, and the bathing person can view the display panel 5026.

In this embodiment, a wall and a unit bath are taken as an example of a dried product, but the present embodiment is not limited to this, and a semiconductor device can be formed on various dried products.

Next, an example in which the semiconductor device is formed integrally with a moving body is presented.

Fig. 34G is a diagram showing an example in which a semiconductor device is formed in an automobile. The display panel 5028 is formed on the vehicle body 5029 of the vehicle, and can display on-demand information inputted from inside or outside of the vehicle body or operation of the vehicle body. It may also have a navigation function.

34H is a diagram showing an example in which a semiconductor device is formed integrally with a passenger airplane. FIG. 34H is a view showing a shape when the display panel 5031 is formed on the ceiling 5030 on the seat top of the passenger airplane. The display panel 5031 is integrally formed with the ceiling 5030 and the hinge portion 5032 and the passenger can view the display panel 5031 by the expansion and contraction of the hinge portion 5032. [ The display panel 5031 has a function of displaying information by being operated by a passenger.

In the present embodiment, examples of the moving body include an automobile body and an airplane body. However, the present invention is not limited to this, and includes a motorcycle, an automatic four-wheeler (including a car, a bus, etc.), a trolley (including a monorail, ), Ships, and the like.

100: circuit 101: transistor
102: transistor 103: transistor
104: circuit 104a: terminal
104b: Terminal 104c: Terminal
104d: terminal 105: circuit
105a: Terminal 105b: Terminal
105c: Terminal 105d: Terminal
105e: Terminal 105f: Terminal
111: Wiring 112: Wiring
113: Wiring 114: Wiring
115: wiring 116: wiring

Claims (12)

A semiconductor device comprising:
A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor,
One of a source and a drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to each other,
One of a source and a drain of the third transistor, one of a source and a drain of the fourth transistor, one of a source and a drain of the fifth transistor, a gate of the first transistor, a gate of the seventh transistor, The gates of the nine transistors are electrically connected to each other,
One of a source and a drain of the sixth transistor, one of a source and a drain of the seventh transistor, a gate of the second transistor, and a gate of the fifth transistor are electrically connected to each other,
One of a source and a drain of the eighth transistor, one of a source and a drain of the ninth transistor, and a gate of the sixth transistor are electrically connected to each other,
The other of the source and the drain of the second transistor, the other of the source and the drain of the fifth transistor, the other of the source and the drain of the seventh transistor, And the other of the drains are electrically connected to each other,
The other of the source and the drain of the sixth transistor, the source and the drain of the eighth transistor, and the gate of the eighth transistor are electrically connected to each other. The method according to claim 1,
And a channel width of the second transistor is larger than a channel width of the fifth transistor. The method according to claim 1,
And the channel width of the ninth transistor is smaller than the channel width of the seventh transistor. 3. The method of claim 2,
And the channel width of the ninth transistor is smaller than the channel width of the seventh transistor. 5. The method according to any one of claims 1 to 4,
And the channel width of the eighth transistor is smaller than the channel width of the sixth transistor. The method according to claim 1,
And the gate of the first transistor is electrically connected to the gate of the seventh transistor via a tenth transistor and an eleventh transistor. A semiconductor device comprising:
A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor,
One of a source and a drain of the first transistor and one of a source and a drain of the second transistor are directly connected to each other,
One of a source and a drain of the third transistor, one of a source and a drain of the fourth transistor, one of a source and a drain of the fifth transistor, and a gate of the first transistor are directly connected to each other,
The gate of the seventh transistor and the gate of the ninth transistor are directly connected to each other,
One of a source and a drain of the sixth transistor, one of a source and a drain of the seventh transistor, a gate of the second transistor, and a gate of the fifth transistor are directly connected to each other,
One of a source and a drain of the eighth transistor, one of a source and a drain of the ninth transistor, and a gate of the sixth transistor are directly connected to each other,
The other of the source and the drain of the second transistor, the other of the source and the drain of the fifth transistor, the other of the source and the drain of the seventh transistor, And the other of the drains are directly connected to each other,
The other of the source and the drain of the sixth transistor, the source and the drain of the eighth transistor, and the gate of the eighth transistor are directly connected to each other. 8. The method of claim 7,
And a channel width of the second transistor is larger than a channel width of the fifth transistor. 8. The method of claim 7,
And the channel width of the ninth transistor is smaller than the channel width of the seventh transistor. 9. The method of claim 8,
And the channel width of the ninth transistor is smaller than the channel width of the seventh transistor. 11. The method according to any one of claims 7 to 10,
And the channel width of the eighth transistor is smaller than the channel width of the sixth transistor. 8. The method of claim 1 or 7,
The one of the source and the drain of the first transistor and the gate of the seventh transistor are electrically connected to the other one of the source and the drain of the second transistor via a transistor,
The other of the source and the drain of the first transistor is electrically connected to the other one of the source and the drain of the sixth transistor,
And the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor and to the gate of the fourth transistor.

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