KR101725208B1 - Inverter - Google Patents

Abstract

The present invention relates to an inverter applied to a display device, and more particularly, to an inverter that receives a reset signal and boosts a voltage input to a gate of a reset transistor. To this end, the inverter according to the present invention includes: an input transistor (T1) for outputting a first output signal having a level inverted from an input signal; A reset transistor (T2) for outputting a second output signal having the same level as the input signal by the reset signal after the first output signal; And a boosting unit using the reset signal to perform a function of making the gate voltage of the reset transistor higher or lower than a voltage applied to the source of the reset transistor.

Description

Inverter {INVERTER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter, and more particularly, to an inverter applied to various display devices.

Display devices commonly used at present include a liquid crystal display device, an organic electro-luminescence display device, a plasma display panel, and a field emission display display device, and the like, and an inverter is provided in the driving driver of such a display device.

That is, when a driving circuit is integrated for driving a liquid crystal display or an organic light emitting display, an inverter is used as described above. The inverter is provided in a driving driver of the display, And controls the output signal.

On the other hand, in the case of an organic light emitting diode display device, a gate driver composed of a shift register for driving the compensation circuit and an emission driver for shifting the signal of the shift register by inverting the signal are required. In the case of the inverter included in the driving circuit, It is necessary to secure the driving margin such as adjusting the width / length of the transistor. Specifically, it is as follows.

1 and 2 show an example of a circuit configuration of a conventional inverter. FIG. 1 shows an N-type inverter, and FIG. 2 shows a P-type inverter.

The inverters formed in the N type or P type can be reset by using a reset signal as shown in FIG. 1 or 2A, or by using a reset transistor T2 (see FIG. 2 ).

Here, the voltage levels of the reset signal, the input signal, VGH, and VGL are generally the same voltage level, in order to reduce the loss of additional power for driving.

The conventional inverter operation will be briefly described by taking an N-type inverter shown in FIG. 1 as an example.

That is, when a high-level input signal is input through the input terminal IN, the input transistor Tl is turned on, VGL is output to the output terminal via T1, and the input signal is turned to the low level When falling, the transistor T1 is turned off and VGH is output to the output terminal through the reset transistor T2.

At this time, an ideal output signal that does not consider the mobility and the threshold voltage will correctly invert the input signal, but the actual output signal is a delayed signal, as shown in FIG. 1 (c) Is generated. This delay is a delay that occurs when Vgs = 0 in T2 because the high voltage of the reset signal is equal to the level of VGH.

Also, in the case of the inverter of the P type as shown in FIG. 2, a delay (see Real Output shown in FIG. 2 (c)) occurs for the same reason as described above.

On the other hand, in the technique of integrating the driver circuits in the display device, the circuit is designed mainly by using a CMOS type poly-Si thin film transistor. However, in this case, in order to integrate N type or P type thin film transistors, Process is required.

Therefore, in the case of the inverter used for the driving driver of the above-described display devices, the inverter is not formed as a CMOS type in order to simplify the process and reduce the cost. As shown in FIGS. 1 and 2, .

That is, as a method of integrating the inverters, there is used a method of integrating the driving circuits by only N-type or P-type thin film transistors. In this case, the driving circuit characteristics are lowered In order to compensate for this, a method of changing the driving circuit in a circuit is used.

Open No. 10-2009-0072854, in which the name of the invention is an inverter, improves the operation margin of the inverter circuit by lowering the output of the low level. In the name of the invention, the inverter and the display device having the same disclosed in Publication No. 10 -2009-0108832, the inverter is composed of three thin film transistors and one capacitor. However, when the inverter is formed in the N type or P type instead of the CMOS type, as described in the description of FIGS. 1 and 2, a reset delay occurs after outputting the inverted signal by receiving the input signal do.

Such a reset delay can reduce the driving margin of the driving circuit, and may cause malfunction of the driving circuit due to deterioration of the thin film transistor or external driving conditions of the driving circuit.

That is, the reset delay generated in the conventional inverter composed only of the N type or P type thin film transistor as described above has the same level as the reset voltage of the reset signal in FIG. 1 (a) In the case of an inverter formed of P type as shown in FIG. 2A, a delay occurs because Vgs = 0, and a delay occurs due to the above-described reason.

On the other hand, a method of increasing the Vgs may be used to remove the reset delay. That is, in the N-type inverter shown in FIG. 1A, a method of reducing the reset delay by setting Vgs > 0 by inputting a voltage higher than VGH at the High voltage of the reset signal is used. However, this method causes a problem that another voltage source must be used.

In the case of the P-type inverter shown in FIG. 2A, if the same method as the above method is used to remove the reset delay, the reset delay can be reduced by setting Vgs < 0, Causing a problem that one more voltage source must be used.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an inverter that receives a reset signal and boosts a voltage input to a gate of a reset transistor.

According to an aspect of the present invention, there is provided an inverter including: an input transistor for outputting a first output signal having a level inverted from an input signal; A reset transistor (T2) for outputting a second output signal having the same level as the input signal by the reset signal after the first output signal; And a boosting unit using the reset signal to perform a function of making the gate voltage of the reset transistor higher or lower than a voltage applied to the source of the reset transistor.

According to the above-mentioned solution, the present invention provides the following effects.

That is, the present invention provides an effect that the delay of the inverted signal can be improved by receiving a reset signal and boosting a voltage input to the gate node of the reset transistor.

Further, the present invention improves the rising or falling delay of the inverter, thereby improving the characteristics of a gate driver or an inverter driver using the inverter, improving the reliability of the display, reducing the driving voltage width of the display, -It does not use a step-up circuit for increasing the driving voltage in IC, thereby reducing power consumption.

In addition, when the driving voltage levels (VGH to VGL) are reduced to improve the power consumption, the conventional inverter may cause a malfunction of the driving circuit due to the relatively increasing delay or affect the image quality of the display. However, In the case of a display having an inverter circuit according to the present invention, it is possible to greatly improve the delay, thereby preventing the malfunction of the driving circuit and the deterioration of image quality.

The present invention also provides the effect that it is not necessary to have an additional voltage source.

Fig. 1 and Fig. 2 are exemplary diagrams showing a circuit configuration of a conventional inverter. Fig.
FIG. 3A and FIG. 3B are views showing the configuration and waveform of an inverter according to the first embodiment of the present invention; FIG.
4A to 4B are views showing the configuration and waveform of an inverter according to a second embodiment of the present invention;
5 is an exemplary view showing a configuration and a waveform of an inverter according to a third embodiment of the present invention;
6 is an exemplary view showing the configuration and waveform of an inverter according to a fourth embodiment of the present invention;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIGS. 3A and 3B are diagrams illustrating the configuration and waveform of an inverter according to the first embodiment of the present invention. Hereinafter, various embodiments of the present invention composed of P-type thin film transistors will be described, but the present invention may also be composed of N-type thin film transistors.

The inverter according to the first embodiment of the present invention includes a reset transistor T2, an input transistor T1, and a boosting unit 100, as shown in FIG. 3 (a).

The reset transistor T2 has a charge voltage input terminal 200 connected to a source for inputting a charge voltage having the same voltage level as the input signal input from the input terminal, And the drain of the input transistor T3 are connected to the gate of the boosting unit 100, and one end of the boosting unit 100 is connected to the gate thereof. Here, since the inverter shown in FIG. 3A is configured as a P type, a low level voltage VGL is applied to the charge voltage input terminal, but a high level voltage can be applied to an N type inverter. Therefore, in the following, the present invention is described as applying the low level voltage VGL to the charge voltage input terminal. That is, the charge voltage inputted through the charge voltage input terminal has the same voltage level as the input signal, and performs a function of outputting a second output signal having the same level as the input signal through the reset transistor. In the following description, the charging voltage refers to a voltage capable of turning on the transistor, and the discharge voltage refers to a voltage for turning off the transistor. Therefore, the following description refers to a P-type inverter as an example, and therefore the charging voltage refers to a low level voltage (VDD = VGL) and the discharge voltage refers to a high level voltage (VSS = VGH). Therefore, in the case of the P type, the opposite voltage is input.

The input transistor T1 has a source connected to a discharge voltage input terminal 400 for inputting a voltage of a level opposite to the voltage level of the input signal input from the input terminal, The drain of the reset transistor T1 is connected, and the input terminal 500 is connected to the gate. Here, since the inverter shown in FIG. 3 is of the P type, the discharge voltage input terminal 400 applies the high level voltage VGH. However, in the case of the N type inverter, the low level voltage is applied . Therefore, the present invention is described below assuming that the discharge voltage input terminal is applying the high level voltage VGH. That is, the discharge voltage inputted through the discharge voltage input terminal has a voltage level inverted with the input signal, and performs a function of outputting a first output signal having a level inverted with the input signal through the input transistor. That is, an input signal is input and a first output signal having a level inverted from the input signal through the input transistor is output. Then, a second output signal having the same level as the input signal through the reset transistor driven by the reset signal Is output.

The boosting unit 100 performs a function of lowering the gate voltage of the reset transistor T2 by using a reset signal input from the reset signal input terminal 600. The boosting unit 100 receives an input signal, A boosting input transistor T4 for lowering the voltage, a capacitor C1 for storing the voltage of the reset signal, a capacitor C1 connected to the gate and a gate of the reset transistor T2 connected to the drain to apply a reset signal And a boosting transistor T5 for boosting the voltage level input to the capacitor C1 to instantaneously lower the gate voltage of the reset transistor T2.

That is, the boosting unit 100 applied to the inverter according to the first embodiment of the present invention as described above is for increasing the driving margin of the display by reducing the reset delay, and is connected to the gate of the reset transistor T2, (T5, T4) and a single capacitor (C1) for receiving the signal and boosting the gate voltage of the reset transistor.

The overall structure of the inverter according to the first embodiment of the present invention including the boosting unit as described above will be described as follows.

That is, the inverter according to the first embodiment of the present invention includes an input transistor T1 for outputting a first output signal (VSS = VGH) inverted from the voltage level of the input signal by an input signal, a first output signal VGH A reset transistor T2 connected in series with T1 for outputting a second output signal VDD = VGL, a gate node ("B" node) and a discharge voltage input terminal 400 (VSS = VGH To the gate node ("B" node) of T2 which outputs VSS (VGH) and the second output signal (VDD = VGL) by an input signal, an input terminal 500 A boosting input transistor T4 having a gate and a source connected in a diode connection manner, a capacitor C1 connected to a drain of T4 and a reset signal CLK input terminal 600 connected in a diode connection manner, and a diode T4 ("B" node) of T2 which outputs the drain of VDD and the drain of the reset signal CLK Is configured to include a boosting transistor (T5) is driven. Here, the transfer transistor T3 may not be provided.

In the first embodiment of the present invention configured as described above, the discharge voltage (VSS = VGH) is output as the first output signal by the input signal (low level voltage = charge voltage), and the voltage level of the input signal The voltage level of the inputted input signal is boosted by the reset signal (CLK) and the capacitor to apply the VDD (VGL) to the gate node voltage of T2 which outputs the second output signal.

In addition, the first embodiment of the present invention can adjust the level of the boosted voltage to the magnitude of C1.

The operation of the inverter according to the first embodiment of the present invention will now be described.

3A, when a low level input signal (VDD = VGL) is input through an input terminal IN, a signal "B (V)" is input through T3 which is turned on by an input signal Quot; node is held at a high level (discharge voltage VGH), and thus T2 is turned off. At the same time, T1 is turned on by the input signal (VDD), so that VGH is output as the first output signal through T1. Further, as T4 is turned on by the input signal, the input signal (low level) is stored in the "A " node through T4.

Next, when the input signal is changed from the low level (VGL = VDD) to the high level (VGH = VSS) as shown in (a) and (b) of FIG. 3B, T1 and T3 are turned off . At this timing, the voltage of the "A" node is output through T5 as the reset signal is changed from the high level (VGH) to the low level (VGL) and T5 is turned on. At this time, since the "A" node voltage is connected to the reset signal via C1, a boosting effect is generated. As a result, when the reset signal is changed from the high level (VGH) to the low level "The node voltage falls even lower than the low level (VGL Level). As a result, when the low level (VGL) is outputted as the second output signal through T2, the gate voltage of T2 becomes lower than the low level voltage (VGL Level), and the reset delay at T2 is reduced.

4A to 4C are diagrams illustrating the configuration and waveform of the inverter according to the second embodiment of the present invention. In the inverter of FIG. 4, Respectively.

That is, in the case of an inverter driven by 3-phase or 4-phase, a second reset signal input complex CLK_B may be added to the boosting unit 300 shown in FIG.

Accordingly, the inverter according to the second embodiment of the present invention includes a reset transistor T2, an input transistor T1, and a boosting unit 100, as shown in FIG. 3A. Here, the configuration and function of the reset transistor T2 and the input transistor T1 are the same as those in the first embodiment, and a detailed description thereof will be omitted.

The boosting unit 100 applied to the second embodiment of the present invention uses the first reset signal input from the first reset signal input terminal CLK_A 610 to set the gate voltage of the reset transistor T2 to the charge voltage A boosting input transistor T4 for receiving an input signal to lower the gate voltage of the reset transistor T2, a boosting input transistor T4 for receiving a voltage of the reset signal, The gate of the reset transistor T2 is connected to the capacitor C1 and the capacitor C1 to boost the voltage level input to the capacitor C1 when the reset signal is applied to the gate of the reset transistor T2, The boosting transistor T5 for lowering the source and the source are connected to the charge voltage input terminal VGL = VDD 200, the drain is connected to the drain node of T5 and the gate of T2, And a voltage holding transistor T6 connected to the reset signal input terminal CLK_B.

The overall configuration of the inverter according to the second embodiment of the present invention including the boosting unit 100 as described above will now be described.

That is, in the inverter according to the second embodiment of the present invention, the charging voltage input terminal 200 and the gate node ("B") of T2 which outputs VDD (VGL) quot; node to reset the gate voltage of T2 to the VDD level by another input signal CLK_B.

Here, the reset signal for resetting may be composed of three phases as shown in (b) of FIG. 4a, or may be composed of four phases as shown in (c) .

The operation of the inverter according to the second embodiment of the present invention will now be described.

4A, when the input signal of the charging voltage level (VHL = VDD) is inputted through the input terminal IN, T3 is turned on by the input signal, and through the T3, the "B & Level (VGH = VSS), so that T2 is turned off. At the same time, T1 is turned on by the input signal, so that the discharge voltage (VGH = VSS) is output to the first output signal via T1. Further, the input signal (low level) is stored in the "A " Node through T4. At this time, since a high level signal (discharge voltage) is inputted from both the first reset signal input terminal 610 and the second reset signal input terminal 620, T5 and T6 are kept in the off state.

Next, as shown in FIG. 4B, when the input signal is changed from the low level (VGL) to the high level (VGH), T1 and T3 are turned off. At this timing, a first reset signal from the first reset signal input terminal is changed from the high level (VGH) to the low level (VGL) and T5 is turned on by the first reset signal, Is output through T5. At this time, since the "A" node voltage is connected to the first reset signal through C1, a boosting effect is generated. As a result, when the first reset signal is changed from the high level (VGH) to the low level (VGL) The node voltage and the "B" node voltage drop lower than the low level (VGL Level). As a result, when the low level VGL is output through T2 to the second output signal (a solid line graph between two graduation lines of the OUT graph shown in FIG. 4B (b)), the gate voltage of T2 becomes the low level voltage (VGL Level), and the reset delay at T2 is reduced. Meanwhile, during the above process, a high level signal is continuously input to the second reset signal input terminal, so that T6 is kept off.

Next, as shown in FIG. 4C, when the input signal is maintained at the high level (VGH), T1 and T3 are kept in the off state. When the second reset signal is changed from the high level (VGH) to the low level (VGL) from the second reset signal input terminal at the above timing, T6 is turned on, and therefore, the first reset signal turns on T2, the VGL is outputted as the second output signal while maintaining the turn-on state continuously even if the first reset signal is changed to the high level.

That is, in the inverter according to the second embodiment of the present invention configured as described above, since T6 is connected between the gate of T2 and the discharge voltage input terminal 200, the second reset signal (CLK_B) And to maintain the second output voltage in the low level in the low level (VGL).

In the above description, the inverter according to the second embodiment of the present invention is operated in three phases. However, the inverter according to the second embodiment of the present invention can also be applied to four phases .

That is, as shown in (c) of FIG. 4, the first output signal inverted to the low level by the first reset signal CLK_A driven in four phases is connected to the second reset signal driven in the four phases The second output signal state of the low level can be maintained.

In other words, when the inverter according to the second embodiment of the present invention is driven in three phases, the second output signal of the low level inverted by the first reset signal is input immediately after the first reset signal And the second reset signal of the low level maintains the low level. However, when the inverter according to the second embodiment of the present invention is driven in four phases, the low-level second output signal inverted by the first reset signal is input at a time interval to the first reset signal And the second reset signal maintains the low level.

5 is a diagram showing an example of a configuration and a waveform of an inverter according to a third embodiment of the present invention.

The inverter according to the third embodiment of the present invention includes a reset transistor T2, an input transistor T1 and a boosting unit 100 as shown in FIG. In the second embodiment, the voltage maintenance of the B node connected to the gate of T2 is strengthened.

Here, the configurations and functions of the reset transistor T2 and the input transistor T1 are the same as in the first embodiment or the second embodiment, and a detailed description thereof will be omitted. That is, in the third embodiment of the present invention shown in FIG. 8, T7 and C2 are added to the boosting unit 100 applied to the second embodiment of the present invention. However, The present invention can be similarly applied to the boosting unit applied to the first embodiment of the present invention.

In the boosting unit 100 applied to the third embodiment of the present invention, a charge voltage input terminal 200 is connected to a source, a capacitor C2 connected to an output terminal is connected to the drain, And a node holding transistor T7 connected thereto. That is, the boosting unit applied to the third embodiment of the present invention includes a capacitor C2 connected to the output terminal for maintaining the voltage of node B and connected to the node B, And a node holding transistor T7 for inputting VDD (VGL) to the "B" node.

Here, T7 feeds back the output signal and maintains the "B" node voltage at the charge voltage level (VGL Level). When a low-level second output signal is output And maintains the B node at a low level continuously.

FIG. 6 is a diagram illustrating the configuration and waveform of an inverter according to a fourth embodiment of the present invention, and shows an inverter that can more stably maintain the output signal of the output terminal shown in FIG. 3 to FIG.

The inverter according to the fourth embodiment of the present invention includes a reset transistor T2, an input transistor T1 and a boosting unit 100 as shown in FIG. 6, The output signal of the low level is more stably maintained.

Here, the configuration and function of the reset transistor T2 and the input transistor T1 are the same as in the first to third embodiments, and a detailed description thereof will be omitted.

That is, the boosting unit 100 applied to the fourth embodiment of the present invention includes the leakage preventing transistor T8 and the second input transistor T1 'in the boosting unit applied to the first to third embodiments, May be further included.

Here, T8 has a source connected to a charging voltage input terminal 200, an output terminal connected to a gate, and a drain connected to the source of the first input transistor T1. The second input transistor T1 'is connected between the discharge voltage input terminal (VSS = VGH) 400 and the first input transistor T1 and is turned on or off by receiving an input signal. Thus, the drain of T8 is connected to the node between T1 'and T1. That is, in the boosting unit according to the fourth embodiment of the present invention, T1 ', which receives an input signal and outputs a discharge voltage (VSS), is connected in series with T1, and an intermediate node between T1 and T1' And T8 which receives a signal as input and inputs a charging voltage (VDD = VGL) to T1. Here, T8 functions to prevent the discharge voltage (VSS = VGH) from leaking through the T1 to the output terminal when the charging voltage (VDD = VGL) is outputted to the output terminal.

Therefore, when the discharge voltage (high level signal) is input to the input terminal as the input signal and the charge voltage (low level signal) is output as the second output signal through the output terminal, the high level voltage VGH is supplied through the T1 It is possible to prevent a phenomenon that the second output signal is changed due to leakage to the output terminal.

That is, when the low level voltage VGL is output as the second output signal, T8 is turned on to transmit the low level voltage VGL to the node between T1 and T1 '. At this time, because a high level signal is input to the gates of T1 and T1 'through the input terminal, T1 and T1' are turned off. In an ideal case, the leak voltage can not be outputted to the output terminal. However, The leakage voltage may be output through T1.

However, in the case where the fourth embodiment of the present invention is applied, even if a leak voltage is output through T1 while the low level is output as the second output signal, since the leak voltage is the low level voltage VGL transmitted through T8 , The second output signal of the output terminal can be maintained at a low level.

The present invention as described above relates to an inverter included in the driving circuit portion when a driving circuit portion for driving the display is integrated in a panel in a flat panel display such as a liquid crystal display device or an organic light emitting display.

That is, in designing an inverter using an amorphous silicon (a-Si) or a polysilicon (polysilicon) thin film transistor, by inverting an input signal and reducing a rising delay or a falling delay, It is possible to improve the operation margin of the circuit when the power consumption is improved by reducing the operating voltage width of the display.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: boosting unit 200: charging voltage input terminal
300: Output terminal 400: Discharge voltage input terminal
500: Input terminal T1: Input transistor
T2: reset transistor T3: transfer transistor
T4: Boosting input transistor T5: Boosting transistor
T6: voltage holding transistor T7: node holding transistor
T8: Anti-leak transistor

Claims (25)

An input transistor (T1) for outputting a first output signal of a level inverted from an input signal;
A reset transistor (T2) for outputting a second output signal having the same level as the input signal by the reset signal after the first output signal; And
And a boosting unit using the reset signal to perform a function of making the gate voltage of the reset transistor higher or lower than a voltage applied to the source of the reset transistor,
And the boosting unit maintains the reset transistor (T2) in a turned-on state when the second output signal is output. The method according to claim 1,
The boosting unit includes:
A boosting input transistor T4 having a gate and a source connected in a diode connection manner to an input terminal for inputting the input signal;
A first capacitor (C1) connected to a drain of the boosting input transistor (T4) and a reset signal input terminal for inputting the reset signal; And
And a boosting transistor T5 connected to the drain of the boosting input transistor and to the gate of the reset transistor T2 to be turned on or off by the reset signal. 3. The method of claim 2,
The boosting unit includes:
The boosting transistor T5 boosts the input signal, which is input through the boosting input transistor T4 and stored in the first capacitor C1, by the reset signal, so that the gate of the reset transistor T2, To the inverter. 3. The method of claim 2,
The boosting unit includes:
And a transfer transistor (T3) coupled to the gate of the reset transistor and to a source of the input transistor, the transfer transistor being turned on or off by the input signal. 5. The method of claim 4,
The transfer transistor (T3)
And the gate of the reset transistor (T2) is turned on by the input signal inputted to the input terminal, and the discharge voltage is applied to the gate of the reset transistor (T2). 5. The method of claim 4,
The boosting unit includes:
The boosting transistor T5 and the reset transistor T2 may be boosted by the reset signal by inputting the input signal inputted through the boosting input transistor T4 and stored in the first capacitor C1, To the gate of the reset transistor (T2). An input transistor (T1) for outputting a first output signal of a level inverted from an input signal;
A reset transistor (T2) for outputting a second output signal having the same level as the input signal by the first reset signal after the first output signal; And
And a boosting unit,
A boosting input transistor T4 having a gate and a source connected in a diode connection manner to an input terminal for inputting the input signal;
A first capacitor (C1) connected to a drain of the boosting input transistor (T4) and a first reset signal input terminal for inputting the first reset signal;
A boosting transistor T5 connected to the drain of the boosting input transistor and to the gate of the reset transistor T2 to be turned on or off by the first reset signal; And
And a voltage holding transistor (T6) for holding the reset transistor at a charge voltage by a second reset signal input from a second reset signal input terminal. 8. The method of claim 7,
Wherein the first reset signal and the second reset signal are driven by any one of a 2-phase, a 3-phase, and a 4-phase. 8. The method of claim 7,
The voltage holding transistor (T6)
Wherein the first reset signal is connected between a gate and a gate of the reset transistor, and is turned on or off by the second reset signal. 8. The method of claim 7,
And a transfer transistor (T3) coupled to the gate of the reset transistor and to a source of the input transistor, the transfer transistor being turned on or off by the input signal. An input transistor (T1) for outputting a first output signal of a level inverted from an input signal;
A reset transistor (T2) for outputting a second output signal having the same level as the input signal to the output terminal by the first reset signal after the first output signal; And
And a boosting unit,
A boosting input transistor T4 having a gate and a source connected in a diode connection manner to an input terminal for inputting the input signal;
A first capacitor (C1) connected to a drain of the boosting input transistor (T4) and a first reset signal input terminal for inputting the first reset signal;
A boosting transistor T5 connected to the drain of the boosting input transistor and to the gate of the reset transistor T2 to be turned on or off by the first reset signal; And
A node for maintaining a node B between the drain of the boosting transistor T5 and the gate of the reset transistor at a charge voltage, the node being connected between a source and a gate of the reset transistor and being turned on by the second output signal, And a holding transistor (T7). 12. The method of claim 11,
And a second capacitor (C2) is connected between a drain of the node holding transistor (T7) and the output terminal. 12. The method of claim 11,
Further comprising a voltage holding transistor (T6) connected between a source and a gate of the reset transistor and being turned on or off by a second reset signal. 14. The method of claim 13,
The voltage holding transistor (T6)
And the reset transistor is maintained at a charge voltage by the second reset signal. 12. The method of claim 11,
Further comprising a transfer transistor (T3) coupled between a gate of the reset transistor and a source of the input transistor, the transfer transistor being turned on or off by the input signal. A first input transistor (T1) for outputting a first output signal having a level inverted from an input signal;
A reset transistor (T2) for outputting a second output signal having the same level as the input signal to the output terminal by the first reset signal after the first output signal; And
And a boosting unit,
A boosting input transistor T4 having a gate and a source connected in a diode connection manner to an input terminal for inputting the input signal;
A first capacitor (C1) connected to a drain of the boosting input transistor (T4) and a first reset signal input terminal for inputting the first reset signal;
A boosting transistor T5 connected between the drain of the boosting input transistor and the gate of the reset transistor T2 and turned on or off by the first reset signal; And
And a leakage prevention transistor (T8) connected between a source of the reset transistor (T2) and a source of the first input transistor (T1). 17. The method of claim 16,
Characterized in that the leakage prevention transistor (T8) is turned on by the second output signal to transfer a charging voltage input to the reset transistor to the source of the first input transistor (T1). 17. The method of claim 16,
Further comprising a second input transistor (T1 ') connected between a discharge voltage input terminal for inputting a discharge voltage and a source of the first input transistor (T1), the second input transistor being driven by the input signal. 17. The method of claim 16,
Further comprising a transfer transistor (T3) coupled between the gate of the reset transistor and a source of the first input transistor (T1), the transfer transistor (T3) being turned on or off by the input signal. 17. The method of claim 16,
And a voltage holding transistor (T6) for holding the reset transistor at a charge voltage by a second reset signal. 21. The method of claim 20,
The voltage holding transistor (T6)
Wherein the first reset signal is connected between a gate and a gate of the reset transistor, and is turned on or off by the second reset signal. 17. The method of claim 16,
A node holding between the source and the gate of the reset transistor and being turned on by the second output signal to maintain the node B between the drain of the boosting transistor T5 and the gate of the reset transistor at the charge voltage An inverter comprising a transistor (T7). 23. The method of claim 22,
And a second capacitor (C2) is connected between a drain of the node holding transistor (T7) and the output terminal. 17. The method of claim 16,
And the leak prevention transistor (T8) is turned on by the second output signal. An input transistor (T1) for outputting an output signal of a level inverted from the input signal;
A reset transistor T2 for outputting an output signal at the same level as the input signal by a reset signal; And
A boosting input transistor T4 having a gate and a source connected in a diode connection manner to an input terminal for inputting the input signal;
A first capacitor (C1) connected to a drain of the boosting input transistor (T4) and an input terminal for inputting the reset signal; And
And a boosting transistor T5 connected to the drain of the boosting input transistor and the gate node of the reset transistor T2 to turn on or off by the reset signal.

Images