KR20120043602A - Inverter - Google Patents

Abstract

PURPOSE: An inverter is provided to amplify voltage inputted to a gate node of a reset transistor by receiving a reset signal, thereby improving a delay of an inverted signal. CONSTITUTION: An input transistor(T1) outputs a first output signal. The first output signal has a level which is reversed to an input signal. A second transistor(T2) outputs a second output signal. The second output signal has the same level as the input signal. A boosting part increases/decreases gate voltage of a reset transistor applied to a source which is higher/lower than voltage applied to a source.

Description

Inverter {INVERTER}

The present invention relates to an inverter, and more particularly, to an inverter applied to various display devices.

Currently used display devices include liquid crystal display devices, organic electro-luminescence display devices, plasma display panels, and field emission displays. display device) and an inverter is provided in the driving driver of the display device.

That is, when the driving circuit is integrated for driving the liquid crystal display or the organic light emitting display, an inverter is used as described above. The inverter is provided in the driving driver of the display device to drive the panel displaying the screen. Control the output signal.

In the organic light emitting diode display, a gate driver including a shift register and an emission driver for inverting and shifting a signal of the shift register are required to drive a compensation circuit. In the case of an inverter included in the driving circuit, a delay is required. It is necessary to secure the driving margin by adjusting the width / length of the transistor to reduce the voltage. Looking at this in detail.

1 and 2 are exemplary diagrams showing a circuit configuration of an inverter used in the related art. FIG. 1 shows an N-type inverter, and FIG. 2 shows a P-type inverter.

An inverter formed of an N type or a P type may use a reset signal as shown in FIG. 1 or 2 (a), or may be bundled in a diode form as shown in FIG. 1 or 2 (b) to reset the transistor T2. ).

Here, the voltage levels of the reset signal, the input signal, the VGH, and the VGL are generally the same voltage level, in order to reduce the loss of forming an additional power source for driving.

The conventional inverter operation will be briefly described by taking the N-type inverter shown in FIG. 1 as an example.

That is, when a high level input signal is input through the input terminal IN, the input transistor T1 is turned on so that the VGL is output to the output terminal through T1, and the input signal is brought to the low level. When falling, T1 is turned off and VGH is output to the output terminal through the reset transistor T2.

In this case, the ideal output signal without considering the mobility and threshold voltage will invert the input signal correctly, but the real output signal is delayed as shown in (c) of FIG. 1. Is generated. This delay is a delay that occurs when Vgs = 0 of T2 because the high voltage of the reset signal and the level of VGH are the same.

In addition, in the case of the inverter formed in the P type as shown in FIG. 2, a delay (see Real Output shown in FIG.

On the other hand, a technology for integrating a driving circuit in a display device is mainly designed by using a CMOS type Poly-Si thin film transistor. The process is necessary.

Therefore, in the case of the inverter used for the driving driver of the display devices as described above, the CMOS type is not formed in order to simplify the process and reduce the cost, and as shown in FIGS. 1 and 2, an N-type or P-type transistor Is formed.

In other words, as a method of integrating an inverter, a method of integrating a driving circuit using only N-type or P-type thin film transistors is used. In this case, the characteristics of the driving circuit are lower than in the case of integrating the driving circuit with a CMOS type thin film transistor. In general, a method of changing a driving circuit in a circuit is used to compensate for this.

For example, Publication No. 10-2009-0072854, titled Inverter, improves the operating margin of the inverter circuit by lowering the output of the low level, and discloses Publication No. 10, which is named Inverter and a display device having the same. In 2009-0108832, an inverter consists of three thin film transistors and one capacitor. However, when the inverter is formed using the N type or the P type rather than the CMOS type, as described in the description of FIGS. 1 and 2, after receiving an input signal and outputting an inverted signal, a reset delay occurs. do.

Such a reset delay may reduce the driving margin of the driving circuit and cause malfunction of the driving circuit due to deterioration of the thin film transistor or external driving conditions of the driving circuit.

That is, as described above, the reset delay generated in the conventional inverter composed of only N-type or P-type thin film transistors has the same level as the high voltage of the reset signal and the level of VGH in FIG. The delay occurs when Vgs = 0, and a delay occurs even in the case of an inverter formed of a P type as shown in FIG.

On the other hand, a method of increasing Vgs may be used to eliminate the reset delay. That is, in the N-type inverter shown in Fig. 1A, a method in which a voltage higher than VGH is input as the high voltage of the reset signal to make Vgs > 0 reduces the reset delay. However, this method causes a problem that one more voltage source should be used.

In addition, even in the case of the P-type inverter shown in Fig. 2A, when the same method as the above method is used to eliminate the reset delay, Vgs <0 can be reduced to reduce the reset delay. It causes a problem that one more voltage source should be used.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object of the present invention is to provide an inverter that receives a reset signal and boosts a voltage input to a gate of a reset transistor.

In accordance with an aspect of the present invention, an inverter includes: an input transistor (T1) for outputting a first output signal having a level inverted from an input signal; A reset transistor (T2) for outputting a second output signal at the same level as the input signal by a reset signal after the first output signal; And a boosting unit configured to increase or decrease a gate voltage of the reset transistor by using the reset signal than a voltage applied to a source of the reset transistor.

According to the above solution, the present invention provides the following effects.

That is, the present invention provides an effect of improving the delay of the inverted signal by boosting the voltage input to the gate node of the reset transistor by receiving the reset signal.

In addition, the present invention improves the characteristics of the gate driver and the inverter driver using the inverter by improving the rising or falling delay of the inverter, thereby increasing the reliability of the display and reducing the driving voltage width of the display. -Reduces power consumption by eliminating the need for a step-up circuit to increase the drive voltage in the IC.

In addition, when the driving voltage level (VGH ~ VGL) is reduced to improve power consumption, the conventional inverter may cause a malfunction of the driving circuit or affect the image quality of the display due to the relatively increased delay. In the case of the display having the inverter circuit according to the present invention, the delay is greatly improved to prevent the malfunction of the driving circuit or the deterioration of the image quality.

In addition, the present invention provides the effect of not having to provide an additional voltage source.

1 and 2 are exemplary diagrams showing a circuit configuration of an inverter conventionally used.
3A and 3B are exemplary views showing a configuration and waveforms of an inverter according to a first embodiment of the present invention.
4A to 4B are exemplary views showing the configuration and waveforms of an inverter according to a second embodiment of the present invention.
5 is an exemplary view showing a configuration and waveforms of an inverter according to a third embodiment of the present invention.
6 is an exemplary view showing a configuration and waveforms of an inverter according to a fourth embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3A and 3B are exemplary views showing the configuration and waveforms of the inverter according to the first embodiment of the present invention. Hereinafter, various embodiments of the present invention configured as a P-type thin film transistor will be described, but the present invention may be configured as an N-type thin film transistor.

As shown in FIG. 3A, the inverter according to the first embodiment of the present invention includes a reset transistor T2, an input transistor T1, and a boosting unit 100.

The reset transistor T2 has a charge voltage input terminal 200 for inputting a charge voltage having the same voltage level as the voltage level of the input signal input from the input terminal to a source, and an output terminal 300 at the drain node. And a drain of the input transistor T3 is connected, and one side of the boosting part 100 is connected to the gate. Here, the charging voltage input terminal applies the low level voltage VGL because the inverter shown in FIG. 3A is configured of the P type, but the high level voltage may be applied to the N type inverter. Therefore, hereinafter, the present invention will be described as the charging voltage input terminal applying the low level voltage VGL. That is, the charging voltage input through the charging voltage input terminal has the same voltage level as the input signal, and performs a function of outputting the second output signal having the same level as the input signal through the reset transistor. In addition, in the following description, a charging voltage means the voltage which can turn on a transistor, and a discharge voltage means the voltage which turns off a transistor. Therefore, since the present invention has been described using the P-type inverter as an example, the charging voltage in the following description refers to a low level voltage (VDD = VGL), and the discharge voltage refers to a high level voltage. (VSS = VGH). Therefore, in the case of P type, the opposite voltage is input.

In the input transistor T1, a discharge voltage input terminal 400 for inputting a voltage opposite to the voltage level of an input signal input from the input terminal is connected to a source, and an output terminal 300 and a drain node are connected to a source. The drain of the reset transistor T1 is connected, and the input terminal 500 is connected to the gate. Here, the discharge voltage input terminal 400 applies a high level voltage VGH since the inverter shown in FIG. 3 is configured as a P type, but in the case of an N type inverter, a low level voltage is applied. Can be. Therefore, hereinafter, the present invention will be described as the discharge voltage input terminal applying the high level voltage VGH. That is, the discharge voltage input through the discharge voltage input terminal has a voltage level inverted from the input signal and performs a function of outputting a first output signal having a level inverted from the input signal through the input transistor. That is, a first output signal having a level inverted from the input signal is output through the input transistor at the same time as the input signal is input, and then a second output signal having the same level as the input signal through the reset transistor driven by the reset signal. Is output.

The boosting unit 100 performs a function of lowering the gate voltage of the reset transistor T2 using the reset signal input from the reset signal input terminal 600. The boosting unit 100 receives an input signal and receives a gate of the reset transistor T2. The boosting input transistor T4 for lowering the voltage, the capacitor C1 for storing the voltage of the reset signal, the capacitor C1 are connected to the gate, and the gate of the reset transistor T2 is connected to the drain to apply the reset signal. And a boosting transistor T5 for boosting the voltage level input to the capacitor C1 to instantly lower the gate voltage of the reset transistor T2.

That is, the boosting unit 100 applied to the inverter according to the first embodiment of the present invention as described above is to increase the driving margin of the display by reducing the reset delay, and is connected to the gate of the reset transistor T2 and reset. Two transistors (T5, T4) and one capacitor (C1) for receiving a signal to boost the voltage of the gate of the reset transistor may be composed.

Meanwhile, the overall configuration of the inverter according to the first embodiment of the present invention including the boosting unit as described above is as follows.

That is, the inverter according to the first embodiment of the present invention includes an input transistor T1 and a first output signal VGH which output a first output signal VSS = VGH which is inverted from the voltage level of the input signal by the input signal. Reset transistor T2 connected in series with T1 outputting a second output signal (VDD = VGL), a gate node (“B” node) and a discharge voltage input terminal 400 (VSS = VGH) of T2. VSS (VGH) connected to the input signal, the transfer transistor T3 and the input terminal 500 for inputting the VSS (VGH) to the gate node ("B" node) of T2 which outputs the second output signal (VDD = VGL). Boosting input transistor (T4) connected to the gate and the source by the diode connection method, the drain and reset signal (CLK) of the T4 connected via the diode connection method, the capacitor (C1) connected to the input terminal 600 and T4 connected by the diode connection method Is connected to the gate node ("B" node) of T2 which outputs the drain of VDD and VDD and Is configured to include a boosting transistor (T5) is driven. Here, the transfer transistor T3 may not be provided.

According to the first embodiment of the present invention configured as described above, the discharge voltage (VSS = VGH) is output as the first output signal by the input signal (low level voltage = charge voltage), and the voltage level of the input signal is increased after a delayed time. When the voltage level of the input signal is changed, the voltage level of the input signal is boosted by the reset signal CLK and the capacitor and applied as the gate node voltage of T2 which outputs the VDD (VGL) as the second output signal.

In addition, the first embodiment of the present invention can adjust the level of the boosted voltage to the size of C1.

The operation of the inverter according to the first embodiment of the present invention configured as described above is as follows.

First, as shown in FIGS. 3A and 3B, when a low level input signal VDD = VGL is input through the input terminal IN, the signal “B” is turned on through T3 turned on by the input signal. "The node is kept at a high level (discharge voltage VGH), so T2 is turned off. At the same time, since T1 is turned on by the input signal VDD, VGH is output as the first output signal through T1. In addition, as T4 is turned on by the input signal, the input signal (low level) is stored in the node "A" through T4.

Next, as shown in (a) and (b) of FIG. 3B, when the input signal is changed from the low level (VGL = VDD) to the high level (VGH = VSS), T1 and T3 are turned off. . At this timing, as the reset signal is changed from the high level VGH to the low level VGL, and the T5 is turned on, the voltage of the "A" node is output through the T5. At this time, since the "A" node voltage is connected to the reset signal through C1, a boosting effect occurs. As a result, when the reset signal is changed from the high level (VGH) to the low level (VGL), the "A" node voltage and "B""The node voltage drops even lower than the VGL level. As a result, when the low level VGL is output as the second output signal through T2, the gate voltage of T2 is lower than the low level voltage VGL Level, thereby reducing the reset delay in T2.

4A to 4C are diagrams illustrating the configuration and waveforms of an inverter according to a second embodiment of the present invention, wherein two reset signals are input to drive an inverter driven in three phases or four phases. The case is shown.

That is, in the case of an inverter driven by 3-Phase or 4-Phase, the second reset signal input terminal CLK_B may be added to the boosting unit 300 illustrated in FIG. 3.

Accordingly, the inverter according to the second embodiment of the present invention includes a reset transistor T2, an input transistor T1, and a boosting unit 100, as shown in FIG. 3A (a). Here, since the configuration and function of the reset transistor T2 and the input transistor T1 are the same as in the first embodiment, detailed description thereof is omitted.

The boosting unit 100 applied to the second embodiment of the present invention charges the gate voltage of the reset transistor T2 by using the first reset signal input from the first reset signal input terminal CLK_A 610. Boosting input transistor T4 for lowering the gate voltage of the reset transistor T2 by receiving an input signal and for storing the voltage of the reset signal as a function of lowering the charging voltage input from the input terminal 200. It is connected to the capacitor C1 and the capacitor C1 and connected to the gate of the reset transistor T2 to boost the voltage level input to the capacitor C1 when the reset signal is applied to instantaneously increase the gate voltage of the reset transistor T2. The boosting transistor T5 and the source for lowering are connected to the charging voltage input terminal (VGL = VDD) 200, the drain is connected to the drain node of T5 and the gate of T2, and the gate is second. And a voltage holding transistor T6 connected to the reset signal input terminal CLK_B.

The overall configuration of the inverter according to the second embodiment of the present invention including the boosting unit 100 as described above is as follows.

That is, the inverter according to the second embodiment of the present invention has a gate node of T2 that outputs the charging voltage input terminal 200 and VDD (VGL) to the boosting unit applied to the inverter according to the first embodiment ("B"). and a voltage holding transistor T6 connected between the nodes to maintain and reset the gate voltage of T2 to the VDD level by another input signal CLK_B.

Here, the reset signal for the reset is composed of three phase (Phase), as shown in (b) of Figure 4a, or composed of four phase (Phase) as shown in (c), or two phase It may be configured.

The operation of the inverter according to the second embodiment of the present invention configured as described above is as follows.

First, as shown in FIG. 4A, when an input signal having a charge voltage level (VHL = VDD) is input through the input terminal IN, T3 is turned on by the input signal, and a node “B” is turned high through T3. Is maintained at the level (VGH = VSS), and therefore T2 is turned off. At the same time, since T1 is turned on by the input signal, the discharge voltage (VGH = VSS) is output as the first output signal through T1. In addition, the input signal (low level) is stored in the "A" Node through T4. At this time, since the high level signal (discharge voltage) is input from both the first reset signal input terminal 610 and the second reset signal input terminal 620, T5 and T6 remain off.

Next, as shown in FIG. 4B, when the input signal is changed from the low level VGL to the high level VGH, T1 and T3 are turned off. At this timing, the first reset signal is inputted from the first reset signal input terminal to the low level VGL from the high level VGH, and T5 is turned on by the first reset signal. The voltage at is output through T5. At this time, since the "A" node voltage is connected to the first reset signal through C1, a boosting effect occurs, and eventually "A" when the first reset signal is changed from the high level (VGH) to the low level (VGL). The node voltage and the "B" node voltage will fall even lower than the VGL level. As a result, when the low level VGL is output through the T2 as the second output signal (solid line graph between two grid lines in the OUT graph shown in Fig. 4B, the gate voltage of T2 is the low level voltage). Lower than (VGL Level), the reset delay at T2 is reduced. Meanwhile, during the process, the high level signal is continuously input to the second reset signal input terminal, and thus, T6 is maintained in the off state.

Next, as shown in FIG. 4C, when the input signal is maintained at the high level VGH, T1 and T3 remain in the off state. When the second reset signal is changed from the high level (VGH) to the low level (VGL) and input from the second reset signal input terminal at the timing, T6 is turned on, and therefore, is turned on by the first reset signal. T2, which is maintained at, outputs the VGL as the second output signal while maintaining the ON state continuously even when the first reset signal is changed to the high level.

That is, in the inverter according to the second embodiment of the present invention configured as described above, since T6 is connected between the gate of T2 and the discharge voltage input terminal 200, VGL is set to T2 by the second reset signal CLK_B. While applied to the gate of may help to maintain the second output voltage of the state inverted to the low level at the low level (VGL).

On the other hand, the above has been described with an example in which the inverter according to the second embodiment of the present invention is operated in three phases, the same applies to the case in which the inverter according to the second embodiment of the present invention is operated in four phases. .

That is, as shown in (c) of FIG. 4A, the first output signal inverted to the low level by the first reset signal CLK_A driven in four phases is connected to the second reset signal driven in four phases. As a result, the state of the second output signal at the low level can be maintained continuously.

In other words, when the inverter according to the second embodiment of the present invention is driven in three phases, the low level second output signal inverted by the first reset signal is input immediately after the first reset signal. The low level is maintained by the second reset signal of the low level. However, when the inverter according to the second embodiment of the present invention is driven in four phases, a low level second output signal inverted by the first reset signal is input at a time interval from the first reset signal. The low level is maintained by the second reset signal.

5 is an exemplary view showing a configuration and waveforms of an inverter according to a third embodiment of the present invention.

As shown in FIG. 5, the inverter according to the third embodiment of the present invention includes a reset transistor T2, an input transistor T1, and a boosting unit 100. In the second embodiment, the voltage retention of the node B connected to the gate of T2 is enhanced.

Here, since the configuration and function of the reset transistor T2 and the input transistor T1 are the same as in the first or second embodiment, detailed description thereof is omitted. That is, in the third embodiment of the present invention shown in FIG. 8, T7 and C2 are added to the boosting unit 100 applied to the second embodiment of the present invention, but the configuration described below is used. The same may be applied to the boosting unit applied to the first embodiment of the present invention.

In the boosting unit 100 according to the third embodiment of the present invention, a charge voltage input terminal 200 is connected to a source, a drain C is connected to a capacitor C2 connected to an output terminal, and an output terminal is connected to a gate. The node holding transistor T7 is further included. That is, in the boosting unit applied to the third embodiment of the present invention, the capacitor C2 connected to the output terminal and connected to the node "B" and the second output signal are turned on to maintain the "B" node voltage. And a node holding transistor T7 for inputting VDD (VGL) to the " B " node.

Here, T7 performs a function of receiving a feedback of an output signal and maintaining a "B" node voltage at a charging voltage level (VGL Level). When a second output signal of a low level is outputted, When turned on, it performs the function of keeping node B low.

FIG. 6 is a diagram illustrating a configuration and waveforms of an inverter according to a fourth exemplary embodiment of the present invention, and illustrates an inverter capable of more stably maintaining an output signal of the output terminal illustrated in FIGS. 3 to 5.

As shown in FIG. 6, the inverter according to the fourth embodiment of the present invention includes a reset transistor T2, an input transistor T1, and a boosting unit 100, and according to the third embodiment of the present invention. In this case, the low level output signal can be more stably maintained.

Here, since the configuration and function of the reset transistor T2 and the input transistor T1 are the same as in the first to third embodiments, detailed description thereof is omitted.

That is, the boosting part 100 applied to the fourth embodiment of the present invention includes the leak prevention transistor T8 and the second input transistor T1 'in the boosting part applied to the first to third embodiments. May be configured to include more.

Here, in T8, the charging voltage input terminal 200 is connected to the source, the output terminal is connected to the gate, and the source of the first input transistor T1 is connected to the drain. In addition, the second input transistor T1 ′ is connected between the discharge voltage input terminal (VSS = VGH) 400 and the first input transistor T1 and is turned on or off by receiving an input signal. Thus, the drain of T8 is connected to the node between T1 'and T1. That is, the boosting unit applied to the fourth embodiment of the present invention connects T1 ', which receives an input signal and outputs a discharge voltage VSS, in series with T1, and outputs a second output to an intermediate node between T1 and T1'. T8, which receives a signal as an input and inputs a charging voltage (VDD = VGL) to T1. Here, T8 performs a function of preventing the discharge voltage VSS = VGH from leaking to the output terminal through T1 when the charging voltage VDD = VGL is output to the output terminal.

Therefore, when the discharge voltage (high level signal) is input to the input terminal as the input signal, and the charge voltage (low level signal) is output as the second output signal through the output terminal, the high level voltage (VGH) through the T1. By leaking to the output terminal, a phenomenon in which the second output signal is changed can be prevented.

That is, when the low level voltage VGL is output as the second output signal, T8 is turned on to transmit the low level voltage VGL to a node between T1 and T1 '. At this time, since the high level signal is input through the input terminal to the gates of T1 and T1 ', T1 and T1' are turned off, so the leakage voltage cannot be output to the output terminal in an ideal case, but the performance is degraded. Due to the leakage voltage may be output through the T1.

However, in the case where the fourth embodiment of the present invention is applied, while the leak voltage is output through T1 while the low level is output as the second output signal, the leak voltage is the low level voltage VGL transmitted through T8. The second output signal of the output terminal may be maintained at a low level.

The present invention as described above relates to an inverter included in the driving circuit portion when the driving circuit portion for driving the display is integrated in a panel in a flat panel display such as a liquid crystal display device or an organic light emitting display.

That is, the present invention, when the inverter design using an amorphous silicon (a-Si) or poly-silicon (Poly-Si) thin film transistor, the circuit using the inverter by reducing the rising delay or falling delay after inverting the input signal The operating characteristics of the circuit can be greatly improved, and the operating margin of the circuit can be improved when the power consumption is reduced by reducing the operating voltage of the display.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

100: boosting unit 200: charging voltage input terminal
300: output terminal 400: discharge voltage input terminal
500: input terminal T1: input transistor
T2: reset transistor T3: transfer transistor
T4: boosting input transistor T5: boosting transistor
T6: voltage holding transistor T7: node holding transistor
T8: Leak-proof transistor

Claims (25)

An input transistor T1 for outputting a first output signal at a level inverted from the input signal;
A reset transistor (T2) for outputting a second output signal at the same level as the input signal by a reset signal after the first output signal; And
And a boosting unit configured to increase or decrease a gate voltage of the reset transistor by using the reset signal than a voltage applied to a source of the reset transistor. The method of claim 1,
The boosting unit,
A boosting input transistor (T4) having a gate and a source connected to the input terminal for inputting the input signal by a diode connection method;
A first capacitor C1 connected to a drain of the boosting input transistor T4 and a reset signal input terminal for inputting the reset signal; And
And a boosting transistor (T5) connected to a drain of the boosting input transistor and a gate of the reset transistor (T2) and turned on or off by the reset signal. The method of claim 2,
The boosting unit,
The input signal stored through the boosting input transistor T4 and stored in the first capacitor C1 is boosted by the reset signal to gate the reset transistor T2 through the boosting transistor T5. Inverter characterized in that the input. The method of claim 2,
The boosting unit,
And a transfer transistor (T3) connected to a gate of the reset transistor and a source of the input transistor and turned on or off by the input signal. The method of claim 4, wherein
The transfer transistor T3 is,
And turned on by the input signal input to the input terminal to apply a discharge voltage to the gate of the reset transistor (T2). The method of claim 4, wherein
The boosting unit,
Boosting the input signal stored through the boosting input transistor T4 and stored in the first capacitor C1 and the voltage between the boosting transistor T5 and the reset transistor T2 by the reset signal. And input to the gate of the reset transistor (T2). An input transistor T1 for outputting a first output signal at a level inverted from the input signal;
A reset transistor (T2) for outputting a second output signal having the same level as the input signal by the first reset signal after the first output signal; And
Boosting unit, the boosting unit,
A boosting input transistor (T4) having a gate and a source connected to the input terminal for inputting the input signal by a diode connection method;
A first capacitor C1 connected to a drain of the boosting input transistor T4 and a first reset signal input terminal for inputting the first reset signal;
A boosting transistor (T5) connected to a drain of the boosting input transistor and a gate of the reset transistor (T2) and turned on or off by the first reset signal; And
And a voltage holding transistor (T6) for holding the reset transistor at a charging voltage by a second reset signal input from a second reset signal input terminal. The method of claim 7, wherein
And the first reset signal and the second reset signal are driven in one of two phases, three phases, and four phases. The method of claim 7, wherein
The voltage holding transistor T6 is
An inverter connected between a source and a gate of the reset transistor and turned on or off by the second reset signal. The method of claim 7, wherein
And a transfer transistor (T3) connected to a gate of the reset transistor and a source of the input transistor and turned on or off by the input signal. An input transistor T1 for outputting a first output signal at a level inverted from the input signal;
A reset transistor (T2) for outputting, after the first output signal, a second output signal having the same level as the input signal to an output terminal by a first reset signal; And
Boosting unit, the boosting unit,
A boosting input transistor (T4) having a gate and a source connected to the input terminal for inputting the input signal by a diode connection method;
A first capacitor C1 connected to a drain of the boosting input transistor T4 and a first reset signal input terminal for inputting the first reset signal;
A boosting transistor (T5) connected to a drain of the boosting input transistor and a gate of the reset transistor (T2) and turned on or off by the first reset signal; And
A node connected between the source and the gate of the reset transistor and turned on by the second output signal to maintain the node B between the drain of the boosting transistor T5 and the gate of the reset transistor at a charging voltage. An inverter comprising a sustain transistor (T7). The method of claim 11,
And a second capacitor (C2) is connected between the drain of the node holding transistor (T7) and the output terminal. The method of claim 11,
And a voltage holding transistor (T6) connected between the source and the gate of the reset transistor and turned on or off by the second reset signal. The method of claim 13,
The voltage holding transistor T6 is
And the reset transistor is maintained at a charging voltage by the second reset signal. The method of claim 11,
And a transfer transistor (T3) coupled between the gate of the reset transistor and the source of the input transistor and turned on or off by the input signal. A first input transistor T1 for outputting a first output signal at a level inverted from the input signal;
A reset transistor (T2) for outputting, after the first output signal, a second output signal having the same level as the input signal to an output terminal by a first reset signal; And
Boosting unit, the boosting unit,
A boosting input transistor (T4) having a gate and a source connected to the input terminal for inputting the input signal by a diode connection method;
A first capacitor C1 connected to a drain of the boosting input transistor T4 and a first reset signal input terminal for inputting the first reset signal;
A boosting transistor (T5) connected between a drain of the boosting input transistor and a gate of the reset transistor (T2) and turned on or off by the first reset signal; And
An inverter comprising a leakage prevention transistor (T8) connected between a source of the reset transistor (T2) and a source of the first input transistor (T1). 17. The method of claim 16,
The leakage preventing transistor (T8) is turned on by the second output signal, characterized in that for transferring the charging voltage input to the reset transistor to the source of the first input transistor (T1). 17. The method of claim 16,
And a second input transistor (T1 ') connected between a discharge voltage input terminal for inputting a discharge voltage and a source of the first input transistor (T1) and driven by the input signal. 17. The method of claim 16,
And a transfer transistor (T3) coupled between the gate of the reset transistor and the source of the input transistor and turned on or off by the input signal. 17. The method of claim 16,
And a voltage holding transistor (T6) for holding the reset transistor at a charging voltage by the second reset signal. The method of claim 20,
The voltage holding transistor T6 is
An inverter connected between a source and a gate of the reset transistor and turned on or off by the second reset signal. 17. The method of claim 16,
A node held between the source and the gate of the reset transistor and turned on by the second output signal to maintain the node B between the drain of the boosting transistor T5 and the gate of the reset transistor at a charging voltage. Inverter including transistor (T7). The method of claim 22,
And a second capacitor (C2) is connected between the drain of the node holding transistor (T7) and the output terminal. 17. The method of claim 16,
And the leakage preventing transistor (T8) is turned on by the second output signal. An input transistor T1 for outputting an output signal of a level inverted from the input signal;
A reset transistor T2 for outputting an output signal of the same level as the input signal by the reset signal; And
A boosting input transistor (T4) having a gate and a source connected to the input terminal for inputting the input signal by a diode connection method;
A first capacitor C1 connected to a drain of the boosting input transistor T4 and an input terminal for inputting the reset signal; And
And a boosting transistor (T5) connected to a drain of the boosting input transistor and a gate node of the reset transistor (T2) and turned on or off by the reset signal.

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