KR101666588B1 - Liquid crystal display device and method for driving the same - Google Patents

Abstract

The present invention relates to a liquid crystal display capable of preventing driving using a driving frequency that does not meet product specifications in order to realize an optimum quality and a driving method thereof, A timing controller for outputting a gate control signal and a data control signal including a source start pulse, a gate driver for driving the gate line in response to the gate control signal, and a gate driver for driving the data line in accordance with the data control signal. (N is a natural number), which is formed between the plurality of data drivers and the respective data drivers to sequentially receive the source start pulse, and delay the rise and fall times of the source start pulse outputted from the nth data driver +1) th data driver, The.

Description

Technical Field [0001] The present invention relates to a liquid crystal display (LCD)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD), and more particularly, to a liquid crystal display capable of preventing driving using a driving frequency that does not meet a product standard in order to realize an optimum quality and a driving method thereof.

In recent years, a liquid crystal display (Liquid Crystal Display) has been most widely used because of its excellent image quality, light weight, thinness, and low power.

The liquid crystal display device displays an image by adjusting the light transmittance of liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display device includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel displays an image by adjusting the light transmittance of the liquid crystal according to the pixel signal.

The driving circuit includes a gate driver for driving the gate lines of the liquid crystal panel, a data driver for driving the data lines, a timing controller for controlling the driving timing of the gate driver and the data driver, and a driving circuit for driving the liquid crystal panel and the driving circuit And a power supply unit for supplying power supply signals.

On the other hand, the liquid crystal panel is manufactured by setting a frequency driven in accordance with its use. Accordingly, the timing controller outputs a plurality of control signals corresponding to the driving frequency of the liquid crystal panel set in advance, and supplies it to the gate driver and the data driver.

If the timing controller outputs a plurality of control signals at a wrong driving frequency and supplies them to the gate driver and the data driver, the liquid crystal panel is driven at a driving frequency that does not meet the product specifications, It may cause the product to malfunction.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device and a driving method thereof that can prevent driving using a driving frequency that does not meet product specifications in order to realize an optimum quality.

According to an aspect of the present invention, there is provided a liquid crystal display device including a liquid crystal panel for defining a pixel region at an intersection of a gate line and a data line, a data control signal including a gate control signal and a source start pulse, A gate driver for driving the gate line in response to the gate control signal, a plurality of data drivers for driving the data line in response to the data control signal and sequentially receiving the source start pulse, And a delay unit formed between the data driver and the delay unit for delaying the rising and falling times of the source start pulse output from the nth data driver (n is a natural number) and supplying the delayed time to the (n + 1) th data driver.

And the delay unit includes a plurality of resistors and capacitors to delay the rise time of the source start pulse.

The liquid crystal panel is set to be driven at a reference frequency, and each data driver sets a reference time for recognizing the source start pulse according to the reference frequency.

 And the rise time of the source start pulse delayed in the delay unit is shorter than the reference time when the timing controller outputs the gate control signal and the data control signal set to the same frequency as the reference frequency.

And the rise time of the source start pulse delayed by the delay unit is longer than the reference time when the timing controller outputs the gate control signal and the data control signal set to a frequency higher than the reference frequency.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display including a gate driver for driving a liquid crystal panel, a plurality of data drivers, A first step of outputting, by the timing controller, a gate control signal and a data control signal including a source start pulse, the method comprising the steps of: And a third step of supplying a start pulse sequentially to the (n + 1) th data driver by delaying the rising and falling times of the source start pulse output from the nth data driver (n is a natural number) .

The third step includes delaying the rise and fall times of the source start pulse by providing a plurality of resistors and capacitors.

The liquid crystal panel is set to be driven at a reference frequency, and each data driver sets a reference time for recognizing the source start pulse according to the reference frequency.

When the timing controller outputs the gate control signal and the data control signal set to the same frequency as the reference frequency in the first step, the rise time of the source start pulse delayed in the third step is shorter than the reference time .

When the timing controller outputs the gate control signal and the data control signal set to a frequency higher than the reference frequency in the first step, the rise time of the source start pulse delayed in the third step is longer than the reference time .

The liquid crystal display according to the present invention includes a delay unit for delaying a rise time and a fall time of a source start pulse provided by each data driver. When the timing controller outputs a plurality of data control signals set to a wrong driving frequency, the delay unit causes an error in the image, thereby preventing the user from using the wrong driving frequency. That is, it is possible to improve the stability of the product and realize the optimum image quality by preventing display quality deterioration, shortening of life time, malfunction, or product malfunction which can be caused by using a driving frequency that does not meet the product standard by the user.

1 is a configuration diagram of a liquid crystal display device according to an embodiment of the present invention;
2 is a configuration diagram of the data driver and the delay unit shown in FIG.
3 is a configuration diagram of the first delay unit shown in Fig.
Fig. 4 is an input and output waveform diagram of the first delay unit shown in Fig. 3; Fig.

Hereinafter, a liquid crystal display device and a driving method thereof according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a liquid crystal display device according to an embodiment of the present invention.

1 includes a liquid crystal panel 2 that defines pixel regions at the intersections of a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, A timing controller 8 for outputting a control signal DCS, a gate driver 6 for driving a plurality of gate lines GL1 to GLn in accordance with a gate control signal GCS, And a data driver 4 for driving the plurality of data lines DL1 to DLm.

1 includes a delay unit 10 connected to the data driver 4 to delay a source start pulse SSP supplied from the data driver 4, . The delay unit 10 prevents the timing controller 8 from supplying the data driving unit 4 with the data control signal DCS of the wrong driving frequency. The delay unit 10 will be described later.

The liquid crystal panel 2 includes a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm. The plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm define respective pixel regions. Each pixel region includes a thin film transistor (hereinafter referred to as TFT), a liquid crystal capacitor Clc connected to the TFT, and a storage capacitor Cst. The liquid crystal capacitor Clc includes a pixel electrode connected to the TFT and a common electrode for applying an electric field to the liquid crystal together with the pixel electrode. The TFT supplies a video signal from each data line DLj (j = 1 to m) to the pixel electrode in response to a scan pulse supplied from each gate line GLi (i = 1 to n). The liquid crystal capacitor Clc charges the difference between the video signal supplied to the pixel electrode and the common voltage Vcom supplied to the common electrode and varies the arrangement of the liquid crystal molecules according to the difference voltage to adjust the light transmittance, . The storage capacitor Cst is connected in parallel with the liquid crystal capacitor Clc so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next video signal is supplied.

The timing controller 8 controls the timing of driving the gate driver 6 and the data driver 4. [ More specifically, the timing controller 8 controls the timing controller 8 using a plurality of synchronous signals (HSync, VSync, dot clock DCLK, and data enable signal DE) And generates and outputs a control signal GCS and a plurality of data control signals DCS. Further, the timing controller 8 aligns the image data (RGB) according to the driving of the liquid crystal panel and supplies it to the date driver.

The plurality of gate control signals GCS include a clock pulse and a gate start pulse (GSP) for instructing the gate driver 6 to start driving. The clock pulse includes a plurality of clock pulses having a phase difference, for example, a 2-phase, 3-phase, 4-phase, or 6-phase clock pulse.

The plurality of data control signals DCS includes a source output enable (SOE) for controlling the output period of the data driver 4, an SSP for instructing the start of data sampling, a source shift A source shift clock (SSC), a polarity control signal for controlling voltage polarity of data, and the like.

The gate driver 6 sequentially supplies scan pulses to the plurality of gate lines GL1 to GLn using a plurality of gate control signals GCS provided from the timing controller 8. [

The data driver 4 converts the video data Data input from the timing controller 8 into a video signal using the reference gamma voltage in accordance with a plurality of data control signals DCS provided from the timing controller 8, And supplies the video signal to the plurality of data lines DL1 to DLm.

Hereinafter, the data driver 4 and the delay unit 10 will be described in more detail.

2 is a configuration diagram of the data driver and the delay unit shown in FIG.

Referring to FIG. 2, the data driver 4 includes at least two data drivers. Here, the number of the data driver units may be two or more, and any one of them may be used. In the following description, three data driver units are provided.

On the other hand, the data driver 4 generates a sequential sampling signal while shifting the SSP provided from the timing controller 8 in accordance with the source shift clock in one horizontal period. The data driver 4 sequentially latches the video data Data input from the timing controller 8 in response to the sampling signal. The data driver 4 latches the image data of one horizontal line sequentially latched in one horizontal period in parallel in the next horizontal period, converts the image data into a video signal, and supplies it to the data lines DL1 to DLm.

Each of the data driver 4 receives SSPs sequentially. To this end, each of the data drivers 4a, 4b, and 4c receives the SSP from the previous data driver, outputs the SSP again, and supplies the SSP to the next data driver. The first data driver 4a as the first data driver receives the SSP from the timing controller 8 and the third data driver 4c as the last data driver outputs the SSP supplied from the second data driver 4b I never do that.

Meanwhile, the delay unit 10 delays the rising and falling times of the SSPs output from the data drivers 4a, 4b, and 4c and supplies the delayed data to the next data driver. Therefore, the delay unit 10 includes the first and second delay units 10a and 10b, which are smaller than the number of the data driver units 4 by one. That is, when the number of data drivers 4 is k (k? 2, k is a natural number), the number of delay units 10 is k-1.

That is, the first data driver 4a receives the SSP from the timing controller 8 and outputs it to the first SSP (SSP1). The first delay unit 10a receives the first SSP (SSP1) from the first data driver 4a and outputs a first delayed SSP (MSSP1) delayed by the first SSP (SSP1). The second data driver 4b receives the first delay SSP (MSSP1) from the first delay unit 10a and outputs it to the second SSP (SSP2). The second delay unit 10b receives the second SSP (SSP2) from the second data driver 4b and outputs a second delayed SSP (MSSP2) delayed by the second SSP (SSP2). The third data driver 4c receives the second delay SSP (MSSP2) from the second delay unit 10b. Accordingly, the path through which the SSP provided from the timing controller 8 is supplied to each of the data drivers 4a, 4b and 4c is the first data driver 4a -> the first delay unit 10a -> the second data driver 4b -> second delay unit 10b -> third data driver 4c.

The delay unit 10 includes a circuit having a plurality of resistors and capacitors for delaying the rise and fall times of the SSPs output by the data drivers 4a, 4b, and 4c, or a circuit having a TFT or OP-Amp A switching circuit may be provided, and a circuit having a plurality of resistors and capacitors will be described below by way of example.

FIG. 3 is a configuration diagram of the first delay unit shown in FIG. 2, and FIG. 4 is an input and output waveform diagram of the first delay unit shown in FIG.

Referring to FIG. 3, the first delay unit 10a includes a delay resistor R and a delay capacitor C. The delay resistor R is connected in series with the signal line to which the first SSP SSP1 is supplied and the delay capacitor C is connected in parallel with the signal line to which the first SSP SSP1 is supplied.

Then, the first SSP SSP1 is delayed according to the time constant RC of the delay capacitor R and the delay capacitor R connected to the signal line of the first SSP SSP1. 4, the first delay unit 10a includes a first delay SSP (delay unit) having a delayed rise time and a fall time according to the time constant RC of the delay resistor R and the delay capacitor C, MSSP2. That is, the rise and fall times (RT2 and DT2) of the first delay SSP (MSSP2) are longer than the rise and fall times (RT1 and DT1) of the first SSP (SSP1).

On the other hand, the liquid crystal panel 2 is manufactured by presetting a frequency to be driven in accordance with its use. The timing controller 8 outputs a plurality of gate control signals GCS and a plurality of data control signals DCS corresponding to the driving frequency of the liquid crystal panel set in advance and supplies them to the gate driver 6 and the data driver 4 . Here, for convenience of description, it is assumed that the liquid crystal panel 2 of the liquid crystal display device according to the embodiment of the present invention is set to be driven at a driving frequency of 60 Hz.

The second reference time ST2 shown in FIG. 4 is a reference time at which the SSP is recognized when the liquid crystal panel 2 is driven at 60 Hz. That is, the rising time of the SSP must be shorter than the second reference time (ST2) so that the SSP can be correctly recognized.

If the timing controller 8 outputs a plurality of data control signals DCS set to 60 Hz corresponding to 60 Hz set in the liquid crystal panel 2, the rise time RT1 of the first SSP (SSP1) 1 rise time RT2 of the delay SSP1 (MSSP1) is shorter than the second reference time ST2. Therefore, the first and second data drivers 4a and 4b correctly recognize the SSPs, and the images are normally displayed. For this, the rise time of the SSP, the first delay SSP (MSSP1), and the second delay SSP (MSSP2) provided by the respective data drivers 4a, 4b and 4c is preferably shorter than the second reference time ST2 Do. That is, the delay time of the delay resistor R and the time constant RC of the delay capacitor C in the delay unit 10 should be set so that the rise time of the delayed SSPs is shorter than the second reference time ST2.

On the other hand, when the timing controller 8 outputs a plurality of data control signals DCS set to a wrong driving frequency, for example, 120 Hz, although the liquid crystal panel 2 is set to be driven at 60 Hz, The reference time becomes the first reference time ST1 shorter than the second reference time ST2. Then, SSPs whose rising time is shorter than the first reference time (ST1) among the SSPs are recognized correctly. Therefore, since the rising time RT1 of the first SSP SSP1 is shorter than the first reference time ST1, the first data driver 4a recognizes the SSP correctly. However, since the rise time RT2 of the first delay SSP (MSSP1) is longer than the first reference time ST1, the second data driver 4b receiving it does not correctly recognize the first delay SSP (MSSP1) . Similarly, the third data driver 4c, which is dependent on the second data driver 4b, does not correctly recognize the second delay SSP (MSSP2). Then, the data line group depending on the second and third data drivers 4b and 4c is supplied with a wrong video signal, and an error occurs in the video image output from the liquid crystal panel 2. [

이고, 구동주파수가 60Hz이고, 8 비트 단위로 신호가 전송된다면 RGB 각각의 화소 영역을 구동하는데 필요한 시간은

가 된다. 따라서, 각 데이터 구동부(4a, 4b, 4c)가 SSP를 인식하는 제 2 기준시간(ST2)는

가 되는 것이 바람직하다.On the other hand, the driving frequency of the liquid crystal panel 2 is a number indicating how many times each pixel region of the liquid crystal panel 2 is driven per second. For example, if the driving frequency set to the liquid crystal panel 2 is 60 Hz, each pixel region is driven 60 times per second. If the resolution of the liquid crystal panel 2 is

, The driving frequency is 60 Hz, and the signal is transmitted in units of 8 bits, the time required to drive each pixel region of RGB is

. Therefore, the second reference time ST2 at which each data driver 4a, 4b, 4c recognizes the SSP

.

As described above, the liquid crystal display according to the embodiment of the present invention includes the delay unit 10 for delaying the rising time and the falling time of the SSP provided by the second and third data drivers 4b and 4c. When the timing controller 8 outputs a plurality of data control signals DCS set to an erroneous driving frequency, the delay unit 10 causes an error in the image, thereby preventing the user from using the wrong driving frequency. That is, the user can improve the stability of the product and realize the optimum quality by preventing display quality deterioration, shortening of life time, malfunction, or product malfunction which can be caused by using a driving frequency that does not meet the product standard.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

2: liquid crystal panel 4: data driver
6: Gate driver 8: Timing controller
10:

Claims (10)

A liquid crystal panel defining an intersecting pixel region of a gate line and a data line;
A timing controller for outputting a gate control signal and a data control signal including a source start pulse;
A gate driver for driving the gate line according to the gate control signal;
A plurality of data drivers for driving the data lines according to the data control signals and sequentially receiving the source start pulses; And
And a delay unit formed between each of the data drivers and delaying the rise and fall times of the source start pulse output from the nth data driver (n is a natural number) and supplying the delayed rise and fall times to the (n + 1)
Wherein when the timing controller outputs a data control signal set to a wrong driving frequency, the delay unit lengthens the rising time of the source start pulse from a reference time for recognizing the source start pulse set according to the erroneous driving frequency, So that an error occurs in the image. The method according to claim 1,
The delay unit
And a plurality of resistors and capacitors for delaying the rising time of the source start pulse. 3. The method of claim 2,
Wherein the liquid crystal panel is set to be driven at a reference frequency, and each of the data drivers sets a reference time for recognizing the source start pulse according to the reference frequency. The method of claim 3,
Wherein the rise time of the source start pulse delayed by the delay unit is shorter than the reference time when the timing controller outputs the gate control signal and the data control signal set to the same frequency as the reference frequency. The method of claim 3,
Wherein the rise time of the source start pulse delayed by the delay unit is longer than the reference time when the timing controller outputs the gate control signal and the data control signal set to a frequency higher than the reference frequency. A driving method of a liquid crystal display device including a gate driver for driving a liquid crystal panel, a plurality of data drivers, and a timing controller for controlling driving timings of the gate driver and the plurality of data drivers,
A first step of outputting a gate control signal and a data control signal including a source start pulse in the timing controller;
A second step of sequentially supplying the source start pulse to the plurality of data drivers;
(n is a natural number), and supplies the delayed rise time and the fall time of the source start pulse to the (n + 1) th data driver. When the timing controller outputs the data control signal set to the wrong drive frequency And a third step of causing an error in the displayed image by lengthening the rise time of the source start pulse from a reference time for recognizing the source start pulse set in accordance with the erroneous driving frequency, Way. The method according to claim 6,
In the third step,
And a step of delaying the rise and fall times of the source start pulse by providing a plurality of resistors and capacitors. The method according to claim 6,
Wherein the liquid crystal panel is set to be driven at a reference frequency, and each data driver sets a reference time for recognizing the source start pulse according to the reference frequency. 9. The method of claim 8,
In the first step
When the timing controller outputs the gate control signal and the data control signal set to the same frequency as the reference frequency, the rise time of the source start pulse delayed in the third step is shorter than the reference time . 9. The method of claim 8,
In the first step
When the timing controller outputs the gate control signal and the data control signal set to a frequency higher than the reference frequency, the rise time of the source start pulse delayed in the third step is longer than the reference time .

Images