KR101666578B1 - Driving circuit for image display device and method for driving the same - Google Patents

Abstract

The present invention relates to a driving apparatus for a video display device and a driving method thereof, which can further improve display image quality while reducing power consumption by applying a data line charge sharing technique according to the degree of gradation of video data A display panel having a plurality of pixel regions to display an image; A plurality of gate integrated circuits for driving the respective gate lines of the display panel; And a display panel for displaying the image data of the current line and the image data of the previous line, wherein the image data of the current line is input every horizontal line when the data lines of the display panel are driven, A plurality of data integration circuits; And a timing controller for controlling the driving timing of each of the gates and the data integrated circuits.

Liquid crystal display, charge share, inversion driving method,

Description

TECHNICAL FIELD [0001] The present invention relates to a driving apparatus for a video display device and a driving method thereof. BACKGROUND OF THE INVENTION [0002]

The present invention relates to a driving apparatus for a video display device and a driving method thereof, which can further improve display image quality while reducing power consumption by applying a data line charge sharing technique according to the degree of gradation of video data .

Description of the Related Art [0002] In recent years, lightweight thin flat panel displays have been mainly used as image display devices used in monitors for personal computers, portable terminals, and various information devices. As such flat panel display devices, a liquid crystal display, a light emitting display, a plasma display panel, a field emission display, and the like are emerging.

The flat panel display devices include a display panel in which a plurality of pixel cells are arranged and a driving circuit for driving the display panel so that the image is displayed on the display panel by the driving circuit.

In recent years, in order to further improve the display quality of an image, that is, the image quality of a display image, a version driving method and a charge share technique are further applied when driving a display panel. Herein, the inversion driving method is a driving method of inverting the polarity of the data voltage supplied to each data line of the display panel, and the charge sharing technique shortens all of the data lines during the initial period of every horizontal period in which the data voltage is supplied, To be shared. When the charge sharing technique is applied while inverting the polarity of the data voltage applied to each pixel cell in units of horizontal lines, it is possible to prevent the display failure due to the horizontal crosstalk phenomenon or the afterimage and reduce the power consumption.

However, in recent years, in order to realize a high-quality image, a driving frequency is increased, and a large-sized display panel of a large screen is being developed. Thus, a data voltage is not fully charged when charge sharing technology is applied. Specifically, in the case of a high-resolution display panel of a large screen or a display panel which is driven by increasing the driving frequency, the period during which the data voltage is charged, that is, every horizontal period becomes short. If the data voltage charging period is shortened, the next data voltage is supplied to the next pixel cell even before the data voltage is charged to the target voltage. In particular, when an image having a large gradation change amount, that is, an image having a high gradation, is displayed, the phenomenon of non-filling is more conspicuously caused by the polarity inversion of each data voltage, so that the image quality of the display image is further reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a driving apparatus and a driving method of a video display device capable of further improving display image quality while reducing power consumption by applying a data line charge sharing technique according to the degree of gradation of image data And a driving method thereof.

According to an aspect of the present invention, there is provided an apparatus for driving an image display apparatus including a display panel having a plurality of pixel regions to display an image; A plurality of gate integrated circuits for driving the respective gate lines of the display panel; And a display panel for displaying the image data of the current line and the image data of the previous line, wherein the image data of the current line is input every horizontal line when the data lines of the display panel are driven, A plurality of data integration circuits; And a timing controller for controlling the driving timing of each of the gates and the data integrated circuits.

Each of the data integrated circuits is provided to correspond to each of the data lines and drives each of the data lines according to the image data and adds the current line image data of the image data and the image data of the previous line, A plurality of channel units for generating data, and sequentially receiving the addition data from the plurality of channel units and comparing the analyzed data with reference data to determine whether to perform charge sharing, And a charge share controller for generating and sharing the data lines during a charge sharing period during the horizontal period according to the charge share control signal.

Wherein each of the plurality of channel units includes: a shift register for outputting a sampling signal in response to a data control signal from the timing controller; a sampling circuit for sampling the image data in the current line data according to the sampling signal, A second latch unit for sampling the current line data input from the first latch unit in accordance with the sampling signal with previous line data and outputting data of a previous line that has been sampled according to the sampling signal, A latch circuit for latching the first data line and the second data line and for outputting the analog data voltage to the latch circuit; The current line data of the latch unit and the second line Characterized in that by adding the previous line data generated by the added data comprises adding portion for supplying it to the charge share controller portion.

Wherein the charge share controller sequentially receives the addition data from the plurality of channel units and detects maximum data having a maximum gray level value among the addition data for every horizontal line, A comparator for comparing the reference data with a charging selection signal for determining whether to perform charge sharing according to the comparison result, and a comparator for comparing the charging selection signal from the charging start signal of the gate high- And outputting a charge-share selection signal for performing or suspending charge-sharing in every horizontal period.

Wherein the maximum value detector comprises: a selection unit for updating one of the addition data sequentially input from the plurality of channel units and the previous data detected as the maximum data to maximum data and outputting as the selection data; A flip-flop unit for storing the maximum data among the addition data for every horizontal line by storing the selection data inputted from the flip-flop unit as the maximum data, A first subtractor for subtracting the data from the first subtractor and outputting a result of the subtraction; and a second subtracter for storing the previously stored maximum data as it is or the newly added sum data as the maximum data according to a subtraction result from the first subtracter And supplies the update selection signal to the selection unit And a selection control unit.

According to another aspect of the present invention, there is provided a method of driving an image display apparatus including driving a gate line of a display panel having a plurality of pixel regions to display an image, Driving each data line of the display panel; And comparing the video data of the current line inputted in every horizontal line unit with the video data of the previous line when each data line of the display panel is driven and occupying the data lines in the charge sharing period during the horizontal line period And a step of sharing.

Wherein the step of charge sharing the data lines comprises the steps of generating current data by adding current line image data of the image data and image data of a previous line through a plurality of channel units respectively corresponding to the data lines, Calculating and outputting a charge share control signal in units of horizontal periods in accordance with whether to perform the charge sharing by comparing and analyzing the addition data sequentially with reference data, And charge-sharing the data lines during a charge sharing period during a horizontal period.

Wherein the step of generating the addition data comprises the steps of outputting a sampling signal in response to a data control signal from a timing controller, sampling the image data in accordance with the sampling signal as current line data, Sampling the current line data input from the first latch unit according to the sampling signal with the previous line data and outputting data of the previous line that has been sampled, outputting the previous line data from the second latch unit, Converting the data into analog data voltages and outputting the analog data voltages; amplifying the data voltages and supplying the amplified data voltages to the corresponding data lines; and adding the current line data and the previous line data to generate and output the added data And All.

Wherein the step of generating and outputting the charge share control signal comprises the steps of sequentially receiving the addition data and detecting maximum data having a maximum gray level value among the addition data for every horizontal line, Generating and outputting a charging selection signal for determining whether or not charge sharing is to be performed according to the comparison result, and performing a logical multiplication operation between the charging start signal of the gate high level and the charging selection signal to perform charge sharing Or outputting a charge share selection signal for stopping each horizontal period unit.

Wherein the step of detecting the maximum data includes the steps of updating any one of the sum data and the previous data detected as the maximum data to maximum data and outputting the selected data as selection data, Storing and outputting the maximum data among the addition data of every horizontal line, subtracting the sum data and the maximum data and outputting the subtraction result, and outputting the maximum data stored previously according to the subtraction result And generating and outputting an update selection signal so as to store the update data as it is, or to update and store newly added sum data as the maximum data.

According to an embodiment of the present invention, a driving apparatus and a driving method of the image display apparatus according to the present invention can improve the display quality while reducing power consumption by applying a data line charge sharing technique according to the degree of gradation of image data . Therefore, the charge share technology can be more easily applied to the display panel of high resolution and high image quality on a large screen.

In addition, since each data integration circuit can analyze the image data and apply the charge sharing technology, it is possible to reduce the manufacturing cost of the image display device by reducing the separate control signal transmission line or transmission pin for controlling each data integration circuit It can also be saved.

Hereinafter, a driving apparatus and a driving method thereof according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a video display device according to an embodiment of the present invention.

1 includes a display panel 2 having a plurality of pixel regions and displaying an image; A display panel (2) a plurality of gate integrated circuits (3) for driving the respective gate lines (GL1 to GLn); The image data of the current line inputted in every horizontal line unit and the image data of the previous line when the data lines DL1 to DLm of the display panel 2 are driven are compared with each other, A plurality of data integration circuits (4) charge-sharing the data lines (DL1 to DLm) during a period; And a timing controller 10 for controlling the driving timings of the gates and the data integrated circuits 3, 4.

The image display device constructed as above may be applied to a liquid crystal display, a field emission display, a plasma display panel and an organic light emitting display, . However, only one example applied to a liquid crystal display device will be described in detail below.

The display panel 2 may be a liquid crystal panel. The liquid crystal panel 2 is formed in each pixel region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm. A thin film transistor (TFT), and a liquid crystal capacitor Clc connected to the TFT. The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT, and a common electrode arranged between the pixel electrode and the liquid crystal. The TFT supplies a video signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the video signal supplied to the pixel electrode and the reference common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage to implement the gradation . The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied. The storage capacitor Cst may be formed by overlapping the pixel electrode with the previous gate line with the insulating film interposed therebetween, or the pixel electrode may be formed by overlapping the storage line with the insulating film interposed therebetween.

The gate integrated circuits 3 for driving the gate lines GL1 to GLn of the liquid crystal panel 2 are mounted on the respective printed circuit films 5 to be connected to one side of the liquid crystal panel 2, 2).

Each of the gate integrated circuits 3 constructed as described above is controlled by a gate control signal from the timing controller 10, for example, a gate start pulse (GSP), a gate shift clock (GSC) And a gate output enable (GOE) signal or the like to supply a scan pulse or a gate low voltage to each of the gate lines GL1 to GLn. In other words, each of the gate integrated circuits 3 shifts the GSP from the timing controller 10 according to the GSC, and sequentially supplies a scan pulse of a gate high voltage to each of the gate lines GL1 to GLn. A gate low voltage is supplied during a period in which no scan pulse is supplied to each of the gate lines GL1 to GLn.

The data integrated circuits 4 for driving the data lines DL1 to DLm of the liquid crystal panel 2 are mounted on the respective printed circuit films 6 and are connected to the other side of the liquid crystal panel 2, (2) and the source printed circuit board (8). In this case, each of the plurality of data integrated circuits 4 is electrically connected to the timing controller 10 via the printed circuit film 6, the source printed circuit board 8, and the like. Here, the number of the gate and data integrated circuits (3, 4) is not limited to the number shown in FIG.

The data integration circuit 4 includes a data control signal from the timing controller 12 such as a source start signal SSP, a source shift clock SSC, a source output enable signal SOE, Source Output Enable) signal to the data lines DL1 to DLm. In other words, each of the data integrated circuits 4 latches the digital image data input according to the SSC, and outputs the digital image data in units of horizontal lines in response to the SOE signal input through the timing controller 10. At this time, the data integration circuit 4 converts the video data of the horizontal line unit into an analog video signal, that is, a data voltage and outputs it.

The data integration circuit 4 compares the latched image data with the image data of the current line and the previous line unit, that is, the image data of the current line with the image data of the previous line. In accordance with the comparison result, the data lines DL1 to DLm are all short-circuited during the charge sharing period, which is an initial period of the horizontal line period, to charge-share the data lines DL1 to DLm. To this end, the data integration circuit 4 is provided with an adding unit for comparing the image data of the current line with the image data of the previous line, and a charge sharing unit for shortening both the charge sharing controller and the data lines DL1 to DLm Respectively. The data integrated circuit 4 of the present invention constructed and operated as described above will be described in detail with reference to the accompanying drawings hereinafter.

The timing controller 10 arranges image data from an external system (not shown) so as to be suitable for driving the liquid crystal panel 2, and supplies the image data to the data integration circuit 4. [ Then, a gate control signal and a data control signal are generated using external synchronization signals, and the respective data integrated circuits 4 and the gate integrated circuits 3 are controlled using the generated gate control signals and data control signals.

FIG. 2 is a configuration diagram specifically showing the data integrated circuit shown in FIG. 1. FIG.

Each of the data integrated circuits 4 shown in FIG. 2 is provided to correspond to each of the data lines DL1 to DLm and drives each of the data lines DL1 to DLm according to the video data, A plurality of channel units (CH1 to CHn) for adding the line image data and the image data of the previous line to generate the addition data, and a plurality of channel units (CH1 to CHn) A charge share controller 50 for determining whether or not to perform charge sharing and generating and outputting a charge share control signal in units of horizontal periods in accordance with the execution of the charge sharing, And a charge sharing section CSB for charge-sharing the data lines DL1 to DLm.

Each of the plurality of channel units CH1 to CHn is provided to correspond to each of the data lines DL1 to DLm to convert image data input in every horizontal line into an analog data voltage, DL1 to DLm. Here, each of the channel units CH1 to CHn sequentially stores the image data of the previous line and the current line, and then sequentially converts and outputs the image data of the previous line and the current line, Thereby generating and outputting the addition data.

The charge share controller 50 sequentially receives the addition data from the plurality of channel units CH1 to CHn and detects the maximum data having the maximum gray level value among the addition data for every horizontal line. Then, the detected maximum data is compared with preset reference data, and whether charge sharing is performed is determined according to the comparison result. If it is determined that charge sharing is to be performed, the charge share control signal is generated and output in every horizontal period according to the determination.

This is because if the maximum data having the maximum gradation value is determined to be larger than the reference data, it is determined that the gradation change width is large and the charge sharing operation is not performed. In this case, even if the polarity is inverted and the variation width of the data voltage supplied to each of the data lines DL1 to DLm becomes large, it is charged for one horizontal period, so that the non-charging phenomenon can be prevented. On the other hand, if it is determined that the maximum data having the maximum gradation value is smaller than the reference data, the charge sharing operation is performed. In this case, since the variation width of the data voltage is not large, the charging amount is sufficient even after performing the charge sharing operation, so that the power consumption can be reduced.

The charge sharing unit CSB shorts all the data lines DL1 to DLm in the charge sharing period during the horizontal period according to the charge sharing control signal CS to charge-share the data lines DL1 to DLm do. The charge share (CSB) may be embedded in the data integration circuit 4 or may be configured separately.

More specifically, the charge share section CSB includes a plurality of charging switches SW1 to SWn for charge-sharing the plurality of data lines DL1 to DLm in accordance with the charge share control signal CS from the charge- Respectively.

The plurality of charging switches SW1 to SWn are provided between the odd-numbered data lines DL1 to DLm-1 and the even-numbered data lines DL2 to DLm, respectively, between the data lines DL1 to DLm. The plurality of charging switches SW1 to SWn are turned on during a charge sharing period which is an initial period of a horizontal period, for example, a period in which a charge sharing control signal CS of a high level is input, To DLm are all short-circuited. At this time, the data lines DL1 to DLm are charged to the average voltage of the charge share, that is, the data lines DL1 to DLm. Here, the charging switches SW1 to SWn may include at least one NMOS or PMOS transistor. In addition, the switching circuits SW1 to SWn may be configured to charge-share each data line DL1 to DLm in accordance with the charge- May be used.

Each of the plurality of channel units CH1 to CHn shown in FIG. 2 includes a shift register 41 for outputting a sampling signal in response to a data control signal from the timing controller 10, A first latch unit for sampling the data from the first latch unit and outputting the current line data sampled according to the data control signal, and a second latch unit for sampling the current line data input from the first latch unit according to the sampling signal, A digital-to-analog converter (DAC) 44 for converting the data of the previous line from the second latch unit to an analog data voltage and outputting it, An output buffer 45 for amplifying the data voltage and supplying the amplified data voltage to the corresponding data lines DL1 to DLm, And an adder 46 for adding the previous line data of the two latches 43 to generate addition data AData and supplying it to the charge share controller 50. [

The shift register 41 generates a sampling signal using the SSC and the SSP from the timing controller 10. [ Specifically, the shift register 21 generates a sampling signal by shifting the source start pulse according to the SSC, and supplies the sampled signal to the first latch unit 42.

The first latch unit 42 samples the video data supplied from the timing controller 10 through a data bus line (not shown) as the current line data according to a sampling signal from the shift register 41. Then, the sampled current line data is stored in units of one horizontal period, and supplied to the latched current line data second latch unit 43 in response to the SOE signal.

The second latch unit 43 samples the current line data input from the first latch unit 42 in accordance with the sampling signal or the SOE signal as previous line data. Then, the sampled previous line data is stored in units of one horizontal period, and the data of the previous line latched in response to the SOE signal is output to the DAC 44.

The DAC 44 outputs the previous line data to the positive polarity (+) or the negative polarity (-) gamma voltage by using a plurality of positive or negative gamma voltages supplied in accordance with the polarity control signal from the timing controller 10. [ (-) data voltage, and outputs the converted data voltage to the corresponding output buffer 45. Here, since the polarity control signal is inverted in units of one horizontal line, each pixel cell of the liquid crystal panel 2 is driven in a line inversion mode or a dot inversion mode in which the polarity thereof is reversed every horizontal line. Specifically, when a plurality of positive (+) gamma voltages are supplied by the polarity control signal, the DAC 44 outputs a positive (+) gamma voltage corresponding to the previous line data from the second latch unit 43 The data voltage is converted into a positive polarity data voltage and output. If a plurality of negative (-) gamma voltages are supplied, a negative (-) gamma voltage corresponding to the previous line data is selected to be converted into a negative data voltage and output.

The output buffer 45 amplifies the data voltage and supplies the amplified data voltage to the charge sharing section CSB (to prevent the data voltage from the DAC 44 from being distorted according to the RC time constant of the data lines DL1 to DLm) . The output buffer 45 includes an operational amplifier to correspond to each of the data lines DL1 to DLm, and amplifies a data voltage input from the DAC 44 using a positive driving voltage and a ground voltage. Then, the amplified data voltage is supplied to the charge share section CBS.

The addition section 46 adds the current line data of the first latch section 42 and the previous line data of the second latch section 43 to generate the addition data AData and supplies it to the charge share controller 50 .

Referring to FIG. 3, the gamma curve representing the magnitude of the data voltage with respect to the gradation level of the image data includes a positive gamma curve and a negative polarity It is common that the gamma curves are set to be opposite to each other. Accordingly, the gradation difference between the previous line data and the current line data arranged adjacent to each other between the two horizontal lines is proportional to the simple sum value of the adjacent data. Therefore, the addition section 46 adds the tone values of the first latch section 42 and the second latch section 43 and supplies them to the charge share controller 50. The video data from the timing controller 10 is transferred from the first channel portion CH1 of the first data integration circuit 4 of the plurality of data integration circuits 4 to the last channel portion CH1 of the last data integration circuit 4 (CHn). Therefore, when the adder 46 provided in the channel section CH1 of the first stage generates and outputs the additive data AData first, the adder 46 of the next stage to the adder 46 of the last stage And sequentially generates and outputs the addition data AData. Each of the adders 46 may further include a high impedance output switching element that maintains an output of a high impedance state while the addition data AData is not output.

FIG. 4 is a block diagram specifically showing the charge-share controller shown in FIG. 2. FIG.

The charge share controller 50 shown in FIG. 4 sequentially receives the addition data (Adata) from the plurality of channel units CH1 to CHn and sequentially outputs the maximum gray level value among the addition data (Adata) A maximum value detecting unit 51 for detecting a maximum data max of a maximum value of a maximum value of a maximum value of a maximum value (SC) and a charging selection signal (SC) from the gate high level charging start signal and the comparison unit (52) to perform charge sharing or And a logic product operation circuit 53 for outputting the charge share selection signal CS for stopping every horizontal period unit.

If it is determined that the maximum data max having the maximum gradation value among the image data of each horizontal line unit is larger than the reference data Ref set in advance, the charge-share controller 50 sets the gradation change width That is, it is determined that the voltage change width is large and the charge sharing operation is not performed. In this case, even if the polarity is inverted and the variation width of the data voltage supplied to each of the data lines DL1 to DLm becomes large, it is charged for one horizontal period, so that the non-charging phenomenon can be prevented. On the other hand, if it is determined that the maximum data max having the maximum gradation value is smaller than the reference data Ref, the charge sharing operation is performed. In this case, since the variation width of the data voltage is not large, even if the charge sharing operation is carried out, the charging amount is sufficient, so that the power consumption can be reduced.

5 is a block diagram showing the maximum value detector and the comparator shown in FIG. 4 in more detail.

The maximum value detector 51 shown in FIG. 5 detects any one of data (Adata) sequentially input from the plurality of channel units (CH1 to CHn) and previous data detected with the maximum data max (Sdata) inputted from the selection unit 61 as maximum data (max), and outputs the selection data (Sdata) as maximum data (max) And the maximum data max from the flip-flop unit 62. The flip-flop unit 62 stores the maximum data max of the addition data Adata of the flip- A first subtractor 63 for subtracting the maximum value max from the first subtractor 63 and outputting the subtracted result, and a second subtracter 63 for storing the previously stored maximum data max as it is, The addition data (Adata) and a selection control unit 64 for generating an update selection signal se so as to update and store the update selection signal se to the selection unit 61. [

The selector 61 includes at least one multiplexer MUX and outputs the added data Adata or the maximum data max currently inputted according to the update selection signal se from the selection controller 64, And supplies it to the flip-flop unit 62. Since the update selection signal se is a signal corresponding to the addition result of the addition data Adata and the maximum data max of the first subtractor 63, And is a signal for updating the data of the larger gray scale among the stored maximum data max to the maximum data max. Accordingly, the selector 61 supplies any one of the addition data Adata and the maximum data max currently input to the flip-flop unit 62 according to the update selection signal se.

The flip-flop unit 62 includes at least one flip-flop and sequentially stores data (Sdata) selected and input from the selector 61 in accordance with a clock pulse input from the outside, with the maximum data max. Accordingly, the flip-flop 62 sequentially updates the maximum data max among the addition data Adata for every horizontal line and outputs the updated data. The flip-flop 62 is reset at the beginning or end of the horizontal line period according to the reset signal Rset input every horizontal line.

The first subtractor 63 subtracts the maximum data max from the flip-flop 62 from the addition data Adata sequentially input. When the subtraction result is 1 or more, it is determined that the currently input sum data (Adata) is larger than the previously stored maximum data (max), and the current input sum data (Adata) The above result data Cdata is output. However, when the subtraction result is less than 1, the result data Cdata of 0 is supplied to the selection control section 64. [

The selection control unit 64 controls the selection control unit 64 to store the previously stored maximum data max as it is according to the subtraction result from the first subtractor 63 or to store the newly inputted accumulated data Adata as the maximum data max And supplies the update selection signal se to the selection unit 61. The selection unit 61 receives the update selection signal se and outputs the update selection signal se.

The comparator 52 shown in FIG. 5 includes a second subtractor 71 for sequentially subtracting the preset reference data Ref from the maximum data max inputted from the maximum value detector 51 and outputting the subtracted result And a selection signal generation unit 72 for generating and outputting a charging selection signal SC for determining whether to perform charge sharing according to the subtraction result from the second subtraction unit 71. [

The reference data Ref may be image data preset by the user and at a time point when the polarity of the polarity is inverted within one horizontal period to fill the charged data voltage. That is, the video data having a gray level value larger than the gray level value of the reference data Ref can not be fully charged in one horizontal period, and the video data having the gray level value smaller than the gray level value of the reference data Ref All of them are charged within the horizontal period. The comparison unit 52 compares the maximum data max input from the maximum value detector 51 with the preset reference data Ref and outputs a charging selection signal SC, As shown in FIG.

As described above, the driving apparatus of the image display apparatus according to the embodiment of the present invention includes:

The data integration circuit 4 itself detects the maximum data max having the maximum tone value among the image data of each horizontal line unit without being separately controlled through the timing controller 10. [ If the data integration circuit 4 determines that the maximum data max is larger than the preset reference data Ref, the data integration circuit 4 determines that the data voltage variation width with the reversed polarity is large and does not perform the charge sharing operation.

6, the data integration circuit 4, as in the third and fourth horizontal periods 3H and 4H, determines whether the maximum data max is greater than or equal to a preset reference If it is determined that the data is larger than the data Ref, the charge share operation is not performed. Thus, even if the polarity is inverted and the variation width of the data voltage Vdata supplied to each of the data lines DL1 to DLm becomes large, as in the third and fourth horizontal periods 3H and 4H, It is possible to prevent an undesired charging phenomenon.

On the other hand, if it is determined that the maximum data max having the maximum gradation value as in the first and second horizontal periods 1H and 2H and the fifth horizontal period 5H is smaller than the reference data Ref, Thereby performing a sharing operation. In this case, since the variation width of the data voltage (Vdata) is not large, even if the charge sharing operation is performed, the amount of charge is sufficient, so that the power consumption can be reduced.

As described above, the present invention makes it possible to more easily apply the charge share technology to the display panel 2 of high resolution and high image quality on a large screen. Since each data integration circuit 4 itself can analyze the image data and apply the charge sharing technology, it is possible to reduce the number of separate control signal transmission lines and transmission pins for controlling the respective data integration circuits 4 The manufacturing cost of the video display device can also be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

1 is a configuration diagram illustrating a video display device according to an embodiment of the present invention;

Fig. 2 is a configuration diagram specifically showing the data integrated circuit shown in Fig. 1. Fig.

3 is a diagram for explaining a process of adding previous data and current data;

4 is a configuration diagram specifically showing the charge-share controller shown in Fig. 2. Fig.

5 is a block diagram showing the maximum value detecting unit and the comparing unit shown in FIG. 4 in more detail.

6 is a driving waveform diagram for explaining effects according to the driving characteristics of the present invention.

Claims (10)

A display panel having a plurality of pixel regions to display an image; A plurality of gate integrated circuits for driving the respective gate lines of the display panel; The image data of the current line and the image data of the previous line, which are input in every horizontal line unit, are generated by adding the image data of the previous line, and the addition data is compared with the reference data, A plurality of data integration circuits for determining whether or not to charge-share based on the data lines and charge-sharing the data lines in a charge sharing period when the charge sharing is performed; And And a timing controller for controlling driving timings of the gates and the data integrated circuits. The method according to claim 1, Each of the data integrated circuits A plurality of channels, each corresponding to each of the data lines, for driving the data lines in accordance with the image data and generating current data by adding current line image data of the image data and image data of a previous line, part, A charge share controller for sequentially receiving the additive data from the plurality of channel units and comparing and analyzing the received additive data with reference data to determine whether charge sharing is to be performed, generating and outputting a charge share control signal in every horizontal period units according to whether the charge sharing is performed, And And a charge share unit for charge-sharing the data lines during a charge sharing period according to the charge share control signal. 3. The method of claim 2, Each of the plurality of channel portions A shift register for outputting a sampling signal in response to a data control signal from the timing controller, A first latch unit for sampling the image data according to the sampling signal as the current line data and outputting the sampled current line data according to the data control signal, A second latch unit for sampling the current line data input from the first latch unit according to the sampling signal with previous line data and outputting data of a previous line that has been sampled, A digital-to-analog converter for converting data of a previous line from the second latch to an analog data voltage, An output buffer for amplifying the data voltage from the digital-analog converter and supplying the amplified data voltage to the corresponding data line, And a summation unit for adding the current line data of the first latch unit and the previous line data of the second latch unit to generate addition data and supplying the addition data to the charge share controller. The method of claim 3, The charge share controller A maximum value detector which sequentially receives the addition data from the plurality of channel units and detects maximum data having a maximum gray level value among addition data for every horizontal line, A comparison unit for comparing the detected maximum data with preset reference data and generating and outputting a charging selection signal for determining whether to perform charge sharing according to the comparison result, And a logic product operation circuit for performing a logical product operation between a charging start signal of a gate high level and a charging selection signal from the comparison section to output a charge share selection signal for performing or suspending charge sharing in units of horizontal periods A driving device for a video display device. 5. The method of claim 4, The maximum value detection unit A selector for updating either one of the addition data sequentially input from the plurality of channel units and the previous data detected as the maximum data to the maximum data and outputting as the selection data, A flip-flop unit for storing and outputting the maximum data among the addition data for every horizontal line by storing the selection data inputted from the selection unit as the maximum data, A first subtractor for subtracting the addition data sequentially input and the maximum data from the flip-flop to output a result of the subtraction; And a selection control unit for generating an update selection signal so as to store the previously stored maximum data as it is or the update data of the newly inputted sum data as the maximum data according to the subtraction result from the first subtraction unit and supply the updated selection signal to the selection unit A driving device for a video display device. Driving each gate line of a display panel having a plurality of pixel regions to display an image; Driving each data line of the display panel; And The image data of the current line and the image data of the previous line, which are input in every horizontal line unit, are generated by adding the image data of the previous line, and the addition data is compared with the reference data, And if the charge sharing is performed, charge-sharing the data lines in the charge sharing period. The method according to claim 6, The step of charge sharing the data lines Generating current data by adding current line image data of the image data and image data of a previous line through a plurality of channel units respectively corresponding to the data lines; Sequentially comparing the addition data with reference data to determine whether or not to perform the charge sharing, generating and outputting a charge share control signal in units of horizontal periods in accordance with whether to perform the charge sharing, And charge-sharing the data lines in the charge-sharing period according to the charge-share control signal. 8. The method of claim 7, The step of generating the addition data Outputting a sampling signal in response to a data control signal from a timing controller, Sampling the image data as current line data according to the sampling signal and outputting the sampled current line data according to the data control signal, Sampling the current line data inputted in accordance with the sampling signal with previous line data and outputting data of a previous line that has been sampled; Converting the output data of the previous line into an analog data voltage and outputting the analog data voltage, Amplifying the data voltage and supplying the data voltage to the corresponding data line, and And adding the current line data and the previous line data to generate and output the added data. 9. The method of claim 8, The step of generating and outputting the charge share control signal comprises: Sequentially receiving the addition data and detecting maximum data having a maximum gray level value among the addition data for every horizontal line, Generating and outputting a charging selection signal for comparing the detected maximum data with preset reference data and determining whether to perform charge sharing according to a result of the comparison; and And outputting a charge share selection signal for performing a logical product operation between the charging start signal of the gate high level and the charging selection signal to perform or suspend charge sharing in units of horizontal periods. 10. The method of claim 9, The step of detecting the maximum data Updating one of the addition data and the previous data detected as the maximum data to the maximum data and outputting it as selection data, Storing and outputting the maximum data among the addition data for every horizontal line by storing the selection data as the maximum data, Subtracting the addition data and the maximum data and outputting the subtraction result, and And generating and outputting an update selection signal to store the previously stored maximum data as it is or to update and update the newly added sum data with the maximum data according to the subtraction result.

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