KR101658140B1 - Thin Film Transistor Array Substrate and Method for Manufacturing the Same - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate having a reduced number of masks and an improved process yield and a method of manufacturing the same. The thin film transistor array substrate of the present invention includes a step of forming an active layer made of polysilicon on a substrate Forming a first photoresist pattern on a substrate including the active layer, defining a doped region by implanting impurities into the active layer using the first photoresist pattern as a mask, Forming a data metal layer on the substrate including the first photoresist pattern and the active layer by lifting off the data metal layer on top of the first photoresist pattern and removing the remaining data metal layer on the active layer; Defining a data line defined as a source electrode and a drain electrode and connected to the source electrode Forming a gate insulating layer on the substrate including the data line, the source electrode, the drain electrode, and the active layer; forming a gate line in a direction intersecting with the data line and a gate electrode protruding from the gate line; Forming a protective film on the entire surface including the gate line and the gate electrode and forming a contact hole exposing a part of the drain electrode; And forming a pixel electrode in the contact hole and on the passivation layer.

5 mask, low temperature polysilicon (LTPS), mask reduction, 6 mask

Description

[0001] The present invention relates to a thin film transistor array substrate and a manufacturing method thereof,

The present invention relates to a liquid crystal display, and more particularly, to a thin film transistor array substrate having a reduced number of masks to reduce the number of processes and yield, and a method of manufacturing the same.

Recently, the demand for low temperature polysilicon thin film transistors as driving elements for display devices such as active matrix liquid crystal display devices (AMLCD) and active matrix organic light emitting diodes (AMOLED) has been increasing.

A thin film transistor (TFT) is mainly used as a switching device for driving a display device, and amorphous silicon is mainly used as an active layer of the thin film transistor.

Particularly, in a liquid crystal display device using a liquid crystal arranged in a certain direction according to an electric field as a component of a display device, a thin film transistor is adopted as a switching device. Today, in order to realize a high response speed and low power consumption, Research on the use of polysilicon as the active layer has been actively conducted.

On the other hand, a process for producing a liquid crystal display device using polysilicon as a channel generally involves forming amorphous silicon on a substrate such as glass by a plasma chemical vapor deposition (PECVD) method and crystallizing the deposited amorphous silicon Process.

As a method of crystallizing the amorphous silicon, there are a high temperature heating method of crystallizing the amorphous silicon through a process of heating and cooling the amorphous silicon for a long time in a high temperature furnace, a high temperature heating method of instantaneously irradiating the high intensity laser energy, A laser annealing method which is a low-temperature process is used.

Since the amorphous silicon layer is heated at a high temperature not lower than the glass transition temperature of the crystallization method, various methods for crystallizing amorphous silicon at low temperature are not suitable because it is not suitable for application to liquid crystal display devices using glass or the like as a substrate Respectively.

Hereinafter, a method of manufacturing a thin film transistor formed by a conventional low-temperature crystallization method will be described with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view showing a conventional thin film transistor array substrate in a transmission mode, and FIG. 2 is a flowchart showing a conventional method of manufacturing a thin film transistor array substrate in a transmission mode.

As shown in Figs. 1 and 2, the conventional manufacturing method of the thin film transistor array substrate in the transmission mode is performed in the following order.

First, a buffer layer 11 is formed on a substrate 10.

Next, an active layer 12 made of polysilicon is formed on the buffer layer 11 by patterning (S10).

Next, a gate insulating film 13 is formed on the entire surface of the buffer layer 11 including the active layer 12.

A gate line is formed in one direction on the gate insulating film 13 and a gate electrode 14 is formed in the center of the active layer 12 to correspond to the upper portion of the gate line 14 (S20) . Here, the common line 14a may be formed on the same layer as the gate electrode 14. [

Impurities are doped into the active layer 12 on both sides of the gate electrode to form a source region and a drain region 12b of the active layer 12 and a channel 12a.

Next, an interlayer insulating film 15 is formed on the entire surface of the gate insulating film 13 including the gate electrode 14, the common line 14a of the same layer, and the gate line (not shown).

A contact process S30 for selectively removing the interlayer insulating film 15 and the gate insulating film 13 to form a contact hole such that a part of the source region and the drain region 12b of the active layer 12 are exposed, Go ahead.

Then, the contact hole is buried and a metal is deposited on the entire surface of the interlayer insulating film 15 and selectively removed to form a data line in a direction crossing the gate line, and the source electrode 16a And a drain electrode 16b spaced therefrom are formed (S40).

After the organic passivation layer 17 is deposited on the entire surface of the interlayer insulating layer 15 including the source / drain electrodes 16a / 16b, a contact hole exposing a portion of the drain electrode 16b is formed (S50) .

Next, a transparent electrode is formed to pass through the inner surface of the contact hole and the surface of the organic passivation layer 17, and then the pixel electrode 18 is formed by patterning the transparent electrode (S60).

As described above, in the conventional manufacturing method of the thin film transistor array substrate of the transmission mode, one mask is required for each step (S10 to S60) of FIG. 1, and the six mask process is applied.

3 is a flowchart showing a method of manufacturing a conventional semi-transmissive mode thin film transistor array substrate.

As shown in FIG. 3, the conventional method of fabricating a semi-transmissive mode thin film transistor array substrate is different from the above-described transmissive mode in that an embossing structure is formed on the surface of the protective film, And a reflective electrode is further formed after the pixel electrode is formed. Accordingly, one or two or more masks are required in comparison with the transmissive mode.

That is, the conventional method of manufacturing a semi-transmissive mode thin film transistor array substrate includes sequentially forming an active layer (S71), a gate line and a gate electrode (S72), a contact for exposure of a source / A data line and a source / drain electrode forming step S74; a protective film and its surface embossed structure forming step S75; a pixel electrode forming step S76; a reflective electrode forming step S77 ). In this case, different masks are required in the respective divided processes, wherein the formation of the protective film and the embossing structure may be formed using two masks.

However, the conventional thin film transistor array substrate and the manufacturing method thereof have the following problems.

Conventional thin film transistor fabrication requires 6 masks in at least the transmissive mode and 7 masks in the semi-transmissive mode.

When applying the mask used in the exposure process, inter-layer alignment is required between the layers applying different masks after the patterning of the previous layer and before the patterning of the next layer. When the mask process is cumulative, the degree of misalignment The larger the number of masks, the lower the yield of the manufactured device. Therefore, efforts have been actively made to reduce the number of masks due to a fatal problem at such a yield.

In addition, in the process of forming a conventional thin film transistor array substrate, formation of a gate line and formation of a data line are formed by different processes, and they are formed in processes other than the formation of the active layer and the doping process , An interlayer insulating film is necessarily provided between the gate line and the data line in addition to the gate insulating film. In addition, when the interlayer insulating film is provided, a process for contact between the source / drain electrode of the same layer as the data line and the semiconductor layer located therebelow is further required, complicating the process, requiring a mask, and disadvantageous in terms of yield .

It is an object of the present invention to provide a thin film transistor array substrate and a method of manufacturing the same that reduce the number of masks to reduce the number of processes and improve the yield.

According to an aspect of the present invention, there is provided a thin film transistor array substrate comprising: a substrate; an active layer formed of polysilicon on the substrate; a first photoresist pattern formed on the substrate including the active layer; Forming a data metal layer on the substrate including the first photoresist pattern and the active layer, forming a second photoresist pattern on the first photoresist pattern and the active layer using the first photoresist pattern as a mask, forming a doped region by implanting impurities into the active layer, And lifting off the data metal layer on top of the first photoresist pattern and removing the remaining data metal layer on the active layer as a source electrode and a drain electrode and defining a data line connected to the source electrode; A gate electrode on the substrate including the data line, the source electrode, the drain electrode, and the active layer; Forming a gate electrode extending in a direction intersecting the data line and a gate electrode protruded from the gate line, forming a protective film on the entire surface including the gate line and the gate electrode, Forming a contact hole exposing a portion of the electrode; And forming a pixel electrode in the contact hole and on the passivation layer.

In the forming of the first photoresist pattern, a portion where the first photoresist pattern is not formed is defined as a formation portion of the data line and the source and drain electrodes.

The step of forming the passivation layer may be performed by depositing an inorganic passivation layer, performing a hydrogenation process, and then depositing an organic passivation layer.

The step of forming the gate line and the gate electrode may include depositing an inorganic protective film on the gate insulating film, forming a gate electrode on the inorganic protective film, Forming a second photoresist pattern on the data line by ashing the second photoresist pattern by selectively removing the inorganic protective film that does not overlap the data line using the second photoresist pattern; Forming a second photoresist pattern on the entire surface including the second photoresist pattern by removing the gate metal layer on the second photoresist pattern and protruding the gate metal layer from the gate line; Gate electrode.

The second photoresist pattern is formed using a diffraction exposure mask or a halftone mask in which a transflective portion is defined at a portion overlapping the data line.

Further, a reflective electrode may be further formed on a part of the pixel electrode.

Here, the reflective electrode is defined by the same mask as the mask for forming the pixel electrode.

The reflective electrode corresponding portion on the organic protective film has irregularities. The concavity and convexity of the reflective electrode corresponding portion is defined when forming the contact hole of the organic protective film.

In order to achieve the same object, a thin film transistor array substrate according to the present invention includes: an active layer made of polysilicon and having doped regions defined on both sides thereof; a source electrode formed in contact with both sides of the active layer; A gate electrode formed on the substrate including the data line, the source electrode, the drain electrode, and the active layer; a gate electrode formed between the source electrode and the drain electrode; A gate line formed to cross the data line and connected to the data line, a protection layer formed on the entire surface including the gate line and the gate electrode and having a contact hole exposing a part of the drain electrode; And a pixel electrode formed in the contact hole and on the passivation layer.

According to another aspect of the present invention, there is provided a thin film transistor array substrate including: an active layer made of polysilicon and having doped regions defined on both sides thereof; A gate electrode formed on the substrate including the data line, the source electrode, the drain electrode, and the active layer; and a source electrode formed on the source electrode and the drain electrode, A gate line formed between the gate electrode and the data line, the gate line being formed between the gate electrode and the data line, the gate line being formed between the gate line and the gate electrode, and a contact hole exposing a part of the drain electrode, A protective film having a reflective portion defined therein; A pixel electrode; And a reflective electrode on the pixel electrode corresponding to the reflective portion.

The above-described thin film transistor array substrate of the present invention and its manufacturing method have the following effects.

As described above, in the manufacture of the thin film transistor array substrate of the present invention, the source electrode / drain electrode is directly contacted with the active layer, the gate electrode is interposed between the source electrode and the drain electrode, It is not necessary to perform a contact process (another definition of the contact hole of the interlayer insulating film) required for contacting the source electrode / drain electrode with the semiconductor layer, so that the number of masks Reduction is possible.

In addition, in the manufacture of the semi-transmissive mode thin film transistor array substrate in which the reflective electrode and the emboss structure are further applied, the embossing structure and the contact hole forming step of the protective film are performed by the same mask, , Yield can be improved to a level similar to the transmission mode.

Hereinafter, a thin film transistor array substrate of the present invention and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

FIG. 4 is a flow chart showing a manufacturing method of the thin film transistor array substrate of the transmission mode of the present invention, and FIG. 5 is a sectional view of the thin film transistor array substrate of the transmission mode formed by the manufacturing method of FIG.

As shown in Figs. 4 and 5, the manufacturing process of the thin film transistor array substrate of the transmission mode according to the embodiment of the present invention is performed in the following order.

First, the buffer layer 101 is formed on the entire surface of the transparent substrate 100.

Next, an active layer 102 made of polysilicon is formed on the buffer layer 101 by using a first mask (not shown) (S101).

Next, impurities are implanted into the active layer 102 by using a second mask (not shown) to define a doped region (a source region and a drain region) 102b. In this case, the second mask masks the region except for the doped region, and defines the data line forming region together. In the active layer 102, a region between the undoped source region and the drain region 102b is a channel region 102a.

Next, a metal layer is deposited on a portion not covered by the second mask to form a data line (not shown), a source electrode 103a protruding from the data line and being in contact with a source region of the active layer 102, Thereby forming an electrode 103b (S102).

Next, a gate insulating film 104 is formed on the entire surface including the active layer 102 and the source electrode 103a / drain electrode 103b.

Next, a metal is deposited on the gate insulating layer 104 and then selectively patterned using a third mask (not shown) so that a gate electrode (not shown) is formed on a portion corresponding to the region between the source electrode 103a and the drain electrode 103b. And a gate line (not shown) connected to the gate electrode is formed (S103). Here, the common line 105a may be formed on the same layer as the gate line 105. [ The common line 105a at this time is for forming a storage capacitor. The common line 105a is not necessarily limited to this position, and may be formed by extending the gate line to function as a storage capacitor electrode in some cases.

Next, an inorganic protective film 106 and an organic protective film 107 are sequentially formed on the entire surface including the gate line 105 and the common line 105a.

Next, the organic passivation layer 107, the inorganic protective layer 106 and the gate insulating layer 104 are patterned using a fourth mask (not shown) to form a contact hole 117 exposing a part of the drain electrode 103b (S104). At this time, the inorganic protective film 106 may be omitted in some cases.

A transparent electrode is deposited to cover the inner surface of the contact hole 117 and the surface of the organic passivation layer 107 and then selectively removed using a fifth mask (not shown) (S105).

As described above, in the manufacture of the thin film transistor array substrate of the present invention, the source electrode / drain electrodes 103a / 103b are formed by directly contacting the active layer 102, and the gate insulating film 104 is interposed therebetween By forming the gate electrode 105, it is not necessary to perform a contact process (another definition of the contact hole of the interlayer insulating film) required to contact the source electrode / drain electrode with the semiconductor layer, The number of masks can be reduced by using a mask.

Hereinafter, a manufacturing method of the thin film transistor array substrate of the transmission mode will be described in detail as follows.

- First Embodiment -

FIGS. 6A to 6G are process plan views illustrating a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention, and FIGS. 7A to 7H illustrate a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention Fig.

First, as shown in FIGS. 6A and 7A, the buffer layer 101 is formed on the entire surface of the transparent substrate 100.

Then, an active layer 102 made of polysilicon is formed on a predetermined region of the buffer layer 101 by patterning using a first mask (not shown).

6B and 7B, a photoresist layer is formed on the active layer 102 and then patterned using a second mask (not shown) to expose the data line region and the source / drain regions A pattern 111 is formed.

In this case, the photoresist layer may be formed as a positive photoresist layer to a thickness of 5 탆 or more, or may be applied as a negative photoresist layer to enable an inverted taper shape.

Next, a p-type or n-type impurity is implanted into the active layer 102 opened by the photoresist pattern 111 to define the doped region (the source region and the drain region) 102b. In this case, the second mask covers the region except for the doped region, and defines a data line forming region together to define the region. In the active layer 102, a region between the undoped source region and the drain region 102b is a channel region 102a.

6C and 7C, a data metal layer 112 is deposited on the entire surface of the substrate 100 including the photoresist pattern 111. Next, as shown in FIGS. At this time, the data metal layer 112 is formed directly on the data line forming portion opened in the second mask and the doped region 102b of the active region directly on the buffer layer 101 on the substrate 100 or the doped region 102 of the active layer 102 And the data metal layer 112 is formed on the upper portion of the substrate 100 where the remaining photoresist pattern 111 is formed.

6D and 7D, the photoresist pattern 111 and the data metal layer 112 thereon are stripped off by lift off together.

The data metal layer remaining in the data line forming portion is the data line 103. The data metal layer that is in contact with the doped region 102b of the active layer 102 is the source electrode 103a and the drain electrode 103b. . In this case, the source electrode 103a is connected to the data line 103, and the drain electrode 103b is formed apart from the source electrode 103a.

7E, a gate insulating layer 104 is formed on the entire surface including the active layer 102, the data line 103 made of a data metal layer, and the source electrode 103a / drain electrode 103b.

Then, the active layer 102 is activated by applying a predetermined temperature of heat.

6E and 7F, a metal is deposited on the gate insulating layer 104 and selectively patterned using a third mask (not shown) to form the source electrode 103a and the drain electrode 103b, And a gate line (not shown) connected to the gate electrode is formed. Here, the common line 105a may be formed on the same layer as the gate line 105. [ The common line 105a at this time is for forming a storage capacitor and is not necessarily limited to this position, but may be formed by extending the gate line.

7G, an inorganic protective film 106 is formed on the entire surface including the gate line 105 and the common line 105a. After the hydrogenating process of the active layer 102 is performed, an organic protective film 107 ). In this case, the reason why the inorganic protective film 106 is formed is to prevent the pattern from collapsing due to heat applied to the lower structure in the hydrogenation process.

6F and 7G, the organic protective film 107, the inorganic protective film 106 and the gate insulating film 104 are patterned using a fourth mask (not shown) to form a part of the drain electrode 103b Thereby forming a contact hole 117 to be exposed. In this case, the contact hole 117 is not overlapped with the common line 105a and is exposed only to a part of the upper portion of the drain electrode 103b, and the pixel electrode 108 and the drain electrode 103b form a direct connection.

6G and 7H, a transparent electrode is deposited to cover the inner surface of the contact hole 117 and the surface of the organic passivation layer 107, and then a fifth mask (not shown) And the pixel electrode 108 is formed. In this case, the storage capacitor includes a first storage capacitor, which is formed by overlapping the common line 105a and the drain electrode 103b and the gate insulating film 104 between the first and second common electrodes 105a and 105b, Which is represented by the overlap of the first storage capacitor 108, the inorganic protective film 106 between the layers and the organic protective film 107, and the storage capacitor shown as an intervening insulating film between the two conventional storage electrodes The storage capacitance value can be secured at the same area.

- Second Embodiment -

8A to 8C are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

The manufacturing method of the thin film transistor array substrate according to the second embodiment of the present invention is the same as the first embodiment except that the protective film is formed by omitting the inorganic protective film.

The same process will be briefly omitted, and the third mask process will be described as follows.

8A, a metal is deposited on the gate insulating layer 104 and selectively patterned using a third mask (not shown) to form a portion corresponding to the region between the source electrode 103a and the drain electrode 103b And a gate line (not shown) connected to the gate electrode and a common line 105a are formed apart from the gate line.

Next, as shown in FIG. 8B, an organic passivation layer 115 is formed on the entire surface including the gate line 105 and the common line 105a.

The organic passivation layer 115 and the gate insulating layer 104 are patterned using a fourth mask (not shown) to form a contact hole 117 exposing a part of the drain electrode 103b.

A transparent electrode is deposited to cover the inner surface of the contact hole 117 and the surface of the organic passivation layer 115 and then selectively removed using a fifth mask (not shown) .

- Third Embodiment -

FIGS. 9A to 9E are process plan views illustrating a method of manufacturing a thin film transistor array substrate according to a third embodiment of the present invention. FIGS. 10A to 10F illustrate a method of manufacturing a thin film transistor array substrate according to a third embodiment of the present invention Fig.

The manufacturing method of the thin film transistor array substrate according to the third embodiment of the present invention is the same as the second mask process (FIGS. 6D to 7D) of the first embodiment described above, and the subsequent steps will be described in detail. same.

The active layer 102 is formed by a first mask process and is contacted with the doped region 102b of the active layer 102 and the doped region 102b by a second mask process A source electrode 103a and a drain electrode 103b and a data line 103 connected to the source electrode 103a and formed in a vertical direction are formed.

Here, in the first masking step, as shown in the figure, the active layer 132 may be left under the data line 103, or may be formed as a single layer of the data line 103.

10A, a gate insulating film 104 is formed on the entire surface including the active layer 102, the data line 103 made of a data metal layer, the source electrode 103a and the drain electrode 103b, The activation process of the layer 102 proceeds. After the inorganic protective film 121 is deposited on the gate insulating film 104, the hydrogenation process is performed. In this case, after the deposition of the inorganic protective film 121, activation and hydrogenation may be performed together.

As shown in FIGS. 9B and 10B, a photoresist layer 122 is formed on the inorganic protective layer 121 by patterning the photoresist layer using a third mask. In this case, the third mask is a kind of halftone mask, and the transmissive portion, transflective portion and shielding portion are defined together. At this time, when the component of the photoresist pattern 122 is a photoresist film, the portion where the gate line and the common line are to be formed on the data line corresponds to the transflective portion of the third mask, and the remaining gate line, The forming region corresponds to the opening portion of the third mask, and the remaining regions correspond to the light shielding portion of the third mask. The thickness of the photoresist pattern 122 corresponding to the transmissive portion is entirely removed in the exposure and development steps, the thickness of the applied portion corresponding to the light shielding portion remains as it is, And a diffractive portion D having a different thickness at the light shielding portion. This photoresist pattern 122 is defined to form a gate line, a common line, and a gate electrode.

Here, when the component of the photoresist pattern 122 is a negative photoresist, the arrangement of the light-shielding portion and the opening portion of the third mask may be reversed.

Next, the inorganic protective film 121 is etched using the photoresist pattern 122 as a mask to form an inorganic protective film pattern 121a.

Next, as shown in FIGS. 9C and 10C, the photoresist pattern 122 is ashed to leave a photoresist residue layer 122a. At this time, the entire thickness corresponding to the diffraction portion D is removed in the ashing process, and the inorganic protective film pattern 121a on the data line 103 is exposed. In this case, the remaining photoresist residual layer 122a is formed to have a sufficient thickness and close to an inverse taper so that the photoresist residual layer 122a and the upper The removal of the gate metal layer is smoothly performed so that electrical separation between the gate metal layers disposed between the photoresist residual layers 122a is normally performed.

10D, a gate metal layer 123 is deposited on the exposed gate insulating layer 104 or the inorganic passivation layer pattern 121a or the photoresist layer 122a. At this time, the photoresist residual layer 122a is formed to have a sufficient thickness and close to the reverse taper, so that the gate metal layer is hardly left on the side thereof.

9D and 10E, the photoresist residual layer 122a and the gate metal layer 123 thereon are lifted off and removed. At this time, the remaining gate metal layer is the gate line 105 in the direction intersecting the data line 103 and the common line 105a parallel thereto. A gate electrode formed to protrude from the gate line 105 is formed between the source electrode 103a and the drain electrode 103b.

9E and 10F, an organic passivation film 125 is formed on the entire surface of the inorganic passivation film 121a including the gate line 105 and the common line 105a. Then, the organic passivation film 125, A contact hole 127 for selectively exposing the protective film pattern 121a and the gate insulating film 104 and exposing a part of the drain electrode 103b is defined.

After a transparent electrode is deposited on the inner surface of the contact hole 127 and the organic passivation layer 125, the transparent electrode is selectively removed to form the pixel electrode 126.

The third embodiment described above differs from the structure of the lower portion of the gate metal layer in that the interlayer thickness is further ensured between the gate line 105 or the common line 105a overlapping with the data line 103 (gate insulating film + Inorganic shielding film) is to prevent the increase of parasitic capacitors between gate metal layer lines (gate lines and common lines) and data lines.

FIG. 11 is a flowchart showing a method of manufacturing a transflective mode thin film transistor array substrate of the present invention, and FIG. 12 is a sectional view showing a transflective mode thin film transistor array substrate of the present invention in which the method of FIG. 11 is formed.

Hereinafter, a method of manufacturing the transflective mode thin film transistor array substrate of the present invention will be described with reference to FIGS. 11 and 12. FIG.

First, the buffer layer 201 is formed on the entire surface of the transparent substrate 200.

Next, an active layer 202 made of polysilicon is formed on the buffer layer 201 by patterning using a first mask (not shown) (S111).

Next, impurities are implanted into the active layer 202 using a second mask (not shown) to define a doped region (source region and drain region) 202b. In this case, the second mask masks the region except for the doped region, and defines the data line forming region together. In the active layer 202, the undoped region between the doped region (source region and drain region) 202b is the channel region 202a.

Next, a metal layer is deposited on a portion not covered by the second mask to form a data line (not shown), a source electrode 203a projecting from the data line and being in contact with the source region of the active layer 202, The electrode 203b is formed (S112).

A gate insulating layer 204 is formed on the entire surface including the active layer 202 and the source and drain electrodes 203a and 203b.

Next, a metal is deposited on the gate insulating layer 204 and then selectively patterned using a third mask (not shown) so that a gate electrode (not shown) is formed on a portion corresponding to the region between the source electrode 203a and the drain electrode 203b. And a gate line (not shown) connected to the gate electrode is formed (S113). Here, the common line 205a may be formed in the same layer as the gate line 205. [ The common line 205a at this time is for forming a storage capacitor and is not necessarily limited to this position. In addition, the common line 205a may be formed by extending the gate line to function as a storage capacitor electrode.

Next, an inorganic protective film 206 and an organic protective film 207 are sequentially formed on the entire surface including the gate line 205 and the common line 205a.

Subsequently, the organic protective film 207, the inorganic protective film 206, and the gate insulating film 204 are processed on the organic protective film 207 corresponding to the reflective portion R using a fourth mask (not shown) And a contact hole 207a through which a part of the drain electrode 203b is exposed is formed (S114). At this time, the inorganic protective film 206 may be omitted in some cases.

Next, a transparent electrode and a reflective metal are sequentially deposited to cover the inner surface of the contact hole 207a and the surface of the organic passivation layer 207, and then, using the fifth mask (not shown) as a diffraction exposure mask, The reflective metal and the transparent electrode are selectively removed to form the pixel electrode 208 and the reflective electrode 209 on the reflective portion R (S115).

As described above, in the manufacture of the thin film transistor array substrate of the present invention, the source electrode / drain electrodes 203a / 203b are formed by directly contacting the active layer 202 and the gate insulating film 204 is interposed therebetween By forming the gate electrode 205, there is no need to carry out a contact process (another definition of the contact hole of the interlayer insulating film) required to contact the source electrode / drain electrode with the semiconductor layer, The number of masks can be reduced by 5 masks.

Hereinafter, a manufacturing method of the thin film transistor array substrate of the transmission mode will be described in detail as follows.

- Fourth Embodiment -

FIGS. 13A to 13G are process plan views illustrating a method of manufacturing a thin film transistor array substrate according to a fourth embodiment of the present invention, and FIGS. 14A to 14H are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a fourth embodiment of the present invention Fig.

First, as shown in FIGS. 13A and 14A, a method of manufacturing a thin film transistor array substrate according to a fourth embodiment of the present invention includes forming a buffer layer 201 entirely on a transparent substrate 200.

Then, an active layer 202 made of polysilicon is formed on a predetermined region of the buffer layer 201 by patterning using a first mask (not shown).

Next, as shown in FIGS. 13B and 14B, a photoresist layer is formed on the active layer 202 and then patterned using a second mask (not shown) to form a data line region and a source / Pattern 211 is formed.

In this case, the photoresist layer may be formed as a positive photoresist layer to a thickness of 5 탆 or more, or may be applied as a negative photoresist layer to enable an inverted taper shape. For example, the photoresist pattern 211 applied when the negative photoresist film is formed preferably has a thickness of 4 탆 or more.

Next, a p-type or n-type impurity is implanted into the active layer 202 opened by the photoresist pattern 211 to define the doped region (source region and drain region) 202b. In this case, the second mask covers the region except for the doped region, and defines a data line forming region together to define the region. In the active layer 202, a region between the undoped source region and the drain region 202b is the channel region 202a.

Next, as shown in FIGS. 13C and 14C, a data metal layer 212 is deposited on the entire surface of the substrate 200 including the photoresist pattern 211. At this time, the data metal layer 212 is directly connected to the data line forming portion opened in the second mask and the doped region 202b of the active region directly to the buffer layer 201 on the substrate 200 or the doped region 202 of the active layer 202 And the data metal layer 212 is formed on the upper portion of the substrate 200 where the remaining photoresist pattern 211 is formed.

As shown in FIGS. 13D and 14D, the photoresist pattern 211 and the data metal layer 212 thereon are stripped off by lift off together.

The data metal layer remaining in the data line forming portion is the data line 203 and the data metal layer that is in contact with the doped region 202b of the active layer 202 is the source electrode 203a and the drain electrode 203b. . In this case, the source electrode 203a is connected to the data line 203, and the drain electrode 203b is formed apart from the source electrode 203a.

14E, a gate insulating layer 204 is formed on the entire surface including the active layer 202, the data line 203 made of a data metal layer, and the source electrode 203a and the drain electrode 203b.

Next, as shown in FIGS. 13E and 14F, a metal is deposited on the gate insulating layer 204 and then selectively patterned using a third mask (not shown) to form the source electrode 203a and the drain electrode 203b. And a gate line (not shown) connected to the gate electrode is formed. Here, the common line 205a may be formed in the same layer as the gate line 205. [ The common line 205a at this time is for forming a storage capacitor and is not necessarily limited to this position. Alternatively, only the gate line 205 may be formed and the common line may be omitted, and the gate line may be extended to serve as one electrode of the storage capacitor.

14G, an inorganic protective film 206 is formed on the entire surface including the gate line 205 and the common line 205a. After the active layer 202 is subjected to a hydrogenation process, an organic passivation film 207 ). In this case, the reason why the inorganic protective film 206 is formed is to prevent the pattern from collapsing due to heat applied to the lower structure in the hydrogenation process.

Next, as shown in FIGS. 13F and 14G, the organic passivation layer 207, the inorganic protective layer 206, and the gate insulating layer 204 are patterned using a fourth mask (not shown) to form a part of the drain electrode 203b And a recessed portion is defined on the organic passivation layer 207 corresponding to the reflective portion R. [ Here, the fourth mask is a halftone mask, a portion corresponding to the contact hole 207a corresponds to an opening, a portion corresponding to the reflective portion R corresponds to a concave-convex defining portion, and the remaining portion corresponds to a light- The concavity and convexity of the reflective portion R can be defined after partially removing the thickness of the organic passivation layer 207 when the contact hole 207a is defined corresponding to the transflective portion.

In this case, a process of reflowing may be added in order to soften the emboss structure of the irregularities of the surface of the reflection portion R after patterning of the organic protective film 207 using the fourth mask.

Next, as shown in FIGS. 13G and 14H, a transparent electrode and a reflective metal are deposited in order to cover the inner surface of the contact hole 207a and the surface of the organic passivation layer 207, and then a photoresist (not shown) And then patterned using a fifth mask (not shown) as a diffraction mask to form a photoresist pattern. Then, the reflective metal and the transparent electrode are selectively removed using the photoresist pattern to form a reflective electrode 209 And a pixel electrode 208 are formed.

The fifth mask is a diffraction exposure mask in which a portion corresponding to the reflection portion R is defined as a light shielding portion and a portion where the remaining pixel electrode 208 except for the reflection portion R remains is a semi- And a buoy where the pixel electrode and the reflective electrode are not formed is defined as a light shielding portion.

Accordingly, the photoresist pattern is exposed and developed by using the fifth mask to leave a full thickness of the light shielding portion, a lower thickness in the transflective portion, and a thickness of the transmissive portion to remove the entire thickness. Accordingly, after the pixel electrode 208 is formed by patterning the reflective metal and the transparent electrode together using the photoresist pattern as a mask, the photoresist pattern is then ashed so as to form a thickness of the photoresist pattern corresponding to the transflective portion And the reflective metal is etched by leaving only the photoresist pattern corresponding to the remaining light-shielding portions, so that the reflective electrode 209 is formed only on the portion corresponding to the reflective portion R.

As described above, in the manufacture of the thin film transistor array substrate of the present invention, the source electrode / drain electrodes 203a / 203b are formed by directly contacting the active layer 202 and the gate insulating film 204 is interposed therebetween The formation of the gate electrode 205 makes it unnecessary to carry out a contact process (another definition of the contact hole of the interlayer insulating film) required to contact the source electrode / drain electrode with the semiconductor layer, The number of masks can be reduced from 7 masks to 5 masks in comparison with the conventional structure.

- Fifth Embodiment -

15A and 15B are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a fifth embodiment of the present invention.

The manufacturing method of the thin film transistor array substrate according to the fifth embodiment of the present invention is the same as the fourth embodiment except that the inorganic protective film is omitted in forming the protective film.

The same process will be briefly omitted, and the fourth mask process will be described as follows.

As shown in FIG. 15A, the organic passivation layer 216 is formed on the entire surface including the gate line 205 and the common line 205a.

Next, the organic passivation layer 216 and the gate insulating layer 204 are patterned using a fourth mask (not shown) to form a contact hole 207a exposing a part of the drain electrode 203b, The concavo-convex portion is defined on the organic protective film 216 corresponding to the portion (R). Here, the fourth mask is a halftone mask, a portion corresponding to the contact hole 207a corresponds to an opening, a portion corresponding to the reflective portion R corresponds to a concave-convex defining portion, and the remaining portion corresponds to a light- In this case, when the contact hole 207a is defined, the thickness of the organic passivation layer 216 may be partially removed to define the concavity and convexity of the reflective portion R in correspondence to the transflective portion.

In this case, a process of reflowing may be added in order to soften the emboss structure of the irregularities of the surface of the reflection portion R after patterning of the organic protective film 216 using the fourth mask.

15B, a transparent electrode and a reflective metal are sequentially deposited to cover the inner surface of the contact hole 207a and the surface of the organic passivation layer 216, and then a photoresist (not shown) is formed on the reflective metal And then patterned using a fifth mask (not shown) as a diffraction mask to form a photoresist pattern. Then, the reflective metal and the transparent electrode are selectively removed using the photoresist pattern to form the reflective electrode 218 and the pixel Electrode 217 is formed.

The fifth mask is a diffraction exposure mask in which a portion corresponding to the reflection portion R is defined as a light shielding portion and a portion of the pixel electrode 217 remaining except for the reflection portion R is a half- And a buoy where the pixel electrode and the reflective electrode are not formed is defined as a light shielding portion. Since the method of forming the reflective electrode 218 and the pixel electrode 217 is the same as the method according to the fourth embodiment, the description of the patterning method is omitted.

- Sixth Embodiment -

FIGS. 16A to 16D are process plan views illustrating a method of manufacturing a thin film transistor array substrate according to a sixth embodiment of the present invention, and FIGS. 17A to 17F are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a sixth embodiment of the present invention Fig.

The manufacturing method of the thin film transistor array substrate according to the sixth embodiment of the present invention is the same as the second mask process (FIGS. 13D to 14D) of the fourth embodiment described above, and the subsequent steps will be described in detail. same.

17A, an active layer 202 is formed by a first mask process and is contacted with the doped region 202b of the active layer 202 and the doped region 202b by a second mask process A source electrode 203a and a drain electrode 203b and a data line 203 connected to the source electrode 203a and formed in a vertical direction are formed.

Here, in the first mask process, as shown in the drawing, the active layer 221 may be left under the data line 203, or may be formed as a single layer of the data line 203.

A gate insulating layer 204 is formed on the entire surface including the active layer 202, the data line 203 made of the data metal layer and the source electrode 203a and the drain electrode 203b. Proceed with the activation process. After the inorganic protective film 222 is deposited on the gate insulating film 204, the hydrogenation process is performed. In this case, after the deposition of the inorganic protective film 222, the activation and the hydrogenation process may be performed together.

As shown in FIGS. 16A and 17B, a photoresist film is coated on the inorganic protective film 222 and then patterned using a third mask to form a photoresist pattern 223. In this case, the third mask is a kind of halftone mask, and the transmissive portion, the transflective portion and the shielding portion are defined together. At this time, when the component of the photoresist pattern 223 is a photoresist film, the portion where the gate line and the common line are to be formed on the data line corresponds to the transflective portion of the third mask, and the remaining gate line, The forming region corresponds to the opening portion of the third mask, and the remaining regions correspond to the light shielding portion of the third mask. The thickness of the photoresist pattern 223 corresponding to the transmissive portion is entirely removed in the exposure and development steps, the thickness of the applied portion remains corresponding to the light shielding portion, And a diffractive portion D having a different thickness at the light shielding portion. This photoresist pattern 223 is defined to form a gate line, a common line, and a gate electrode.

Here, when the component of the photosensitive film pattern 223 is a negative photosensitive film, the arrangement of the light shielding portion and the opening portion of the third mask described above may be reversed.

Next, the inorganic protective film 222 is etched using the photoresist pattern 223 as a mask to form an inorganic protective film pattern 222a.

Next, as shown in FIGS. 16B and 17C, the photosensitive film pattern 223 is ashed to leave a photosensitive film residual layer 223a. At this time, the entire thickness corresponding to the diffraction part D is removed in the ashing process, and the inorganic protective film pattern 222a on the data line 203 is exposed. In this case, the remaining photoresist residual layer 223a is formed to have a sufficient thickness and close to an inverse taper, so that the photoresist residual layer 223a and the upper The removal of the gate metal layer is performed smoothly so that electrical separation between the gate metal layers disposed between the photoresist residual layers 223a is normally performed.

17D, a gate metal layer 224 is deposited on the exposed gate insulating layer 204 or the inorganic passivation layer pattern 222a or the photoresist layer 223a. At this time, the photoresist residual layer 223a is formed to have a sufficient thickness and close to the reverse taper, so that the gate metal layer is hardly left on the side thereof.

16C and 17E, the photoresist residual layer 223a and the gate metal layer 224 thereon are lifted off and removed. At this time, the remaining gate metal layer is a gate line 225 in the direction intersecting the data line 203 and a common line 225a parallel thereto. A gate electrode formed to correspond to the region between the source electrode 203a and the drain electrode 203b from the gate line 225 is formed to be protruded.

16D and 17F, an organic protective film 226 is formed on the inorganic protective film pattern 222a including the gate line 225 and the common line 225a, and the organic protective film 226, A contact hole 237 for selectively exposing a portion of the drain electrode 203b by selectively patterning the protective film pattern 222a and the gate insulating film 204 is defined.

After sequentially depositing a transparent electrode and a reflective metal so as to cover the inner surface of the contact hole 237 and the surface of the organic passivation layer 216, a photosensitive film (not shown) is coated on the reflective metal, The reflective metal layer and the transparent electrode are selectively removed using the photoresist pattern to form the reflective electrode 228 and the pixel electrode 227 in a patterned state using a fifth mask (not shown) .

The fifth mask is a diffraction exposure mask in which a portion corresponding to the reflection portion R is defined as a light shielding portion and a portion of the pixel electrode 227 remaining except for the reflection portion R is a semitransparent portion And a buoy where the pixel electrode and the reflective electrode are not formed is defined as a light shielding portion. Since the method of forming the reflective electrode 228 and the pixel electrode 227 is the same as the method according to the fourth embodiment, the description of the patterning method will be omitted.

The sixth embodiment described above differs from the fourth embodiment in the configuration of the lower portion of the gate metal layer. In this manner, the interlayer thickness between the gate line 225 or the common line 205a overlapping the data line 203 (Gate insulating film + inorganic protective film) is to prevent an increase in parasitic capacitances between gate metal layer lines (gate lines and common lines) and data lines.

As described above, the method of manufacturing a thin film transistor array substrate of the present invention is a method of manufacturing a thin film transistor array substrate in which the number of masks is reduced and the layer to be patterned, which is required for one mask process, and the step of coating the photoresist, The required number of steps can be reduced to 4 steps or 12 steps, thereby improving the yield.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

1 is a cross-sectional view of a conventional thin film transistor array substrate in a transmission mode

2 is a flowchart showing a conventional manufacturing method of a thin film transistor array substrate in a transmission mode

3 is a flowchart showing a conventional method of manufacturing a thin film transistor array substrate in a transflective mode

4 is a flowchart showing a manufacturing method of the thin film transistor array substrate of the transmission mode of the present invention

5 is a cross-sectional view showing a thin film transistor array substrate in a transmission mode formed by the manufacturing method of FIG.

6A to 6G are process plan views illustrating a method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention

7A to 7H are cross-sectional views showing a manufacturing method of the thin film transistor array substrate according to the first embodiment of the present invention

8A to 8B are cross-sectional views showing a manufacturing method of a thin film transistor array substrate according to a second embodiment of the present invention

9A to 9E are process plan views illustrating a method of manufacturing a thin film transistor array substrate according to a third embodiment of the present invention

10A to 10F are cross-sectional views showing a manufacturing method of a thin film transistor array substrate according to a third embodiment of the present invention

11 is a flowchart showing a method of manufacturing the transflective mode thin film transistor array substrate of the present invention

12 is a cross-sectional view of a transflective mode thin film transistor array substrate of the present invention having the method of FIG. 11 formed thereon

13A to 13G are process plan views illustrating a method of manufacturing a thin film transistor array substrate according to a fourth embodiment of the present invention

14A to 14H are cross-sectional views showing a manufacturing method of a thin film transistor array substrate according to a fourth embodiment of the present invention

15A and 15B are cross-sectional views showing a manufacturing method of a thin film transistor array substrate according to a fifth embodiment of the present invention

16A to 16D are process plan views illustrating a method of manufacturing a thin film transistor array substrate according to a sixth embodiment of the present invention

FIGS. 17A to 17F are cross-sectional views showing a manufacturing method of a thin film transistor array substrate according to a sixth embodiment of the present invention

Description of the Related Art [0002]

100: substrate 101: buffer layer

102: active layer 103: data line

103a: source electrode 103b: drain electrode

104: gate insulating film 105: gate line

105a: common line 106: inorganic shielding film

107: organic passivation layer 117: contact hole

108: pixel electrode 209: reflective electrode

R:

Claims (11)

Forming an active layer of polysilicon on the substrate; Forming a first photoresist pattern on a substrate including the active layer; Implanting impurities into both sides of the active layer using the first photoresist pattern as a mask to define a doped region; Forming a data metal layer on the substrate including the first photoresist pattern and the active layer; The data metal layer is removed by lifting off the first photoresist pattern and the data metal layer on the first photoresist pattern, and only the data metal layer remaining in contact with the upper portion of the doped region of the active layer is defined as a source electrode and a drain electrode, ; Forming a gate insulating film on the substrate including the data line, the source electrode, the drain electrode, and the active layer; Depositing a first inorganic protective film on the gate insulating film; Forming a second photoresist pattern remaining on the gate line and the gate electrode formation portion on the first inorganic protective film; Selectively removing the first inorganic protective film that does not overlap with the data line using the second photosensitive film pattern; Depositing a gate metal layer on the entire surface including the second photosensitive film pattern after ashing the second photosensitive film pattern to expose the first inorganic protective film on the data line; Removing the second photoresist pattern and the gate metal layer on the second photoresist pattern to form a gate metal layer that is left in a direction intersecting the data line as a gate line and a gate metal layer protruding therefrom as a gate electrode; Forming a top protective film on a front surface including the gate line and the gate electrode and forming a contact hole exposing a part of the drain electrode; And And forming a pixel electrode in the contact hole and on the upper passivation layer. The method according to claim 1, Wherein a portion where the first photoresist pattern is not formed is defined as a formation portion of a data line and a source electrode and a drain electrode in the step of forming the first photoresist pattern. The method according to claim 1, The step of forming the upper protective film Wherein the second inorganic protective film is deposited, and then a hydrogenation process is performed, and then an organic protective film is deposited. delete The method according to claim 1, Wherein the second photoresist pattern is formed by using a diffraction exposure mask or a halftone mask in which a transflective portion is defined in a portion overlapping with the data line. The method of claim 3, Wherein a reflective electrode is further formed on a part of the pixel electrode. The method according to claim 6, The reflective electrode Wherein the mask is defined by the same mask as the mask for forming the pixel electrode. The method according to claim 6, Wherein the reflective electrode corresponding portion on the organic protective film has projections and depressions. 9. The method of claim 8, Wherein the concavity and convexity of the reflective electrode corresponding portion is defined together with the formation of the contact hole of the organic passivation layer. delete delete

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