JP2008270241A - Active matrix display device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of manufacturing steps and improve productivity. <P>SOLUTION: A TFT array substrate 11 is provided with an insulating substrate 21. A polysilicon layer 22 is formed on one part of the insulating substrate 21. The polysilicon layer 22 has a channel region 22a, a source region 22b and a drain region 22c which constitute a TFT element 14. A wiring layer 23 is formed so as to partially cover each of the source region 22b and the drain region 22c on the polysilicon layer 22. A gate insulating film 24 is formed on both the wiring layer 23 and the polysilicon layer 22 where the wiring layer 23 is not laminated so as to cover the layers. On the gate insulating film 24, a gate electrode layer 25 is formed on a position opposite the channel region 22a via the gate insulating film 24. A capacitor upper electrode layer 26 is formed on one part of the surface of the gate insulating film 24. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an active matrix display device and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, an active matrix display device including a thin film transistor (TFT) element that drives a pixel at each intersection of a data line and a scanning line is known. This active matrix display device has a higher image quality than the passive matrix display device having no active element in the pixel, and has become the mainstream of high-quality organic EL display devices and liquid crystal display devices.

  Polysilicon or alpha moss silicon can be used as the material of the TFT element of this active matrix display device. Polysilicon has a higher TFT driving capability than alpha moss silicon, and can realize a higher performance active matrix display device.

  A TFT element (LTPS-TFT) made of low-temperature polysilicon can be made on an insulating substrate such as a glass substrate as a peripheral circuit of the display device, whereby the periphery of the display device can be simplified and the display device can be narrowed. And high reliability can be realized. When LTPS-TFT is used in the liquid crystal display device, the capacitance of the switching transistor arranged for each pixel is reduced, and the area of the capacitor connected to the drain side of the switching transistor is reduced. Thereby, a high-brightness liquid crystal display device (LCD) having high resolution and a high aperture ratio can be realized. At present, the liquid crystal display device using LTPS-TFT realizes a high resolution of QVGA (pixel number: 240 × 320) and VGA (pixel number: 480 × 640) with the size of a small panel for a mobile phone. Yes.

LTPS-TFT generally has many manufacturing processes and low productivity. In order to solve this problem, a configuration is known in which the source wiring and the drain wiring are arranged under the gate insulating film, and the source wiring and the drain wiring are directly connected to the source region and the drain region of the silicon layer ( Patent Documents 1 to 4). In such a configuration, the source wiring and the drain wiring also function as the lower electrode of the capacitor, and it is possible to omit the formation of the polysilicon for the lower electrode that has been conventionally formed between the wiring layer and the silicon layer.
Japanese Patent Laid-Open No. 6-194689 JP 2003-131260 A Japanese Patent Laid-Open No. 10-177163 Japanese Patent Laid-Open No. 10-254383

  In the active matrix display device described above, a silicon layer is formed on a wiring layer made of metal. In a normal LTPS-TFT manufacturing process, the surface of the alpha moss silicon layer is locally heated with a laser to crystallize the alpha moss silicon layer to form a silicon layer. During this heating, metal diffuses from the wiring layer formed under the silicon layer to the silicon layer. As a result, there is a problem that the junction of the TFT element formed in the silicon layer deteriorates and the leakage current increases.

  The source / drain regions having metal wirings at the end portions have a linear heating region, so that the crystal structure is different in each of the vertical and parallel directions. This difference in crystal structure causes a difference in TFT characteristics in each pixel within a certain display device. Due to these problems, when the active matrix display device is applied to an LTPS-TFT, variations in TFT characteristics and leakage occur, resulting in a decrease in reliability.

  In the active matrix display device according to the present invention, a plurality of scanning lines and a plurality of data lines intersecting the scanning lines are arranged, and one pixel is formed in a region surrounded by the scanning lines and the data lines, Corresponding to each pixel, an active matrix display device having at least one thin film transistor connected to the scan line and the data line at each intersection of the scan line and the data line, the source region of the thin film transistor , A drain region, a silicon layer having a channel region formed between the source region and the drain region, a first wiring layer formed on the silicon layer and connected to the source region, and the silicon A second wiring layer formed on the layer and connected to the drain region; and formed on the first and second wiring layers. A gate insulating film; and a gate electrode layer formed on the gate insulating film, the side surface of the first wiring layer that is separated from the channel region, and the second wiring layer The side surface on the side separated from the channel region does not protrude beyond the side surface of the silicon layer.

  The present invention has been made with respect to the above problems, and has the effects of simplifying the manufacturing process and improving reliability and productivity.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
First embodiment.
FIG. 1 is a plan view showing a configuration of an active matrix display device according to a first embodiment of the present invention as an example of a liquid crystal display device. This active matrix display device has a configuration in which a liquid crystal layer (not shown) is sandwiched between a TFT array substrate 11 and a counter substrate 12.

  As shown in FIG. 1, the TFT array substrate 11 includes a plurality of scanning lines GL and a plurality of data lines DL. Pixel electrodes 13 are respectively disposed in regions surrounded by the scanning lines GL and the data lines DL. At least one TFT element 14 is connected to one pixel electrode 13. The TFT element 14 has a source connected to the data DL, a gate connected to the scanning line GL, and a drain connected to the pixel electrode 13. A counter electrode (not shown) formed on the counter substrate 12 is disposed opposite to the pixel electrode 13. A common potential is supplied to the counter electrode, whereby the TFT element 14 controls an electric field applied to the liquid crystal layer between the pixel electrode 13 and the counter electrode. A capacitor 10 is connected between the drain of the TFT element 14 and the pixel electrode 13. The capacitor 10 is configured to accumulate electric charges of a signal input to the pixel electrode 13.

  The TFT array substrate 11 includes a scanning line driving circuit 15 that drives the scanning lines GL and a data line driving circuit 16 that drives the data lines DL. The scanning line driving circuit 15 and the data line driving circuit 16 receive a control signal from the outside, and selectively drive the scanning line GL and the data line DL based on the control signal. In this embodiment, the scanning line driving circuit 15 and the data line driving circuit 16 are formed inside the TFT array substrate 11, but the scanning line driving circuit 15 and the data line driving circuit 16 are outside the TFT array substrate 11. It may be provided.

  FIG. 2 is a plan view showing the vicinity of the intersection of the scanning line GL and the data line DL of the TFT array substrate 11 when one TFT for one pixel is provided. 3 is an XY cross-sectional view of FIG. The TFT array substrate 11 includes an insulating substrate 21. The insulating substrate 21 preferably has a protective insulating layer formed on a glass substrate. Even when the protective insulating layer is formed on the conductive substrate, the effect of the present invention can be obtained. A polysilicon layer 22 is formed on the insulating substrate 21. The polysilicon layer 22 includes a channel region 22a, a source region 22b, and a drain region 22c that constitute the TFT element 14. The channel region 22a is formed in a region sandwiched on both sides by the source region 22b and the drain region 22c.

  A wiring layer 23 is formed on the polysilicon layer 22 so as to cover a part of each of the source region 22b and the drain region 22c. The wiring layer 23 is formed of a conductive material in which an underlying silicon layer 23c, a metal layer 23a, and an interface conductive film 23b are stacked in this order from the bottom. An interfacial conductive film 23b is formed on the surface of the metal layer 23a, and an underlay silicon layer 23c is formed on the bottom surface of the metal layer 23a. The side surface far from the channel region 22a of the wiring layer 23 is formed inside the side surface of the polysilicon layer.

  The wiring layer 23 is preferably made of a metal having a high melting point and conductivity so that it can withstand high-temperature heat treatment in the manufacturing process. The metal layer 23a and the interfacial conductive film 23b preferably contain at least one of Ti, Cr, Zr, Ta, W, Mo, TiN, ZrN, TaN, WN, and VN. Since the resistance of the wiring layer 23 greatly affects the performance of the TFT array substrate 11, it is preferable that the metal layer 23 a is composed mainly of Al or Cu when further resistance reduction is required. In order to reduce metal contamination from the metal layer 23 a to the underlying polysilicon layer 22, an interfacial conductive film may be further provided between the metal layer 23 a and the polysilicon layer 22. The underlying silicon layer 23c is made of alpha moss or microcrystalline silicon in order to reduce the resistance at the interface between the wiring layer 23 and the polysilicon layer 22, and has a source region 22b and a drain that the underlying polysilicon layer 22 has. An impurity having the same conductivity type as that of the region 22c is included.

  The gate insulating film 24 is formed so as to cover the wiring layer 23 and the surface of the polysilicon layer 22 that becomes the channel region 22a. A gate electrode layer 25 is formed on the gate insulating film 24 at a position facing the channel region 22a with the gate insulating film 24 interposed therebetween. The gate electrode layer 25 constitutes the TFT element 14 together with the polysilicon layer 22 having the channel region 22a, the source region 22b, and the drain region 22c. The gate electrode layer 25 extends in the vertical direction in FIG. 2 and constitutes a scanning line GL of the active matrix display device. A capacitor upper electrode layer 26 is formed on a part of the surface of the gate insulating film 24. The capacitor upper electrode layer 26 extends in the vertical direction in FIG. 2 in parallel with the gate electrode layer 25 and constitutes a common potential wiring. This common potential wiring also serves as the capacitor upper electrode layer 26 and constitutes the capacitor 10 with the wiring layer 23 arranged in the lower layer, and accumulates the charge of the signal input to the pixel.

  When it is desired to change the capacitance of the capacitor 10, it is possible to partially change the film thickness or film type of the gate insulating film 24. In the gate electrode layer 25 and the capacitor upper electrode layer 26, interfacial conductive films 25b and 26b are formed on the surfaces of the metal layers 25a and 26a. An interlayer insulating film 27 is formed on the gate electrode layer 25 and the capacitor upper electrode layer 26. A pixel electrode 13 is formed on the interlayer insulating film 27. The pixel electrode 13 is connected to the lower wiring layer 23 through a contact hole 28 formed in the gate insulating film 24 and the interlayer insulating film 27.

  Next, a manufacturing method of the active matrix display device configured as described above will be described. FIG. 4 is a first process diagram of the TFT array substrate according to the first embodiment. First, an alpha moss silicon film is formed on the insulating substrate 21 by using plasma CVD (Chemical Vapor Deposition). Amorphous silicon film is irradiated with XeCl excimer laser (wavelength: 308 nm) or YAG2ω laser (Yttrium Aluminum Garnet) (wavelength: 532 nm), so that the amorphous alpha moss silicon film becomes a polycrystalline polysilicon film. Convert to Thereby, the polysilicon layer 220 is formed.

Next, an alpha moss silicon film or a microcrystal silicon film into which p-type or n-type impurities are introduced is deposited by PECVD (plasma enhanced chemical vapor deposition). Here, in the case of introducing a p-type impurity, PECVD (in a mixed gas of phosphine (PH ₃ ) and silane (SiH ₄ ) in the case of introducing a n-type impurity in a diborane (B ₂ H ₆ ) gas. Perform Plasma Enhanced Chemical Vapor Deposition. Thereby, the underlying silicon layer 230c into which the p-type or n-type impurity is introduced is formed. Since the concentration of conductive impurities introduced into the underlying silicon layer 230c is determined by the concentration of diborane (B ₂ H ₆ ) or phosphine (PH ₃ ), diborane (B ₂ H ₆ ) or phosphine (PH ₃ ) It is preferable to use it diluted with hydrogen. When introducing an n-type impurity, silicon tetrafluoride (SiF ₄ ) can be used instead of silane (SiH ₄ ). A metal layer 230a is deposited on the formed underlying silicon layer 230c by sputtering. The surface of the metal layer 230a is covered with an interfacial conductive film 230b. Thereby, the wiring layer 230 is formed, and the TFT array substrate 11A shown in FIG. 4 is obtained.

  A first resist layer 31 is deposited on the wiring layer 230. Then, when exposed through a mask pattern (not shown) having a light transmitting part, a semi-light transmitting part, and a light shielding part, the first resist layer 31 is formed in a desired film thickness as shown in FIG. For example, if the first resist layer 31 is a positive type, a light-shielding portion is disposed in the region A that is not removed, a semi-translucent portion is disposed in the region B that is removed to some extent, and a translucent portion is disposed in the region C that is completely removed. Arrange. The first resist layer 31 remains in the region A, the first resist layer 31 remains in the region B according to the amount of light transmitted through the first resist layer 31, and the first resist layer 31 is removed in the region C. Thereby, the 1st resist layer 31 from which film thickness differs is formed. When the region A is a second region and the region B is a first region, the first resist layer 31 includes a first region and a second region.

As the semi-transparent portion of the mask pattern, a film having a low transmissivity with respect to g-ray light and i-line light used for normal exposure or a film having a light-shielding pattern below the resolution limit is used. Can do. The resolution limit used in normal lithography can be obtained by the following Rayleigh equation.
(Formula 1) R = k * λ / NA
(R: resolution limit dimension, k: coefficient by transfer process, NA: numerical aperture of projection optical system, λ: exposure wavelength)
In g-line projection lithography used for normal LCD manufacturing, k = 0.7, NA = 0.1, λ = 0.437 [μm], so the resolution limit dimension R = 3 [μm] is set. obtain. Therefore, a light-shielding pattern having a line width interval of 2 [μm] or less which is sufficiently smaller than the resolution limit dimension may be formed in the semi-translucent portion. FIG. 6 is a diagram showing the relationship between the exposure amount and the remaining film amount in a normally used positive resist. From this figure, the exposure amount that passes through the semi-translucent portion may be set so that, for example, the exposure amount is about 30 to 50%.

Using the first resist layer 31 thus formed in a predetermined shape as a mask, the wiring layer 230 and the polysilicon layer 220 in the region C are removed by etching. That is, the wiring layer 230 and the polysilicon layer 220 located in the region (region C) other than the first and second regions are removed. Thereby, the TFT array substrate 11B shown in FIG. 5 having the polysilicon layer 221 and the wiring layer 231 having the underlying silicon layer 231c, the metal layer 231a, and the interface conductive film 231b is obtained.
The etching of the wiring layer 230 and the polysilicon layer 220 can be formed by etching with different etching gas and conditions. For etching the wiring layer 230, wet etching may be used. Next, the film thickness of the first resist layer 31 is reduced by etching. This etching is performed to a depth where the wiring layer 23 is exposed in the region B. As described above, the first resist layer 31 is etched and the first region is removed, thereby forming the second resist layer 32 having the second region. For the etching, RIE (Reactive Ion Etching) using O ₂ gas can be used. When performing the RIE using O _{2 gas,} when mixing CF 4, SF ₆ or the like _{O 2} gas, the etching rate becomes faster along with etching can be stabilized.

  Next, as shown in FIG. 7, the wiring layer 231 in the region B is removed by etching using the second resist layer 32 as a mask. The side surface of the wiring layer 23 may be formed more inside than the side surface of the polysilicon layer 221 due to side etching during etching. Since the second resist layer 32 is formed only in the second region (region A), the wiring layer 231 other than the second region is removed. As a result, the wiring layer 23 having the underlying silicon layer 23c, the metal layer 23a, and the interface conductive film 23b is formed, and the TFT array substrate 11C is obtained. Dry etching is preferably used for etching the underlying silicon layer 231c. When dry-etching the underlying silicon layer 231c, it is necessary to determine the dry etching conditions in consideration of the etching characteristics of the underlying polysilicon layer 221. When the second resist layer 32 is removed, a TFT array substrate 11D shown in FIG. 8 is obtained.

Next, as shown in FIG. 9, a gate insulating film 24 is formed on the surfaces of the wiring layer 23 and the polysilicon layer 22. As the gate insulating film 24, a SiO ₂ film can be formed by PECVD using a material gas containing TEOS (Tetra Ethyl Ortho Silicate). On the gate insulating film 24, Al or an Al alloy is deposited by sputtering, and the gate electrode layer 25 and the capacitor upper electrode layer 26 are simultaneously formed by photoetching. For the gate electrode layer 25 and the capacitor upper electrode layer 26, it is necessary to select a material having good electrical connection with the pixel electrode 13. For example, when ITO (Indium Tin Oxide) is used for the pixel electrode 13, two layers (or laminates) constituting the gate electrode layer 25 and the capacitor upper electrode layer 26 are bonded to the surface of the metal layers 25a and 26a with ITO. It is preferable to deposit interfacial conductive films 25b and 26b such as TiN having good properties by sputtering. Thereby, the TFT array substrate 11E shown in FIG. 9 is obtained.

  Next, as shown in FIG. 10, ion implantation is performed using the gate electrode layer 25 as a mask to form a source region 222b and a drain region 222c. As a result, a polysilicon layer 222 having a channel region 222a, a source region 222b, and a drain region 222c between the source region 222b and the drain region 222c is formed, and a TFT array substrate 11F as shown in FIG. 10 is obtained. As the mask, both a resist (not shown) formed on the gate electrode layer 25 in addition to the gate electrode layer 25 can be used.

  Next, impurities are diffused from the underlying silicon layer 23c to the polysilicon layer 222 side by heat treatment or the like to form a polysilicon layer 22 having a channel region 22a, a source region 22b, and a drain region 22c, as shown in FIG. . By diffusing impurities in this manner, the contact area between the underlying silicon layer 23c and the source region 22b and drain region 22c is increased, and the electrical connection between the wiring layer 23 and the source region 22b and drain region 22c is stabilized. . Next, an interlayer insulating film 27 is formed so as to cover the gate insulating film 24, the gate electrode layer 25, and the capacitor upper electrode layer 26. The contact hole 28 is formed by photoetching and penetrates the interlayer insulating film 27 and the gate insulating film 24. For this photoetching, it is desirable to use dry etching. Thereby, a TFT array substrate 11G as shown in FIG. 11 is obtained.

  Next, the pixel electrode 13 is formed on the interlayer insulating film 27 and in the contact hole 28. Thereby, the TFT array substrate 11 shown in FIG. 3 is obtained. In the case of manufacturing a transmissive LCD, the pixel electrode 13 is formed by depositing a transparent conductive film such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide) by sputtering. Can be formed. In the case of manufacturing a reflective LCD, the pixel electrode 13 uses a reflective electrode such as Al or Ag.

  In the active matrix display device configured as described above, since the wiring layer 23 is also formed on the polysilicon layer 22 other than the channel region 22a and the multi-tone exposure technique is used, the polysilicon layer 22 and the wiring layer 23 are used. Since the patterning can be performed in one photolithography process, the manufacturing process is reduced. According to this embodiment, when the amorphous silicon film is crystallized by laser irradiation, the amorphous silicon film is not in contact with the metal, so that the crystallization is performed uniformly, and the crystallization that occurs when the amorphous silicon film is in contact with the metal is prevented. There is no variation in TFT characteristics due to uniformity.

  In general, the etching selectivity between the silicon layer 22 and the silicon oxide film or silicon nitride film constituting the gate insulating film 24 is low, and the polysilicon layer 22 penetrates when the contact hole 28 is opened. However, in the present embodiment, since the wiring layer 23 having high etching selectivity is interposed between the gate insulating film 24 in which the contact hole 28 is formed and the polysilicon layer 22, penetration is unlikely to occur. Thereby, the contact hole 28 can be formed stably, and the productivity of the active matrix display device can be improved. Since the wiring layer 23 functions as the lower electrode of the capacitor 10, a conventional polysilicon layer for the lower electrode is not necessary.

Second embodiment.
FIG. 12 is a partial cross-sectional view of a TFT array substrate according to the second embodiment of the present invention. The overall configuration is the same as that of FIG. 1 described in the first embodiment. Hereinafter, about the same component, the description is abbreviate | omitted by attaching | subjecting the same code | symbol. A feature of the TFT array substrate of the second embodiment is that the pixel electrode 13 is connected to the wiring layer 23 in an area larger than that of the first embodiment.

  As shown in FIG. 12, this TFT array substrate has an insulating substrate 21, a polysilicon layer 22, a wiring layer 23, a gate insulating film 24, a gate electrode layer 25, and a capacitor upper electrode layer 26, as in the first embodiment. And an interlayer insulating film 27. The pixel electrode 13 formed on the interlayer insulating film 27 is formed so as to be in contact with the surface of a part of the exposed portion of the wiring layer 23 after etching away the interlayer insulating film 27 in a predetermined portion of the pixel and the gate insulating film 24 therebelow. Is done.

  Since the TFT array substrate configured as described above can connect the wiring layer 23 and the pixel electrode 13 with a wide contact area, a pixel defect due to a contact failure hardly occurs. Further, when a transparent conductive film is used as a material of the pixel electrode 13 and a transmissive liquid crystal display device is formed, the interlayer insulating film 27 and the gate insulating film 24 are not provided in a place serving as a transmissive region. The light quantity of the backlight due to the insulating film does not decrease.

  When the second embodiment is applied to a transflective LCD, the wiring layer 23 can be configured as a reflective electrode and the pixel electrode 13 can be configured as a transparent electrode. In this case, it is preferable to remove as much as possible the transparent electrode (pixel electrode 13) located on the reflective electrode (wiring layer 23). Thereby, the reflectance of a reflective electrode (wiring layer 23) can be improved. If the interfacial conductive film 23b on the reflective electrode (wiring layer 23) is removed, the reflectance can be further increased.

Third embodiment.
FIG. 13 is a partial cross-sectional view of a TFT array substrate according to the third embodiment of the present invention. The overall configuration is the same as that of FIG. 1 described in the first embodiment. The feature of the third embodiment is that the underlying silicon layer 23c in the first embodiment is not provided. Since the underlying silicon layer 23c contains a conductive impurity, it is advantageous for an active matrix display device composed of only one of an n-channel TFT and a P-channel TFT. However, in an active matrix display device including a complementary circuit configuration formed by both n-channel and P-channel TFTs, a patterning process is required to distinguish the conductivity type of the underlying silicon layer 23c. In the third embodiment, there is no underlying silicon 23c, and there is no such patterning process. However, a device for doping conductive impurity ions into the polysilicon layer through the wiring layer 23 is required.

  An interfacial conductive film 23d is formed on the bottom surface of the metal layer 23a. The source region 22b and the drain region 22c are formed by doping conductive impurities through the wiring layer 23 after the wiring layer 23 is patterned or before the wiring layer 23 is patterned. Since other configurations are substantially the same as those of the first embodiment, description thereof is omitted.

In order to self-align the gate electrode layer 25 and the channel region 22a, it is desirable to form the source region 22b and the drain region 22c by selective ion implantation after forming the gate electrode layer 25 and using the gate electrode layer 25 as a mask. During the selective ion implantation, the wiring layer 23 on the polysilicon layer 22 in the source region 22b and the drain region 22c becomes an obstacle to ion implantation. At the time of ion implantation, it is necessary to devise measures such as reducing the thickness of the gate insulating film 24 in the ion implanted portion and reducing the thickness of the wiring layer 23. The metal layer 23a and the interfacial conductive films 23b and 22d are preferably made of a material having a relatively low ion stopping power. According to SRIM (Non-Patent Document 1), which is a simulation software for ion implantation, the order of ion stopping power at ion energies of 100 to 200 [keV] is as follows.
James F. Ziegler, "The Stopping and Range of Ions in Matter", [online], [Search April 2, 2007], Internet <URL: http://www.srim.org/>

Stopping power ranking in phosphorus ions; Si <Al <Ti <Zr ≦ Sn <Cu
Stopping power ranking in boron ions; Si <Al <Ti ≦ Zr <Sn <Cu
From the above order, the wiring layer 23a is desirably an Al film, and the interfacial conductive films 23b and 23c are desirably films containing Ti, Zr, and conductive Ti and Zr compounds. Alternatively, it is desirable that the wiring layer 23 be a single layer film containing Ti, Zr and conductive Ti, Zr compounds. However, from the viewpoint of wiring resistance, a combination of Al and an interfacial conductive film is preferable.

  According to Non-Patent Document 1, since the implantation depth of phosphorus ions is about 1/3 of the implantation depth of boron ions, phosphorous ions are more difficult to implant than boron ions. The phosphorus ions that form the n-type region require approximately three times the implantation energy of the boron ions that form the p-type region.

  According to Non-Patent Document 1, when the gate insulating film 24 is a silicon oxide film having a thickness of 300 mm, the wiring layer 23 is an Al film having a thickness of 650 mm, and the interface conductive films 23b and 23d are Ti films having a thickness of 200 mm, phosphorus ions The energy for injecting silicon into the polysilicon layer 22 is required to be 100 [keV] or more. When only the thickness of the wiring layer 23 formed of Al is changed to 1600 mm, the implantation energy needs to be 200 [keV] or more.

  Similarly, according to Non-Patent Document 1, when the gate insulating film 24 is a silicon oxide film having a thickness of 300 mm, the wiring layer 23 is an Al film having a thickness of 2100 mm, and the interfacial conductive films 23b and 23d are Ti films having a thickness of 200 mm. The energy for implanting boron ions into the polysilicon layer 22 is required to be 100 [keV] or more. Compared with the condition of phosphorus ion implantation, it can be seen that boron ion implantation is much easier.

  When the TFT array substrate configured as described above is applied to an active matrix display device including a complementary circuit configuration formed by both n-channel and p-channel TFT transistors, the conductivity of the underlying polysilicon layer 22 is determined. There is no need to pattern the underlying silicon layer 23c in accordance with the mold. Thereby, the manufacturing process of the active matrix display device can be simplified and the productivity can be improved. In the third embodiment, the second embodiment can be implemented, and the pixel electrode 13 can be connected to the wiring layer 23 in a larger area than in the first embodiment.

Fourth embodiment.
FIG. 14 is a partial cross-sectional view of a TFT array substrate according to the fourth embodiment of the present invention. The overall configuration is the same as that of FIG. 1 described in the first embodiment. The feature of the fourth embodiment is that the wiring layer 23 formed above the source region 22b in the first embodiment is partially in contact with the channel region 22a. Here, since the underlying silicon layer 23c is formed in the wiring layer 23, the metal layer 23a and the channel region 22a are not connected and do not short-circuit. The gate electrode layer 25 is formed closer to the source region 22b than in the first embodiment. In the manufacturing method of the TFT array substrate, in the first embodiment, the gate electrode layer 25 is formed so as to overlap the wiring layer 23 on the source region 22b.

  As described above, by reducing the region of the source region 22b that does not overlap with the wiring layer 23, the resistance of the source region 22b occupying a large proportion of the parasitic resistance of the TFT element 14 can be reduced. When the fourth embodiment is applied to a TFT array substrate having an LDD (Lightly Doped Drain) structure or a GOLD (Gate Overlapped Lightly Doped Drain) structure, the resistance on the source side can be further reduced. However, in the fourth embodiment, since the opening accuracy of the wiring layer 23 is deteriorated, the gate length may vary as compared with the first embodiment.

Fifth embodiment.
FIG. 15 is a partial cross-sectional view of a TFT array substrate according to the fifth embodiment of the present invention. The overall configuration is the same as that of FIG. 1 described in the first embodiment. The feature of the fifth embodiment is that the wiring layer 23 is in contact with both sides of the surface of the channel region 22a. Since the underlying silicon layer 23c is formed in the wiring layer 23, the underlying silicon layer 23c constitutes the source region 22b and the drain region 22c, and the metal layer 23a is not electrically short-circuited to the channel region 22a. In the method of manufacturing the TFT array substrate, in the first embodiment, the gate electrode layer 25 may be formed so as to overlap the wiring layer 23 on the source region 22b and the drain region 22c.

  With this structure, since the source region 22b and the drain region 22c are directly connected to the wiring layer 23, the resistance of the source region 22b and the drain region 22c is reduced, and the parasitic resistance of the TFT element 14 is greatly reduced. Since the surfaces of the source region 22b and the drain region 22c are covered with the wiring layer 23, the ion implantation step can be omitted. The underlying silicon layer 23c is doped with n-type or p-type impurities. By controlling the impurity concentration, the electric field strength at the interface between the channel region 22a and the drain region 22c is reduced, and the hot electron effect is obtained. Can be reduced. In the fifth embodiment, since the opening accuracy of the wiring layer 23 is deteriorated, the gate length may vary as compared with the first embodiment.

  In the first to fifth embodiments, an active matrix display device in which TFT elements 14 are made of low-temperature polysilicon formed by laser annealing is taken as an example. The effects of the present invention can also be achieved by using low-temperature polysilicon formed by other methods or crystalline silicon formed by various other methods instead of such low-temperature polysilicon. For example, the present invention can also be implemented in an active matrix display device using microcrystalline silicon as a TFT element.

  The effects of improving the productivity and reliability of the present invention can be achieved by using not only crystalline silicon but also amorphous silicon. When amorphous silicon is used, the silicon layer 22 and the underlying silicon layer 23c containing conductive impurities can be formed in succession, and the productivity is further improved.

  In the first to fifth embodiments, the SA (Self Aligned) TFT has been described. However, the present invention can also be applied to a TFT having an LDD or GOLD structure. In the first to fifth embodiments, the LCD is taken as an example, but the present invention is not limited to the LCD, and can be applied to other active matrix display devices such as an active matrix organic EL. . When the present invention is applied to a bottom emission type organic EL, a transparent electrode such as ITO, IZO, or IZTO is used as the pixel electrode 13 as in the case of a transmissive LCD. When the present invention is applied to a top emission type organic EL, a transparent electrode made of ITO, IZO, IZTO or the like and a reflective electrode made of a highly reflective material such as Al or Ag are used as the pixel electrode 13. Thereby, various types of active matrix display devices can achieve the same effects as the LCD described above.

1 is a plan view of an active matrix display device according to a first embodiment. It is a top view which shows the TFT array substrate which concerns on 1st Embodiment. It is XY sectional drawing of FIG. FIG. 6 is a first process diagram of the TFT array substrate according to the first embodiment. FIG. 6 is a second process diagram of the TFT array substrate according to the first embodiment. It is a figure which shows the relationship between exposure amount and the amount of remaining films. It is a 3rd process drawing of the TFT array substrate concerning a 1st embodiment. It is a 4th process drawing of the TFT array substrate concerning a 1st embodiment. It is a 5th process drawing of the TFT array substrate concerning a 1st embodiment. It is a 6th process drawing of the TFT array substrate concerning a 1st embodiment. It is a 7th process drawing of the TFT array substrate concerning a 1st embodiment. FIG. 6 is a partial cross-sectional view of a TFT array substrate according to a second embodiment. FIG. 5 is a partial cross-sectional view of a TFT array substrate according to a third embodiment. It is a partial cross section figure of the TFT array substrate which concerns on 4th Embodiment. FIG. 9 is a partial cross-sectional view of a TFT array substrate according to a fifth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Capacitor 13 ... Pixel electrode 21 ... Insulating substrate 22 ... Polysilicon layer 22a ... Channel region 22b ... Source region 22c ... Drain region 23 ... Wiring layer 24. ..Gate insulating film 25 ... Gate electrode layer 26 ... Capacitor upper electrode layer 27 ... Interlayer insulating film 28 ... Contact hole

Claims (10)

A plurality of scanning lines and a plurality of data lines intersecting each other are arranged, and one pixel is formed in a region surrounded by the scanning lines and the data lines, and the scanning lines and the data are corresponding to each pixel. An active matrix display device having a thin film transistor connected to the scanning line and the data line at each line intersection,
A silicon layer having a source region, a drain region of the thin film transistor, and a channel region formed between the source region and the drain region;
A first wiring layer formed on the silicon layer and connected to the source region; and a second wiring layer formed on the silicon layer and connected to the drain region;
A gate insulating film formed on the first and second wiring layers;
A gate electrode layer formed on the gate insulating film,
The side surface far from the channel region of the first wiring layer and the side surface far from the channel region of the second wiring layer do not protrude beyond the side surface of the silicon layer. Active matrix display device. Using the second wiring layer as a lower electrode,
A capacitor upper electrode layer formed on the gate insulating film;
An interlayer insulating film formed on the gate electrode layer and the capacitor upper electrode layer;
A pixel electrode formed on the interlayer insulating film and connected to the second wiring layer;
The active matrix display device according to claim 1, further comprising:   3. The active matrix display device according to claim 2, wherein the pixel electrode is connected to the second wiring layer through a contact hole formed in the gate insulating film and the interlayer insulating film.   3. The active matrix display device according to claim 2, wherein the pixel electrode is connected to a region including an end portion of the second wiring layer.   At least one of the first wiring layer and the second wiring layer includes an underlying silicon layer having conductivity on the bottom surface, and is electrically connected to the channel region via the source region or the drain region. The active matrix display device according to claim 1, wherein the active matrix display device is provided.   The second wiring layer has a function as a reflective electrode that reflects incident light from a display surface side of the active matrix display device and contributes to display. 2. An active matrix display device according to item 1.   The first wiring layer and the second wiring layer include at least one of Ti, Cr, Ta, W, Mo, TiN, ZrN, WN, and VN. The active matrix display device according to any one of the above. A method of manufacturing an active matrix display device having a plurality of scanning lines, a plurality of data lines, and a thin film transistor connected to the scanning lines and the data lines,
A silicon layer is formed on one main surface of the insulating substrate,
Forming a wiring layer on the entire surface of the silicon layer;
Forming a first resist having first and second regions having different thicknesses on the wiring layer;
Removing the wiring layer and the silicon layer in regions other than the first resist;
Forming a second resist having the second region by removing the resist corresponding to the thickness of the first region of the first resist;
Removing the wiring layer in a region other than the second resist;
Removing the second resist;
A method of manufacturing an active matrix display device, comprising: forming a gate insulating film on the silicon layer and the wiring layer. A gate electrode layer and a capacitor upper electrode layer are simultaneously formed on the gate insulating film,
Forming an interlayer insulating film covering the gate electrode layer and the capacitor upper electrode layer;
The method of manufacturing an active matrix display device according to claim 8, wherein a pixel electrode is formed on the interlayer insulating film.   10. The active matrix according to claim 8, wherein the first and second regions are formed by exposing through a mask pattern having a light transmitting portion, a light shielding portion, and a semi-light transmitting portion. Manufacturing method of display device.

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