KR101198217B1 - LCD and Method of fabricating of the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device with a driving circuit integrated therein and a method of manufacturing the same.

The present invention provides a liquid crystal display device having a driving circuit integrated into a non-display portion including a driver portion and a display portion including a pixel region, wherein the light blocking means included in the non-display portion is configured on the upper color filter substrate. The light blocking means configured in the first aspect of the present invention is configured in the lower array substrate.

In addition, a seal pattern for bonding the array substrate and the color filter substrate is configured, wherein the light blocking means of the portion corresponding to the seal pattern is removed.

Description

LCD and its manufacturing method {LCD and Method of fabricating of the same}

FIG. 1 is a plan view schematically illustrating a general liquid crystal display device having a single integrated driving circuit.

2A and 2B are cross-sectional views schematically illustrating a configuration of a liquid crystal display device incorporating a driving circuit according to the related art.

3A to 3I and 4A to 4I are cross-sectional views illustrating a manufacturing process of an array substrate for a liquid crystal display device integrated with a driving circuit according to the prior art, according to a process sequence;

5 is a schematic plan view of a liquid crystal display device integrated with a driving circuit displaying light blocking means and a seal pattern;

6A and 6B are cross-sectional views schematically showing the configuration of the liquid crystal display device with integrated driving circuit of the present invention;

7A to 7C are cross-sectional views illustrating a manufacturing process of the driving circuit-integrated color filter substrate according to the present invention,

8A to 8J and FIGS. 9A to 9J are cross-sectional views illustrating a manufacturing process of an array substrate for a liquid crystal display device with integrated driving circuit according to the present invention, in the order of a process.

Description of the Related Art

CS: Color filter board AS: Array board

110: seal pattern 300: seal pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device with a driving circuit integrated therein and a method of manufacturing the same.

In general, a liquid crystal display device injects a liquid crystal between an array substrate including a thin film transistor (TFT) and a color filter substrate, and displays an image by using a difference in refractive index of light due to the anisotropy of the liquid crystal. It is a display device.

The thin film transistor used as the switching element of the display device may be configured in various forms according to the design of the array unit, and in particular, the semiconductor layer used as the active layer uses amorphous silicon or polycrystalline silicon (polysilicon).

In this case, a hydrogenated amorphous silicon (a-Si: H) is mainly used as a general switching element, because a low temperature process is possible and a low-cost insulating substrate may be used.

However, since hydrogenated amorphous silicon has a disordered atomic arrangement, weak Si-Si bonds and dangling bonds exist, and thus, they are changed to a quasi-stable state when irradiated with light or applied with an electric field, and used as a thin film transistor device. Stability is emerging as a problem, and its electrical characteristics (low field effect mobility: 0.1∼1.0㎠ / V? S) are not good, making it difficult to use as a driving circuit.

On the other hand, since polysilicon has a higher field effect mobility than amorphous silicon, a driving circuit can be made on a substrate.If the driving circuit is directly made on a substrate using polysilicon, the mounting becomes very simple and the liquid crystal panel is more compact. There is an advantage that can be produced.

1 is a schematic diagram of an array substrate for a liquid crystal display device incorporating a general driving circuit.

As illustrated, the insulating substrate 10 may be largely defined as a display unit D1 and a non-display unit D2, and a plurality of pixels P are arranged in a matrix form on the display unit D1, and a switching element for each pixel. T and the pixel electrode 17 connected thereto are formed.

In addition, a gate line 12 extending along one side of the pixel P and a data line 14 perpendicular to the gate line 12 are formed.

The non-display part D2 includes driving circuit parts 16 and 18, and the driving circuit parts 16 and 18 are located at one side of the substrate 10 to apply a signal to the gate wiring 12. And a data driving circuit portion 18 positioned on the other side of the substrate 10, which is not parallel thereto, to apply a signal to the data line 14.

The gate and data driving circuit units 16 and 18 are devices for supplying a display control signal and a data signal to the pixel unit P through the gate and data lines 12 and 14, respectively, by controlling signals input from the outside. .

Accordingly, the gate and data driver circuits 16 and 18 are generally composed of a thin film transistor having a complementary metal-oxide semiconductor (CMOS) structure which is an inverter to properly output an input signal.

The CMOS is a semiconductor technology used in a thin film transistor for driving circuits requiring high-speed signal processing. The CMOS uses extra electrons (n-type semiconductor) and negatively charged holes (p-type semiconductor) charged with negative electricity. It is used as a complementary method for forming a conductor and forming a current gate by effective electrical control of the two kinds of semiconductors.

As described above, the CMOS device constituting the driving circuit portion of the non-display portion is made of a combination of n-type and p-type polycrystalline thin film transistors, and the switching element of the display portion is made of an n-type or p-type polycrystalline thin film transistor.

Hereinafter, the cross-sectional structure of a conventional driving circuit-integrated liquid crystal display device will be described with reference to FIGS. 2A and 2B.

2A and 2B are cross-sectional views schematically showing a cross-sectional structure of a conventional liquid crystal display device with a drive circuit. FIG. 2A is a drive circuit portion and FIG. 2B is a display portion.

As shown in FIGS. 2A and 2B, the liquid crystal display LP having an integrated driving circuit is defined by a display unit D1 and a non-display unit D2 including a plurality of pixel regions P, and an array substrate AS. The color filter substrate CS is bonded to each other while being spaced apart from each other with the liquid crystal layer LC therebetween.

In the array substrate AS, a driving circuit DC is formed corresponding to the non-display unit D2, and the switching element T, the pixel electrode 78, and the storage are stored for each single pixel region P of the display unit D1. Capacitor Cst is configured.

Although not shown, a gate wiring (not shown) for inputting a scan signal to the switching element T and a data wiring (data not shown) for inputting a data signal to the switching element T are illustrated. ) Is configured.

In the above-described configuration, the driving circuit (DC) is generally made of a combination of CMOS consisting of n-type polycrystalline thin film transistor (T (n) and p-type polycrystalline thin film transistor (T (p)), the switching element is n-type or p-type polycrystalline thin film transistor.

The color filter substrate CS bonded to the array substrate AS configured as described above includes a black matrix 52 and a color filter 54 which are light blocking means, and the color filter 54 includes red, green, The blue color filters are sequentially arranged in the plurality of pixel areas P.

The common electrode 56 is formed on the entire surface of the substrate 30 including the black matrix 52 and the color filter 54.

The black matrix 52 is configured at the boundary of the pixel region 54 and at positions corresponding to the switching element T and the driving circuit DC.

In this case, since the black matrix 52 serves to block light leakage, an alignment error occurring when the array substrate AS and the color filter substrate CS are bonded should be considered.

If an alignment error occurs, despite the presence of the black matrix 52, light leakage may occur and display quality may be degraded.

Therefore, in the related art, when the black matrix 52 is designed, an alignment margin α of about 5 μm or more is always provided to prepare for an alignment error, thereby greatly encroaching on the opening area.

Hereinafter, a manufacturing process of an array substrate for a driving circuit-integrated liquid crystal display device according to the related art will be described with reference to the process drawings.

3A to 3I and FIGS. 4A to 4I are cross-sectional views illustrating a manufacturing process of a driving circuit-integrated thin film transistor array substrate according to a conventional process.

(FIGS. 3A to 3I are process sectional views showing the driving circuit, and FIGS. 4A to 4I are process sectional views showing a single pixel of the display area.)

3A and 4A are cross-sectional views illustrating a first mask process.

As illustrated, the substrate 30 is defined by the display unit D1 and the non-display unit D2, and the display unit D1 is defined as a plurality of pixel regions P again.

In this case, the P region A1 and the N region A2 are defined in the non-display portion D2 for convenience, and the switching region A3 and the storage region A4 are defined in the pixel region P. FIG.

As described above, the buffer layer 32 is formed by depositing an insulating material on one surface of the substrate 30 in which the plurality of regions A1, A2, A3, and A4 are defined, and amorphous silicon is formed on the buffer layer 32. After depositing (a-Si: H), a crystallization process is performed.

Various heat transfer means may be used for the crystallization, but generally, crystallization is performed by using a laser.

The first to third semiconductor layers 34, which function as an active layer in the P region A1, the N region A2, and the switching region A3 by patterning the crystallized layer by a crystallization process, 36 and 38, and a fourth semiconductor layer 40 serving as an electrode in the storage area A4 is formed.

3B and 4B illustrate a second mask process and are cross-sectional views illustrating a process of doping ions into the fourth semiconductor layer 40 of the storage area A4.

As shown in the drawing, a photoresist is applied to the entire surface of the substrate 30 on which the first to fourth semiconductor layers 34, 36, 38, and 40 are formed, and then patterned by a second mask process. The photosensitive pattern 42 which shields the P area | region A1, the N area | region A2, and the switching area | region A3 is formed.

Next, a process of doping ions onto the surface of the fourth semiconductor layer 40 of the storage area A4 that is not shielded by the photosensitive pattern 42 is performed.

Since the fourth semiconductor layer 40 must serve as an electrode, a process of doping ions (n or p-type ions) must be performed as described above in order to achieve conductivity.

As described above, when the process of doping ions into the fourth semiconductor layer 40 of the storage area A4 is completed, the process of removing the photosensitive pattern 42 is performed.

3C and 4C are cross-sectional views illustrating a third mask process.

As illustrated, after the process of doping ions into the fourth semiconductor layer 40 of the storage area A4 to form the storage first electrode, the first and fourth semiconductor layers 34 and 36 may be formed. A gate insulating layer 46 is formed on the entire surface of the substrate 30 on which the 38 and 40 are formed.

The gate insulating layer 46 may be formed by depositing at least one material selected from the group of inorganic insulating materials including silicon nitride (SiNx) and silicon oxide (SiO ₂ ).

Next, a conductive metal is deposited and patterned on the entire surface of the substrate 30 on which the gate insulating layer 46 is formed, thereby forming a first on the upper portion corresponding to the center of the first to third semiconductor layers 34, 36, and 38. To third gate electrodes 48, 50, and 52 are formed, and a storage second electrode 54 is formed on the fourth semiconductor layer 40 of the storage area A4.

In this case, a gate line (not shown) extending from the gate electrode 52 formed in the switching area A3 to one side of the pixel area P is formed in the display unit D1.

3D and 4D show a fourth mask process and are cross-sectional views for doping n + ions into the semiconductor layers of the N region A2 and the switching region A3.

As shown, a photo-resist is formed on the entire surface of the substrate 30 on which the first to third gate electrodes 48, 50, 52, the storage second electrode 54, and the gate electrode (not shown) are formed. ), And then patterned by a fourth mask process to form a photosensitive pattern 56 to block the P region (A1).

Next, a process of doping n + ions to the N region A2 and the switching region A3 exposed between the photosensitive patterns 56 is performed.

In this way, the second gate electrode 50 and the third gate electrode 52 of the second semiconductor layer 36 and the third semiconductor layer 38 in the N region A2 and the switching region A3 are formed. N + ions are doped on the surface of the exposed portion of the region, and the regions doped with ions have ohmic contact characteristics.

In this case, when n + ions are doped in the storage area A4, the photosensitive pattern may not be formed in the storage area A 4 in the step of doping the n + ions.

When the fourth mask process as described above is completed, the process of removing the photosensitive pattern 56 is performed.

3E and 4E show a fifth mask process and are cross-sectional views for doping p + ions into the semiconductor layer of the P region A1.

As shown in the drawing, a photoresist is applied to the entire surface of the substrate 30 on which the first to third gate electrodes 48, 50, and 52 and the storage second electrode 54 are formed, and then a fifth mask process is performed. By patterning, a photosensitive pattern 58 is formed to block the N area A2, the switching area A3, and the storage area A4.

Next, a process of doping p + ions to a surface exposed to the periphery of the gate electrode 48 of the exposed first semiconductor layer 34 in the P region A1 is performed.

In this case, the ion-doped region has an ohmic contact characteristic as mentioned above.

3F and 4F are cross-sectional views illustrating the sixth mask process.

As described above, an inorganic material including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 30 on which the ohmic region forming process is performed on the first to third semiconductor layers 34, 36, and 38. One selected from the group of insulating materials is deposited to form an interlayer insulating layer 60.

Next, the interlayer insulating film 60 and the lower gate insulating film 46 are patterned by a sixth mask process, so that ion doped regions (omic contact regions) of the first to third semiconductor layers 34, 36, and 38 are formed. Form a contact hole exposing the.

In detail, first contact holes 62a, 64a, and 66a exposing the semiconductor layers 34, 36, and 38, that is, ohmic regions, on both sides of the first, second, and third gate electrodes 48, 50, and 52, respectively. ) And second contact holes 62b, 64b, and 66b.

3G and 4G are cross-sectional views illustrating a seventh mask process.

Chromium (Cr), molybdenum (Mo), tungsten (W), copper (Cu) on the entire surface of the substrate 30 on which the interlayer insulating film 60 exposing the first to third semiconductor layers 34, 36, 38 are formed. ), And depositing and patterning one selected from a group of conductive metals including aluminum alloy (AlNd), and source electrode 68a, 70a, 72a and drain electrode 68b, 70b, 72b in contact with the exposed ohmic region. To form.

In this case, a data line (not shown) extending from the source electrode 72a formed in the switching area A3 and extending to one side of the pixel area P may be formed to cross the gate line (not shown).

Through the above-described first to seventh mask processes, a CMOS device, which is a combination of a p-type polycrystalline thin film transistor and an n-type polycrystalline thin film transistor, is formed in the non-display portion D2, and the switching region A3 of the display region D1. An n-type polycrystalline thin film transistor is formed in the storage region A4, and a storage capacitor Cst including the storage first electrode 40 and the storage second electrode 54 is formed.

3H and 4H are cross-sectional views illustrating the eighth mask process.

As shown, the above-described insulating material group on the entire surface of the substrate 30 in which the source electrodes 68a, 70a, 72a and the drain electrodes 68b, 70b, 72b are formed in each of the regions A1, A2, and A3. One or more selected materials are deposited to form the protective layer 74.

The protective layer 74 is patterned by an eighth mask process to form a drain contact hole 76 exposing the drain electrode 72b of the switching region A3.

3I and 4I are process sectional views showing the ninth mask process.

As shown, a selected one of a transparent conductive metal group including indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited on the entire surface of the substrate 30 on which the protective layer 74 is formed. 9, the pixel electrode 78 positioned in the pixel region P is formed while contacting the drain electrode 72b.

As described above, the thin film transistor array substrate of the liquid crystal panel integrated with the driving circuit according to the related art may be manufactured through the first to ninth mask processes as described above.

The color filter substrate bonded to the array substrate manufactured as described above is manufactured by the following process.

First mask process: formation of a black matrix as a light blocking means.

Second to fourth mask processes: forming red, green, and blue color filters for each pixel region.

Accordingly, as described above, the conventional liquid crystal display integrated with a driving circuit may be manufactured through a total of 13 mask processes in which manufacturing processes of a color filter substrate and an array substrate are combined.

However, as mentioned above, the conventional liquid crystal display device with integrated driving circuit has a problem in that the aperture ratio is lowered because the margin is considered when the black matrix is designed on the color filter substrate.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and a first object of the present invention is to propose a liquid crystal display device with an integrated driving circuit having an improved aperture ratio, and to prevent signal delay of the driving circuit. It is a third object to prevent a defect.

According to an exemplary embodiment of the present invention, there is provided a liquid crystal display integrated with a driving circuit, including: a display area including a switching area and a pixel area; Bonding means (seal patterns) positioned in the non-display area to bond the first substrate and the second substrate to each other; First light blocking means and a align key located in the non-display area; A driving circuit portion formed in the non-display area of the first substrate and composed of a combination of polycrystalline thin film transistors; A polycrystalline thin film transistor positioned in the switching region of the first substrate, a pixel electrode connected to the polycrystalline thin film transistor and configured in the pixel region; Second light blocking means formed in the non-display area of the second substrate and having an etching hole exposing the second substrate in a portion corresponding to the seal pattern; A color filter configured in the pixel region of the second substrate; It includes a common electrode configured on the front of the color filter.

The seal pattern may be configured to contact the second substrate exposed through the etching hole.

The driving circuit is a combination of a CMOS device consisting of an n-type polycrystalline thin film transistor and a p-type polycrystalline thin film transistor, wherein the polycrystalline thin film transistor of the switching region is n-type, the n-type polycrystalline thin film transistor is a polycrystalline active layer, A gate electrode and a source and a drain electrode on the active layer, wherein a surface of the active layer in contact with the source and drain electrodes is doped with n + ions and a region between the n + ion doped region and the gate electrode; The surface of the active layer is characterized in that it comprises a low concentration doped region doped with n-ion.

According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, comprising: preparing a first substrate and a second substrate; Defining a display area including a switching area and a pixel area on one surface of the first substrate and a non-display area; Forming a first light blocking means in a display area of the first substrate and an alignment key in the non-display area; Forming a driving circuit including a combination of polycrystalline thin film transistors in a non-display area of the first substrate; Forming a polycrystalline thin film transistor in the switching region of the first substrate; Forming a pixel electrode connected to the polycrystalline thin film transistor in the pixel region; Forming a light filter on the pixel region, the second light blocking means having an etch hole for exposing the second substrate corresponding to the non-display area of the second substrate; Forming a common electrode on the front surface of the color filter; Bonding the first substrate and the second substrate to each other through an adhesive means (sealant pattern), wherein the second substrate surface and the sealant pattern are in contact with the inside of the etching hole.

The first light blocking means and the alignment key are formed of a metal material having a low light reflectance such as chromium (Cr), and the second light blocking means stacks the red, green, and blue color resin layers forming the color filter. It characterized by forming.

The method may further include forming a storage capacitor in the display area of the first substrate.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device having a driving circuit, comprising: defining a display area including a switching area and a pixel area on a first substrate, and a non-display area including a driving circuit part; A first mask process step of forming light blocking means in the display area and an alignment key in a portion of the non-display area; Forming a first semiconductor layer and a second semiconductor layer in the driving circuit portion, and forming a third semiconductor layer in the switching region; A third mask process step of doping n + ions to a portion of the second semiconductor layer and the third semiconductor layer; Forming a gate insulating film on an entire surface of the first substrate on which the first to third semiconductor layers are formed; A fourth mask process step of forming a gate electrode on the gate insulating film corresponding to the center of the first to third semiconductor layers, respectively; A fifth mask process step of doping p + ions in a region of the first semiconductor layer not covered with the gate electrode; Doping n− ions in a region where n + ions are not doped in the second to third semiconductor layers; A sixth mask process step of forming an interlayer insulating film on the entire surface of the first substrate on which the gate electrode is formed and then patterning the layer to expose the p + doped region of the first semiconductor layer and the n + doped region of the second and third semiconductor layers; ; A seventh mask process step of forming source and drain electrodes in contact with each of the exposed first to third semiconductor layers; An eighth mask process step of forming a protective layer on an entire surface of the first substrate on which the source and drain electrodes are formed and exposing a drain electrode in contact with the third semiconductor layer; And a ninth mask process step of forming a pixel electrode in contact with the drain electrode.

The light blocking means has a lattice shape in the display area.

In the third mask process step, the first semiconductor layer is defined as a first active region and a second active region, and the second semiconductor layer and the third semiconductor layer are defined as a first active region, a second active region, and a third active region. Defining an active area; After the photosensitive layer was formed on the entire surface of the first substrate on which the first to third semiconductor layers were formed, the photosensitive layer was exposed and developed using a second mask to develop all of the first semiconductor layers and the second and third semiconductors. Forming a photosensitive pattern covering the first and third active regions of the layer; And forming an ohmic contact region by doping n + ions to the second active regions of the second and third semiconductor layers.

 The third active region may be a region doped with the n-ion.

The fifth mask process may include forming a photosensitive layer on the entire surface of the first substrate on which the gate electrode is formed, developing the photomask with a fifth mask, and then exposing the photomask to completely shield the second and third semiconductor layers. And forming an ohmic region by doping p + ions to a surface exposed to the outside of the gate electrode of the second semiconductor layer.

In the first to fifth mask processes, the first to fifth mask processes may be performed after aligning the mask on the first substrate using the alignment key at the correct position.

In the second mask process, forming a fourth semiconductor layer extending from the third semiconductor layer, doping n + ions to the surface of the fourth semiconductor layer in the third mask process, and in the fourth mask process The method may further include forming a storage capacitor by forming a metal electrode on the fourth semiconductor layer.

The method of manufacturing a drive circuit-integrated liquid crystal display device according to the present invention described above comprises the steps of: forming a drive circuit-integrated array substrate by the method of claim 9; Preparing a second substrate spaced apart from and bonded to the array substrate; Defining a display unit and a non-display unit including a plurality of pixel areas on the second substrate; Forming red, green, and blue color filters sequentially in the pixel region of the second substrate facing the array substrate, and stacking the red, green, and blue color filters on the non-display unit to form light blocking means; ; Forming an etching hole in the light blocking unit to expose the surface of the second substrate; Forming a common electrode on a front surface of the red, green, and blue color filters; The array substrate, the second substrate on which the red, green, and blue color filters and the light blocking means are formed are bonded to each other through an adhesive means, and the surface of the second substrate exposed into the etching hole and the second substrate are exposed. Contacting the adhesive means.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device with integrated driving circuit according to an embodiment of the present invention will be described.

Example

According to a first aspect of the present invention, a light blocking means corresponding to the non-display part is configured on the upper color filter substrate, and a light blocking means corresponding to the display part is configured on the lower array substrate. The second feature is that the substrate is attached directly to the sealant by removing a portion corresponding to the sealant.

FIG. 5 is a plan view schematically showing a liquid crystal display device integrated with a driving circuit according to the present invention in which only light blocking means is displayed.

As illustrated, the liquid crystal display device LP is configured by bonding an array substrate AS and a color filter substrate CS with a liquid crystal layer interposed therebetween, and the color filter substrate AS or array. A sealant pattern 300 is formed on the substrate AS and used as the bonding means.

The array substrate AS and the color filter substrate CS may be divided into a display unit D1 and a non-display unit D2, and black matrices 202 and 110 which are light blocking means corresponding to the display unit D1 and the non-display unit D2. ).

In this case, the first feature of the present invention is to configure the light blocking means 110 corresponding to the display unit D1 on the array substrate AS and the light blocking means 110 corresponding to the non-display unit D2. It is comprised in the board | substrate CS.

The light blocking means 202 of the array substrate is made of a metal material such as chromium (Cr) having a low reflectance, and the light blocking means 110 of the color filter substrate is formed by stacking red, green, and blue color resins. Form.

In this case, when the light blocking means 110 is configured in the non-display portion D2, the light blocking means 110 is directly attached to the substrate surface by removing a portion corresponding to the sealant pattern 300.

According to a second aspect of the present invention, in the process of forming the light blocking means 202 made of a metal material on the array substrate AS, an alignment key AK is arranged on the outer corners of the array substrate AS. To form.

In the structure according to the first aspect, when the light blocking means 202 corresponding to the non-display unit D2 is formed of a color resin on the color filter substrate CS, a driving circuit formed on the non-display unit D2 (not shown) ), There is an advantage that can prevent the signal delay (signal delay) that can occur in.

In detail, the light blocking means 202 formed on the array substrate AS is the first layer formed on the surface of the substrate and is a metal layer using a metal material. Therefore, the light blocking means of the metal material is not displayed (D2). ), Since the light blocking means and the upper metal wiring are positioned with the insulating film (buffer layer) interposed therebetween, the parasitic cap is present in the insulating film. Le causes a delay in the signal.

Therefore, the structure of forming the light blocking means corresponding to the non-display unit D2 (the driving circuit unit) on the color filter substrate with the color resin has an advantage in terms of signal flow.

In addition, due to the structure of removing the light blocking means 110 of the portion corresponding to the sealant pattern 300, it may occur due to poor adhesive properties between the sealant of the resin component and the light blocking means of the resin component. The liquid crystal (not shown) may be prevented from leaking to the outside due to the seal pattern bursting defect.

In the structure of the second aspect, the structure in which the light blocking means 202 is formed on the array substrate in correspondence with the display portion D1 is designed to omit the bonding margin when the light blocking means is formed, so that the structure is bonded. There is an advantage that can further secure the opening area as much as the margin.

In addition, the structure in which the light blocking means 202 is formed on the display unit D1 and at the same time the alignment key AK is formed on the outer portion of the display unit D1 is self-aligned in subsequent processes through the alignment key AK. This makes it possible to omit some mask processes compared to the prior art.

6A and 6B are cross-sectional views schematically illustrating a configuration of a driving circuit-integrated liquid crystal display device according to the present invention.

(Fig. 6A is a cross sectional view showing a CMOS of the driving circuit section, and Fig. 6B is a cross sectional view showing a single pixel of the display section.)

As illustrated, the liquid crystal display LP having an integrated driving circuit according to the present invention includes a sealant 300 having an upper color filter substrate CS and a lower array substrate AS interposed therebetween with a liquid crystal layer (not shown). Combining through the configuration.

In this case, the color filter substrate CS and the array substrate AS may be divided into a display unit D1 and a non-display unit D2, and the color filter substrate CS may include a plurality of pixel regions defined in the display unit D1. Red, green, and blue color filters 102a, 104a (not shown) corresponding to each P), and red, green, and blue color filters 102a, 104a (not shown) corresponding to the non-display unit D2; The light blocking means 110 is formed by stacking the green and blue color resins 201b, 104b and 106b. In addition, the transparent common electrode 114 is formed on the front surface of the substrate on which the color filters 102a and 104a (not shown) and the light blocking means 110 are formed.

In this case, the first feature is to remove the light blocking means 110 of the portion where the seal pattern 300 is located.

The driving circuit-integrated array substrate AS forms a driving circuit DC in the non-display portion D2 and corresponds to the pixel region P of the display portion D1 and includes a switching element (polycrystalline thin film transistor, T) and a storage capacitor. Cst and the pixel electrode 248 are formed.

In this case, the driving circuit DC is generally formed of a CMOS combination consisting of an n-type polycrystalline thin film transistor T (n) and a p-type polycrystalline thin film transistor T (p), and the switching element T is n-type polycrystalline thin film transistor.

Meanwhile, the light blocking means 202 is formed to correspond to the display unit D1. The light blocking unit 202 is formed below the boundary corresponding to the boundary between the switching element, the storage capacitor, and the pixel areas T, Cst, and P.

At this time, the light blocking means (black matrix, 202) is formed corresponding to the display unit D1, and an alignment key (AK in FIG. 5) is formed on the periphery of the substrate 200 corresponding to the non-display unit D2. do.

Due to the existence of the alignment key, self-alignment is possible in the mask process, thereby simplifying the process.

As described above, when the light blocking means of the color filter substrate CS is formed in the thin film transistor array substrate AS in response to the display unit, it is possible to secure the opening area as much as the bonding margin because no bonding margin is required. .

In addition, since self alignment is possible using the alignment key, the doping process of different regions may be performed in the same process, thereby reducing the mask process. (Storage region and n region) N + doping process is performed on the semiconductor layer at the same time.)

Hereinafter, a manufacturing process of a color filter substrate for a driving circuit-integrated liquid crystal display device according to the present invention will be described with reference to the drawings.

7A to 7C are cross-sectional views illustrating a method of manufacturing a color filter substrate for a liquid crystal display device with an integrated driving circuit according to the present invention, in order of process.

As shown in FIG. 7A, the substrate 100 includes a non-display portion D2 including a driving circuit portion (not shown), and a plurality of pixel regions P (R), P (G), and P (B). It is defined by the display unit D1.

Next, a photosensitive red color resin (optional) is first laminated among red, green, and blue color resins on one surface of the substrate 100 and patterned using a first mask process to form the plurality of pixel regions (P (R). ), P (G), P (B)) selectively form a red color filter 102a, and simultaneously form a red color resin layer 102b in the non-display area D2.

As shown in FIG. 7B, the photosensitive green color resin is coated on the entire surface of the substrate 100 on which the red color filter and the red color resin layers 102a and 102b are formed, and then patterned by a second mask process. The green color filter 104a is formed by selecting one of the areas where the red color filter 102a is not formed corresponding to the pixel areas P (R), P (G), and P (B), and forms the non-display area ( In response to D2), the green color resin layer 104b is formed on the red color resin layer 102b by laminating it.

As shown in FIG. 7C, the photosensitive blue color resin is coated on the entire surface of the substrate 100 on which the red color filter 102a and the green color filter 104a are formed, and then patterned. A blue color filter 106a is formed on a portion that is not formed, and at the same time, a blue color resin layer 106b is formed on the green color resin layer 104b to correspond to the non-display portion D2.

7A to 7C, the red, green, and blue color filters 102a, 104a, and 106a may be formed in correspondence with the display area D1, and correspond to the non-display area D2. The light blocking means 110, which is a black resin layer formed by stacking the red, green, and blue color resin layers 102b, 104b, and 106b, may be formed.

Next, the process of forming the etching hole 112 exposing the substrate 100 is performed by removing the portion in which the seal pattern 300, which is the bonding means, is formed to correspond to the light blocking means 110 through the fourth mask process. do.

As shown in FIG. 7D, indium-tin-oxide (ITO) and indium- are formed on the entire surface of the substrate 100 on which the black resin layer 110 and the red, green, and blue color filters 102a, 104a, and 106a are formed. A transparent conductive metal including zinc oxide (IZO) is deposited to form a common electrode 114.

In the above-described process, since the seal pattern 300 may contact the exposed substrate 100 by being located inside the etching hole 112, the contact characteristics of the seal pattern 300 may be improved.

If the seal pattern 300 is in direct contact with the light blocking means (black resin layer 110), the seal due to the degradation of the contact characteristics of the seal pattern 300 and the light blocking means 110 formed of the resin A failure of the pattern 300 to pop may occur. Therefore, the above-described structure has an advantage of preventing such a problem in advance.

The manufacturing process of the array substrate bonded to the color filter substrate fabricated as described above will be described below with reference to the process drawings.

8A to 8J and FIGS. 9A to 9J are views illustrating a manufacturing process of a thin film transistor array substrate for a liquid crystal display device with integrated driving circuit according to the present invention.

8A to 8J and 9A to 9J are cross-sectional views illustrating a manufacturing process of a driving circuit-integrated thin film transistor array substrate according to a process sequence.

(FIGS. 8A to 8J are process sectional views showing a driving circuit, and FIGS. 9A to 9J are process sectional views showing a single pixel of a display area.)

8A and 9A are cross-sectional views illustrating a first mask process.

As illustrated, the substrate 200 is defined as the display unit D1 and the non-display unit D2, and the display unit D1 is defined as a plurality of pixel areas P again.

In this case, the P area A1 and the N area A2 are defined in a part of the non-display part D2, and the switching area A3 and the storage area A4 are defined in the pixel area P.

As described above, a metal having a low reflectance such as chromium (Cr) is deposited and patterned on one surface of the substrate 200 in which the plurality of regions A1, A2, A3, and A4 are defined, so that the pixel region P The black matrix 202 which is a light blocking means is formed corresponding to the boundary and the switching area and the storage area A3 and A4.

The light blocking means 202 is formed, and an alignment key (AK in FIG. 5) is formed on the outer side of the substrate 200.

In this case, the black matrix is not formed in a portion corresponding to the non-display portion D2.

8B and 9B illustrate a second mask process.

As illustrated, an insulating material is deposited on the entire surface of the substrate 200 on which the black matrix 202 is formed to form a buffer layer 204, and amorphous silicon (a-Si: H) is formed on the buffer layer 204. After depositing the crystallization process is performed.

Various heat transfer means may be used for the crystallization, but generally, crystallization is performed by using a laser.

First to third patterns of the silicon layer crystallized in a crystallization process by a second mask process to function as an active layer in the P region A1, the N region A2, and the switching region A3. The semiconductor layers 206, 208, and 210 are formed, and a fourth semiconductor layer 212 serving as an electrode is formed in the storage area A4.

8C and 9C illustrate a third mask process, in which a semiconductor layer is doped with n + ions.

As shown, a photoresist is applied to the entire surface of the substrate 200 on which the first to fourth semiconductor layers 206, 208, 210 and 212 are formed, and then patterned by a second mask process to form the N region A2 and A photosensitive pattern 214 is formed to shield part of the switching area A3 and the P area A1.

In this case, a first active region B1 and a second active region B2 are defined in the N region A2 and the switching region A3, and a first portion is formed between the first and second active regions B1 and B2. 3 Define the active area B3.

In particular, the photosensitive pattern 214 may include, for example, first and third active regions B1 and B3 of the second semiconductor layer 208 and the third semiconductor layer 210 formed in the N region A2 and the switching region A3. ) To shield.

Next, a process of doping n + ions on the entire surface of the substrate 200 on which the photosensitive pattern 214 is formed is performed.

In this way, the second active region B2 of the N region A2 and the switching region A3 is doped with n + ions to become an ohmic region (an region having ohmic contact characteristics). The fourth semiconductor layer 212 functions as a storage first electrode.

As described above, a process of doping ions into the second and third semiconductor layers 208 and 210 of the N region A2 and the switching region A3 and the fourth semiconductor layer 212 of the storage region A4 is performed. Upon completion, the process of removing the photosensitive pattern 214 is performed.

8D and 9D are cross-sectional views illustrating a fourth mask process.

As shown, after the n + ion doping process is performed through the third mask process, a gate insulating film 216 is formed on the entire surface of the substrate.

The gate insulating layer 216 may be formed by depositing at least one material selected from the group of inorganic insulating materials including silicon nitride (SiNx) and silicon oxide (SiO ₂ ).

Next, a conductive metal is deposited and patterned on the entire surface of the substrate 200 on which the gate insulating layer 216 is formed, and formed on the upper portion corresponding to the center (first active region) of the first to third semiconductor layers 206, 208, and 210. First to third gate electrodes 218, 220, and 222 are formed, and a storage second electrode 224 is formed on an upper portion corresponding to the fourth semiconductor layer 212 of the storage area A4.

8E and 9E illustrate a fifth mask process and are cross-sectional views for doping p + ions into a semiconductor layer of a P region.

As shown, after the photo-resist is applied to the entire surface of the substrate 200 on which the first to third gate electrodes 218, 220, and 222 and the storage second electrode 224 are formed, a pattern is performed by a fourth mask process. As a result, a photosensitive pattern 226 is formed to block the N region A2, the switching region A3, and the storage region A4.

Next, a process of doping p + ions to the P region A1 exposed between the photosensitive patterns 226 is performed.

In this way, the second active region B2 of the P region A1 is doped with p + ions and has ohmic contact characteristics.

When the fifth mask process as described above is completed, the process of removing the photosensitive pattern 226 is performed.

8F and 9F illustrate a process of forming the lightly doped region LDD in the semiconductor layers 208 and 210 of the N region A2 and the switching region A3.

As described above, after the photosensitive pattern 226 is removed, a process of doping n-ion on the entire surface of the substrate 200 is performed.

In this manner, the lightly doped region LDD may be formed in the third active region B3 of the second and third semiconductor layers 208 and 210 positioned in the N region A2 and the switching region A3.

At this time, since the amount of n− ions is extremely small, even if p + ions are doped on the surface of the doped first semiconductor layer 206, the characteristics of the first semiconductor layer are not affected.

8G and 9G show a sixth mask process.

As illustrated, nitride is formed on the entire surface of the substrate 200 on which the first to third semiconductor layers 206, 208, and 210 and the storage first electrode 222 are formed, respectively, in the same process as described above. One selected from the group of inorganic insulating materials including silicon (SiN _X ) and silicon oxide (SiO ₂ ) is deposited to form an interlayer insulating layer (interlayer) 228.

Next, the interlayer insulating layer 228 and the lower gate insulating layer 216 are patterned using a seventh mask process to expose the ion doped regions (omic contact regions) of the first to third semiconductor layers 206, 208, and 210. Form a hole.

In detail, the first contact holes 230a, 232a, and 234a and the second contact holes exposing the semiconductor layers 206, 208, and 210, that is, the ohmic regions, on both sides of the first to third gate electrodes 218, 220, and 222, respectively. (230b, 232b, 234b) are formed.

8H and 9H are cross-sectional views illustrating the seventh mask process.

Chromium (Cr), molybdenum (Mo), tungsten (W), copper (Cu), and aluminum alloy on the entire surface of the substrate 200 on which the interlayer insulating film 228 exposing the first to third semiconductor layers 206, 208, and 210 are formed. Depositing and patterning a selected one of the conductive metal groups including (AlNd) and the like, and disposing the source electrodes 236a, 238a, 240a and the drain electrodes 236b, 238b, 240b in contact with the exposed ohmic contact regions. Form.

Through the above-described first through sixth mask processes, a CMOS device, which is a combination of a p-type polycrystalline thin film transistor and an n-type polycrystalline thin film transistor, is formed in the non-display portion D2, and the switching region A3 of the display region D1. An n-type polycrystalline thin film transistor is formed in the storage region A4, and a storage capacitor Cst including the storage first electrode 212 and the storage second electrode 224 is formed.

8I and 9I are process cross-sectional views illustrating an eighth mask process.

As shown in the drawing, among the aforementioned insulating material groups in front of the substrate 200 in which the source electrodes 236a, 238a and 240a and the drain electrodes 236b, 238 and 240b are formed in each of the regions A1, A2 and A3. The protective layer 242 is formed by depositing one or more selected materials.

Next, the protective layer 242 is patterned by an eighth mask process to form a drain contact hole 246 exposing the drain electrode 240b of the switching region.

8J and 9J are process sectional views showing the ninth mask process.

As shown, a selected one of a transparent conductive metal group including indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited on the entire surface of the substrate 200 on which the protective layer 242 is formed. The pixel electrode 248 positioned in the pixel region P is formed by contacting the drain electrode 240b by patterning using a ninth mask process.

Through the above-described process it is possible to manufacture an array substrate according to an embodiment of the present invention.

As described above, the array substrate having the light blocking means formed on the display portion and the color filter substrate having the light blocking means formed on the non-display portion may be bonded to each other to manufacture the driving circuit-integrated liquid crystal display device according to the present invention.

The driving circuit-integrated liquid crystal display device according to the present invention was able to fabricate the array substrate by the 9 mask process, even though the array substrate further includes a black matrix.

Therefore, the fabrication of the array substrate can be simplified compared to the conventional process. For this reason, since the alignment of the mask and the substrate can be precisely performed in the subsequent mask process through the alignment key, the doping process of the two regions is performed. This is because it is possible to proceed in one process.

In addition, when the light blocking means is formed on the color filter substrate, the structure that removes the area where the seal pattern touches may cause the seal pattern to directly contact the substrate, resulting in improved adhesion characteristics of the seal pattern. The occurrence of pattern burst failure can be prevented in advance.

Therefore, the manufacturing method of the array substrate for the driving circuit-integrated liquid crystal display device according to the present invention has the following effects.

First, by configuring the light blocking means used in the color filter substrate in the array substrate, it is possible to secure the opening area as much as the bonding margin by ensuring no bonding margin, which is necessarily considered when designing the light blocking means. It can be effective.

Second, in the process of constructing the light blocking means on the array substrate, an alignment key can be formed on the outside of the substrate, so that accurate alignment is possible in the mask process, and thus in the ion doping process or the electrode formation process. Since no error occurs, there is an effect that can improve the process yield.

Third, when configuring the n-type thin film transistor, there is an effect that can improve the off characteristics of the switching element by forming the LDD region.

Fourth, by configuring the light blocking means on the upper color filter substrate corresponding to the driving circuit unit, there is an effect that can prevent the signal delay that may occur in the driving circuit unit in advance.

Fifth, when the light blocking means is formed in the driving circuit part, by removing the area where the seal pattern touches, the seal pattern is directly in contact with the substrate to improve the contact characteristics of the seal pattern in advance that the seal burst failure occurs in advance It is effective to prevent.

Claims (17)

A display area including a switching area and a pixel area, a first substrate and a second substrate on which a non-display area is defined; Bonding means (seal patterns) positioned in the non-display area to bond the first substrate and the second substrate to each other; First light blocking means and a align key located in the non-display area; A driving circuit portion formed in the non-display area of the first substrate and composed of a combination of polycrystalline thin film transistors; A polycrystalline thin film transistor positioned in the switching region of the first substrate, a pixel electrode connected to the polycrystalline thin film transistor and configured in the pixel region; Second light blocking means formed in the non-display area of the second substrate and having an etching hole exposing the second substrate in a portion corresponding to the seal pattern; A color filter configured in the pixel region of the second substrate; Common electrode formed on the front of the color filter Driving circuit-integrated liquid crystal display device comprising a. The method of claim 1, And the seal pattern is in contact with the second substrate exposed through the etching hole. The method of claim 1, And the driving circuit is a combination of a CMOS element composed of an n-type polycrystalline thin film transistor and a p-type polycrystalline thin film transistor, and the polycrystalline thin film transistor of the switching region is n-type. The method of claim 3, wherein The n-type polycrystalline thin film transistor includes a polycrystalline active layer, a gate electrode, a source and a drain electrode on the active layer, and an n + ion-doped region on a surface of the active layer in contact with the source and drain electrodes, and a lightly doped region doped with n-ion on the surface of the active layer corresponding to the region between the n + ion doped region and the gate electrode. Preparing a first substrate and a second substrate; Defining a display area including a switching area and a pixel area on one surface of the first substrate and a non-display area; Forming a first light blocking means in a display area of the first substrate and an alignment key in the non-display area; Forming a driving circuit including a combination of polycrystalline thin film transistors in a non-display area of the first substrate; Forming a polycrystalline thin film transistor in the switching region of the first substrate; Forming a pixel electrode connected to the polycrystalline thin film transistor in the pixel region; Forming a light filter on the pixel region, the second light blocking means having an etch hole for exposing the second substrate corresponding to the non-display area of the second substrate; Forming a common electrode on the front surface of the color filter; Bonding the first substrate and the second substrate to each other through an adhesive means (sealant pattern), wherein the second substrate surface in the etch hole contacts the sealant pattern; A driving circuit-integrated liquid crystal display device manufacturing method comprising a. 6. The method of claim 5, And the first light blocking means and the alignment key are made of a metal material having low light reflectance such as chromium (Cr). 6. The method of claim 5, And the second light blocking means is formed by stacking red, green, and blue color resin layers forming the color filter. 6. The method of claim 5, And forming a storage capacitor in the display area of the first substrate. Defining a display area including a switching area and a pixel area on the first substrate and a non-display area including a driving circuit unit; A first mask process step of forming light blocking means in the display area and an alignment key in a portion of the non-display area; Forming a first semiconductor layer and a second semiconductor layer in the driving circuit portion, and forming a third semiconductor layer in the switching region; A third mask process step of doping n + ions to a portion of the second semiconductor layer and the third semiconductor layer; Forming a gate insulating film on an entire surface of the first substrate on which the first to third semiconductor layers are formed; A fourth mask process step of forming a gate electrode on the gate insulating film corresponding to the center of the first to third semiconductor layers, respectively; A fifth mask process step of doping p + ions in a region of the first semiconductor layer not covered with the gate electrode; Doping n− ions in a region where n + ions are not doped in the second to third semiconductor layers; A sixth mask process step of forming an interlayer insulating film on the entire surface of the first substrate on which the gate electrode is formed and then patterning the layer to expose the p + doped region of the first semiconductor layer and the n + doped region of the second and third semiconductor layers; ; A seventh mask process step of forming source and drain electrodes in contact with each of the exposed first to third semiconductor layers; An eighth mask process step of forming a protective layer on an entire surface of the first substrate on which the source and drain electrodes are formed and exposing a drain electrode in contact with the third semiconductor layer; A ninth mask process step of forming a pixel electrode in contact with the drain electrode Array circuit manufacturing method for a drive circuit-integrated liquid crystal display device comprising a. The method of claim 9, And the light blocking means is a lattice shape in a display area. 11. The method of claim 10, And the light blocking means and the alignment key are made of a metal material having low light reflectance such as chromium (Cr). The method of claim 9, The third mask process step, Defining the first semiconductor layer as a first active region and a second active region, and defining the second semiconductor layer and the third semiconductor layer as a first active region, a second active region, and a third active region; After the photosensitive layer was formed on the entire surface of the first substrate on which the first to third semiconductor layers were formed, the photosensitive layer was exposed and developed using a second mask to develop all of the first semiconductor layers and the second and third semiconductors. Forming a photosensitive pattern covering the first and third active regions of the layer; Forming an ohmic contact region by doping n + ions to the second active region of the second and third semiconductor layers Array circuit manufacturing method for a drive circuit-integrated liquid crystal display device comprising a. 13. The method of claim 12, And said third active region is a region to which the n-ion is doped. The method of claim 9, The fifth mask process step, After forming a photosensitive layer on the entire surface of the first substrate on which the gate electrode is formed, developing it with a fifth mask and exposing it to completely shield the second and third semiconductor layers, Doping p + ions to the externally exposed surface to form an ohmic region Array circuit manufacturing method for a drive circuit-integrated liquid crystal display device comprising a. The method according to any one of claims 9 to 14, In the first to fifth mask process, the alignment circuit is aligned on the first substrate using the alignment key and then the first to fifth mask process is performed. Method of manufacturing array substrate for display device. The method of claim 9, In the second mask process, forming a fourth semiconductor layer extending from the third semiconductor layer, doping n + ions to the surface of the fourth semiconductor layer in the third mask process, and in the fourth mask process And forming a storage capacitor by forming metal electrodes on the fourth semiconductor layer. Forming a drive circuit-integrated array substrate by the method of claim 9; Preparing a second substrate spaced apart from and bonded to the array substrate; Defining a display unit and a non-display unit including a plurality of pixel areas on the second substrate; Forming red, green, and blue color filters sequentially in the pixel region of the second substrate facing the array substrate, and stacking the red, green, and blue color filters on the non-display unit to form light blocking means; ; Forming an etching hole in the light blocking unit to expose the surface of the second substrate; Forming a common electrode on a front surface of the red, green, and blue color filters; The array substrate, the second substrate on which the red, green, and blue color filters and the light blocking means are formed are bonded to each other through an adhesive means, and the surface of the second substrate exposed into the etching hole and the second substrate are exposed. Contacting the adhesive means A driving circuit-integrated liquid crystal display device manufacturing method comprising a.

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