KR101648222B1 - Package structure and method for manufacturing the same - Google Patents

Package structure and method for manufacturing the same Download PDF

Info

Publication number
KR101648222B1
KR101648222B1 KR1020100030468A KR20100030468A KR101648222B1 KR 101648222 B1 KR101648222 B1 KR 101648222B1 KR 1020100030468 A KR1020100030468 A KR 1020100030468A KR 20100030468 A KR20100030468 A KR 20100030468A KR 101648222 B1 KR101648222 B1 KR 101648222B1
Authority
KR
South Korea
Prior art keywords
epoxy
substrate
guide
package structure
chips
Prior art date
Application number
KR1020100030468A
Other languages
Korean (ko)
Other versions
KR20110111075A (en
Inventor
이기민
Original Assignee
엘지이노텍 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지이노텍 주식회사 filed Critical 엘지이노텍 주식회사
Priority to KR1020100030468A priority Critical patent/KR101648222B1/en
Publication of KR20110111075A publication Critical patent/KR20110111075A/en
Application granted granted Critical
Publication of KR101648222B1 publication Critical patent/KR101648222B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The present invention relates to a package structure and a manufacturing method thereof.
That is, the package structure of the present invention includes a substrate on which electrode lines are formed; A chip mounted on the substrate and electrically connected to the electrode lines; And a molding unit covering the chip and printed on the substrate.

Description

[0001] Package structure and method for manufacturing same [0002]

The present invention relates to a package structure capable of solving the problem that an epoxy flows and contaminates a substrate or causes a defective shape of a molding part, and a manufacturing method thereof.

2. Description of the Related Art [0002] In recent years, the size of individual components mounted in a mobile terminal has become smaller due to the trend toward smaller and slimmer wireless communication terminals.

In this trend, parts packaged in a conventional metal can structure are subjected to a transfer mold process or a print mold process, so that they are packaged for miniaturization and slimming down.

Although the above-mentioned print mold process has recently been emphasized because it does not apply high temperature and high pressure to parts and substrates, when the print area of the epoxy is wide, there is a disadvantage that the epoxy flows before curing and is contaminated.

An object of the present invention is to solve the problem of causing the epoxy to flow to contaminate the substrate or to cause defects in the shape of the molding part.

According to the present invention,

A substrate on which electrode lines are formed;

A chip mounted on the substrate and electrically connected to the electrode lines;

There is provided a package structure including a molding part covered with the chip and printed on the substrate.

According to the present invention,

A substrate on which electrode lines are formed;

A plurality of chips mounted on the substrate and electrically connected to the electrode lines;

There is provided a package structure including a first hardened region printed on the substrate and covering the plurality of chips and a second hardened region located outside the first hardened region.

According to the present invention,

Mounting a chip on a substrate on which electrode lines are formed, and electrically connecting the electrode lines to the chip;

Placing a guide capable of heating on the substrate, filling the inside of the guide and printing the chip with epoxy;

Curing a portion of the printed molded epoxy with the heatable guide;

Releasing the guide from the substrate and the epoxy, and curing the remaining area of the print-molded epoxy.

The package structure of the present invention can provide a uniform shape on the external side of the package, and is effective for packaging a good product.

Further, the method of manufacturing the package structure of the embodiment of the present invention has an effect that the lapping step is unnecessary.

In addition, in the method of manufacturing the package structure of the embodiment of the present invention, since the edge of the epoxy is hardened by the heatable guide, the molding part can have a predetermined angle, thereby satisfying the uniformity of the package structure, .

The package structure of the present invention is a package structure in which a plurality of chips are mounted on a substrate and a molding process including a first curing area and a second curing area is performed on each of some or some of the plurality of chips, It is possible to solve the problem that the epoxy flows in the molding process to contaminate the substrate or to cause defects in the shape of the molding part.

1 is a schematic cross-sectional view of a package structure according to a first embodiment of the present invention
2 is a schematic perspective view of a package structure according to a first embodiment of the present invention;
Fig. 3 is an enlarged view of Fig. 1
4A to 4F are schematic cross-sectional views for explaining a method of manufacturing the package structure according to the first embodiment of the present invention
5A to 5F are schematic cross-sectional views for explaining a method of manufacturing a package structure according to a comparative example of the present invention
Fig. 6 is an enlarged view of B in Fig.
7 is a schematic cross-sectional view for explaining a method of manufacturing the package structure according to the second embodiment of the present invention

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic cross-sectional view of a package structure according to a first embodiment of the present invention.

The package structure according to the first embodiment of the present invention includes a substrate 100 on which electrode lines are formed; A chip 200 mounted on the substrate 100 and electrically connected to the electrode lines; And a molding unit 250 covering the chip 200 and printed on the substrate 100.

The passive elements 220 may be mounted on the substrate 100, and the passive elements 220 may be covered with the molding part 250.

The chip 200 is preferably a chip for driving a wireless communication terminal.

A printed circuit board may be used as the substrate 100, and the printed circuit board may be a multilayer printed circuit board.

After the molding part 250 is printed on the substrate 100, the part is cured by a guide described later, and then the entire part is cured to prevent the epoxy from spreading to the side, so that the top surface is structurally flat .

As shown in FIG. 3, the edge of the molding part 250 has a predetermined angle?.

That is, the upper surface of the molding part 250 is flattened and the side surface is substantially vertical by the cutting process described later, so that the upper surface and the side surface of the molding part 250 meet at a predetermined angle.

In other words, the corner of the molding part 250 of the package structure of the present invention is not a curved state in which there is no angle at all, but is the same as the corner of a square pillar as shown in FIG. 2 where an angle exists.

Therefore, the package structure of the present invention can provide a uniform shape on the external side of the package, which is advantageous in that a good-quality package can be realized.

4A to 4F are schematic cross-sectional views for explaining a method of manufacturing the package structure according to the first embodiment of the present invention.

First, a chip 200 is mounted on a substrate 100 on which electrode lines are formed, and the electrode lines are electrically connected to the chip 200 (FIG. 4A)

Electrical connection between the chip 200 and the electrode lines may be performed by wire bonding as shown in FIG. 4A.

A guide 300 capable of heating is placed on the substrate 100 and the chip 200 is filled with the guide 300 so that the chip 200 is printed with the epoxy 500 (FIG. 4B)

After the epoxy 500 is positioned in the guide 300, the epoxy 500 is uniformly filled in the guide 300 while pushing the epoxy 500 with a squeeze 550 as shown in FIG. 4B At the same time, the upper surface of the epoxy 500 to be printed-molded is planarized as shown in FIG. 4C.

In addition, the guide 300, which can be heated, includes means for heating the guide body.

For example, when heating is incorporated in the guide body and power is applied to the hot wire in curing, the epoxy 500 can be heated.

In addition, the heating-capable guide 300 may be realized by forming a resistance coil pattern that generates heat when an electric current is passed through an upper surface or a lower surface.

An electrical contact terminal can be formed at both ends of the resistance coil pattern. When the heating-capable guide 300 is positioned on the substrate 100, the electrical contact terminal is electrically connected to the power supply terminal So that power can be supplied to the guide 300 capable of heating.

At this time, the power supply terminal may be implemented as a terminal installed in the equipment for packaging the package structure of the present invention.

In addition, epoxy 300 filled in the guide 300 in the shape of a ring remains in the guide 300 and does not leak to the outside of the guide 300.

Thereafter, a part of the epoxy 500 is cured by the heatable guide 300 (FIG. 4D)

Here, the epoxy 510 adjacent to the guide 300 is cured, and the epoxy 520 remote from the guide 300 is not cured.

The hardening of a part of the epoxy 500 may be performed by rapidly curing the epoxy 500 at about 200 ° C to 300 ° C to prevent the epoxy from flowing even when the guide 300 is released.

Subsequently, the guide 300 is removed from the substrate 100 and the epoxy 500, and the remaining area of the print-molded epoxy 500 is cured (FIG. 4E)

The temperature at which the remaining area of the epoxy resin 500 is cured is preferably about 120 ° C to 160 ° C for about 30 minutes.

Subsequently, the cured printed molding epoxy 500 and the substrate 100 are cut to separate into a single package structure with the chip 200 embedded therein (Figure 4f)

When cutting the cured printed molded epoxy 500, some cured epoxy areas by the guide 300 may be removed as shown in FIG. 4d.

On the other hand, in the above-described manufacturing method, the package structure including a plurality of chips may be implemented without performing the process of Fig. 4F.

Such a package structure can be achieved by a structure in which a module performing a specific function is sealed with one molding portion, and some hardened epoxy regions can not be removed and remain in the package structure.

That is, the package structure includes a substrate on which electrode lines are formed; A plurality of chips mounted on the substrate and electrically connected to the electrode lines; And a molding unit printed on the substrate, the molding unit including a first hardened region covering the plurality of chips and a second hardened region located outside the first hardened region.

Here, the first cured region exists inside the molding unit and is formed by curing in the curing process of FIG. 4E. The second cured region is formed by curing by a guide 300 capable of heating, (The edge of the molding part) of the one hardening area.

Further, all of the plurality of chips are covered with the molding part.

5A to 5F are schematic cross-sectional views for explaining a method of manufacturing a package structure according to a comparative example of the present invention.

A method of manufacturing a package structure according to a comparative example of the present invention includes mounting a chip 710 on a substrate 700 on which electrode lines are formed and electrically connecting the electrode lines and the chip 710 (FIG. 5A) , The guide 720 is placed on the substrate 700 and the chip 710 is printed with the epoxy 730 by filling the inside of the guide 720 (Figures 5B and 5C)

Subsequently, the guide 720 is released from the substrate 700 and the epoxy 730, and the whole of the print-molded epoxy 730 is cured (FIG. 5D)

At this time, if the guide 720 is released, the epoxy 730 may flow to the side and contaminate the substrate.

The upper surface of the cured epoxy 730 is planarized by lapping the cured epoxy 730 (FIG. 5E)

Thereafter, the epoxy 730 and the substrate 700 are cut and separated into a single package structure in which the chip 710 is embedded (FIG. 5F).

In the method of manufacturing the package structure of this comparative example, there is a disadvantage in that the process is complicated by carrying out a process of planarizing the cured epoxy upper surface by performing the lapping process. However, in the method of manufacturing the package structure of the embodiment of the present invention, There is no advantage.

Also, in the method of manufacturing the package structure of the comparative example, there is a possibility that a short occurs due to the problem that the epoxy flows down when the guide is detached, and the edge of the hardened epoxy has a curved surface as shown in Fig. 6 However, in the method of manufacturing the package structure of the embodiment of the present invention, the edge of the epoxy is hardened by the heatable guide, so that the molding part can have a predetermined angle, And the yield of good products can be increased.

7 is a schematic cross-sectional view for explaining a method of manufacturing a package structure according to a second embodiment of the present invention.

A substrate 900 on which a plurality of chips 910 and 920 are mounted and on which electrode lines are formed is prepared and a guide 930 capable of heating the substrate 900 is placed outside a part of the plurality of chips 910 and 920, The inside of the guide 930 is filled and some chips or some chips of the plurality of chips 910 and 920 are printed with the epoxy 940 and then a part of the epoxy 940 is cured with the guide 930, After the guide 930 is removed, the remaining area of the epoxy 940 is cured to manufacture the package structure according to the second embodiment.

At this time, when the epoxy 940 is partially cured by the guide 930, the cured epoxy 940 is partially cured at about 150 ° C to 200 ° C for about 10 seconds to increase the viscosity of the cured epoxy 940, The epoxy 940 may be prevented from flowing.

Thereafter, in the process of curing the remaining area of the epoxy 940, a partial area of the epoxy 940 is completely cured.

In the second package structure thus manufactured, only a part of the chips of the substrate are encapsulated with epoxy, and the substrate has the electrode lines formed thereon. A plurality of chips mounted on the substrate and electrically connected to the electrode lines; And a molding part printed on the substrate and including a first curing area covering each of the chips or a part of the plurality of chips and a second curing area existing outside the first curing area.

The package structure according to the second embodiment of the present invention is a package structure in which a plurality of chips are mounted on a substrate and a molding part composed of a first hardened area and a second hardened area is mounted on each of some chips or some chips of the plurality of chips, And the epoxy resin flows through the molding process to contaminate the substrate or to cause defects in the shape of the molding part.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

delete delete delete delete delete Mounting a chip on a substrate on which electrode lines are formed, and electrically connecting the electrode lines to the chip;
Placing a guide capable of heating on the substrate, filling the inside of the guide and printing the chip with epoxy;
Curing a portion of the printed molded epoxy with the heatable guide;
Releasing the guide from the substrate and the epoxy, and curing the remaining area of the print-molded epoxy.
The method of claim 6,
After releasing the guide from the substrate and the epoxy and curing the remaining area of the print-molded epoxy,
Further comprising cutting the cured printed molded epoxy and the substrate into a single package structure with the chip embedded therein.
The method of claim 6,
Wherein a plurality of chips are mounted on the substrate,
The above-mentioned epoxy resin-
And performing only some chips or some chips among the plurality of chips.
The method of claim 6,
The heating-
And a resistive coil pattern is formed on the upper surface or the lower surface to generate heat when an electric current is passed therethrough.
The method of claim 9,
Wherein electrical contact terminals are further formed at both ends of the resistance coil pattern,
Wherein the electrical contact terminal is electrically connected to the power supply terminal when the heatable guide is positioned on the substrate so that power can be supplied to the heatable guide.











KR1020100030468A 2010-04-02 2010-04-02 Package structure and method for manufacturing the same KR101648222B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100030468A KR101648222B1 (en) 2010-04-02 2010-04-02 Package structure and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100030468A KR101648222B1 (en) 2010-04-02 2010-04-02 Package structure and method for manufacturing the same

Publications (2)

Publication Number Publication Date
KR20110111075A KR20110111075A (en) 2011-10-10
KR101648222B1 true KR101648222B1 (en) 2016-08-12

Family

ID=45027357

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100030468A KR101648222B1 (en) 2010-04-02 2010-04-02 Package structure and method for manufacturing the same

Country Status (1)

Country Link
KR (1) KR101648222B1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3393247B2 (en) * 1995-09-29 2003-04-07 ソニー株式会社 Optical device and method of manufacturing the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3163419B2 (en) * 1997-08-22 2001-05-08 日本レック株式会社 Electronic component manufacturing method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3393247B2 (en) * 1995-09-29 2003-04-07 ソニー株式会社 Optical device and method of manufacturing the same

Also Published As

Publication number Publication date
KR20110111075A (en) 2011-10-10

Similar Documents

Publication Publication Date Title
JP6654994B2 (en) Circuit component manufacturing method
CN107026107B (en) Electronic component manufacturing apparatus and manufacturing method, and electronic component
KR101847691B1 (en) Method and apparatus for producing electronic component
WO2001043518A1 (en) Chip package with molded underfill
JP6400509B2 (en) Manufacturing method of electronic parts
CN104124216A (en) Substrate chip carrier CSP package and production method thereof
CN104425465A (en) Electronic component module and method of manufacturing same
KR101352233B1 (en) Semiconductor package and the method
US9502337B2 (en) Flip-chip on leadframe semiconductor packaging structure and fabrication method thereof
CN108321092B (en) Method for manufacturing circuit component and circuit component
KR101077887B1 (en) Terminal Integrated Type Metal-Based Package Module and Terminal Integrated Type Packaging Method for Metal-Based Package Module
US9899339B2 (en) Discrete device mounted on substrate
KR101648222B1 (en) Package structure and method for manufacturing the same
KR20080074468A (en) Surface mounting method of semi-conduct chip using the ultrasonic wave
US6124152A (en) Method for fabricating cob type semiconductor package
TWI596718B (en) A circuit module package structure and packaging method thereof
CN203026495U (en) Chip packaging structure
JP5308107B2 (en) Circuit device manufacturing method
KR101661919B1 (en) Manufacturing method of semiconductor package
CN108281398A (en) Semiconductor package assembly and a manufacturing method thereof
CN114937611B (en) Fan-out type wafer level packaging structure and preparation method thereof
JP6420551B2 (en) Lead frame and manufacturing method of semiconductor device
JP3923661B2 (en) Semiconductor device
KR102024227B1 (en) Methods of fabricating semiconductor package
JP6171920B2 (en) Mold package

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20190711

Year of fee payment: 4