KR101640510B1 - Silicon interposer having capacitor and fabrication method therefor - Google Patents

Abstract

A silicon interposer having a capacitor and a manufacturing method thereof are disclosed. The silicon interposer according to an embodiment of the present invention includes: a silicon substrate; a through via hole formed through the silicon substrate, having a conductive material deposited on the inner wall thereof, and having a polymer material filled therein; an embedded capacitor having one terminal thereof receiving a voltage applied from the outside, and having the other terminal electrically connected to the conductive material deposited on the inner wall of the through via hole; and an exposure electrode formed on the rear surface of the silicon substrate, and electrically connected to the conductive material deposited on the inner wall of the through via hole. The silicon interposer and the manufacturing method thereof can miniaturize a semiconductor package, and can reduce manufacturing costs and a manufacturing time as well.

Description

TECHNICAL FIELD [0001] The present invention relates to a silicon interposer having a capacitor,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon interposer used in a semiconductor package manufacturing process and a method of manufacturing the same. More particularly, the present invention relates to a silicon interposer capable of improving integration by incorporating a capacitor and a manufacturing method thereof.

In order to expand the capacity and function of a semiconductor device, the degree of integration in a wafer fabrication process is gradually increasing. In the process of assembling a semiconductor package, the use of two or more semiconductor chips or a semiconductor package having two or more semiconductor packages integrated into one is common .

That is, by integrating two or more semiconductor chips or two or more semiconductor packages into a single semiconductor chip in the process of assembling the semiconductor chip into a semiconductor package in a wafer state, it is possible to increase the degree of integration with less facility investment and cost do. Accordingly, semiconductor device manufacturers have developed integrated semiconductor packages such as SIP (System In Package), MCP (Multi Chip Package) and POP (Package On Package) And is spurring research and development on.

In order to efficiently manufacture the integrated semiconductor package of the SIP, MCP and POP structures, an interposer having a through-hole, which is used as a connection path for connecting the basic frame of the semiconductor package or the upper and lower semiconductor chips, Is being introduced.

On the other hand, a large capacity capacitor is required depending on the semiconductor package. At this time, when a capacitor having a large capacitance is coupled from the outside, the semiconductor package as a whole is disadvantageously enlarged.

Accordingly, a silicon interposer capable of miniaturizing the entire semiconductor package is required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a silicon interposer capable of miniaturizing a semiconductor package as a whole and a manufacturing method thereof.

In order to accomplish the above object, one aspect of the present invention relates to a silicon interposer. The silicon interposer of the present invention comprises a silicon substrate; A through via hole formed through the silicon substrate, the via hole being formed by depositing a conductive material on an inner wall and filling a polymer material therein; And a conductive layer formed on the inner wall of the through via hole and electrically connected to the conductive material deposited on the inner wall of the through via hole, A capacitor; And an exposed electrode formed on a rear surface of the silicon substrate, the exposed electrode being electrically connected to the conductive material deposited on the inner wall of the through via hole.

According to another aspect of the present invention, there is provided a method of manufacturing a silicon interposer. A method of manufacturing a silicon interposer according to the present invention includes the steps of: A) forming a via recess on a front surface of a silicon substrate by etching so as not to penetrate the silicon substrate; B) forming a conductive material on the inner wall of the via recess; C) depositing the polymer material on the entire surface of the silicon substrate to fill the inside of the via recess formed with the conductive material on the inner wall with a polymer material; D) planarizing the front surface of the silicon substrate on which the polymer material is deposited to expose the conductive material of the via recess; E) forming a built-in capacitor on the planarized silicon substrate; And forming an exposed electrode connected to the conductive material on the rear surface of the silicon substrate after the rear surface of the silicon substrate on which the polymer material is deposited is ground so as to expose the conductive material of the via recess, Step.

In the interposer of the present invention and the manufacturing method thereof, the capacitor is embedded in the front surface of the silicon substrate. Further, a conductive material is formed on the inner wall of the through via hole of the silicon interposer, and the inside thereof is filled with the polymer material. As a result, according to the interposer and the manufacturing method thereof of the present invention, it is possible to miniaturize the semiconductor package as a whole, and also to reduce manufacturing cost and manufacturing time.

A brief description of each drawing used in the present invention is provided.
1 is a view for explaining a silicon interposer according to an embodiment of the present invention.
2 is a flow chart for explaining a method of manufacturing a silicon interposer according to an embodiment of the present invention.
3 is a diagram specifically showing the step S600 of FIG.
4 to 11 are cross-sectional views illustrating a method of manufacturing a silicon interposer according to an embodiment of the present invention.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be understood, however, that the description of the embodiments is provided to enable the disclosure of the invention to be complete, and will fully convey the scope of the invention to those skilled in the art. In the accompanying drawings, the constituent elements are shown enlarged for the sake of convenience of explanation, and the proportions of the constituent elements may be exaggerated or reduced.

When an element is described as being "on" or "connected to" another element, it is possible that another element may be directly in contact with or connected to the image, but there may be another element in between It should be understood. On the other hand, when an element is described as being "directly on" another element, it can be understood that there is no other element in between. Other expressions that describe the relationship between components, for example, "between" and "directly between"

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms may only be used for the purpose of distinguishing one element from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

The singular forms "a", "an," and "the" include plural referents unless the context clearly dictates otherwise. By way of example, "having" or "comprising" or the like is used to designate the presence of stated features, integers, steps, operations, elements, parts, or combinations thereof, Numerals, steps, operations, elements, parts, or combinations thereof, may be added.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a view for explaining a silicon interposer according to an embodiment of the present invention, showing a cross section of a silicon interposer. FIG.

Referring to FIG. 1, the silicon interposer of the present invention includes a silicon substrate 100, a via hole SVH, a built-in capacitor CAPIN, and an exposed electrode ELOP.

Since the silicon substrate 100 is used only for simple connection through a metal wiring in a semiconductor package, a silicon wafer having a defect in the silicon wafer manufacturing process can be recycled and used.

The through-via holes SVH are formed through the silicon substrate 100. At this time, a conductive material 110 is deposited on the inner wall of the through via hole SVH, and the polymer material 120 is filled therein.

Preferably, the conductive material 110 is copper (Cu).

The built-in capacitor CAPIN is formed on the entire surface of the silicon substrate 100 so as to be surrounded by a protective layer. One terminal of the built-in capacitor CAPIN is electrically connected to the conductive material 100 deposited on the inner wall of the through via hole SVH.

The exposed electrode ELOP is formed on the rear surface of the silicon substrate 100. [ At this time, the exposed electrode ELOP is electrically connected to the conductive material 110 deposited on the inner wall of the through via hole SVH. As a result, the exposed electrode ELOP is electrically connected to another terminal of the built-in capacitor ELOP.

For reference, the reference numerals of the respective components in FIG. 1 may be the same as those in the method of manufacturing the silicon interposer of the present invention, which will be described subsequently.

In the interposer of the present invention as described above, the capacitor is embedded in the front surface of the silicon substrate. Further, a conductive material is formed on the inner wall of the through via hole of the silicon interposer, and the inside thereof is filled with the polymer material. As a result, according to the interposer of the present invention, the semiconductor package as a whole can be downsized, and the manufacturing cost and the manufacturing time are reduced.

Next, a method for producing the silicon interposer of the present invention is described. 2 is a flow chart for explaining a method of manufacturing a silicon interposer according to an embodiment of the present invention.

Referring to FIG. 2, a silicon substrate which can be used as a silicon interposer is prepared (S100).

Next, as shown in FIG. 4, a via recess 102 is formed on the entire surface of the silicon substrate 100 so as not to penetrate the silicon substrate 100 (S200). The via recess 102 is formed by etching the front surface (upper surface in this embodiment) of the silicon substrate 100 in a region for the via hole SVH (see FIG. 1).

In this embodiment, the etching is preferably performed by a dry etching method. The dry etching can be performed using a reactive ion etching (RIE) method using a gas such as Cl2, Ar, He, CF4, SiF4, etc. As the etching mask, a single film such as an oxide film, Or a composite membrane may be used. The dry-vision process can be modified in various manners at the level of those skilled in the art within the scope of dry etching.

5, the conductive material 110 may be formed on the entire surface of the silicon substrate 100 on which the via recess 102 is formed so as to form the conductive material 110 on the inner wall of the via recess 102, 110) (S300).

Specifically, a protective film 106 of about 1 μm is formed on the entire surface of the silicon substrate 100 on which the via recess 102 is formed. At this time, the passivation layer 106 may be formed of an oxide (SiO 2) material. The material of the protective film 106 can be replaced with various kinds of film materials within the scope of the ordinary artisan in the technical field of the present invention.

Next, a barrier layer (not shown) of about 0.3 mu m is formed on the entire surface of the silicon substrate on which the protective film 106 is formed by a sputtering method. The barrier layer (not shown) may be formed using a material such as titanium (Ti), titanium nitride (TiN), or the like.

Next, a seed layer (not shown) of about 1 μm is formed on the back surface of the silicon substrate on which the barrier layer (not shown) is formed by a sputtering method. The seed layer is preferably formed using copper, which is easy to be electroplated.

Then, the seed layer is grown by an electroplating method to form the first conductive material 110 having a thickness of 10 um or more on the outer wall of the via recess 102.

6, the polymer material 120 is deposited on the entire surface of the silicon substrate 100 to fill the inside of the via recess 102 with the polymer material 120 (S400 ).

At this time, the filling of the polymer material 120 is preferably performed with the tapping of the silicon substrate 100 twice per second. Through this tapping, the density of the polymer material 120 to be filled is improved.

When the polymer material 120 is deposited, the temperature of the plate (not shown) heating the silicon substrate 100 is preferably in the range of 50 ° C ± 10%. That is, if the temperature is too high, the fluidity becomes severe, and if the temperature is too low, the uniformity is degraded.

In addition, when the polymer material 120 is deposited, the internal pressure of the chamber (not shown) in which the silicon substrate 100 is mounted is preferably in the range of 10 Torr ± 10%. That is, if the air pressure is too low, the fluidity becomes severe, and if the air pressure is too high, the uniformity is lowered.

7, the entire surface of the silicon substrate 100 is subjected to a planarization process using a chemical mechanical polishing (CMP) process (S500).

In the chemical mechanical polishing process, the protective layer 106 may be used as a polishing stopper.

Then, a built-in capacitor CAPIN (see FIG. 1) is formed on the planarized surface of the silicon substrate 100 (S600).

3 is a flowchart specifically showing the step S600 of FIG. Referring to FIG. 3, step S600 is described in detail.

8, after the insulating layer 121 is formed on the entire surface of the planarized silicon substrate 100, the conductive material 110 of the via recess 102 is exposed, The insulating layer 121 is patterned and etched (S610).

9, a first metal layer 123, a dielectric layer 125, and a second metal layer 127 are sequentially formed to implement a built-in capacitor CAPIN (S630).

The first metal layer 123 is formed on the insulating layer 121 by patterning so as to be electrically connected to the conductive material 110 of the via recess 102. The dielectric layer 125 is formed on the first metal layer 123 and the second metal layer 127 is formed on the dielectric layer 125 by patterning.

Next, as shown in FIG. 10, a third metal layer 133 is formed to allow voltage to be applied to the second metal layer 127 of the built-in capacitor CAPIN (S650).

Specifically, the isolation layer 131 is patterned on the second metal layer 127, and as a result, a portion of the second metal layer 127 is exposed. A third metal layer 133 is deposited on the isolation layer 131 to be electrically connected to the second metal layer 127.

Accordingly, a voltage can be applied to the second metal layer 127 forming one end of the built-in capacitor CAPIN through the third metal layer 133.

2, an exposed electrode ELOP is formed on the rear surface (lower surface in this embodiment) of the silicon substrate 100 after the built-in capacitor CAPIN is formed. (S700)

Specifically, as shown in FIG. 11, an exposure electrode ELOP is formed on the rear surface of the silicon substrate 100.

The conductive material 110 of the via recess 102 is ground to expose and the lower insulating layer 151 is formed. That is, the rear surface of the silicon substrate 100 filled with the polymer material 120 is ground to expose the conductive material 110 of the via recess 102. The lower insulating layer 151 is patterned on the rear surface of the silicon substrate 100 to expose the conductive material 110 of the via recess 102.

A fourth metal layer 153 is formed on the lower insulating layer 151 by patterning. The fourth metal layer 153 may be an exposed electrode ELOP connected to the conductive material 110. That is, a voltage can be applied to the first metal layer 123 forming the other terminal of the built-in capacitor CAPIN through the exposed electrode ELOP, and the ball BALL can be coupled.

According to the method of manufacturing a silicon interposer of the present invention as described above, the silicon interposer of the present invention as shown in FIG. 1 can be provided.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (5)

delete delete A method of manufacturing a silicon interposer,
A) forming a via recess by etching the entire surface of the silicon substrate so as not to penetrate the silicon substrate;
B) forming a conductive material on the inner wall of the via recess;
C) depositing the polymer material on the entire surface of the silicon substrate to fill the inside of the via recess formed with the conductive material on the inner wall with a polymer material;
D) planarizing the front surface of the silicon substrate on which the polymer material is deposited to expose the conductive material of the via recess;
E) forming a built-in capacitor on the planarized silicon substrate; And
Forming an exposed electrode connected to the conductive material on the rear surface of the silicon substrate after the rear surface of the silicon substrate on which the polymer material is deposited is exposed so as to expose the conductive material of the via recess; And,
The step C)
Wherein the polymer material is deposited on the entire surface of the silicon substrate on which the conductive material is formed while performing a tapping process.
A method of manufacturing a silicon interposer,
A) forming a via recess by etching the entire surface of the silicon substrate so as not to penetrate the silicon substrate;
B) forming a conductive material on the inner wall of the via recess;
C) depositing the polymer material on the entire surface of the silicon substrate to fill the inside of the via recess formed with the conductive material on the inner wall with a polymer material;
D) planarizing the front surface of the silicon substrate on which the polymer material is deposited to expose the conductive material of the via recess;
E) forming a built-in capacitor on the planarized silicon substrate; And
Forming an exposed electrode connected to the conductive material on the rear surface of the silicon substrate after the rear surface of the silicon substrate on which the polymer material is deposited is exposed so as to expose the conductive material of the via recess; And,
Tapping
Wherein the silicon interposer is a silicon wafer.
A method of manufacturing a silicon interposer,
A) forming a via recess by etching the entire surface of the silicon substrate so as not to penetrate the silicon substrate;
B) forming a conductive material on the inner wall of the via recess;
C) depositing the polymer material on the entire surface of the silicon substrate to fill the inside of the via recess formed with the conductive material on the inner wall with a polymer material;
D) planarizing the front surface of the silicon substrate on which the polymer material is deposited to expose the conductive material of the via recess;
E) forming a built-in capacitor on the planarized silicon substrate; And
Forming an exposed electrode connected to the conductive material on the rear surface of the silicon substrate after the rear surface of the silicon substrate on which the polymer material is deposited is exposed so as to expose the conductive material of the via recess; And,
The step E)
E1) forming the insulation layer by patterning so that the conductive material of the via recess is exposed on the entire surface of the planarized silicon substrate;
Forming a first metal layer on the insulating layer by patterning the first metal layer so as to be electrically connected to the conductive material of the via recess, forming a dielectric layer on the first metal layer, E2) forming by patterning; And
E3) patterning the isolation layer on the second metal layer to expose a portion of the second metal layer, and depositing a third metal layer on the isolation layer to electrically connect the second metal layer to the second metal layer And forming a silicon interposer on the substrate.

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