TWI441308B - Stacked wafer for 3d integration - Google Patents

Description

Stacked wafer for 3D integration Field of invention

The present invention relates to stacked wafers for integrating multiple wafer platforms into a single scaled package. In particular, the present invention relates to a method for fabricating the package to facilitate combining a plurality of components in a single integrated structure.

Background of the invention

The semiconductor industry has been looking for a viable solution for wafer level integration for many years because it allows the use of a large number of very short vertical interconnects to distribute and recombine IC designs on a single substrate. The IC thus fabricated provides higher density and speed due to the smaller grain size and correspondingly shorter RC delay. Incompatible processes, such as analog and digital (non-compromising), can be fabricated on different wafers using a fully optimized process and then recombined to produce a 3-dimensional (3D) IC. Thus, wafer level heterogeneous substrate integration for ultra high performance (eg, Si and SiGe for digital and RF components, respectively) can be obtained.

3D integration includes the integration of specific components, such as memory, sensors, and the like. The components are fabricated on respective substrates and then bonded to form a single package that includes several components. In order to maintain the package at a size that can be used in state of the art applications, the wafer on which the respective components are placed must be thinned such that the overall size of the 3D integrated package is comparable to the size of the currently used unit.

In addition to the size advantages of multiple components in a single package, 3D integration A combination of incompatible technologies is also provided while improving the speed performance and functionality of the packaged components. Thus, without 3D integration, multiple components can be separated by a greater distance that requires additional wiring, or even further, for completely incompatible techniques, the components can rely on external routing that further attenuates the performance of the combined system.

3D integrated packaging or system-in-a-package (SIP) can reduce or eliminate external wiring associated with non-integrated components, resulting in lower manufacturing costs while improving performance and thereby maintaining new end-product applications. The demand is up to date.

Therefore, any attempt to combine multiple components at the wafer level requires external routing and thus severely affects the performance of the components. Alternatively, 3D integration has been attempted at the transistor level whereby multiple components are connected by a transistor while still in the same stack. The integration at the transistor level has a limiting effect on the speed of the integrated components when better results are obtained in terms of size than at the wafer level. In any case, the manufacture of such stacked components involves a considerable level of manufacturing cost, as the connectivity between the components requires more complicated connections in order to achieve the desired results.

Summary of invention

Accordingly, it is an object of the present invention to provide a method of forming an integrated package without the problems of the prior art.

In a first aspect, the present invention provides a method of forming a stacked wafer component, comprising the steps of: providing a first wafer; forming a plurality of copper pads in a first surface of the first wafer; Formed in the first wafer At least one embedded vertical connector isolated by a copper pad of a wafer; providing a second wafer; forming a plurality of copper pads in the first surface of the second wafer, and arranging the copper pads Positioning a copper pad of the first wafer; forming at least one embedded vertical connector isolated from the copper pad of the second wafer in the second wafer; contacting the first surface of the wafer to facilitate contact with the copper a pad; applying a force to the wafer at a predetermined pressure and a predetermined temperature until the copper pads are bonded, and thereby forming the stacked wafer elements from the bonded first and second wafers.

Thereby, the wafer is brought into contact at the liner and subjected to heat and pressure for a specific period of time to obtain thermal diffusion of the liner and thus the wafer.

Integration is a key aspect of technology development. When monolithic integration has evolved considerably, it will reach a point where further development is limited due to the need for a wide range of different material systems that must be used in the unit. The present invention provides polylithic integration that allows each material to perform its most suitable task. By achieving true multi-chip integration, components fabricated in accordance with the present invention provide enhanced performance due to higher speed, density, reliability, and power consumption.

Compared with other manufacturing methods, such as Multi-Chip-Module (MCM), Multi-Chip-Package (MCP) or System-in-Package (SIP), where interconnection between layers is possible Limiting to a few hundred or several thousand inter-die connections, elements formed in accordance with the present invention can be orders of magnitude higher (on the order of millions).

In addition, ULSI designs can be split into smaller parts and recombined to produce higher yields. Shorter connections through higher integration, To reduce RC delay, resulting in lower power consumption and higher speed.

In a preferred embodiment, the vertical connector and substrate can be embedded by a barrier layer.

In a preferred embodiment, the barrier layer may comprise a metal barrier layer comprising any one of the following or a combination thereof: Ti, TiN, Ti _x Si _y N _z , Ta, TaN, Ta _x Si _y N _z , W , WN and WN ₂ . In another embodiment, the barrier layer can include an oxide layer. In yet another embodiment, the barrier layer can include a nitride layer.

In a preferred embodiment, a plurality of copper pads can be placed on the same plane as the dummy copper pads, the plurality of copper pads electrically connecting the two connection wafers and bonding purposes, and the dummy copper liner The pads do not electrically connect the two connection wafers and are used only for connection purposes.

In a preferred embodiment, a plurality of copper pads can be formed simultaneously from two or more shaped bond pads on the same plane.

In a preferred embodiment, the at least one embedded vertical connector can be formed by a dry etching process using a fluorine based plasma. In a more preferred embodiment, the embedded vertical connector can extend from the IMD (inter-metal dielectric layer) into the Si substrate.

In a preferred embodiment, the embedded vertical connection depth embedded in the Si substrate can be in the range of 4-10 μm deep. In addition, the diameter of the embedded vertical connector can be in the range of 0.2-10 μm.

In a preferred embodiment, the vertical connector can be embedded by PECVD deposition of a dielectric barrier layer, which layer can comprise undoped SiO ₂ , tetraethyl-orthosilicate (TEOS), SiON, Phosphorus silicate glass (PSG), fluorosilicate glass (FSG), SiOC, borophosphosilicate glass (BPSG) and SiN.

In a preferred embodiment, the thickness of the dielectric barrier layer can range from 0.05 [mu]m to 0.3 [mu]m.

In a preferred embodiment, copper, tungsten, aluminum, and alloys thereof are used in the vertical connector of the embedded vertical connector of claim 1.

In a preferred embodiment, the metallization of the vertical connector can be formed by a dry etch process or a CMP process.

In a preferred embodiment, lithographic alignment targets can be formed simultaneously, such as step alignment targets. Additionally, the size of the alignment target can be varied to have a size that is compatible with the diameter of the vertical connector.

In a preferred embodiment, a relatively large Si etch stop layer is formed that is relatively larger than the vertical connector. In addition, the size of the Si etch stop layer may range from 1 μm to 100 μm.

In a preferred embodiment, a wet (or dry) etch process can be used to form a bump of the copper bond pad surface from the dielectric surface by lowering the dielectric surface. In addition, BOE (buffered oxide etchant) can be used for this treatment.

In a preferred embodiment, the copper surface can be wet cleaned using acetic acid and an ammonium fluoride solution. Alternatively, acetic acid:ammonium fluoride:DI aqueous solution can be used in a 1:1:1 ratio. Alternatively, a 1:10:40 ratio of hydrogen peroxide: ethylenediamine: DI aqueous solution can be used as a combination treatment.

In a more preferred embodiment, diluted ethylenediamine can be used as a combination treatment. In addition, BAT (benzotriazole) can be used as a combination treatment.

In a preferred embodiment, a fluorine-based plasma can be used to surface the wafer surface. Raised copper pad. Alternatively, the surface of the copper may be cleaned using hydrogen plasma or nitrogen plasma after processing or during processing.

In a preferred embodiment, the thinning of the outer surface of the stacked (bonded) wafer can be formed by grinding, CMP, and wet/dry etching processes, or a combination thereof.

In a preferred embodiment, a bottom surface embedded in the vertical connector can be used as the Si etch stop layer during the thinning process.

In a preferred embodiment, Si can be thinned by wet etching using a KOH-based, TMAH-based, EDP etching solution during the thinning process. Alternatively, Si can be thinned by a fluorine-based plasma dry etching process. In another alternative embodiment, Si can be thinned by a CMP process.

In a preferred embodiment, the etch stop layer can be detected using a laser or white light source, which may be a dielectric layer at the bottom of the vertical connection via.

In a preferred embodiment, a resistance measurement method on the polishing pad can be used to detect the etch stop layer, which may be a dielectric layer at the bottom of the vertical connection via.

In a preferred embodiment, a temperature measurement method on the polishing pad can be used to detect the etch stop layer, which may be a dielectric layer at the bottom of the vertical connection via.

In a preferred embodiment, Si may be further etched after the bottom of the vertical connection via has been detected. In addition, the thickness of Si further etched may range from 0.2 μm to 2 μm.

In a preferred embodiment, an etch stop layer detection signal can be obtained from the large etch stop layer that is simultaneously formed during vertical connection via formation.

In a preferred embodiment, the dielectric layer can be planarized by a dielectric CMP process. Alternatively, the dielectric layer can be planarized by a blanket photoresist etch-back process.

In a preferred embodiment, the step of providing a wafer includes forming a wafer by plasma enhanced chemical vapor deposition.

In a preferred embodiment, the step of providing a wafer includes forming a wafer by a SOG (Spin On Glass) method, which may include SOG, SiLK (Spin-on Low-k dielectric).

In a preferred embodiment, the method further includes the steps of: depositing a dielectric layer using conventional CVD techniques; and processing the dielectric layer using a CMP process to provide a planar surface.

Simple illustration

It will be convenient to further describe the present invention with respect to the drawings that describe possible configurations of the present invention. Other configurations of the present invention are possible, and therefore, the particularity of the drawings is not to be construed as limiting the generality of the foregoing description of the present invention.

1a is a front view of a CMOS wafer according to a first embodiment of the present invention; FIG. 1b is a front view of a CMOS wafer according to a second embodiment of the present invention; and FIG. 2 is an embedded vertical according to an embodiment of the present invention Front view of the connector; Figure 3a is a front view of the CMOS wafer of Figure 1a after planarization; Figure 3b is a CMOS wafer of Figure 3a exposed to expose the vertical connector Figure 3c is a front view of the CMOS wafer of Figure 1a stacked with the CMOS wafer of Figure 3b according to the third embodiment of the present invention; and Figure 4 is a third view of the CMOS wafer after the copper pad is placed. FIG. 5 is a front view of another CMOS wafer of FIG. 1a stacked on the CMOS wafer of FIG. 4; FIG. 6 is a front view of the CMOS wafer of FIG. 1A of the CMOS wafer stack; FIG. A front view of the I/O pads stacked on the CMOS wafer of Figure 5.

Detailed description of the preferred embodiment

Figures 1a and 1b illustrate two embodiments of the invention that both include an IC layered CMOS process wafer. The IC layers 15, 20 have been formed in the dielectric layers 41, 42 and are formed together on the germanium substrates 40, 45. The outer surfaces of the wafers 5, 10 have copper pads 35, 38 embedded in the surface of the dielectric.

The main difference between the embodiments of Figures 1a and 1b is the arrangement of the vertical connectors 25,30. In the case of Figure 1a, the vertical connector has been embedded in the wafer 5 prior to formation of the first IC layer 46 (metal-1). Figure 1b has a vertical connector 30 embedded in the wafer 10 after the integrated circuit layer 20 is disposed, but before the copper pads 38 are disposed. In fact, the present invention does not rely on any particular location or stage of vertical connector 25, 30 formation, which may be disposed prior to any IC metal layer (e.g., metal-1 to metal-6 of Figure 1).

A feature of the invention that distinguishes the embodiments of Figures 1a and 1b is a vertical connector 25, 30 and copper pads 35, 38 connection relationship. In Fig. 1a, the connection is hidden because the copper pad 35 is connected from the vertical connector 25 through several IC layers 15. The IC layer 15 can be constructed in any conventional manner, and the precise characteristics and structure of these integrated circuit components are well known to those skilled in the art. In Figure 1b, the connection is straightforward, connecting the vertical connector 30 to the copper pad 38, either by simultaneously forming the two components using a copper dual damascene process, or by making the connector 30 in two steps, and then Copper pad 38.

Fig. 2 shows a detailed view of the vertical connector 25 according to the embodiment of Fig. 1a.

This embodiment shows a vertical connector 25 embedded in a germanium substrate 40 and a dielectric layer 42, such as hafnium oxide. It should be noted that the substrate 40 can be of several different materials, as will be understood by those skilled in the art, including Si, SeGe or GaAs. The process begins by etching vias into dielectric layer 42 and germanium substrate 40. Next, a nitride layer 70, then an oxide layer 65, and then a metal barrier layer 60 are deposited before the via holes are filled with the metal 55.

The nitride layer 70 has a dual function, first acting as a diffusion barrier to prevent diffusion of the metal 55 from the vias into the surrounding substrate. It also has a second function that acts as an etch stop layer during the wet etch process used to thin the backside of the stacked wafer. The nitride layer 70 may have a thickness in the range of 0.05 to 0.1 μm and may be SiN.

The oxide layer 65 acts as an electrical insulator between the surrounding substrate and the vertical connector, which may be a ceria layer, possibly in the range of 0.05 to 0.3 microns. It also has a second function that acts as an etch stop layer during the dry etch process used to thin the backside of the stacked wafer.

Metal diffusion barrier layer 60 is over oxide layer 65 to further prevent metal 55 from diffusing into the wafer. Preferably, the diffusion barrier layer 60 has a thickness in the range of 200 to 1000 angstroms and includes metals such as Ti, TiN, Ti _x Si _y N _z , Ta, TaN, Ta _x Si _y N _z , W, WN and WN. ₂ . It also has a second function that acts as an etch stop layer during the CMP process used to thin the backside of the stacked wafer. Preferably, the barrier metal for Cu may be Ta as a connector conductive material, and for Al or W conductive material Ti/TiN as a lower layer.

The vias are then filled with a metal 55, such as tungsten, aluminum, copper, or alloys thereof to complete the vertical connector 25. The benefits provided by such a vertical connector 25 include very short inter-wafer interconnections, which are less than 15 μm for layer-to-layer (wafer to wafer connectivity). Importantly, it will provide white light to the target for the lithography process on the reverse side of the thinned wafer that is subsequently stacked on the wafer. The diameter of the vertical connector can be in the range of 1 to 10 μm and enter the substrate 4-6 μm deep.

The formation of the vertical connector 30 can have a construction similar to the embodiment of Figure 1a and other embodiments that actually fall within the broader invention. The vertical connector 30 can also be constructed as an integral part of the copper pad 38 using a conventional dual damascene process.

Referring to Figures 3a through 3c, stacked wafers 72 are formed by combining two wafers 5, 75 to contact a plurality of copper pads 90, 95 at interface 85. Contact at the interface 85 copper pads 90, 95 is ensured by recessing adjacent oxide regions (0.03 - 0.1 μm, using wet/dry etching) around the pads. Due to the exposure of the pre-cleaned copper pads 90, 95, a high degree of inter-diffusion of the copper pads can be obtained and must be within the limits required to fabricate the stacked wafers 72. A copper liner is then prepared for bonding, for example, a cleaning liner and a peripheral surface recession process. Preferably, the bumps on the surface of the copper bond pad can be obtained by recessing the surrounding dielectric surface by a wet or dry etch process followed by a wet or dry etch process to treat the Cu pad surface. However, BOE (a mixture of ammonium fluoride, hydrofluoric acid and water) can simultaneously clean the surface of the Cu bond liner and recess the surrounding dielectric surface if the surrounding dielectric surface is composed of SiO ₂ .

When in contact, the wafer is subjected to sufficient pressure and temperature conditions to cause the copper liner to enter thermal diffusion and thereby bond the wafers 5, 75 at the interface 85 between the copper pads 90, 95. The conditions for obtaining copper thermal diffusion may be in an oxygen-free (nitrogen, inert gas or vacuum) environment, at a temperature in the range of 300 to 450 ° C, at a pressure in the range of 20 to 60 psi, staying 5 to 50 Minutes of time.

Once the bonding at interface 85 has been obtained, the components of the two wafer stacks can be fabricated by thinning the bottom wafer on which the I/O pads need to be built. The back surface of the bottom wafer can be thinned by coarse and fine grinding followed by CMP followed by a wet/dry etching process until the bottom surface 100 of the vertical connector 102 appears on the thinned surface. Thus, by bonding the wafers 5, 75 to form the stacked wafer 72, the individual wafers can be thinned during processing or later processing due to the increased robustness due to the stacked top wafers 75. 5 There is no risk of thinning the wafer. As shown in Figures 3a and 3b, the exposed surface 100 is recessed by 0.2 to 2 μm using a dry or wet etch process to ensure vertical bumps on the peripheral surface 103 of the connector 102. A layer of SiO ₂ 81 having a thickness of 0.3 to 2 μm is then deposited on the surfaces 100 and 103. The layer 81 is then planarized using standard techniques, namely oxide CMP or an optional oxide etch back process, to ensure that the surface of the vertical electrical connector 102 is exposed. An I/O pad metal layer 140 composed of Ti/TiN and an Al alloy is sputter deposited. Using the alignment targets visible on the exposed surface 100 (the bottom of the connector 102), the I/O pad metal mask can be aligned with high precision. Finally, the I/O pad metal is defined by an etching process using conventional methods.

In order to form more complex stacked wafers (three and more), as shown in FIG. 4, a thinning process is performed on the back side of the top wafer of the two wafer stacks. After the upper surface 100 of the vertical connector 102 has been reached, Si is further recessed as described above. A SiO ₂ layer of 0.3 to 2 μm is deposited on the surface of the recessed Si, followed by a planarization process. The white surface exposure tool can then be used to pattern the new surface 80 to ultimately form the copper liner 105 using conventional single copper damascene process steps. After the adjacent oxide surface 80 is recessed, the two wafer stacks can be combined with another wafer. It should be noted that the copper pad may include an electrical connection pad for connecting two or more wafer elements and a dummy pad on the same plane as the electrical connection pads. In this configuration, the dummy pads promote bond strength to adjacent wafers.

FIG. 5 illustrates the addition of another wafer 115 to form a more complex stacked wafer 110. As with the bonding step described above, the respective pad arrays 120, 125 are aligned to form the interface 130, so that when a certain amount of dwell time is applied thereto at a certain temperature, the pads are bonded by thermal diffusion. . To build a more complex stacked wafer, the process can continue until the desired components have been formed.

After the bottom wafer 5 is thinned, the process steps of forming an I/O liner as described above with reference to FIG. 3a are then performed to produce the I/O liner of FIG. The backside treatment for I/O and other processing for Cu include 0.3-2 A μm thick dielectric, preferably PECVD TEOS deposited at 400C. In IC fabrication, all I/O pads are formed on the back side of the wafer for the first time. For IC fabrication, the passivation mask is removed (since the circuit is buried under the Si surface containing the I/O pads).

Other features of the invention may include alignment targets (for white light and IR alignment) that use a backside embedded in a vertical connector (preferably placed between the scribe lines), allowing the standard lithography machine to identify sellers to recommend and/or change Benchmark. In addition, the thinning control may comprise a composite material on the sidewalls of the vertical connector having a thickness ranging from 0.05 to 0.1 μm for SiN, 0.05 to 0.3 μm for SiO ₂ and 0.025 to 0.1 for Ta or Ti/TiN. .

5, 10, 75‧‧‧ wafers

81‧‧‧SiO ₂ layer

15, 20‧‧‧IC layer

85‧‧‧ interface

25, 30‧‧‧ vertical connectors

90, 95‧‧‧ copper pad

30‧‧‧Connector

100‧‧‧ bottom surface

35, 38‧‧‧ copper pad

100,103‧‧‧ surface

40, 45‧‧‧矽 substrate

102‧‧‧Vertical connectors

41, 42‧‧‧ dielectric layer

105‧‧‧copper pad

55‧‧‧Metal

115‧‧‧ wafer

60‧‧‧Metal barrier

110‧‧‧Stacked wafer

65‧‧‧Oxide layer

120, 125‧‧‧ spacer array

70‧‧‧ deposited nitride layer

130‧‧‧ interface

72‧‧‧Stacked wafer

140‧‧‧I/O gasket metal layer

1a is a front view of a CMOS wafer according to a first embodiment of the present invention; FIG. 1b is a front view of a CMOS wafer according to a second embodiment of the present invention; and FIG. 2 is an embedded vertical according to an embodiment of the present invention Front view of the connector; Figure 3a is a front view of the CMOS wafer of Figure 1a after planarization; Figure 3b is a front view of the CMOS wafer of Figure 3a after etching to expose the vertical connector; Figure 3c A front view of a CMOS wafer of FIG. 1a stacked with a CMOS wafer of FIG. 3b according to a third embodiment of the present invention; and FIG. 4 is a stacked view of the CMOS wafer of FIG. 3b after the copper pad is placed. a front view of the CMOS wafer of Figure 1a; Figure 5 is a front elevational view of another CMOS wafer of Figure 1a stacked on the CMOS wafer of Figure 4; and Figure 6 is a front view of the I/O pad stacked on the CMOS wafer of Figure 5. Figure.

5, 75‧‧‧ wafer

102‧‧‧Vertical connectors

110‧‧‧Stacked wafer

115‧‧‧ wafer

Claims (28)

A method of forming a stacked wafer component, comprising the steps of: providing a first wafer; forming a plurality of copper pads in a first surface of the first wafer; forming the same in the first wafer Forming at least one embedded vertical connector of the copper pads of a wafer; providing a second wafer; forming a plurality of copper pads in a first surface of the second wafer, the copper pads Arranging a position coincident with a copper pad of the first wafer; forming at least one embedded vertical connector isolated from the copper pads of the second wafer in the second wafer; The first surfaces are in contact to facilitate contact with the copper pads; a force is applied to the wafers at a predetermined pressure and a predetermined temperature until the copper pads are bonded and thereby bonded from the first And forming the stacked wafer component with the second wafer. The method of claim 1, wherein the step of forming the plurality of copper pads comprises any one of the following: a single damascene process using a CMP process, a dual damascene process using a CMP process, a dry etching process, and a wet etching process. Process or both wet and dry etch processes. The method of claim 1 or 2, wherein the step of forming the plurality of copper pads is to place a barrier layer to isolate the plurality of copper pads and the wafer, the layer comprising the following Any one or a combination thereof: Ti, TiN, Ti _x Si _y N _z , Ta, TaN, Ta _x Si _y N _z , W, WN and WN ₂ . The method of claim 1, wherein the step of providing the wafer comprises forming the wafer by plasma enhanced chemical vapor deposition. The method of claim 4, wherein the wafer comprises undoped SiO ₂ , tetraethyl orthosilicate (TEOS), SiON, phosphonite glass (PSG), fluorosilicate glass (FSG), SiOC, borophosphonate glass (BPSG). The method of claim 1, wherein the step of providing the wafer comprises forming the wafer by a SOG (Spin On Glass) method. The method of claim 6, wherein the wafers comprise SOG, SiLK (spin-coated low-k dielectric). The method of claim 1, wherein the step of forming at least one embedded vertical connector is obtained by a dry etching process using a fluorine-based plasma. The method of claim 1, wherein the embedded vertical connector extends from the intermetal dielectric layer into the wafer substrate. The method of claim 9, wherein the vertical connector is embedded in the wafer to a depth in the range of 4 to 10 μm. The method of claim 1, wherein the vertical connector has a diameter ranging from 0.2 to 10 μm. The method of claim 1, further comprising the step of: exposing the copper pads by lowering the dielectric surface by using either or both of a wet process and a dry etching process to facilitate bulging from the surface of the wafer The liner. The method of claim 12, wherein the copper pads are exposed It is convex from the surface in a range of 0.2 μm to 2 μm. The method of claim 1, wherein at least one of the materials embedded in the vertical connector is more resistant to CMP than the material of the corresponding wafer. The method of claim 12 or 13, further comprising the steps of: depositing a dielectric layer using conventional CVD techniques; and treating the dielectric layer using a CMP process to provide a planar surface. The method of claim 15, wherein the dielectric layer has a thickness in the range of 1 to 2 μm. The method of claim 15, further comprising the step of forming an I/O liner on a second side of the first wafer. The method of claim 1, further comprising the steps of: grinding an outer surface of the stacked wafer component, and then performing CMP to expose the embedded vertical connector of either or both of the first and second wafers At least part of it. The method of claim 1, further comprising the steps of: providing a third wafer; forming a plurality of copper pads in a first surface of the third wafer; forming the same in the third wafer At least one of the copper pads isolated from the third wafer is embedded in the vertical connector; such that the first surface of the third wafer is in contact with an outer surface of the stacked wafer component to facilitate contact with the copper pads; A force is applied to the third wafer and stacked wafer elements at a predetermined pressure and at a predetermined temperature until the copper pads are bonded. The method of claim 19, wherein the contacting the first surface of the third wafer with the outer surface of the stacked wafer comprises the step of using the visible back surface of the vertical connector as a white light alignment reference. The method of claim 1, further comprising the steps of: printing the I/O metal layer using the visible back surface of the vertical connector as a white light alignment reference; and defining the I/O liner by a conventional metal etching process Produce electrically active stacked wafer components. The method of claim 1, wherein the material used to form any of the individual embedded vertical connectors comprises any one of titanium, tungsten, aluminum, copper, or an alloy thereof. The method of claim 22, wherein the embedded vertical connector is isolated from the substrate by a barrier layer. The method of claim 23, wherein the barrier layer comprises a metal barrier layer comprising any one or a combination of the following: Ti, TiN, Ti _x Si _y N _z , Ta, TaN, Ta _x Si _y N _z , W, WN and WN ₂ . The method of claim 23, wherein the barrier layer comprises an oxide layer. The method of claim 23, wherein the barrier layer comprises a nitride layer. The method of claim 1, wherein the at least one wafer comprises a substrate comprising Si, SeGe or GaAs. The method of claim 1, wherein the plurality of copper pads comprises electrical connection pads for connecting two or more wafer elements, and dummy linings on the same plane as the electrical connection pads A pad for promoting bonding strength of adjacent wafers.