TWI441308B - Stacked wafer for 3d integration - Google Patents

Stacked wafer for 3d integration Download PDF

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TWI441308B
TWI441308B TW096101429A TW96101429A TWI441308B TW I441308 B TWI441308 B TW I441308B TW 096101429 A TW096101429 A TW 096101429A TW 96101429 A TW96101429 A TW 96101429A TW I441308 B TWI441308 B TW I441308B
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wafer
forming
copper pads
vertical connector
copper
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TW096101429A
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Chinese (zh)
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Sangki Hong
Chockalingam Ramasamy
Subhash Gupta
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Tezzaron Semiconductor S Pte Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

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  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Description

用於3D整合的堆疊晶圓Stacked wafer for 3D integration 發明領域Field of invention

本發明涉及用於將多個晶圓平臺(platforms)整合為單規模封裝(single scaled package)的堆疊晶圓。尤其是,本發明涉及一種用於製造所述封裝的方法,以便於將多個部件組合在單個整合結構中。The present invention relates to stacked wafers for integrating multiple wafer platforms into a single scaled package. In particular, the present invention relates to a method for fabricating the package to facilitate combining a plurality of components in a single integrated structure.

發明背景Background of the invention

多年以來半導體行業一直在尋求晶圓級整合的可行方案,因為它允許使用大量非常短的垂直互連來分配和重新組合單片襯底上的IC設計。由於更小的晶粒尺寸和相應更短的RC延遲,所以由此製造的IC提供更高的密度和速度。可以使用完全最優的工藝在不同晶圓上製造不相容的工藝,例如類比和數位(不折衷功能),然後重新組合以產生3維(3D)IC。從而,可以獲得用於超高性能的晶圓級異質襯底整合(例如,Si和SiGe分別用於數位和RF部件)。The semiconductor industry has been looking for a viable solution for wafer level integration for many years because it allows the use of a large number of very short vertical interconnects to distribute and recombine IC designs on a single substrate. The IC thus fabricated provides higher density and speed due to the smaller grain size and correspondingly shorter RC delay. Incompatible processes, such as analog and digital (non-compromising), can be fabricated on different wafers using a fully optimized process and then recombined to produce a 3-dimensional (3D) IC. Thus, wafer level heterogeneous substrate integration for ultra high performance (eg, Si and SiGe for digital and RF components, respectively) can be obtained.

3D整合包括特定部件的整合,例如記憶體、感測器等。在各自襯底上製造所述部件,然後鍵合(bonded)以形成包括幾個元件的單封裝。為了將封裝維持在本領域發展水平應用中可以使用的尺寸,必須使其上放置有各自元件的晶圓變薄,使得3D整合封裝的總尺寸與當前使用的單元件的尺寸相當。3D integration includes the integration of specific components, such as memory, sensors, and the like. The components are fabricated on respective substrates and then bonded to form a single package that includes several components. In order to maintain the package at a size that can be used in state of the art applications, the wafer on which the respective components are placed must be thinned such that the overall size of the 3D integrated package is comparable to the size of the currently used unit.

除了在單封裝中包含多元件的尺寸優點之外,3D整合 還提供了不相容技術的組合,同時改善封裝元件的速度性能和功能性。因此,沒有3D整合,多元件可以被需要附加佈線的更大距離分隔開,或者更進一步地,對於完全不相容的技術,所述元件可以依賴於進一步減弱組合系統性能的外部佈線。In addition to the size advantages of multiple components in a single package, 3D integration A combination of incompatible technologies is also provided while improving the speed performance and functionality of the packaged components. Thus, without 3D integration, multiple components can be separated by a greater distance that requires additional wiring, or even further, for completely incompatible techniques, the components can rely on external routing that further attenuates the performance of the combined system.

3D整合封裝或者系統級封裝(system-in-a-package,SIP)可以降低或者消除與非整合元件相關的外部佈線,導致製造成本的降低,同時改善性能,並由此保持新終端產品應用的需求最新。3D integrated packaging or system-in-a-package (SIP) can reduce or eliminate external wiring associated with non-integrated components, resulting in lower manufacturing costs while improving performance and thereby maintaining new end-product applications. The demand is up to date.

因此,在晶片級組合多個元件的任何嘗試都需要外部佈線並由此嚴重地影響了元件的性能。可替換地,已經在電晶體級嘗試產生3D整合,由此,多個元件通過電晶體連接,同時仍然在相同的堆疊中。當就尺寸而言比在晶片級獲得更好結果時,在電晶體級的整合對整合元件的速度具有限制的影響。在任何情況下,這種堆疊元件的製造涉及相當大級別的製造成本,因為為了獲得所需的結果,元件之間的連接性需要更複雜的連接。Therefore, any attempt to combine multiple components at the wafer level requires external routing and thus severely affects the performance of the components. Alternatively, 3D integration has been attempted at the transistor level whereby multiple components are connected by a transistor while still in the same stack. The integration at the transistor level has a limiting effect on the speed of the integrated components when better results are obtained in terms of size than at the wafer level. In any case, the manufacture of such stacked components involves a considerable level of manufacturing cost, as the connectivity between the components requires more complicated connections in order to achieve the desired results.

發明概要Summary of invention

因此,本發明的目的是提供一種形成整合封裝的方法,而不具有現有技術的問題。Accordingly, it is an object of the present invention to provide a method of forming an integrated package without the problems of the prior art.

在第一方面中,本發明提供了一種形成堆疊晶圓元件的方法,包括步驟:提供第一晶圓;在第一晶圓的第一表面中形成多個銅襯墊(copper pads);在第一晶圓中形成與第 一晶圓的銅襯墊隔離的至少一個嵌入垂直連接器(embedded vertical connector);提供第二晶圓;在第二晶圓的第一表面中形成多個銅襯墊,銅襯墊的佈置與第一晶圓的銅襯墊的位置重合;在第二晶圓中形成與第二晶圓的銅襯墊隔離的至少一個嵌入垂直連接器;使得晶圓的第一表面接觸,以便於接觸銅襯墊;以預定的壓力和預定的溫度向晶圓施加力,直到銅襯墊鍵合,並由此從鍵合的第一和第二晶圓形成堆疊晶圓元件。In a first aspect, the present invention provides a method of forming a stacked wafer component, comprising the steps of: providing a first wafer; forming a plurality of copper pads in a first surface of the first wafer; Formed in the first wafer At least one embedded vertical connector isolated by a copper pad of a wafer; providing a second wafer; forming a plurality of copper pads in the first surface of the second wafer, and arranging the copper pads Positioning a copper pad of the first wafer; forming at least one embedded vertical connector isolated from the copper pad of the second wafer in the second wafer; contacting the first surface of the wafer to facilitate contact with the copper a pad; applying a force to the wafer at a predetermined pressure and a predetermined temperature until the copper pads are bonded, and thereby forming the stacked wafer elements from the bonded first and second wafers.

由此,使得晶圓在襯墊處接觸,並經受一段特定時間的熱和壓力,以獲得襯墊的熱擴散和由此的晶圓。Thereby, the wafer is brought into contact at the liner and subjected to heat and pressure for a specific period of time to obtain thermal diffusion of the liner and thus the wafer.

整合是技術發展的關鍵方面。當單片整合已經有相當的發展時,會到達一個時刻,由於對必須用於單元件中的大範圍不同材料系統的需求,所以限制了進一步發展。本發明提供了多片(polylithic)整合,允許每種材料完成其最適合的任務。通過獲得真正的多片整合,根據本發明製造的元件由於較高速度、密度、可靠性和功耗而提供了增強的性能。Integration is a key aspect of technology development. When monolithic integration has evolved considerably, it will reach a point where further development is limited due to the need for a wide range of different material systems that must be used in the unit. The present invention provides polylithic integration that allows each material to perform its most suitable task. By achieving true multi-chip integration, components fabricated in accordance with the present invention provide enhanced performance due to higher speed, density, reliability, and power consumption.

與其他製造方法相比較,例如多晶片模組(Multi-Chip-Module,MCM)、多晶片封裝(Multi-Chip-Package,MCP)或者系統級封裝(SIP),其中層之間的互連可能限制到幾百或者幾千的晶粒間連接,根據本發明形成的元件能夠高出幾個數量級(百萬的量級)。Compared with other manufacturing methods, such as Multi-Chip-Module (MCM), Multi-Chip-Package (MCP) or System-in-Package (SIP), where interconnection between layers is possible Limiting to a few hundred or several thousand inter-die connections, elements formed in accordance with the present invention can be orders of magnitude higher (on the order of millions).

另外,ULSI設計可以分裂成更小的部分並重新組合以產生更高的產量。通過更高的整合而具有更短的連接,可 以降低RC延遲,導致更低功耗和更高速度。In addition, ULSI designs can be split into smaller parts and recombined to produce higher yields. Shorter connections through higher integration, To reduce RC delay, resulting in lower power consumption and higher speed.

在優選實施例中,可通過阻擋層分隔嵌入垂直連接器和襯底。In a preferred embodiment, the vertical connector and substrate can be embedded by a barrier layer.

在優選實施例中,阻擋層可以包括金屬阻擋層,該金屬阻擋層包括下面的任何一種或者其組合:Ti、TiN、Tix Siy Nz 、Ta、TaN、Tax Siy Nz ,W、WN和WN2 。在另一實施例中,阻擋層可以包括氧化物層。在又一實施例中,阻擋層可以包括氮化物層。In a preferred embodiment, the barrier layer may comprise a metal barrier layer comprising any one of the following or a combination thereof: Ti, TiN, Ti x Si y N z , Ta, TaN, Ta x Si y N z , W , WN and WN 2 . In another embodiment, the barrier layer can include an oxide layer. In yet another embodiment, the barrier layer can include a nitride layer.

在優選實施例中,可在與虛設(dummy)銅襯墊相同平面上放置多個銅襯墊,該多個銅襯墊可電連接兩個連接晶圓以及鍵合目的,而該虛設銅襯墊不電連接兩個連接晶圓且僅用於連接目的。In a preferred embodiment, a plurality of copper pads can be placed on the same plane as the dummy copper pads, the plurality of copper pads electrically connecting the two connection wafers and bonding purposes, and the dummy copper liner The pads do not electrically connect the two connection wafers and are used only for connection purposes.

在優選實施例中,多個銅襯墊可由在相同平面上的兩種以上形狀的鍵合襯墊同時形成。In a preferred embodiment, a plurality of copper pads can be formed simultaneously from two or more shaped bond pads on the same plane.

在優選實施例中,可利用氟基電漿通過乾蝕刻工藝形成該至少一個嵌入垂直連接器。在更優選的實施例中,嵌入垂直連接器可從IMD(金屬間介電層)延伸到Si襯底中。In a preferred embodiment, the at least one embedded vertical connector can be formed by a dry etching process using a fluorine based plasma. In a more preferred embodiment, the embedded vertical connector can extend from the IMD (inter-metal dielectric layer) into the Si substrate.

在優選實施例中,嵌入在Si襯底中的嵌入垂直連接深度可在4-10μm深的範圍中。另外,嵌入垂直連接器的直徑尺寸可在0.2-10μm的範圍。In a preferred embodiment, the embedded vertical connection depth embedded in the Si substrate can be in the range of 4-10 μm deep. In addition, the diameter of the embedded vertical connector can be in the range of 0.2-10 μm.

在優選實施例中,可通過介電阻擋層的PECVD沈積隔離嵌入垂直連接器,所述層可包含非摻雜的SiO2 、四乙基正矽酸鹽(tetraethyl-orthosilicate,TEOS)、SiON、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、氟矽酸鹽玻璃 (fluorosilicate glass,FSG)、SiOC、硼磷矽酸鹽玻璃(borophosphosilicate glass,BPSG)和SiN。In a preferred embodiment, the vertical connector can be embedded by PECVD deposition of a dielectric barrier layer, which layer can comprise undoped SiO 2 , tetraethyl-orthosilicate (TEOS), SiON, Phosphorus silicate glass (PSG), fluorosilicate glass (FSG), SiOC, borophosphosilicate glass (BPSG) and SiN.

在優選實施例中,介電阻擋層的厚度可在0.05μm到0.3μm的範圍中。In a preferred embodiment, the thickness of the dielectric barrier layer can range from 0.05 [mu]m to 0.3 [mu]m.

在優選實施例中,當銅、鎢、鋁和它們的合金用於權利要求1的嵌入垂直連接器時的垂直連接器。In a preferred embodiment, copper, tungsten, aluminum, and alloys thereof are used in the vertical connector of the embedded vertical connector of claim 1.

在優選實施例中,可通過乾蝕刻工藝或者CMP工藝形成垂直連接器的金屬化。In a preferred embodiment, the metallization of the vertical connector can be formed by a dry etch process or a CMP process.

在優選實施例中,可同步形成光刻對準目標,例如步進對準目標。另外,可改變對準目標的尺寸,以具有與垂直連接器的直徑相相容的尺寸。In a preferred embodiment, lithographic alignment targets can be formed simultaneously, such as step alignment targets. Additionally, the size of the alignment target can be varied to have a size that is compatible with the diameter of the vertical connector.

在優選實施例中,可同步形成比垂直連接器相對較大的Si蝕刻終止層。另外,Si蝕刻終止層的尺寸可在1μm到100μm的範圍中。In a preferred embodiment, a relatively large Si etch stop layer is formed that is relatively larger than the vertical connector. In addition, the size of the Si etch stop layer may range from 1 μm to 100 μm.

在優選實施例中,可使用濕法(或者幹法)蝕刻工藝,通過降低介電表面,而形成銅鍵合襯墊表面從介電表面的凸起。另外,可使用BOE(緩衝的氧化物蝕刻劑)用於這種處理。In a preferred embodiment, a wet (or dry) etch process can be used to form a bump of the copper bond pad surface from the dielectric surface by lowering the dielectric surface. In addition, BOE (buffered oxide etchant) can be used for this treatment.

在優選實施例中,可使用乙酸和氟化銨溶液濕法清洗銅表面。另外,可以使用1:1:1比例的乙酸:氟化銨:DI水溶液。另外,可使用1:10:40比例的過氧化氫:乙二胺:DI水溶液作為組合處理。In a preferred embodiment, the copper surface can be wet cleaned using acetic acid and an ammonium fluoride solution. Alternatively, acetic acid:ammonium fluoride:DI aqueous solution can be used in a 1:1:1 ratio. Alternatively, a 1:10:40 ratio of hydrogen peroxide: ethylenediamine: DI aqueous solution can be used as a combination treatment.

在更優選的實施例中,可使用稀釋的乙二胺作為組合處理。另外,可使用BAT(苯三唑)作為組合處理。In a more preferred embodiment, diluted ethylenediamine can be used as a combination treatment. In addition, BAT (benzotriazole) can be used as a combination treatment.

在優選實施例中,可使用氟基電漿以在晶圓表面上面 凸起銅襯墊。另外,在處理之後或者處理過程中,可使用氫電漿或者氮電漿清洗銅的表面。In a preferred embodiment, a fluorine-based plasma can be used to surface the wafer surface. Raised copper pad. Alternatively, the surface of the copper may be cleaned using hydrogen plasma or nitrogen plasma after processing or during processing.

在優選實施例中,可通過研磨、CMP和濕法/乾蝕刻工藝或者其組合而形成堆疊(鍵合)晶圓的外表面的減薄。In a preferred embodiment, the thinning of the outer surface of the stacked (bonded) wafer can be formed by grinding, CMP, and wet/dry etching processes, or a combination thereof.

在優選實施例中,在減薄過程中,可使用嵌入垂直連接器的底表面作為Si蝕刻終止層。In a preferred embodiment, a bottom surface embedded in the vertical connector can be used as the Si etch stop layer during the thinning process.

在優選實施例中,在減薄過程中可使用KOH基、TMAH基、EDP蝕刻溶液通過濕法蝕刻減薄Si。或者,可通過氟基電漿乾蝕刻工藝減薄Si。在另一個替換實施例中,可通過CMP工藝減薄Si。In a preferred embodiment, Si can be thinned by wet etching using a KOH-based, TMAH-based, EDP etching solution during the thinning process. Alternatively, Si can be thinned by a fluorine-based plasma dry etching process. In another alternative embodiment, Si can be thinned by a CMP process.

在優選實施例中,可使用鐳射或者白光源檢測蝕刻終止層,其可能是在垂直連接通孔的底部處的介電層。In a preferred embodiment, the etch stop layer can be detected using a laser or white light source, which may be a dielectric layer at the bottom of the vertical connection via.

在優選實施例中,可使用抛光墊上的電阻測量方法,以檢測蝕刻終止層,其可能是在垂直連接通孔的底部處的介電層。In a preferred embodiment, a resistance measurement method on the polishing pad can be used to detect the etch stop layer, which may be a dielectric layer at the bottom of the vertical connection via.

在優選實施例中,可使用抛光墊上的溫度測量方法,以檢測蝕刻終止層,其可能是在垂直連接通孔的底部處的介電層。In a preferred embodiment, a temperature measurement method on the polishing pad can be used to detect the etch stop layer, which may be a dielectric layer at the bottom of the vertical connection via.

在優選實施例中,在已經檢測到垂直連接通孔的底部之後,可進一步蝕刻Si。另外,進一步蝕刻的Si的厚度可在0.2μm到2μm的範圍。In a preferred embodiment, Si may be further etched after the bottom of the vertical connection via has been detected. In addition, the thickness of Si further etched may range from 0.2 μm to 2 μm.

在優選實施例中,可從大蝕刻終止層獲得蝕刻終止層檢測信號,該蝕刻終止層在垂直連接通孔形成過程中同時形成。In a preferred embodiment, an etch stop layer detection signal can be obtained from the large etch stop layer that is simultaneously formed during vertical connection via formation.

在優選實施例中,可通過介電CMP工藝平面化介電層。可替換地,可通過覆蓋式光阻回蝕工藝(blanket photoresist etch-back process)平面化介電層。In a preferred embodiment, the dielectric layer can be planarized by a dielectric CMP process. Alternatively, the dielectric layer can be planarized by a blanket photoresist etch-back process.

在優選實施例中,提供晶圓的步驟包括通過電漿增強化學汽相沈積形成晶圓。In a preferred embodiment, the step of providing a wafer includes forming a wafer by plasma enhanced chemical vapor deposition.

在優選實施例中,提供晶圓的步驟包括通過SOG(旋塗玻璃)方法形成晶圓,該等晶圓可包括SOG、SiLK(旋塗低k電介質)。In a preferred embodiment, the step of providing a wafer includes forming a wafer by a SOG (Spin On Glass) method, which may include SOG, SiLK (Spin-on Low-k dielectric).

在優選實施例中,還包括步驟:使用常規CVD技術沈積介電層;以及使用CMP工藝處理介電層以提供平面的表面。In a preferred embodiment, the method further includes the steps of: depositing a dielectric layer using conventional CVD techniques; and processing the dielectric layer using a CMP process to provide a planar surface.

圖式簡單說明Simple illustration

相對於描述本發明的可能配置的附圖而進一步描述本發明將是方便的。本發明的其他配置是可能的,因此,不能將附圖的特殊性理解為代替本發明的前面描述的普遍性。It will be convenient to further describe the present invention with respect to the drawings that describe possible configurations of the present invention. Other configurations of the present invention are possible, and therefore, the particularity of the drawings is not to be construed as limiting the generality of the foregoing description of the present invention.

第1a圖是根據本發明第一實施例的CMOS晶圓的正視圖;第1b圖是根據本發明第二實施例的CMOS晶圓的正視圖;第2圖是根據本發明實施例的嵌入垂直連接器的正視圖;第3a圖是第1a圖的CMOS晶圓在平面化之後的正視圖;第3b圖是第3a圖的CMOS晶圓在蝕刻露出垂直連接器 之後的正視圖;第3c圖是根據本發明第三實施例用第3b圖的CMOS晶圓堆疊的第1a圖的CMOS晶圓的正視圖;第4圖是放置銅襯墊之後,用第3b圖的CMOS晶圓堆疊的第1a圖的CMOS晶圓的正視圖;第5圖是堆疊在第4圖的CMOS晶圓上的第1a圖的另一CMOS晶圓的正視圖;第6圖是堆疊在第5圖的CMOS晶圓上的I/O襯墊的正視圖。1a is a front view of a CMOS wafer according to a first embodiment of the present invention; FIG. 1b is a front view of a CMOS wafer according to a second embodiment of the present invention; and FIG. 2 is an embedded vertical according to an embodiment of the present invention Front view of the connector; Figure 3a is a front view of the CMOS wafer of Figure 1a after planarization; Figure 3b is a CMOS wafer of Figure 3a exposed to expose the vertical connector Figure 3c is a front view of the CMOS wafer of Figure 1a stacked with the CMOS wafer of Figure 3b according to the third embodiment of the present invention; and Figure 4 is a third view of the CMOS wafer after the copper pad is placed. FIG. 5 is a front view of another CMOS wafer of FIG. 1a stacked on the CMOS wafer of FIG. 4; FIG. 6 is a front view of the CMOS wafer of FIG. 1A of the CMOS wafer stack; FIG. A front view of the I/O pads stacked on the CMOS wafer of Figure 5.

較佳實施例之詳細說明Detailed description of the preferred embodiment

第1a和1b圖示出了都包括IC分層CMOS工藝晶圓的本發明兩個實施例。IC層15、20已經形成在介電層41、42中,並一起形成在矽襯底40、45上。晶圓5、10的外表面具有嵌入在電介質的表面中的銅襯墊35、38。Figures 1a and 1b illustrate two embodiments of the invention that both include an IC layered CMOS process wafer. The IC layers 15, 20 have been formed in the dielectric layers 41, 42 and are formed together on the germanium substrates 40, 45. The outer surfaces of the wafers 5, 10 have copper pads 35, 38 embedded in the surface of the dielectric.

第1a和1b圖的實施例之間的主要區別點是垂直連接器25、30的佈置。在第1a圖的情況中,在第一IC層46(金屬-1)形成之前,垂直連接器已經嵌入在晶圓5中。第1b圖具有在積體電路層20佈置之後,但是在銅襯墊38佈置之前,嵌入在晶圓10中的垂直連接器30。實際上,本發明不依賴於垂直連接器25、30形成的任何特定位置或者階段,它們可以在任何IC金屬層(例如第1圖的金屬-1到金屬-6)之前佈置。The main difference between the embodiments of Figures 1a and 1b is the arrangement of the vertical connectors 25,30. In the case of Figure 1a, the vertical connector has been embedded in the wafer 5 prior to formation of the first IC layer 46 (metal-1). Figure 1b has a vertical connector 30 embedded in the wafer 10 after the integrated circuit layer 20 is disposed, but before the copper pads 38 are disposed. In fact, the present invention does not rely on any particular location or stage of vertical connector 25, 30 formation, which may be disposed prior to any IC metal layer (e.g., metal-1 to metal-6 of Figure 1).

區別第1a和1b圖的實施例的本發明特徵是垂直連接器 25、30與銅襯墊35、38的連接關係。在第1a圖中,連接是隱藏的,因為從垂直連接器25通過幾個IC層15連接銅襯墊35。可以以任何常規的方式構成IC層15,這些積體電路元件的精確特性和結構對於本領域技術人員是公知的。在第1b圖中,連接是直接的,將垂直連接器30連接到銅襯墊38,是通過使用銅雙鑲嵌工藝同時形成這兩個元件,或者是用兩個步驟,製造連接器30,然後銅襯墊38。A feature of the invention that distinguishes the embodiments of Figures 1a and 1b is a vertical connector 25, 30 and copper pads 35, 38 connection relationship. In Fig. 1a, the connection is hidden because the copper pad 35 is connected from the vertical connector 25 through several IC layers 15. The IC layer 15 can be constructed in any conventional manner, and the precise characteristics and structure of these integrated circuit components are well known to those skilled in the art. In Figure 1b, the connection is straightforward, connecting the vertical connector 30 to the copper pad 38, either by simultaneously forming the two components using a copper dual damascene process, or by making the connector 30 in two steps, and then Copper pad 38.

第2圖示出了根據第1a圖實施例的垂直連接器25的具體圖。Fig. 2 shows a detailed view of the vertical connector 25 according to the embodiment of Fig. 1a.

該實施例示出了嵌入在矽襯底40和介電層42(例如二氧化矽)中的垂直連接器25。應當注意的是,襯底40可以是幾種不同的材料,這是本領域技術人員可以理解的,包括Si、SeGe或者GaAs。該工藝從將通孔蝕刻到介電層42和矽襯底40中開始。接下來在用金屬55填充通孔之前,沈積氮化物層70,然後氧化物層65,然後金屬阻擋層60。This embodiment shows a vertical connector 25 embedded in a germanium substrate 40 and a dielectric layer 42, such as hafnium oxide. It should be noted that the substrate 40 can be of several different materials, as will be understood by those skilled in the art, including Si, SeGe or GaAs. The process begins by etching vias into dielectric layer 42 and germanium substrate 40. Next, a nitride layer 70, then an oxide layer 65, and then a metal barrier layer 60 are deposited before the via holes are filled with the metal 55.

氮化物層70具有雙重功能,首先,充當擴散阻擋層以防止金屬55從通孔擴散到周圍襯底中。它還有第二功能是,在用於減薄堆疊晶圓背面的濕法蝕刻過程中充當蝕刻終止層。氮化物層70的厚度可在0.05到0.1μm的範圍中,並可以是SiN。The nitride layer 70 has a dual function, first acting as a diffusion barrier to prevent diffusion of the metal 55 from the vias into the surrounding substrate. It also has a second function that acts as an etch stop layer during the wet etch process used to thin the backside of the stacked wafer. The nitride layer 70 may have a thickness in the range of 0.05 to 0.1 μm and may be SiN.

氧化物層65充當周圍襯底和垂直連接器之間的電絕緣體,該氧化層可是二氧化矽層,可能在0.05到0.3微米的範圍中。它還有第二功能是,在用於減薄堆疊晶圓背面的乾蝕刻過程中充當蝕刻終止層。The oxide layer 65 acts as an electrical insulator between the surrounding substrate and the vertical connector, which may be a ceria layer, possibly in the range of 0.05 to 0.3 microns. It also has a second function that acts as an etch stop layer during the dry etch process used to thin the backside of the stacked wafer.

金屬擴散阻擋層60在氧化物層65之上,以進一步防止金屬55擴散到晶圓中。優選地,擴散阻擋層60的厚度在200到1000埃的範圍內,並包括金屬,例如Ti、TiN、Tix Siy Nz 、Ta、TaN、Tax Siy Nz ,W、WN和WN2 。它還有第二功能是,在用於減薄堆疊晶圓背面的CMP過程中充當侵蝕終止層。優選地,對於Cu的阻擋層金屬可以是Ta作為連接器導電材料,對於Al或者W導電材料Ti/TiN作為下層。Metal diffusion barrier layer 60 is over oxide layer 65 to further prevent metal 55 from diffusing into the wafer. Preferably, the diffusion barrier layer 60 has a thickness in the range of 200 to 1000 angstroms and includes metals such as Ti, TiN, Ti x Si y N z , Ta, TaN, Ta x Si y N z , W, WN and WN. 2 . It also has a second function that acts as an etch stop layer during the CMP process used to thin the backside of the stacked wafer. Preferably, the barrier metal for Cu may be Ta as a connector conductive material, and for Al or W conductive material Ti/TiN as a lower layer.

然後用金屬55,例如鎢、鋁、銅或者其合金填充通孔,以完成垂直連接器25。通過這種垂直連接器25提供的好處包括非常短的晶圓間互連,對於層到層(晶圓到晶圓的連接性),短於15μm。重要的是,對於隨後在晶圓堆疊的減薄晶圓的反面上的光刻過程,它將提供白光對準目標。垂直連接器的直徑可在1到10μm的範圍中,並進入襯底4-6μm深。The vias are then filled with a metal 55, such as tungsten, aluminum, copper, or alloys thereof to complete the vertical connector 25. The benefits provided by such a vertical connector 25 include very short inter-wafer interconnections, which are less than 15 μm for layer-to-layer (wafer to wafer connectivity). Importantly, it will provide white light to the target for the lithography process on the reverse side of the thinned wafer that is subsequently stacked on the wafer. The diameter of the vertical connector can be in the range of 1 to 10 μm and enter the substrate 4-6 μm deep.

垂直連接器30的形成可具有與第1a圖的實施例以及實際上落在更寬發明內的其他實施例相類似的構建。也可使用傳統的雙鑲嵌工藝將垂直連接器30構建為銅襯墊38的整體部分。The formation of the vertical connector 30 can have a construction similar to the embodiment of Figure 1a and other embodiments that actually fall within the broader invention. The vertical connector 30 can also be constructed as an integral part of the copper pad 38 using a conventional dual damascene process.

參考第3a到3c圖,通過組合兩個晶圓5、75以在介面85使多個銅襯墊90、95接觸而形成堆疊晶圓72。通過使襯墊周圍的相鄰氧化物區(0.03~0.1μm,使用濕法/乾蝕刻)凹進,確保在介面85銅襯墊90、95的接觸。由於預清洗的銅襯墊90、95的露出,所以可獲得銅襯墊的高程度熱內擴散(inter-diffusion),並必定在製造堆疊晶圓72所需的限度內。然後準備銅襯墊用於鍵合,例如,清洗襯墊和周圍表面凹 進處理。優選地,通過用濕法或者乾蝕刻工藝使周圍介電表面凹進,接著用濕法或者乾蝕刻技術清洗處理Cu襯墊表面,可獲得銅鍵合襯墊表面的凸起。然而,BOE(氟化銨、氫氟酸和水的混合物)可同時清洗Cu鍵合襯墊表面並使周圍介電表面凹進,假如周圍介電表面是由SiO2 構成的。Referring to Figures 3a through 3c, stacked wafers 72 are formed by combining two wafers 5, 75 to contact a plurality of copper pads 90, 95 at interface 85. Contact at the interface 85 copper pads 90, 95 is ensured by recessing adjacent oxide regions (0.03 - 0.1 μm, using wet/dry etching) around the pads. Due to the exposure of the pre-cleaned copper pads 90, 95, a high degree of inter-diffusion of the copper pads can be obtained and must be within the limits required to fabricate the stacked wafers 72. A copper liner is then prepared for bonding, for example, a cleaning liner and a peripheral surface recession process. Preferably, the bumps on the surface of the copper bond pad can be obtained by recessing the surrounding dielectric surface by a wet or dry etch process followed by a wet or dry etch process to treat the Cu pad surface. However, BOE (a mixture of ammonium fluoride, hydrofluoric acid and water) can simultaneously clean the surface of the Cu bond liner and recess the surrounding dielectric surface if the surrounding dielectric surface is composed of SiO 2 .

當接觸時,使晶圓經受足夠的壓力和溫度條件,以促使銅襯墊進入熱擴散,並由此在銅襯墊90、95之間的介面85處鍵合晶圓5、75。用於獲得銅熱擴散的條件可以是在無氧(氮、惰性氣體或者真空)的環境中,在300到450℃範圍內的溫度下,在20到60psi範圍內的壓力下,停留5到50分鐘的時間。When in contact, the wafer is subjected to sufficient pressure and temperature conditions to cause the copper liner to enter thermal diffusion and thereby bond the wafers 5, 75 at the interface 85 between the copper pads 90, 95. The conditions for obtaining copper thermal diffusion may be in an oxygen-free (nitrogen, inert gas or vacuum) environment, at a temperature in the range of 300 to 450 ° C, at a pressure in the range of 20 to 60 psi, staying 5 to 50 Minutes of time.

已經獲得介面85處的鍵合後,可通過使需要在其上構建I/O襯墊的底晶圓減薄,而製造兩個晶圓堆疊的元件。可通過粗和細研磨,接著CMP,然後使它經受濕法/乾蝕刻工藝,直到垂直連接器102的底表面100出現在減薄表面,而減薄底晶圓的背表面。由此,通過鍵合晶圓5、75以形成堆疊晶圓72,由於因堆疊的頂晶圓75而增強的堅固性,所以在處理過程中或者後面的處理中,可減薄單獨的晶圓5而沒有所減薄晶圓破裂的風險。如第3a和3b圖所示,使用幹法或者濕法蝕刻工藝使露出的表面100凹進0.2~2μm,以保證在周圍表面103上垂直連接器102的凸起。然後在表面100和103上沈積0.3~2μm厚的SiO2 層81。然後使用標準技術,也就是氧化物CMP或者可選的氧化物回蝕工藝來平面化層81,以保證垂直電連接器102的表面露出。濺射沈積由Ti/TiN 和Al合金構成的I/O襯墊金屬層140。使用露出表面100(連接器102的底部)上可見的對準目標,可使I/O襯墊金屬掩模以高精度對準。最後使用常規方法通過蝕刻工藝限定I/O襯墊金屬。Once the bonding at interface 85 has been obtained, the components of the two wafer stacks can be fabricated by thinning the bottom wafer on which the I/O pads need to be built. The back surface of the bottom wafer can be thinned by coarse and fine grinding followed by CMP followed by a wet/dry etching process until the bottom surface 100 of the vertical connector 102 appears on the thinned surface. Thus, by bonding the wafers 5, 75 to form the stacked wafer 72, the individual wafers can be thinned during processing or later processing due to the increased robustness due to the stacked top wafers 75. 5 There is no risk of thinning the wafer. As shown in Figures 3a and 3b, the exposed surface 100 is recessed by 0.2 to 2 μm using a dry or wet etch process to ensure vertical bumps on the peripheral surface 103 of the connector 102. A layer of SiO 2 81 having a thickness of 0.3 to 2 μm is then deposited on the surfaces 100 and 103. The layer 81 is then planarized using standard techniques, namely oxide CMP or an optional oxide etch back process, to ensure that the surface of the vertical electrical connector 102 is exposed. An I/O pad metal layer 140 composed of Ti/TiN and an Al alloy is sputter deposited. Using the alignment targets visible on the exposed surface 100 (the bottom of the connector 102), the I/O pad metal mask can be aligned with high precision. Finally, the I/O pad metal is defined by an etching process using conventional methods.

為了形成更複雜的堆疊晶圓(3個以及更多),如第4圖所示,在兩晶圓堆疊的頂晶圓的背面進行減薄工藝。已經達到了垂直連接器102的上表面100後,如上所述將Si進一步凹進。0.3~2μm的SiO2 層沈積在凹進的Si表面上,接著進行平面化工藝。然後可利用白光曝光工具來圖案化新表面80,以使用常規單銅鑲嵌工藝步驟最終製成銅襯墊105。在使相鄰氧化物表面80凹進之後,兩晶圓堆疊就可與另一晶圓組合。應當注意的是,銅襯墊可包括用於連接兩個或者多個晶圓元件的電連接襯墊以及與電連接襯墊在相同平面上的虛設襯墊。在該配置中,虛設襯墊促進了鄰近晶圓的鍵合強度。In order to form more complex stacked wafers (three and more), as shown in FIG. 4, a thinning process is performed on the back side of the top wafer of the two wafer stacks. After the upper surface 100 of the vertical connector 102 has been reached, Si is further recessed as described above. A SiO 2 layer of 0.3 to 2 μm is deposited on the surface of the recessed Si, followed by a planarization process. The white surface exposure tool can then be used to pattern the new surface 80 to ultimately form the copper liner 105 using conventional single copper damascene process steps. After the adjacent oxide surface 80 is recessed, the two wafer stacks can be combined with another wafer. It should be noted that the copper pad may include an electrical connection pad for connecting two or more wafer elements and a dummy pad on the same plane as the electrical connection pads. In this configuration, the dummy pads promote bond strength to adjacent wafers.

第5圖示出了增加另一晶圓115以形成更複雜的堆疊晶圓110。如用上述的鍵合步驟,相應的襯墊陣列120、125被對準以形成介面130,因此,當在某溫度下向那裏施加壓力一段特定的停留時間時,襯墊通過熱擴散而鍵合。為了構建更複雜的堆疊晶圓,可以持續該過程,直到已經形成所需的元件。FIG. 5 illustrates the addition of another wafer 115 to form a more complex stacked wafer 110. As with the bonding step described above, the respective pad arrays 120, 125 are aligned to form the interface 130, so that when a certain amount of dwell time is applied thereto at a certain temperature, the pads are bonded by thermal diffusion. . To build a more complex stacked wafer, the process can continue until the desired components have been formed.

在減薄了底晶圓5之後,接著進行如上面參考第3a圖所示形成I/O襯墊的處理工藝步驟,可產生第6圖中的I/O襯墊。對於I/O的背面處理和對於Cu的其他處理包括0.3-2 μm厚的電介質,優選在400C下沈積的PECVD TEOS。在IC製造中,所有的I/O襯墊第一次形成在晶圓的背面。對於IC製造,除去鈍化掩模(因為電路埋藏在包含I/O襯墊的Si表面下面)。After the bottom wafer 5 is thinned, the process steps of forming an I/O liner as described above with reference to FIG. 3a are then performed to produce the I/O liner of FIG. The backside treatment for I/O and other processing for Cu include 0.3-2 A μm thick dielectric, preferably PECVD TEOS deposited at 400C. In IC fabrication, all I/O pads are formed on the back side of the wafer for the first time. For IC fabrication, the passivation mask is removed (since the circuit is buried under the Si surface containing the I/O pads).

本發明的其他特徵可包括對準目標(對於白光和IR對準),其使用嵌入垂直連接器(優選放置在劃線之間)的背面,允許標準光刻機識別賣主推薦的和/或改變的基準。另外,減薄控制可包括在垂直連接器的側壁上的複合材料,所具有的厚度範圍對於SiN在0.05-0.1μm,對於SiO2 在0.05-0.3μm以及對於Ta或者Ti/TiN在0.025-0.1。Other features of the invention may include alignment targets (for white light and IR alignment) that use a backside embedded in a vertical connector (preferably placed between the scribe lines), allowing the standard lithography machine to identify sellers to recommend and/or change Benchmark. In addition, the thinning control may comprise a composite material on the sidewalls of the vertical connector having a thickness ranging from 0.05 to 0.1 μm for SiN, 0.05 to 0.3 μm for SiO 2 and 0.025 to 0.1 for Ta or Ti/TiN. .

5、10、75‧‧‧晶圓5, 10, 75‧‧‧ wafers

81‧‧‧SiO281‧‧‧SiO 2 layer

15、20‧‧‧IC層15, 20‧‧‧IC layer

85‧‧‧介面85‧‧‧ interface

25、30‧‧‧垂直連接器25, 30‧‧‧ vertical connectors

90、95‧‧‧銅襯墊90, 95‧‧‧ copper pad

30‧‧‧連接器30‧‧‧Connector

100‧‧‧底表面100‧‧‧ bottom surface

35、38‧‧‧銅襯墊35, 38‧‧‧ copper pad

100,103‧‧‧表面100,103‧‧‧ surface

40、45‧‧‧矽襯底40, 45‧‧‧矽 substrate

102‧‧‧垂直連接器102‧‧‧Vertical connectors

41、42‧‧‧介電層41, 42‧‧‧ dielectric layer

105‧‧‧銅襯墊105‧‧‧copper pad

55‧‧‧金屬55‧‧‧Metal

115‧‧‧晶圓115‧‧‧ wafer

60‧‧‧金屬阻擋層60‧‧‧Metal barrier

110‧‧‧堆疊晶圓110‧‧‧Stacked wafer

65‧‧‧氧化物層65‧‧‧Oxide layer

120、125‧‧‧襯墊陣列120, 125‧‧‧ spacer array

70‧‧‧沈積氮化物層70‧‧‧ deposited nitride layer

130‧‧‧介面130‧‧‧ interface

72‧‧‧堆疊晶圓72‧‧‧Stacked wafer

140‧‧‧I/O襯墊金屬層140‧‧‧I/O gasket metal layer

第1a圖是根據本發明第一實施例的CMOS晶圓的正視圖;第1b圖是根據本發明第二實施例的CMOS晶圓的正視圖;第2圖是根據本發明實施例的嵌入垂直連接器的正視圖;第3a圖是第1a圖的CMOS晶圓在平面化之後的正視圖;第3b圖是第3a圖的CMOS晶圓在蝕刻露出垂直連接器之後的正視圖;第3c圖是根據本發明第三實施例用第3b圖的CMOS晶圓堆疊的第1a圖的CMOS晶圓的正視圖;第4圖是放置銅襯墊之後,用第3b圖的CMOS晶圓堆疊的第1a圖的CMOS晶圓的正視圖; 第5圖是堆疊在第4圖的CMOS晶圓上的第1a圖的另一CMOS晶圓的正視圖;第6圖是堆疊在第5圖的CMOS晶圓上的I/O襯墊的正視圖。1a is a front view of a CMOS wafer according to a first embodiment of the present invention; FIG. 1b is a front view of a CMOS wafer according to a second embodiment of the present invention; and FIG. 2 is an embedded vertical according to an embodiment of the present invention Front view of the connector; Figure 3a is a front view of the CMOS wafer of Figure 1a after planarization; Figure 3b is a front view of the CMOS wafer of Figure 3a after etching to expose the vertical connector; Figure 3c A front view of a CMOS wafer of FIG. 1a stacked with a CMOS wafer of FIG. 3b according to a third embodiment of the present invention; and FIG. 4 is a stacked view of the CMOS wafer of FIG. 3b after the copper pad is placed. a front view of the CMOS wafer of Figure 1a; Figure 5 is a front elevational view of another CMOS wafer of Figure 1a stacked on the CMOS wafer of Figure 4; and Figure 6 is a front view of the I/O pad stacked on the CMOS wafer of Figure 5. Figure.

5、75‧‧‧晶圓5, 75‧‧‧ wafer

102‧‧‧垂直連接器102‧‧‧Vertical connectors

110‧‧‧堆疊晶圓110‧‧‧Stacked wafer

115‧‧‧晶圓115‧‧‧ wafer

Claims (28)

一種形成一堆疊晶圓元件的方法,包括步驟:提供一第一晶圓;在該第一晶圓的一第一表面中形成多個銅襯墊;在該第一晶圓中形成與該第一晶圓的該等銅襯墊隔離的至少一個嵌入垂直連接器;提供一第二晶圓;在該第二晶圓的一第一表面中形成多個銅襯墊,該等銅襯墊的佈置與該第一晶圓的銅襯墊的位置重合;在該第二晶圓中形成與該第二晶圓的該等銅襯墊隔離的至少一個嵌入垂直連接器;使得該等晶圓的該等第一表面接觸,以便於接觸該等銅襯墊;以預定的壓力和預定的溫度向該等晶圓施加力,直到該等銅襯墊鍵合,並由此從鍵合的第一和第二晶圓形成該堆疊晶圓元件。 A method of forming a stacked wafer component, comprising the steps of: providing a first wafer; forming a plurality of copper pads in a first surface of the first wafer; forming the same in the first wafer Forming at least one embedded vertical connector of the copper pads of a wafer; providing a second wafer; forming a plurality of copper pads in a first surface of the second wafer, the copper pads Arranging a position coincident with a copper pad of the first wafer; forming at least one embedded vertical connector isolated from the copper pads of the second wafer in the second wafer; The first surfaces are in contact to facilitate contact with the copper pads; a force is applied to the wafers at a predetermined pressure and a predetermined temperature until the copper pads are bonded and thereby bonded from the first And forming the stacked wafer component with the second wafer. 如申請專利範圍第1項的方法,其中形成該多個銅襯墊的步驟包括下述的任何一個:利用CMP工藝的單鑲嵌工藝、利用CMP工藝的雙鑲嵌工藝、乾蝕刻工藝、濕法蝕刻工藝或者濕法和乾蝕刻工藝兩者。 The method of claim 1, wherein the step of forming the plurality of copper pads comprises any one of the following: a single damascene process using a CMP process, a dual damascene process using a CMP process, a dry etching process, and a wet etching process. Process or both wet and dry etch processes. 如申請專利範圍第1或者2項的方法,其中形成該多個銅襯墊的步驟之前的步驟是放置一阻擋層以隔離該多個銅襯墊和該晶圓,所述層包括下述的任何一個或者其組合:Ti、TiN、Tix Siy Nz 、Ta、TaN、Tax Siy Nz ,W、WN 和WN2The method of claim 1 or 2, wherein the step of forming the plurality of copper pads is to place a barrier layer to isolate the plurality of copper pads and the wafer, the layer comprising the following Any one or a combination thereof: Ti, TiN, Ti x Si y N z , Ta, TaN, Ta x Si y N z , W, WN and WN 2 . 如申請專利範圍第1項的方法,其中提供所述晶圓的步驟包括通過電漿增強化學汽相沈積形成該等晶圓。 The method of claim 1, wherein the step of providing the wafer comprises forming the wafer by plasma enhanced chemical vapor deposition. 如申請專利範圍第4項的方法,其中該等晶圓包括非摻雜的SiO2 、四乙基正矽酸鹽(TEOS)、SiON、磷矽酸鹽玻璃(PSG)、氟矽酸鹽玻璃(FSG)、SiOC、硼磷矽酸鹽玻璃(BPSG)。The method of claim 4, wherein the wafer comprises undoped SiO 2 , tetraethyl orthosilicate (TEOS), SiON, phosphonite glass (PSG), fluorosilicate glass (FSG), SiOC, borophosphonate glass (BPSG). 如申請專利範圍第1項的方法,其中提供所述晶圓的步驟包括通過SOG(旋塗玻璃)方法形成該等晶圓。 The method of claim 1, wherein the step of providing the wafer comprises forming the wafer by a SOG (Spin On Glass) method. 如申請專利範圍第6項的方法,其中該等晶圓包括SOG、SiLK(旋塗低k電介質)。 The method of claim 6, wherein the wafers comprise SOG, SiLK (spin-coated low-k dielectric). 如申請專利範圍第1項的方法,其中形成至少一個嵌入垂直連接器的步驟是利用氟基電漿通過乾蝕刻工藝而獲得的。 The method of claim 1, wherein the step of forming at least one embedded vertical connector is obtained by a dry etching process using a fluorine-based plasma. 如申請專利範圍第1項的方法,其中該嵌入垂直連接器從金屬間介電層延伸到該晶圓襯底中。 The method of claim 1, wherein the embedded vertical connector extends from the intermetal dielectric layer into the wafer substrate. 如申請專利範圍第9項的方法,其中該垂直連接器嵌入在晶圓中的深度在4到10μm的範圍。 The method of claim 9, wherein the vertical connector is embedded in the wafer to a depth in the range of 4 to 10 μm. 如申請專利範圍第1項的方法,其中該垂直連接器具有0.2-10μm的直徑範圍。 The method of claim 1, wherein the vertical connector has a diameter ranging from 0.2 to 10 μm. 如申請專利範圍第1項的方法,還包括步驟:使用濕法和乾蝕刻工藝的任一種或者兩種,通過降低介電表面,而露出該等銅襯墊,以便於從晶圓表面凸起所述襯墊。 The method of claim 1, further comprising the step of: exposing the copper pads by lowering the dielectric surface by using either or both of a wet process and a dry etching process to facilitate bulging from the surface of the wafer The liner. 如申請專利範圍第12項的方法,其中露出的該等銅襯墊 以0.2μm到2μm的範圍從該表面凸起。 The method of claim 12, wherein the copper pads are exposed It is convex from the surface in a range of 0.2 μm to 2 μm. 如申請專利範圍第1項的方法,其中至少一個嵌入垂直連接器的材料比相應晶圓的材料對CMP有更大的抵抗力。 The method of claim 1, wherein at least one of the materials embedded in the vertical connector is more resistant to CMP than the material of the corresponding wafer. 如申請專利範圍第12或者13項的方法,還包括步驟:使用常規CVD技術沈積一介電層;以及使用CMP工藝處理該介電層以提供一平面的表面。 The method of claim 12 or 13, further comprising the steps of: depositing a dielectric layer using conventional CVD techniques; and treating the dielectric layer using a CMP process to provide a planar surface. 如申請專利範圍第15項的方法,其中該介電層的厚度在1到2μm的範圍。 The method of claim 15, wherein the dielectric layer has a thickness in the range of 1 to 2 μm. 如申請專利範圍第15項的方法,還包括步驟:在該第一晶圓的一第二側上形成I/O襯墊。 The method of claim 15, further comprising the step of forming an I/O liner on a second side of the first wafer. 如申請專利範圍第1項的方法,還包括步驟:研磨該堆疊晶圓元件的外表面,然後實施CMP以露出該第一和該第二晶圓的任一個或者兩者的該嵌入垂直連接器的至少一部分。 The method of claim 1, further comprising the steps of: grinding an outer surface of the stacked wafer component, and then performing CMP to expose the embedded vertical connector of either or both of the first and second wafers At least part of it. 如申請專利範圍第1項的方法,還包括步驟:提供一第三晶圓;在該第三晶圓的一第一表面中形成多個銅襯墊;在該第三晶圓中形成與該第三晶圓的該等銅襯墊隔離的至少一個嵌入垂直連接器;使得該第三晶圓的該第一表面與該堆疊晶圓元件的外表面接觸,以便於接觸該等銅襯墊;在預定的壓力和在預定的溫度下向該第三晶圓和堆疊晶圓元件施加力,直到該等銅襯墊鍵合。 The method of claim 1, further comprising the steps of: providing a third wafer; forming a plurality of copper pads in a first surface of the third wafer; forming the same in the third wafer At least one of the copper pads isolated from the third wafer is embedded in the vertical connector; such that the first surface of the third wafer is in contact with an outer surface of the stacked wafer component to facilitate contact with the copper pads; A force is applied to the third wafer and stacked wafer elements at a predetermined pressure and at a predetermined temperature until the copper pads are bonded. 如申請專利範圍第19項的方法,其中使得該第三晶圓的該第一表面與該堆疊晶圓的外表面接觸包括步驟:使用該垂直連接器的可見背表面作為白光對準基準。 The method of claim 19, wherein the contacting the first surface of the third wafer with the outer surface of the stacked wafer comprises the step of using the visible back surface of the vertical connector as a white light alignment reference. 如申請專利範圍第1項的方法,還包括步驟:使用該垂直連接器的可見背表面作為白光對準基準,印製I/O金屬層;以及通過常規金屬蝕刻工藝界定I/O襯墊以產生電有源的堆疊晶圓元件。 The method of claim 1, further comprising the steps of: printing the I/O metal layer using the visible back surface of the vertical connector as a white light alignment reference; and defining the I/O liner by a conventional metal etching process Produce electrically active stacked wafer components. 如申請專利範圍第1項的方法,其中用於形成任何獨立的嵌入垂直連接器的材料包括鈦、鎢、鋁、銅的任何一種或者其合金。 The method of claim 1, wherein the material used to form any of the individual embedded vertical connectors comprises any one of titanium, tungsten, aluminum, copper, or an alloy thereof. 如申請專利範圍第22項的方法,其中該嵌入垂直連接器通過一阻擋層與該襯底隔離。 The method of claim 22, wherein the embedded vertical connector is isolated from the substrate by a barrier layer. 如申請專利範圍第23項的方法,其中阻擋層包括一金屬阻擋層,該金屬阻擋層包括下述的任何一種或者其組合:Ti、TiN、Tix Siy Nz 、Ta、TaN、Tax Siy Nz ,W、WN和WN2The method of claim 23, wherein the barrier layer comprises a metal barrier layer comprising any one or a combination of the following: Ti, TiN, Ti x Si y N z , Ta, TaN, Ta x Si y N z , W, WN and WN 2 . 如申請專利範圍第23項的方法,其中該阻擋層包括一氧化物層。 The method of claim 23, wherein the barrier layer comprises an oxide layer. 如申請專利範圍第23項的方法,其中該阻擋層包括一氮化物層。 The method of claim 23, wherein the barrier layer comprises a nitride layer. 如申請專利範圍第1項的方法,其中至少一個晶圓包括含有Si、SeGe或者GaAs的襯底。 The method of claim 1, wherein the at least one wafer comprises a substrate comprising Si, SeGe or GaAs. 如申請專利範圍第1項的方法,其中該多個銅襯墊包括用於連接兩個或者更多晶圓元件的電連接襯墊,以及在與該等電連接襯墊相同平面上的虛設襯墊,所述虛設襯墊用於促進相鄰晶圓的鍵合強度。 The method of claim 1, wherein the plurality of copper pads comprises electrical connection pads for connecting two or more wafer elements, and dummy linings on the same plane as the electrical connection pads A pad for promoting bonding strength of adjacent wafers.
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