CN116779454A

CN116779454A - Method for forming package and package structure

Info

Publication number: CN116779454A
Application number: CN202310564005.6A
Authority: CN
Inventors: 蔡昇翰; 邱元升; 许周叡; 林宗澍
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-05-26
Filing date: 2023-05-18
Publication date: 2023-09-19

Abstract

According to an embodiment of the present application, there is provided a method of forming a package, including forming a plurality of dielectric layers over a semiconductor substrate, forming a plurality of metal lines and vias in the plurality of dielectric layers, forming a lower portion of an inner seal ring and a lower portion of an outer seal ring extending into the plurality of dielectric layers, depositing a first dielectric layer over the plurality of metal lines and vias, and etching the first dielectric layer to form an opening through the first dielectric layer. After the first dielectric layer is etched, a top surface of the lower portion of the inner seal ring is exposed and the entire top surface of the lower portion of the outer seal ring is in contact with a bottom surface of the first dielectric layer. An upper portion of the inner seal ring is then formed to extend into the opening and connect a lower portion of the inner seal ring. A second dielectric layer is deposited to cover an upper portion of the inner seal ring. According to other embodiments of the present application, a package structure is also provided.

Description

Method for forming package and package structure

Technical Field

Embodiments of the present application relate to methods of forming packages and package structures.

Background

The packaging of integrated circuits is becoming more and more complex, with more device dies being integrated in the same package to achieve more functionality. For example, integrated system on chip (SoIC) has been developed to include multiple device dies, such as a processor and a memory multi-dimensional dataset, in the same package. The SoIC may include device dies formed using different techniques and have different functions bonded to the same device die, thereby forming a system. This may save manufacturing costs and achieve optimized device performance.

Disclosure of Invention

According to one embodiment of the present application, a method of forming a package is provided that includes forming a first package assembly, the forming the first package assembly including forming a plurality of dielectric layers over a semiconductor substrate; forming a plurality of metal lines and vias in the plurality of dielectric layers; forming a lower portion of the inner seal ring and a lower portion of the outer seal ring extending into the plurality of dielectric layers; depositing a first dielectric layer over the plurality of metal lines and the via holes; and etching the first dielectric layer to form an opening penetrating the first dielectric layer, wherein after etching, a top surface of the lower portion of the inner seal ring is exposed, and an entire topmost surface of the lower portion of the outer seal ring is in contact with a bottom surface of the first dielectric layer; forming an upper portion of the inner seal ring to extend into the opening and to connect a lower portion of the inner seal ring; and depositing a second dielectric layer to cover an upper portion of the inner seal ring.

According to another embodiment of the present application, there is provided a package structure including a device die including a semiconductor substrate; a plurality of dielectric layers over the semiconductor substrate; an inner seal ring. Wherein the inner seal ring comprises a first lower portion in the plurality of dielectric layers; and an upper portion above the first lower portion and the upper portion is connected to the first lower portion. The device die further includes an outer seal ring surrounding the inner seal ring, wherein the outer seal ring includes a second lower portion in the plurality of dielectric layers, and wherein a first topmost surface of the inner seal ring is higher than a second topmost surface of the outer seal ring; and a first dielectric layer over the upper portion of the inner seal ring and contacting the upper portion of the inner seal ring.

According to yet another embodiment of the present application, there is provided a package structure including a device die including a first seal ring including a first lower portion, wherein the first lower portion includes a first damascene structure and includes copper; and an upper portion above the first lower portion and connected to the first lower portion, wherein the first lower portion and the upper portion comprise different metals. And the device die further comprising a second seal ring closer to an edge of the device die than the first seal ring, wherein the second seal ring comprises a second lower portion comprising a second damascene structure and comprising copper, wherein a first topmost surface of the first seal ring is higher than a second topmost surface of the second seal ring. The above structure further includes a package assembly over the device die, and the package assembly is bonded to the device die.

Embodiments of the present application relate to a semiconductor package including a stepped seal ring and a method of forming the same.

Drawings

Aspects of the disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawing figures. It is noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-8 illustrate cross-sectional views at intermediate stages in the formation of a package, according to some embodiments.

Fig. 9 illustrates a cross-sectional view of a package including multiple dies bonded to another device die, in accordance with some embodiments.

Fig. 10 illustrates a cross-sectional view of a package including a plurality of dies bonded to a carrier, in accordance with some embodiments.

Fig. 11-13 illustrate cross-sectional views at intermediate stages in the formation of a device die including a stepped seal ring, in accordance with some embodiments.

Fig. 14-16 illustrate top views of example device dies according to some embodiments.

Fig. 17 and 18 illustrate enlarged views of corner portions of some device dies according to some embodiments.

Fig. 19 illustrates a process flow for forming a package according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, of the different components used to implement the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

A package and method of forming the same are provided according to various embodiments. The package may include a device die that may include an inner seal ring and an outer seal ring surrounding the inner seal ring. The inner seal ring may include a lower portion and an upper portion. The lower portion may comprise copper and the upper portion may comprise aluminum. The outer seal ring may have no aluminum upper portion or may include a narrower aluminum upper portion than the aluminum upper portion of the inner seal ring. Because the outer seal ring has no aluminum ring or a narrow aluminum ring, cracking and/or non-bonding problems at the corners of the device die are reduced when the device die is bonded to another package assembly, such as another device die or carrier. An intermediate stage of forming the package is shown according to some embodiments. Some variations of some embodiments are discussed. Like reference numerals are used to designate like elements throughout the various views and illustrative embodiments. It should be understood that although the formation of the package is used as an example to explain the concept of the embodiments of the present disclosure, the embodiments of the present disclosure may be easily applied to other bonding methods and structures in which the metal pad and the via are bonded to each other.

Fig. 1-8 illustrate cross-sectional views at intermediate stages in the formation of a package according to some embodiments of the present disclosure. The process as shown in fig. 1-8 is also schematically reflected in the process flow 200 as shown in fig. 19.

Fig. 1 illustrates a cross-sectional view in the formation of a package assembly 2, according to some embodiments. The corresponding process is shown as process 202 in process flow 200 as shown in fig. 19. According to some embodiments, the package assembly 2 is a device wafer including active devices 22 (such as transistors and/or diodes) and possibly passive devices (such as capacitors, inductors, resistors, etc.). The package assembly 2 may include a plurality of chips 4 therein, one of the chips 4 being shown. The chip 4 is hereinafter alternatively referred to as a (device) die. According to some embodiments, device die 4 is a logic die, which may be a Central Processing Unit (CPU) die, a Micro Control Unit (MCU) die, an Input Output (IO) die, a baseband (BB) die, an Application Processor (AP) die, or the like. The device die 4 may also be a memory die, such as a Dynamic Random Access Memory (DRAM) die or a Static Random Access Memory (SRAM) die.

According to an alternative embodiment of the present disclosure, the package assembly 2 is a carrier, which may be formed of a homogeneous material, such as silicon. According to some embodiments, the carrier 2 comprises a substrate 20, which may be a silicon substrate. The carrier 2 has no active and passive devices and no wiring metal lines. As shown in fig. 2, there may be several dielectric layers over the substrate 20, where the dielectric layers are used to bond to the device die 104 above. According to yet another alternative embodiment, the package assembly 2 is or includes an interposer wafer. In the discussion that follows, a device wafer is discussed as an example package assembly 2. Embodiments of the present disclosure may also be applied to other types of package components, such as interposer wafers.

According to some embodiments, wafer 2 includes a semiconductor substrate 20 and components formed at a top surface of semiconductor substrate 20. The semiconductor substrate 20 may be formed of crystalline silicon, crystalline germanium, crystalline silicon germanium, or the like. The semiconductor substrate 20 may also be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Shallow Trench Isolation (STI) regions (not shown) may be formed in the semiconductor substrate 20 to isolate active regions in the semiconductor substrate 20. Although not shown, a through-hole may (or may not) be formed to extend into the semiconductor substrate 20, and the through-hole is used to electrically interconnect components on the opposite side of the wafer 2.

According to some embodiments, wafer 2 includes integrated circuit devices 22 formed on a top surface of semiconductor substrate 20. Example integrated circuit devices 22 may include Complementary Metal Oxide Semiconductor (CMOS) transistors, resistors, capacitors, diodes, and/or the like. Details of integrated circuit device 22 are not shown herein. According to an alternative embodiment, wafer 2 is used to form an interposer without active and passive devices.

An interlayer dielectric (ILD) 24 is formed over the semiconductor substrate 20 and fills spaces between gate stacks of transistors (not shown) in the integrated circuit device 22. According to some embodiments, ILD 24 is formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), fluorine doped silicate glass (FSG), silicon oxide, or the like. ILD 24 may be formed using spin-on, flowable Chemical Vapor Deposition (FCVD), chemical Vapor Deposition (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), low Pressure Chemical Vapor Deposition (LPCVD), and the like.

Contact plugs 28 are formed in ILD 24 and contact plugs 28 are used to electrically connect integrated circuit device 22 to overlying metal lines 34 and vias 36. According to some embodiments, the contact plug 28 is formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and/or multilayers thereof. The formation of the contact plug 28 may include forming a contact opening in the ILD 24, filling a conductive material into the contact opening, and performing a planarization, such as a Chemical Mechanical Polishing (CMP) process, to level the top surface 28 of the contact plug with the top surface of the ILD 24.

An interconnect structure 30 is formed over ILD 24 and contact plug 28. Interconnect structure 30 includes a dielectric layer 32 and metal lines 34 and vias 36 formed in dielectric layer 32. The dielectric layer 32 is also referred to interchangeably as an inter-metal dielectric (IMD) layer 32 hereinafter. According to some embodiments, at least the lower dielectric layer 32 is formed of a low-k dielectric material having a dielectric constant (k value) of less than about 3.5 or about 3.0. Dielectric layer 32 may be formed of a carbon-containing low-k dielectric material, hydrogen Silsesquioxane (HSQ), methyl Silsesquioxane (MSQ), or the like. According to alternative embodiments of the present disclosure, some or all of dielectric layer 32 is formed of a non-low-k dielectric material, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and the like. An etch stop layer (not shown), which may be formed of silicon carbide, silicon nitride, aluminum oxide, aluminum nitride, or the like, or a plurality of layers thereof, is formed between IMD layers 32, and is not shown for simplicity.

Metal lines 34 and vias 36 are formed in dielectric layer 32. The metal lines 34 at the same level are hereinafter collectively referred to as a metal layer. According to some embodiments, interconnect structure 30 includes a plurality of metal layers interconnected by vias 36. Metal lines 34 and vias 36 are formed by a single damascene and/or dual damascene process. Metal lines 34 and vias 36 may include diffusion barriers and copper-containing metal material over the respective diffusion barriers. The diffusion barrier layer may include titanium, titanium nitride, tantalum nitride, and the like.

The metal lines 34 include metal lines/pads 34A, which are sometimes referred to as top metal lines. The top metal lines/pads 34A are also collectively referred to as a top metal layer. The corresponding dielectric layer 32A may be formed of a non-low-k dielectric material such as Undoped Silicate Glass (USG), silicon oxide, silicon nitride, or the like. Dielectric layer 32A may also be formed of a low-k dielectric material, which may be selected from similar candidate materials for underlying IMD layer 32.

According to some embodiments, dielectric layer 38, dielectric layer 40, and dielectric layer 42 are formed over the top metal layer. Dielectric layer 38 and dielectric layer 42 may be formed of silicon oxide, silicon oxynitride, silicon oxycarbide, or the like. The dielectric layer 40 is formed of a dielectric material different from that of the dielectric layer 42, and may be formed of silicon nitride, aluminum oxide, or the like. According to some embodiments, dielectric layer 42 is formed using High Density Plasma Chemical Vapor Deposition (HDPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), atomic Layer Deposition (ALD), or the like.

As also shown in fig. 1, a via 44 and a bond pad 46 are formed. According to some embodiments, the formation process of via 44 and bond pad 46 includes etching dielectric layer 42, dielectric layer 40, and dielectric layer 38 to form trenches and via openings, filling the trenches and via openings with a conformal barrier layer and a metallic material, and performing a planarization process, such as a Chemical Mechanical Polishing (CMP) process or a mechanical grinding process, to remove excess portions of the barrier layer and the metallic material. The barrier layer and the remainder of the metal material are the via 44 and the bond pad 46. According to some embodiments, the barrier layer comprises Ti, tiN, ta, taN, or the like. The metallic material may include copper.

Fig. 11-13 illustrate intermediate stages in the formation of a wafer 100 according to some embodiments. In fig. 11, the lower part of the sealing ring has been formed. The corresponding process is shown as process 204 in process flow 200 as shown in fig. 19. Wafer 100 includes device die 104 therein, device die 104 to be bonded to wafer 2. According to some embodiments, device die 104 is a logic die, which may be a CPU die, MCU die, IO die, baseband die, or AP die. The device die 104 may also be a memory die, package, interposer, or the like.

Wafer 100 includes a semiconductor substrate 120, which may be a silicon substrate. A Through Silicon Via (TSV) 126, sometimes referred to as a semiconductor via or through-hole, is formed to extend from the top surface of the semiconductor substrate 120 to an intermediate level between the top and bottom surfaces of the semiconductor substrate 120. TSVs 126 are used to connect devices and metal lines formed on the front side (top side shown) of semiconductor substrate 120 to the back side in the resulting package.

According to some embodiments, integrated circuit device 122 is formed at a surface of semiconductor substrate 120, and integrated circuit device 122 may include circuit devices such as transistors, diodes, and the like. ILD 124 is formed over substrate 120. Contact plugs 128 are formed to penetrate ILD 124 and may be electrically connected to integrated circuit device 122. Interconnect structure 130 may include a dielectric layer 132, metal lines 134, and vias 136. The materials, structures, and formation processes of the components in wafer 100 may be the same as the corresponding components in interconnect structure 30 (fig. 1). Accordingly, these details may not be repeated here. According to some embodiments, the metal lines 134 and vias 136 may be formed by a damascene process, and may include a conformal barrier layer (such as a TiN barrier layer) and a fill metal on the barrier layer. The filler metal may be formed from or comprise, for example, greater than about 99 atomic percent copper. In addition, the metal lines 134 and the vias 136 may be free of aluminum. Dielectric layer 132 may comprise a low-k dielectric material, such as a carbon-containing dielectric material.

Next, referring to fig. 12, a passivation layer 150 (sometimes referred to as passivation-1 or blunt-1) is formed over the interconnect structure 130. According to some embodiments, passivation layer 150 is formed of a non-low k and dense dielectric material having a dielectric constant equal to or greater than that of silicon oxide. Passivation layer 150 may be formed of or include an inorganic dielectric material, which may include an optional dielectric materialFrom, but not limited to, silicon nitride (SiN), silicon oxide (SiO ₂ ) Silicon oxynitride (SiON), silicon oxycarbide (SiOC), and the like, combinations thereof, and/or multilayers thereof.

As further shown in fig. 12, metal features 158 and 154U are formed and include some wire/pad portions over passivation layer 150 and some via portions extending into passivation layer 150 to connect to underlying features, such as metal wire/pad 134. Metal part 156U is also shown as a dashed line, which indicates that metal part 156U may or may not be formed. Metal part 154U and metal part 156U are upper portions of the seal ring. The corresponding process is shown as process 206 in process flow 200 as shown in fig. 19.

According to some embodiments, metal feature 158 and metal feature 154U (and 156U if formed) are formed of a material different from the material of metal lines/pads 134 and vias 136. The material of metal part 158 and metal part 154U may also be different from the material of bond pad 164 (fig. 13) above. Accordingly, metal features 158 and 154U (and 156U if formed) have Coefficients of Thermal Expansion (CTE) that are different from those of underlying metal lines/pads 134 and vias 136 and those of overlying bond pads 164.

According to some embodiments, metal part 158 and metal part 154U may comprise aluminum, and may be formed of aluminum copper or aluminum without copper therein. Assuming that metal line/pad 134 and bond pad 164 have a first aluminum atomic percent AlAP1, the first aluminum atomic percent AlAP1 may be zero or a smaller value, e.g., less than about 1%, metal feature 158 and metal feature 154U may have a second aluminum atomic percent AlAP2 that is greater than the first aluminum atomic percent AlAP 1.

According to some embodiments, the second aluminum atomic percent AlAP2 in metal part 158 and metal part 154U may be greater than about 30%, and may be in a range between about 30% and about 90%. Further, the difference (AlAP 2-AlAP 1) may be greater than about 20%, 80% or more. Throughout the description, the metal part 158 and the metal part 154U are alternatively referred to as an aluminum pad 158 and an aluminum upper seal ring portion 154U.

Metal feature 158 and metal feature 154U (and 156U if formed) are formed in a common formation process, which may include etching passivation layer 150 to form via openings (occupied by via portions of metal feature 158, metal feature 154U and metal feature 156U). Thus, the top surface of the underlying metal line/pad 134 is exposed through the via opening in the passivation layer 150.

According to some embodiments, metal feature 158, metal feature 154U, and metal feature 156U are formed by depositing a blanket metal material, such as aluminum or aluminum copper, that includes portions that extend into the via openings, followed by a photolithographic process to etch unwanted portions, leaving metal feature 158, metal feature 154U, and metal feature 156U.

According to an alternative embodiment, the formation process of metal feature 158, metal feature 154U, and metal feature 156U includes, after forming the via openings, depositing a metal seed layer (not shown) that extends into the openings in passivation layer 150, forming a patterned plating mask (not shown), and plating a metal material (discussed above, and which may include aluminum) into the openings in the patterned plating mask. The patterned plating mask may then be removed, followed by etching of exposed portions of the metal seed layer that were previously covered by the patterned plating mask. The remaining portion of the metallization material and the metal seed layer thus collectively form metal feature 158, metal feature 154U, and metal feature 156U.

Each of the device dies 104 thus includes an inner seal ring 154 and an outer seal ring 156 surrounding the inner seal ring 154. The inner seal ring 154 and the outer seal ring 156 may be electrically floating, electrically grounded, or may be electrically connected to the substrate 120. Although not shown, there may (or may not) be additional inner seal rings surrounded by inner seal ring 154. Furthermore, if there is more than one additional seal ring, each of the outer ones of the additional seal rings surrounds a corresponding inner one of the additional seal rings. Each of the additional seal rings on the inner side of the inner seal ring 154 will also include an upper portion that is formed simultaneously with the metal part 158 and the metal part 154U.

The inner seal ring 154 includes a lower seal ring portion 154L and an upper seal ring portion 154U. The outer seal ring 156 includes a lower seal ring portion 156L. According to some embodiments, when forming metal part 158 and metal part 154U, no seal ring portion is formed directly above lower seal ring portion 156L. Thus, the topmost end of the outer seal ring 156 is lower than the topmost end of the inner seal ring 154. The topmost surface of the outer seal ring 156 may be in contact with the bottom surface of the passivation layer 150. Since the inner seal ring 154 is higher than the outer seal ring 156 according to these embodiments, the seal rings 154 and 156 are referred to as stepped seal rings throughout the description.

According to an alternative embodiment, metal part 156U is also formed as a top portion of seal ring 156 in the same process used to form metal part 158 and metal part 154U. Thus, the topmost end of the outer seal ring 156 is at the same level as the topmost end of the inner seal ring 154. Thus, the topmost surface of the outer seal ring 156 may be in contact with a bottom surface of a subsequently formed dielectric layer, such as dielectric layer 160 or passivation layer 152 (fig. 13.) according to these embodiments, the upper seal ring portion 156U may be designed to be narrower than the upper seal ring portion 154U, and/or may have some corner portions where the upper seal ring portion 156U is not formed (as shown in fig. 16), as will be discussed in detail in subsequent paragraphs.

Referring again to fig. 12, each of the seal ring 154 and the seal ring 156 includes respective portions of the contact plug 128, the metal line 134, and the via 136. The respective contact plugs 128, metal lines 134 and vias 136 in the seal ring are formed simultaneously with and share the same forming process as the respective contact plugs 128, metal lines 134 and vias 136 for electrical connection. Each of the contact plugs 128, metal lines 134, and vias 136 in the seal rings 154 and 156 may be physically connected with upper and lower ones of these components to form an integrated seal ring. Each of the contact plugs 128, the metal lines 134, and the through holes 136 in the seal rings 154 and 156 may form a complete ring without breaking when viewed from the top.

According to some embodiments, the contact plugs 128 in the seal rings 154 and 156 are electrically connected to the semiconductor substrate 120. There may (or may not) be a silicide region between the respective contact plug 128 and the semiconductor substrate 120 and physically connect the respective contact plug 128 and the semiconductor substrate 120. According to an alternative embodiment, the contact plugs 128 in the seal rings 154 and 156 are in physical contact with the semiconductor substrate 120. According to yet another alternative embodiment, the contact plugs 128 in the seal rings 154 and 156 are spaced apart from the semiconductor substrate 120 by a dielectric layer such as a contact etch stop layer (below the ILD 124, not shown), the ILD 124, and/or the like.

Next, referring to fig. 13, a passivation layer 152 is formed over the passivation layer 150. According to some embodiments, as shown in fig. 13, passivation layer 152 has a top surface that is coplanar with the top surfaces of metal features 158, 154U, and 156U. According to an alternative embodiment, passivation layer 152 is formed as a conformal layer on sidewalls of metal feature 158 and seal ring 154 and seal ring 156 and covering top surfaces of metal feature 158 and seal ring 154 and seal ring 156. According to some embodiments, passivation layer 152 is formed of or includes an inorganic dielectric material that may include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, and the like, combinations thereof, and/or multilayers thereof. The material of the passivation layer 152 may be the same as or different from the material of the passivation layer 150. The deposition process may be performed by a conformal deposition process such as ALD, CVD, or the like.

Dielectric layer 160 and dielectric layer 161 may then be formed. The dielectric layer 161 may be a bonding layer and may be formed of or include a silicon-containing dielectric material, which may be formed of or include silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon nitride, or the like. According to some embodiments, dielectric layer 160 is formed of a dielectric material that is different from the dielectric material of dielectric layer 161 and may act as an etch stop layer in the etching of dielectric layer 161. The dielectric layer 160 may also be formed of or include silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, aluminum nitride, or the like, or a plurality of layers thereof. According to some embodiments, the topmost surface of the inner seal ring 154 is lower than the bottom surface of the dielectric layer 160 and may be in physical contact with the bottom surface of the dielectric layer 160. According to an alternative embodiment, the topmost surface of the inner seal ring 154 may be in physical contact with the bottom surface of the passivation layer 152, the passivation layer 152 conformally covering the inner seal ring 154.

According to some embodiments in which hybrid bonding is to be performed, bond pads 164 are formed in dielectric layer 161 and dielectric layer 160. The corresponding process is shown as process 208 in process flow 200 as shown in fig. 19. According to an alternative embodiment in which fusion bonding is to be performed, the bond pads 164 are not formed. The formation of bond pad 164 includes etching dielectric layer 160 and dielectric layer 161 to form an opening, exposing metal feature 158 through the opening, filling the opening with a conductive material, and performing a planarization process to remove an excess portion of the conductive material above the top surface of dielectric layer 161.

Each of the bond pads 164 may also include a conformal conductive barrier layer (formed of Ti, tiN, ta, taN, etc.) and a metal fill material over the conductive barrier layer. According to some embodiments, the metal fill material may be formed of or include copper, and may be free or substantially free of aluminum. For example, the atomic percent of copper in the metal fill material may be greater than about 99%. The metal fill material of bond pad 164 may also be the same as the metal fill material of metal line/pad 134.

In a subsequent process, the wafer 100 is singulated, e.g., sawed along scribe lines 166 to form discrete package assemblies 104 or package assemblies 104', which may be device die. The corresponding process is shown as process 210 in process flow 200 as shown in fig. 19. When the bond pads 164 are formed, the corresponding package assembly is denoted as package assembly 104, as shown in fig. 2. The corresponding package assembly is shown as package assembly 104' when bond pads 164 are not formed, as shown in fig. 2. Throughout the description, the package assembly 104 and the package assembly 104' are referred to as package assemblies 104/104' to indicate that they may be package assemblies 104 or 104'. In the discussion that follows, the package assembly 104/104' is also referred to as a device die 104/104', and the package assembly 104/104' may also be an interposer, package substrate, package, or the like, according to some example embodiments.

Referring back to fig. 2, the device die 104 is bonded to the device die 4 by hybrid bonding. The corresponding process is shown as process 212 in process flow 200 as shown in fig. 19. The bond pad 46 is bonded to the bond pad 164 by a metal-to-metal bond, as the metals (such as copper) in the bond pad 46 and the bond pad 164 interdiffuse to bond them together. Dielectric layer 42 is bonded to dielectric layer 161 by fusion bonding, resulting in the creation of Si-O-Si bonds.

According to some embodiments, device die 104' is also bonded to device die 4 according to some embodiments. The device die 104' may have a similar structure as the device die 104 except that no bond pads are formed in the corresponding dielectric layer 161. Thus, the dielectric layer 42 is bonded to the dielectric layer 161 using fusion bonding. The device die 104' may have the same, similar, or different circuitry as the device die 104. The semiconductor substrate and TSVs in device die 104' are denoted as semiconductor substrate 120' and TSV 126', respectively.

Referring to fig. 3, after the bonding process, a back-grinding process may be performed to thin the device die 104 and the device die 104', for example to a thickness between about 15 μm and about 30 μm, according to some embodiments. By thinning the device die 104 and the device die 104', the aspect ratio of the gap between the device die 104 and the device die 104' is reduced to perform gap filling. Otherwise, gap filling may be difficult due to the high aspect ratio of the gap. After back-grinding, TSVs 126 of device die 104 and TSVs 126 'of device die 104' may be exposed. Alternatively, TSVs 126 and 126 'are not exposed at this time, and back grinding is stopped when there is still a thin layer of substrate covering TSVs 126 and 126'. According to these embodiments, TSVs 126 and 126' may be exposed when the gap-fill layer is planarized, as shown in fig. 5. According to other embodiments where the aspect ratio of the gap is not too high, back grinding is skipped.

Fig. 4 illustrates the deposition of a gap-fill layer that includes a dielectric layer 52 and an underlying etch stop layer 50. The corresponding process is shown as process 214 in process flow 200 as shown in fig. 19. Etch stop layer 50 is formed of a dielectric material that has good adhesion to the sidewalls of device die 104 and device die 104' and the top surface of dielectric layer 42. According to some embodiments, the etch stop layer 50 is formed of a nitride-containing material, such as silicon nitride. The etch stop layer 50 may be formed to be co-formed. Deposition may include conformal deposition methods such as ALD or Chemical Vapor Deposition (CVD).

The dielectric layer 52 is formed of a material different from that of the etch stop layer 50. According to some embodiments, dielectric layer 52 is formed of silicon oxide, and other dielectric materials such as silicon carbide, silicon oxynitride, silicon oxycarbonitride, PSG, BSG, BPSG, and the like may also be used. Dielectric layer 52 may be formed using CVD, HDPCVD, flowable CVD, spin coating, or the like.

Next, a planarization process, such as a CMP process or a mechanical polishing process, is performed to remove excess portions of the gap-fill dielectric layer 52 and the etch stop layer 50, thereby exposing the device die 104 and the device die 104'. In addition, TSVs 126 and 126' are exposed. The remaining portions of dielectric layer 52 and etch stop layer 50 are collectively referred to as (gap-fill) isolation regions 54. The resulting structure is shown in FIG. 5.

Next, dielectric isolation layer 62 is formed on the back surfaces of semiconductor substrate 120 and semiconductor substrate 120 'of device die 104 and device die 104', respectively. The forming process may include recessing the semiconductor substrate 120 and the semiconductor substrate 120' such that top portions of the TSVs 126 and 126' protrude above the recessed semiconductor substrate 120 and the semiconductor substrate 120', respectively. A dielectric material, such as silicon oxide, may then be filled into the recess, followed by a planarization process to remove excess portions of the dielectric material, thus forming dielectric layer 62, and TSVs 126 and 126' are exposed through dielectric layer 62.

Fig. 5-8 further illustrate the formation of RDLs, vias, metal pads, PPIs, under Bump Metals (UBMs), and electrical connectors. The corresponding process is shown as process 216 in process flow 200 as shown in fig. 19. With further reference to fig. 5, redistribution lines (RDLs) 64 and dielectric layers 66 are formed. According to some embodiments, the dielectric layer 66 is formed of an oxide such as silicon oxide, a nitride such as silicon nitride, or the like. RDL 64 may be formed using a damascene process.

According to some embodiments, more device dies are bonded over device die 104 and device die 104', as schematically illustrated in fig. 9. According to alternative embodiments, no more die are bonded over device die 104 and device die 104'. Fig. 6 illustrates the formation of an electrical connection structure over the device die 104 and the device die 104', which may include a passivation layer, a metal pad, and an overlying dielectric layer. A passivation layer 68 (sometimes referred to as passivation-1) is formed over dielectric layer 66 and a via 70 is formed in passivation layer 68 to electrically connect to RDL 64. A metal pad 72 is formed over passivation layer 68 and electrically connected to RDL 64 through via 70. The metal pad 72 may be an aluminum pad or an aluminum copper pad, and other metal materials may be used.

As also shown in fig. 6, a passivation layer 76 (sometimes referred to as passivation-2) is formed over passivation layer 68. Each of passivation layer 68 and passivation layer 76 may be a single layer or a composite layer and may be formed of a non-porous material. According to some embodiments, each of passivation layer 68 and passivation layer 76 may be a composite layer including a silicon oxide layer (not separately shown) and a silicon nitride layer (not separately shown) over the silicon oxide layer. Passivation layers 68 and 76 may also be formed of other non-porous dielectric materials such as Undoped Silicate Glass (USG), silicon oxynitride, and the like.

Next, passivation layer 76 is patterned such that portions of metal pad 72 are exposed through openings in passivation layer 76. Some of the remaining portion of passivation layer 76 covers the edge portion of metal pad 72. A polymer layer 78 is then formed and then patterned to expose the metal pads 72. The polymer layer 78 may be formed of polyimide, polybenzoxazole (PBO), or the like.

Referring to fig. 7, a Post Passivation Interconnect (PPI) 80 is formed. The forming process may include forming a metal seed layer and patterning a mask layer (not shown) over the metal seed layer, and plating the PPI 80 in the patterned mask layer. The patterned mask layer and portions of the metal seed layer that overlap the patterned mask layer are then removed in an etching process. Then, the polymer layer 82 is formed, and the polymer layer 82 may be formed of PBO, polyimide, or the like.

Referring to fig. 8, UBM 84 is formed. UBM 84 extends into polymer layer 82 to connect to PPI 80. An electrical connector 86 is also formed and may include a solder area, a metal post, or the like. Thereby forming reconstituted wafer 90. The reconstituted wafer 90 may be singulated in a sawing process to form discrete packages 90'. The corresponding process is shown as process 218 in process flow 200 as shown in fig. 19.

Fig. 9 shows a package 90' according to an alternative embodiment. These embodiments are similar to the embodiment shown in fig. 8, except that more layers of device die 88 are bonded over device die 104, device die 104', and under the electrical connection structure. Details of device die 88 (schematically represented in fig. 9) may be found with reference to device die 104/104' shown in fig. 10.

Fig. 10 shows a package 90' according to an alternative embodiment. These embodiments are similar to the embodiment shown in fig. 9, except that the first tier devices 104 'are bonded to the carrier 4' instead of on the device die (or device wafer). The engagement structure is in the frame 89. According to some embodiments, the carrier 4' comprises a silicon substrate 20' formed of a homogeneous material, devices, such as active devices and passive devices, not being formed in the carrier 4 '. A dielectric layer 42' is formed at the top surface of carrier 4' and is used to bond to dielectric layer 161 in device die 104 '. The device die 104' has no bond pads at its bottom surface and the bonding of the device die 104' to the carrier 4' is by fusion bonding. Above the device die 104', there may be one or more layers of device die 104 and/or device die 104' bonded. Electrical connections (not shown) may be made over the top layer of the device die 104/104'.

Fig. 14, 15, and 16 illustrate top views of device die 104 (or 104') according to some embodiments. Each device die 104/104' may include an inner seal ring 154 and an outer seal ring 156 surrounding the inner seal ring 154. Each of the inner seal ring 154 and the outer seal ring 156 is formed as a complete ring (with no breaks therein) comprising four portions, each portion being adjacent and parallel to one of the respective edges of the device die 104/104'. In the following discussion, device die 104 may be discussed, but the discussion also applies to device die 104'.

According to some embodiments, the device die 104 has edges 104E and corners 104C, as labeled in fig. 14. In order to visually distinguish the upper seal ring portion 154U and the upper seal ring portion 156U from the lower seal ring portion 154L and the lower seal ring portion 156L, the upper seal ring portion 154U and the upper seal ring portion 156U are drawn narrower than the respective lower seal ring portion 154L and lower seal ring portion 156L, whereas in actual construction, the width W1 (fig. 14) of the lower seal ring portion 154L may be smaller, equal to, or larger than the width W2 of the respective upper seal ring portion 154U. Each sealing ring 154 may include four edge portions 154E that are parallel to the nearest edge 104E, and each sealing ring 156 may include four edge portions 156E that are parallel to the nearest edge 104E. Seal ring 154 and seal ring 156 may also include corner portions 154C and 156C, respectively, corner portions 154C and 156C interconnecting adjacent edge portions 154E and interconnecting adjacent edge portions 156E. Corner portions 154C and 156C, also referred to as chamfer portions, may form 120 degree angles with respective edge portions/sections 154E and 156E.

According to some embodiments, there may be additional sealing rings surrounded by the inner sealing ring 154, as described above. When forming the additional seal rings, each of the additional seal rings will also have both a lower portion and an upper portion, the lower portion extending into the same dielectric layer as lower portion 154L, and the upper portion extending into the same dielectric layer as upper seal ring portion 154U.

According to some embodiments, the width W4 of the upper seal ring portion 156U may be in a range between about 0 μm and about 25 μm, where 0 μm means that the upper portion 156U is not formed. The width W3 of the lower seal ring portion 156L may be in a range between about 0.1 μm and about 25 μm. The width W1 of the lower seal ring portion 154L and the width W2 of the upper seal ring portion 154U may be in a range between about 0.2 μm and about 25 μm. The width W3 may be smaller than the width W1. According to some embodiments, the ratio W3/W1 may be less than about 0.5.

As shown in fig. 14, the inner seal ring 154 includes both a lower portion 154L and an upper seal ring portion 154U, each being a complete ring. The outer seal ring 156 has a lower portion 156L and does not have an upper portion 156U. The upper seal ring portion 154U and the upper seal ring portion 156U are formed of a material different from that of the lower seal ring portion 154L and the lower seal ring portion 156L, and the upper seal ring portion 154U and the upper seal ring portion 156U have Coefficients of Thermal Expansion (CTE) different from CTE of the lower seal ring portion 154L and the lower seal ring portion 156L. Thus, in the bonding of the device die 104 and the device die 104' involving the heat treatment, stress is generated near the interface between the upper and lower portions of the seal ring. The stress at the corner portions of the seal ring near the corners 104C of the respective device die 104 (and 104') is particularly high. Stress may cause non-bonding problems in corner regions 92 (fig. 8) and cracking of gap-fill region 54 (fig. 8). Furthermore, the outer seal ring 156 is more prone to causing non-bonding and cracking problems than the inner seal ring 154. Thus, by not forming the upper seal ring portion 156U for the outer seal ring 156, stress can be reduced. Since the inner seal ring 154 is farther from the edges and corners of the device die 104/104', it has less effect on stress, and thus the inner seal ring 154 may form an upper seal ring portion 154U.

Fig. 15 illustrates a top view of a device die 104/104' according to an alternative embodiment. These embodiments are similar to the embodiment shown in fig. 14, except that the outer seal ring 156 also includes both a lower seal ring portion 156L and an upper seal ring portion 156U, each being a complete ring. Further, the ratio W4/W2 may be less than about 0.5, and may be in a range between 0 and about 0.5, or in a range between 0 and about 0.25. This means that the upper seal ring portion 156U is at least narrower than half of the upper seal ring portion 154U, or may not be formed. Reducing the width of the upper seal ring portion 156U may reduce stress due to CTE mismatch between the upper seal ring portion 156U and the lower seal ring portion 156L.

Fig. 16 illustrates a top view of a device die 104/104' according to an alternative embodiment. These embodiments are similar to the embodiment shown in fig. 15, except that the outer seal ring 156 includes an edge portion and does not include a corner portion. Thus, the upper seal ring portion 156U has a break, is an incomplete ring. Since the stress is highest at the corners of the device die 104/104 'and lower at the edges of the device die 104/104', removing the corner portions of the upper seal ring portion 156U may effectively reduce the stress while the edge portions of the upper seal ring portion 156U may still function to prevent a substantial portion of moisture penetration.

With further reference to fig. 14, 15, and 16, the device die 104/104' has corner regions, one of which is labeled as corner region 94 in fig. 14 as an example. Corner region 94 includes circuit clearance region 95. No integrated circuit devices are formed in the circuit clearance region 95 and no wiring metal lines may be formed therein. However, around the circuit clearance area 95, there is an inner seal ring 154 and an aluminum pad 158. This results in significant differences in the density of the aluminum pads/components, so the stresses in these areas are high and non-bonding and cracking problems may occur. Accordingly, as shown in fig. 17 and 18, some dummy conductive features 158' are added to the circuit gap region 95 to reduce density differences and reduce stress.

Fig. 17 and 18 show an enlarged view of region 94 of fig. 14, 15 and 16, wherein some details are shown, which are not shown in fig. 14, 15 and 16. Referring to fig. 17, a plurality of dummy conductive features 158' are formed in the circuit clearance region 95. The dummy conductive feature 158' is formed simultaneously with the formation of the conductive feature 158 and the upper seal ring portion 154U and the upper seal ring portion 156U (if formed). According to some embodiments, the dummy conductive feature 158' has a width W5 and a length L5 in a range between about 3 μm and about 20 μm. The length L5 and width W5 may also be less than the lateral dimensions of the conductive member 158 (which may be an aluminum pad).

According to some embodiments, dummy conductive features 158', which may be single row and/or single column, are formed in the circuit clearance region 95. According to alternative embodiments, more columns and/or rows of dummy conductive features 158' may be formed in the circuit clearance region 95. For example, a dashed square is drawn to represent additional row/column dummy conductive features 158'. According to some embodiments, the dummy conductive features 158 'of the additional rows and/or columns have the same dimensions as the dummy conductive features 158' of the first row/column. According to alternative embodiments, the dummy conductive features 158' closer to the center 97 of the circuit clearance region 95 may be smaller than those closer to the conductive features 158 and the seal ring 154. For example, some of the dummy conductive features 158' may have a length L6 and a width W6 that are less than the length L5 and the width W5. The ratio L6/L5 and the ratio W6/W5 may range between about 0.1 and about 1. According to some embodiments, the length L6 and the width W6 may be in a range between about 2 μm and about 3 μm.

Fig. 18 shows an embodiment of a dummy conductive feature 158' having a plurality of rows and columns therein. Similarly, the dummy conductive feature 158 'closer to the center 97 of the circuit gap region 95 may be the same size as the dummy conductive feature 158' farther from the center 97, or the dummy conductive feature 158 'closer to the center 97 of the circuit gap region 95 may be smaller than the dummy conductive feature 158' farther from the center 97.

Embodiments of the present disclosure have some advantageous features. By eliminating an upper portion of the outer seal ring (such as aluminum) (or reducing the size of the upper portion of the outer seal ring), stresses at corners and edges of the device die may be reduced. Thus solving the problems of non-bonding and cracking. These embodiments may be applied to both hybrid and fusion bonds.

According to some embodiments, a method includes forming a first package assembly, the forming the first package assembly including forming a plurality of dielectric layers over a semiconductor substrate; forming a plurality of metal lines and vias in the plurality of dielectric layers; forming a lower portion of the inner seal ring and a lower portion of the outer seal ring extending into the plurality of dielectric layers; depositing a first dielectric layer over the plurality of metal lines and the via holes; and etching the first dielectric layer to form an opening penetrating the first dielectric layer, wherein after etching, a top surface of the lower portion of the inner seal ring is exposed, and an entire topmost surface of the lower portion of the outer seal ring is in contact with a bottom surface of the first dielectric layer; forming an upper portion of the inner seal ring to extend into the opening and to connect a lower portion of the inner seal ring; and depositing a second dielectric layer to cover an upper portion of the inner seal ring.

In an embodiment, the method further comprises bonding a second package component over the first package component, wherein the first topmost surface of the inner seal ring is higher than the second topmost surface of the outer seal ring when bonding is performed. In an embodiment, the second package component is joined to the first package component by fusion bonding. In an embodiment, the second package component is bonded to the first package component by hybrid bonding. In an embodiment, when the top surface of the lower portion of the inner seal ring is exposed through the opening, the entire topmost surface of the lower portion of the outer seal ring is not exposed. In an embodiment, the lower portion of the inner seal ring has a first atomic percent of aluminum and the upper portion of the inner seal ring has a second atomic percent of aluminum that is higher than the first atomic percent of aluminum.

In some embodiments, wherein the first aluminum atomic percent is 0% and the second aluminum atomic percent is greater than about 10%.

In an embodiment, the inner seal ring comprises a corner portion, wherein the circuit gap region is immediately adjacent to the corner portion, and wherein the method further comprises forming a plurality of dummy metal pads in the circuit gap region when forming the upper portion of the inner seal ring. In an embodiment, the plurality of dummy metal pads includes a first row closer to a center of the circuit gap region and a second row farther from the center than the first row, and wherein the dummy metal pads in the first row are smaller than the dummy metal pads in the second row.

A structure according to some embodiments includes a device die including a semiconductor substrate; a plurality of dielectric layers over the semiconductor substrate; an inner seal ring. Wherein the inner seal ring comprises a first lower portion in the plurality of dielectric layers; and an upper portion above the first lower portion and the upper portion is connected to the first lower portion. The device die further includes an outer seal ring surrounding the inner seal ring, wherein the outer seal ring includes a second lower portion in the plurality of dielectric layers, and wherein a first topmost surface of the inner seal ring is higher than a second topmost surface of the outer seal ring; and a first dielectric layer over the upper portion of the inner seal ring and contacting the upper portion of the inner seal ring.

In an embodiment, the structure further comprises a second dielectric layer over the first dielectric layer; and a bond pad extending into the second dielectric layer. In an embodiment, the entire topmost surface of the second lower portion of the outer seal ring is in contact with the dielectric material. In an embodiment, the first lower portion of the inner seal ring has a first atomic percent of aluminum and the upper portion of the inner seal ring has a second atomic percent of aluminum that is higher than the first atomic percent of aluminum. In an embodiment, the outer seal ring does not extend to an upper portion in the same dielectric layer as the upper portion of the inner seal ring extends to.

In an embodiment, the inner seal ring comprises a corner portion, wherein the circuit gap region is immediately adjacent to the corner portion, and wherein the structure further comprises a plurality of dummy metal pads in the circuit gap region, wherein the plurality of dummy metal pads extend into the same dielectric layer as the upper portion of the inner seal ring extends into. In an embodiment, the plurality of dummy metal pads includes a first row closer to a center of the circuit gap region and a second row farther from the center, and wherein the dummy metal pads in the first row are smaller than the dummy metal pads in the second row.

According to some embodiments, a structure includes a device die including a first seal ring including a first lower portion, wherein the first lower portion includes a first damascene structure and includes copper; and an upper portion above the first lower portion and connected to the first lower portion, wherein the first lower portion and the upper portion comprise different metals. And the device die further comprising a second seal ring closer to an edge of the device die than the first seal ring, wherein the second seal ring comprises a second lower portion comprising a second damascene structure and comprising copper, wherein a first topmost surface of the first seal ring is higher than a second topmost surface of the second seal ring.

The above structure further includes a package assembly over the device die, and the package assembly is bonded to the device die. In an embodiment, the entire second topmost surface is in contact with the bottom surface of the dielectric layer. In an embodiment, the first lower portion is free of aluminum and the upper portion comprises aluminum. In an embodiment, the device die and the package assembly are bonded to each other by hybrid bonding or fusion bonding.

The foregoing outlines components of several embodiments or examples so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples presented herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A method of forming a package, comprising:

forming a first package assembly comprising:

forming a plurality of dielectric layers over a semiconductor substrate;

forming a plurality of metal lines and vias in the plurality of dielectric layers;

Forming a lower portion of an inner seal ring and a lower portion of an outer seal ring extending into the plurality of dielectric layers;

depositing a first dielectric layer over the plurality of metal lines and vias; and

etching the first dielectric layer to form an opening through the first dielectric layer, wherein after the etching, a top surface of the lower portion of the inner seal ring is exposed, and an entire topmost surface of the lower portion of the outer seal ring is in contact with a bottom surface of the first dielectric layer; and

forming an upper portion of the inner seal ring to extend into the opening and to connect the lower portion of the inner seal ring; and

a second dielectric layer is deposited to cover the upper portion of the inner seal ring.

2. The method of claim 1, further comprising bonding a second package component over the first package component, wherein a first topmost surface of the inner seal ring is higher than a second topmost surface of the outer seal ring when the bonding is performed.

3. The method of claim 2, wherein the second package component is bonded to the first package component by fusion bonding.

4. The method of claim 2, wherein the second package component is bonded to the first package component by hybrid bonding.

5. The method of claim 1, wherein the entire topmost surface of the lower portion of the outer seal ring is not exposed when the top surface of the lower portion of the inner seal ring is exposed through the opening.

6. The method of claim 1, wherein the lower portion of the inner seal ring has a first atomic percent of aluminum and the upper portion of the inner seal ring has a second atomic percent of aluminum that is higher than the first atomic percent of aluminum.

7. The method of claim 6, wherein the first aluminum atomic percent is 0% and the second aluminum atomic percent is greater than 10%.

8. The method of claim 1, wherein the inner seal ring comprises a corner portion, wherein a circuit gap region is immediately adjacent to the corner portion, and wherein the method further comprises forming a plurality of dummy metal pads in the circuit gap region when forming the upper portion of the inner seal ring.

9. A package structure, comprising:

a device die, comprising:

a semiconductor substrate;

a plurality of dielectric layers over the semiconductor substrate;

an inner seal ring, the inner seal ring comprising:

A first lower portion in the plurality of dielectric layers; and

an upper portion above the first lower portion and connected to the first lower portion;

an outer seal ring surrounding the inner seal ring, wherein the outer seal ring comprises a second lower portion in the plurality of dielectric layers, and wherein a first topmost surface of the inner seal ring is higher than a second topmost surface of the outer seal ring; and

a first dielectric layer over the upper portion of the inner seal ring and contacting the upper portion of the inner seal ring.

10. A package structure, comprising:

a device die, the device die comprising:

a first seal ring, the first seal ring comprising:

a first lower portion, wherein the first lower portion comprises a first damascene structure and comprises copper; and

an upper portion above the first lower portion and connected to the first lower portion, wherein the first lower portion and the upper portion comprise different metals; and

a second seal ring closer to an edge of the device die than the first seal ring, wherein the second seal ring comprises a second lower portion comprising a second damascene structure and comprising copper, wherein a first topmost surface of the first seal ring is higher than a second topmost surface of the second seal ring; and

A package assembly over the device die, and the package assembly is bonded to the device die.