CN110854116A - Three-dimensional heterogeneous integrated chip and preparation method thereof - Google Patents
Three-dimensional heterogeneous integrated chip and preparation method thereof Download PDFInfo
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- CN110854116A CN110854116A CN201911028369.2A CN201911028369A CN110854116A CN 110854116 A CN110854116 A CN 110854116A CN 201911028369 A CN201911028369 A CN 201911028369A CN 110854116 A CN110854116 A CN 110854116A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
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Abstract
The application provides a three-dimensional heterogeneous integrated chip and a preparation method thereof, wherein the chip comprises: a first chip; the first chip includes: the semiconductor device comprises a first substrate, a first active region layer, a first metal layer, a first dielectric layer and a first through hole; the first substrate, the first active region layer, the first metal layer and the first dielectric layer are sequentially connected in a laminated mode, the first through hole is formed in the first dielectric layer, and the first through hole is connected with the first metal layer and the outer portion of the first dielectric layer; a second chip including a second substrate, a first memory layer, a second dielectric layer, and a second via; the first storage layer is connected with the second substrate, the second dielectric layer is connected with the first storage layer, the second through hole is formed in the second dielectric layer, and the second through hole is connected with the second storage layer and the outside of the second dielectric layer; the first chip is internally provided with a first conductive channel, one end of the first conductive channel is connected with the first metal layer, the other end of the first conductive channel is connected with the outside of the first substrate, and the first conductive channel is used as an input end or an output end of the chip.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a three-dimensional heterogeneous integrated chip and a preparation method thereof.
Background
Under the classic computer architecture, storage and calculation are separated and are embodied on a board level, a storage chip and a calculation chip are independently packaged on a circuit board, and data are interacted through a board level lead. But the board-level wire has large diameter and large parasitic capacitance, so that the data transmission speed is limited; the exposed wires can enable an attacker to eavesdrop the wire signals to acquire the secret key, and great potential safety hazards are caused. Three-dimensional integrated circuits (3D-ICs) using wafer-wafer stacking have been expected to break this challenge.
The Memory architecture is composed of Static Random-Access Memory (SRAM), Dynamic Random-Access Memory (DRAM), and Flash Memory (Flash) in sequence from fast to slow. However, these conventional charge-type memories are approaching physical limits and cannot be scaled down. The novel memory has the advantages of high speed, low power consumption, non-volatility, and being scalable, and includes a Magnetic Random Access Memory (MRAM), a Resistive Random Access Memory (RRAM), a Phase Change Memory (PCM), and the like. Among them, the device speed of the phase change memory has approached the SRAM, but its application depends on the innovative design of the architecture.
Therefore, how to further improve the speed and security of the computing system and solve the application difficulty of the new memory has become a technical problem to be solved urgently by those skilled in the art.
Disclosure of Invention
The method and the device solve the technical problems that the speed and the safety of a computing system in the prior art are limited, and a novel memory is difficult to apply.
In order to solve the above technical problem, an embodiment of the present application discloses a three-dimensional heterogeneous integrated chip, including:
a first chip; the first chip includes: a first substrate, a first active region layer, a first metal layer, a first dielectric layer and at least one first via; the first substrate, the first active region layer, the first metal layer and the first dielectric layer are sequentially connected in a laminated mode, the first through hole is formed in the first dielectric layer and connected with the first metal layer and the outer portion of the first dielectric layer, and the first through hole is the input end or the output end of the first chip;
a second chip including a second substrate, a first memory layer, a second dielectric layer, and at least one second via; the first storage layer is connected with the second substrate, the second dielectric layer is connected with the first storage layer, the second through hole is connected with the second storage layer and the outside of the second dielectric layer, and the second through hole is an input end or an output end of the second chip;
the first dielectric layer is connected with the second dielectric layer in a laminated mode, and the first through holes correspond to the second through holes one to one;
a first conductive path; the first conductive channel is arranged in the first chip, one end of the first conductive channel is connected with the first metal layer, the other end of the first conductive channel is connected with the outside of the first substrate, and the first conductive channel is used as an input end or an output end of the three-dimensional heterogeneous integrated chip.
Further, the three-dimensional heterogeneous integrated chip further comprises:
a third chip; the third chip comprises a third substrate, a second storage layer and a third dielectric layer; the second storage layer is connected with the third substrate, and the third dielectric layer is connected with the second storage layer; at least one third through hole is formed in the third dielectric layer, the third through hole is connected with the second storage layer and the outside of the third dielectric layer, and the third through hole is used as the input and the output of the third chip;
the third dielectric layer is connected with the second substrate, and the first chip, the second chip and the third chip are stacked;
a second conductive channel is arranged in the second chip, one end of the second conductive channel is connected with the inside of the second chip, and the other end of the second conductive channel is connected with the third through hole;
when data are input into the three-dimensional heterogeneous integrated chip, the data flow direction is sequentially a first conductive channel, a first chip, a second conductive channel and a third chip; the first chip is used for calculation, the second chip is used for hot data storage, and the third chip is used for cold data storage;
when the three-dimensional heterogeneous integrated chip outputs data, the data flow direction is a third chip, a second conductive channel, a second chip, a first chip and a first conductive channel; the first chip is used for calculation, the second chip is used for hot data exchange, and the third chip is used for cold data reading.
Further, the three-dimensional heterogeneous integrated chip further comprises: a second metal layer between the first storage layer and the second dielectric layer;
and/or;
a third metal layer between the second storage layer and the third dielectric layer.
Furthermore, the three-dimensional heterogeneous integrated chip further comprises a conductive bump, the conductive bump is arranged at one end of the first conductive channel, and the conductive bump is connected with the first conductive channel.
Further, the first active area comprises at least one of a storage peripheral circuit, a central processing unit, an image processor, a field programmable logic array, an application specific integrated circuit, a digital signal processor, an artificial intelligence chip and a modem;
the first storage layer comprises at least one of a phase change storage array, a resistance change storage array, a magnetic storage array, a static random access storage array, a dynamic random access storage array or a flash memory storage array;
the second storage layer comprises at least one of a phase change storage array, a resistance change storage array, a magnetic storage array, a static random access storage array, a dynamic random access storage array or a flash memory storage array.
Another aspect of the embodiments of the present application provides a method for manufacturing a three-dimensional heterogeneous integrated chip, including the following steps:
preparing a first chip; the method comprises the following steps: obtaining a first substrate, forming a first active area layer on the surface of the first substrate, and forming a first metal layer on the surface of the first active area; forming a first dielectric layer on the surface of the first metal layer; forming at least one first through hole in the first dielectric layer, wherein the first through hole is connected with the first metal layer and the outside of the first dielectric layer, and the first through hole is an input end or an output end of the first chip;
preparing a second chip; the method comprises the following steps: obtaining a second substrate, and forming a first storage layer on the surface of the second substrate; forming a second dielectric layer on the surface of the first storage layer; forming a second through hole in the second dielectric layer, wherein the second through hole is connected with the first storage layer and the outside of the second dielectric layer, and the second through hole is an input end or an output end of the second chip;
connecting the first dielectric layer and the second dielectric layer in a laminated manner, wherein the first through hole and the second through hole are connected in a bonding manner; and preparing a first conductive channel inside the first chip, wherein one end of the first conductive channel is connected with the first metal layer, the other end of the first conductive channel is connected with the outside of the first substrate, and the first conductive channel is an input end or an output end of the three-dimensional heterogeneous integrated chip.
Further, the preparation method of the three-dimensional heterogeneous integrated chip also comprises the following steps:
preparing a third chip; the method comprises the following steps: obtaining a third substrate, and forming a second storage layer on the surface of the third substrate; forming a third dielectric layer on the surface of the second storage layer; forming a third through hole in the third dielectric layer, wherein the third through hole is connected with the second storage layer and the outside of the third dielectric layer and is used as the input and the output of the third chip;
connecting the third dielectric layer with the second substrate to realize the lamination of the first chip, the second chip and the third chip;
and preparing a second conductive channel in the second chip, wherein one end of the second conductive channel is connected with the inside of the second chip, and the other end of the second conductive channel is connected with the third through hole.
Further, the preparation method of the three-dimensional heterogeneous integrated chip also comprises the following steps:
preparing a second metal layer on the surface of the first storage layer, and then preparing a second dielectric layer on the surface of the second metal layer;
and/or;
and preparing a third metal layer on the surface of the second storage layer, and then preparing a third dielectric layer on the surface of the third metal layer.
Further, the first active area layer comprises at least one of a storage peripheral circuit, a central processing unit, an image processor, a field programmable logic array, an application specific integrated circuit, a digital signal processor, an artificial intelligence chip and a modem;
the first storage layer comprises at least one of a phase change storage array, a resistance change storage array, a magnetic storage array, a static random access storage array, a dynamic random access storage array or a flash memory storage array;
the second storage layer comprises at least one of a phase change storage array, a resistance change storage array, a magnetic storage array, a static random access storage array, a dynamic random access storage array or a flash memory storage array.
Furthermore, the preparation method of the three-dimensional heterogeneous integrated chip further comprises the step of preparing and forming a conductive bump on the surface of the first conductive channel, wherein the conductive bump is connected with the first conductive channel.
By adopting the technical scheme, the application has the following beneficial effects:
the three-dimensional heterogeneous integrated chip provided by the application has no exposed wires, data can be processed inside, a relatively closed computing system is formed, the difficulty of obtaining the secret key is increased, and the safety risk is reduced; the three-dimensional heterogeneous integrated chip transmits data by using metal or through holes in the chip, and compared with an off-chip wiring, the three-dimensional heterogeneous integrated chip is low in wire parasitic capacitance and high in data exchange speed.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a three-dimensional heterogeneous integrated chip according to an embodiment of the present application;
FIG. 2 is a schematic diagram illustrating a data flow direction of a three-dimensional heterogeneous integrated chip during data input according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating a data flow direction of a three-dimensional heterogeneous integrated chip during data output according to an embodiment of the present application;
FIG. 4 is a schematic structural diagram of a method for fabricating a three-dimensional heterogeneous integrated chip according to an embodiment of the present application;
the following is a supplementary description of the drawings:
1-a first chip; 10-a first substrate; 11-a first active region; 12-first metal layer 13-first dielectric layer; 14-a first via;
2-a second chip; 20-a second substrate; 21-a first storage layer; 22-a second metal layer; 23-a second dielectric layer; 24-a second via;
3-a third chip; 30-a third substrate; 31-a second storage layer; 32-a third metal layer; 33-a third dielectric layer; 34-a third through hole;
4-a first conductive path; 5-a second conductive path; 6-conductive bump.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the present application. In the description of the embodiments of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a three-dimensional heterogeneous integrated chip according to an embodiment of the present application, as shown in fig. 1, the three-dimensional heterogeneous integrated chip includes:
a first chip 1; the first chip 1 includes: a first substrate 10, a first active region layer 11, a first metal layer 12, a first dielectric layer 13, and a first via 14; the number of the first through holes 14 may be one or more; the first substrate 10, the first active region layer 11, the first metal layer 12 and the first dielectric layer 13 are sequentially connected in a laminated manner, the first through hole 14 is formed in the first dielectric layer 13, the first through hole 14 is connected with the first metal layer 12 and the outside of the first dielectric layer 13, and the first through hole 14 is an input end or an output end of the first chip 1;
a second chip 2, the second chip 2 comprising a second substrate 20, a first memory layer 21, a second dielectric layer 23 and a second via 24; the number of the second through holes 24 may be one or more; the first storage layer 21 is connected with the second substrate 20, the second dielectric layer 23 is connected with the first storage layer 21, the second through hole 24 is arranged inside the second dielectric layer 23, the second through hole 24 is connected with the second storage layer 31 and the outside of the second dielectric layer 23, and the second through hole 24 is an input end or an output end of the second chip 2;
the first dielectric layer 13 and the second dielectric layer 23 are connected in a stacked manner to realize the stacking of the first chip and the second chip, wherein the first through holes and the second through holes are in one-to-one correspondence and are connected in a bonding manner.
The first chip 1 is internally provided with a first conductive channel 4, one end of the first conductive channel 4 is connected with the first metal layer 12, the other end of the first conductive channel 4 is connected with the outside of the first substrate 10, and the first conductive channel 4 is used as an input end or an output end of the three-dimensional heterogeneous integrated chip.
In the embodiment of the present application, the three-dimensional heterogeneous integrated chip may further include a third chip 3; the third chip 3 comprises a third substrate 30, a second memory layer 31 and a third dielectric layer 33; the second memory layer 31 is connected to the third substrate 30, and the third dielectric layer 33 is connected to the second memory layer 31; a third via hole 34 is formed in the third dielectric layer 33, wherein the number of the third via holes 34 may be one or multiple; a third via 34 connecting the second memory layer 31 and the outside of the third dielectric layer 33, the third via 34 serving as an input and an output of the third chip 3;
the third dielectric layer 33 is connected with the second substrate 20, so that the first chip 1, the second chip 2 and the third chip 3 are stacked;
a second conductive channel 5 is arranged in the second chip 2, one end of the second conductive channel 5 is connected with the inside of the second chip 2, and the other end of the second conductive channel 5 is connected with the third through hole 34.
As described above, in the embodiment of the present application, in an implementation scheme, the three-dimensional heterogeneous integrated chip may be formed by connecting the first chip 1 and the second chip 2, or may be formed by sequentially stacking and connecting the first chip 1, the second chip 2, and the third chip 3.
In the embodiment of the present application, when the three-dimensional heterogeneous chip is formed by a scheme of connecting the first chip 1 and the second chip 2, the three-dimensional heterogeneous integrated chip may further include a second metal layer 22, and the second metal layer 22 is located between the first storage layer 21 and the second dielectric layer 23;
when the three-dimensional heterogeneous chip is formed by a scheme of sequentially connecting the first chip 1, the second chip 2 and the third chip 3 in a stacked manner, the three-dimensional heterogeneous integrated chip may include only the second metal layer 22, and the second metal layer 22 is located between the first storage layer 21 and the second dielectric layer 23;
it may also comprise only a third metal layer 32, the third metal layer 32 being located between the second storage layer 31 and the third dielectric layer 33;
it is also possible to include both a second metal layer 22 and a third metal layer 32, the second metal layer 22 being located between the first storage layer 21 and the second dielectric layer 23, and the third metal layer 32 being located between the second storage layer 31 and the third dielectric layer 33.
In the embodiment of the present application, when the three-dimensional heterogeneous chip is formed by sequentially stacking and connecting the first chip 1, the second chip 2, and the third chip 3, the first conductive channel 4 may also be disposed inside the third chip 3 as an input end or an output end of the three-dimensional heterogeneous integrated chip, one end of the first conductive channel 4 is connected to the third metal layer 32, and the other end of the first conductive channel 4 is connected to the outside of the third substrate 30.
In the embodiment of the present application, the three-dimensional heterogeneous integrated chip further includes a conductive bump 6, the conductive bump 6 is disposed at one end of the first conductive via 4, and the conductive bump 6 is connected to the first conductive via 4.
In the embodiment of the present application, fig. 2 is a schematic diagram of a data flow direction when data is input to the three-dimensional heterogeneous integrated chip, as shown in fig. 2, when data is input to the three-dimensional heterogeneous integrated chip, the data flow direction is a first conductive channel 4, a first chip 1, a second chip 2, a second conductive channel 5, and a third chip 3, the first chip 1 is used for calculation, the second chip 2 is used for thermal data storage, and the third chip 3 is used for cold data storage;
fig. 3 is a schematic diagram of a data flow direction during data output of the three-dimensional heterogeneous integrated chip, and as shown in fig. 3, the data flow direction during data output of the three-dimensional heterogeneous integrated chip is a third chip 3, a second conductive channel 5, a second chip 2, a first chip 1 and a first conductive channel 4, the first chip 1 is used for calculation, the second chip 2 is used for hot data exchange, and the third chip 3 is used for cold data readout.
In the embodiment of the present application, the first active region layer 11 may be at least one of a memory peripheral circuit, a central processing unit, an image processor, a field programmable logic array, an application specific integrated circuit, a digital signal processor, an artificial intelligence chip, and a modem;
the first storage layer 21 comprises at least one of a phase change storage array, a resistance change storage array, a magnetic storage array, a static random access storage array, a dynamic random access storage array or a flash memory storage array;
the first memory layer 21 comprises at least one memory array, for example, the first memory layer 21 may be formed by stacking a phase change memory array and a static random access memory array.
The second memory layer 31 includes at least one of a phase change memory array, a resistance change memory array, a magnetic memory array, a static random access memory array, a dynamic random access memory array, or a flash memory array. The second storage layer 31 includes at least one storage array, for example, the second storage layer 31 may include only one flash storage array, or may be formed by stacking one flash storage array and one dynamic random access memory array.
In the embodiment of the present application, the first substrate 10, the second substrate 20, and the third substrate 30 may be any semiconductor substrate known in the art, such as a single crystalline silicon substrate, a group iv compound substrate, a group iii-group compound substrate, or the like; or an epitaxial layer on the surface of the substrate; the substrate and a buried oxide layer (BOX) on the surface thereof may be used; but also any other semiconductor or non-semiconductor material, such as a silicon oxide substrate, a glass substrate, a plastic substrate, a metal substrate or a ceramic substrate.
In the embodiment of the present application, the first dielectric layer 13, the second dielectric layer 23, and the third dielectric layer 33 may be made of any suitable insulating material including oxide (e.g., silicon oxide, aluminum oxide, hafnium oxide, etc.), silicon nitride, silicon oxynitride, etc., and the like, which is not limited herein. The formation process includes, but is not limited to, electroplating, chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
In the embodiment of the present application, the first metal layer 12, the second metal layer 22, the third metal layer 32, the first via 14, the second via 24, and the third via 34 may be made of any suitable conductive material, such as metal, metal alloy, metal silicide, or highly doped semiconductor (e.g., tungsten (W), tungsten silicide (WSiX), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), doped polysilicon, etc.), and formed by a process including, but not limited to, electroplating, chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
Specifically, the first conductive via 4 and the second conductive via 5 may use a Through Silicon Via (TSV) structure, and may be made of any suitable conductive material such as metal, metal alloy, metal silicide, or highly doped semiconductor (e.g., tungsten (W), tungsten silicide (WSiX), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), doped polysilicon, etc.).
In the embodiment of the application, the three-dimensional heterogeneous integrated chip transmits data by using metal, through holes or Through Silicon Vias (TSV) in the chip, and compared with an off-chip wiring, the three-dimensional heterogeneous integrated chip is low in wire parasitic capacitance and high in data exchange speed. When data is input, the data flow direction is the first conductive channel 4, the first chip 1, the second chip 2, the second conductive channel 5 and the third chip 3. The first chip 1 is logic for computation, the second chip 2 is a new type of memory for hot data storage, and the third chip 3 may be a flash memory for cold data storage. The whole computing and storing framework is designed according to the speed from fast to slow and the data capacity from small to large, so that the system is high in energy efficiency and low in cost;
and the three-dimensional heterogeneous integrated chip has no exposed wires, data can be processed internally, a relatively closed computing system is formed, the difficulty of obtaining a secret key is increased, and the security risk is reduced.
In the embodiment of the present application, the first chip 1, the second chip 2, and the third chip 3 may adopt different manufacturing processes, so as to increase the speed, reduce the cost, and reduce the mutual influence in the manufacturing process. This advantage covers computing components, hot data storage components and cold data storage components.
Another aspect of the embodiments of the present application provides a method for manufacturing a three-dimensional heterogeneous integrated chip, where the method for manufacturing a three-dimensional heterogeneous integrated chip provided in the embodiments and the three-dimensional heterogeneous integrated chip are based on the same concept, and fig. 4 is a schematic flow chart of the manufacturing method, where the method includes the following steps:
preparing a first chip 1; the method comprises the following steps:
s1, obtaining a first substrate 10, and forming a first active region layer 11 on the surface of the first substrate 10;
s2, forming a first metal layer 12 on the surface of the first active region;
s3, forming a first dielectric layer 13 on the surface of the first metal layer 12;
s4, forming a first via 14 inside the first dielectric layer 13, the first via 14 connecting the first metal layer 12 and the outside of the first dielectric layer 13, the first via 14 being an input terminal or an output terminal of the first chip 1;
preparing a second chip 2; the method comprises the following steps:
s5, obtaining a second substrate 20, and forming a first storage layer 21 on the surface of the second substrate 20;
s6, forming a second dielectric layer 23 on the surface of the first memory layer 21; alternatively, the second metal layer 22 may be prepared on the first memory layer 21, and the second dielectric layer 23 may be prepared on the second metal layer;
s7, forming a second via 24 in the second dielectric layer 23, the second via 24 connecting the first storage layer 21 and the second dielectric layer 23, the second via 24 being an input terminal or an output terminal of the second chip 2;
s8, connecting the first dielectric layer 13 and the second dielectric layer 23 in a laminated manner, wherein the first through hole 14 and the second through hole 24 are connected in a bonding manner;
s9: a first conductive channel 4 is prepared inside the first chip 1, one end of the first conductive channel 4 is connected with the first metal layer 12, the other end of the first conductive channel 4 is connected with the outside of the first substrate 10, and the first conductive channel 4 is an input end or an output end of the three-dimensional heterogeneous integrated chip.
In the embodiment of the present application, the method for preparing a three-dimensional heterogeneous integrated chip may further include the following steps:
preparing a third chip 3; the method comprises the following steps:
s10, obtaining a third substrate 30, and forming a second storage layer 31 on the surface of the third substrate 30;
s11, forming a third dielectric layer 33 on the surface of the second memory layer 31; optionally, the step may be to prepare a third metal layer 32 on the surface of the second storage layer 31, and prepare a third dielectric layer 33 on the surface of the third metal layer 32;
s12, forming a third via hole 34 in the third dielectric layer 33, the third via hole 34 connecting the second storage layer 31 and the outside of the third dielectric layer 33, the third via hole 34 being used as the input and output of the third chip 3;
s13, connecting the third dielectric layer 33 with the second substrate 20 to realize the lamination of the first chip 1, the second chip 2 and the third chip 3;
and S14, preparing a second conductive channel 5 in the second chip 2, wherein one end of the second conductive channel 5 is connected with the inside of the second chip 2, and the other end of the second conductive channel 5 is connected with the third through hole 34.
S15: and preparing and forming a conductive bump 6 on the surface of the first conductive channel 4, wherein the conductive bump 6 is connected with the first conductive channel 4 to be used as an input end or an output end of the three-dimensional heterogeneous integrated chip.
In the embodiment of the present application, when the three-dimensional heterogeneous integrated chip includes the scheme for preparing the third chip 3, the first conductive via 4 may also be disposed inside the third chip 3 as an input end or an output end of the three-dimensional heterogeneous integrated chip, one end of the first conductive via 4 is connected to the third metal layer 32, and the other end of the first conductive via 4 is connected to the outside of the third substrate 30.
In the embodiment of the present application, fig. 2 is a schematic diagram of a data flow direction when data is input to the three-dimensional heterogeneous integrated chip, as shown in fig. 2, when data is input to the three-dimensional heterogeneous integrated chip, the data flow direction is a first conductive channel 4, a first chip 1, a second chip 2, a second conductive channel 5, and a third chip 3, the first chip 1 is used for calculation, the second chip 2 is used for thermal data storage, and the third chip 3 is used for cold data storage;
fig. 3 is a schematic diagram of a data flow direction during data output of the three-dimensional heterogeneous integrated chip, and as shown in fig. 3, the data flow direction during data output of the three-dimensional heterogeneous integrated chip is a third chip 3, a second conductive channel 5, a second chip 2, a first chip 1 and a first conductive channel 4, the first chip 1 is used for calculation, the second chip 2 is used for hot data exchange, and the third chip 3 is used for cold data readout.
In the embodiment of the present application, the first active region layer 11 may be at least one of a memory peripheral circuit, a central processing unit, an image processor, a field programmable logic array, an application specific integrated circuit, a digital signal processor, an artificial intelligence chip, and a modem;
the first storage layer 21 comprises at least one of a phase change storage array, a resistance change storage array, a magnetic storage array, a static random access storage array, a dynamic random access storage array or a flash memory storage array; the first memory layer 21 includes at least one memory array, for example, the first memory layer 2113 may be formed by stacking a phase change memory array and a static random access memory array.
The second memory layer 31 includes at least one of a phase change memory array, a resistance change memory array, a magnetic memory array, a static random access memory array, a dynamic random access memory array, or a flash memory array. The second storage layer 31 includes at least one storage array, for example, the second storage layer 31 may include only one flash storage array, or may be formed by stacking one flash storage array and one dynamic random access memory array.
In the embodiment of the present application, the first substrate 10, the second substrate 20, and the third substrate 30 may be any semiconductor substrate known in the art, such as a single crystalline silicon substrate, a group iv compound substrate, a group iii-group compound substrate, or the like; or an epitaxial layer on the surface of the substrate; the substrate and a buried oxide layer (BOX) on the surface thereof may be used; but also any other semiconductor or non-semiconductor material, such as a silicon oxide substrate, a glass substrate, a plastic substrate, a metal substrate or a ceramic substrate.
In the embodiment of the present application, the first dielectric layer 13, the second dielectric layer 23, and the third dielectric layer 33 may be made of any suitable insulating material including oxide (e.g., silicon oxide, aluminum oxide, hafnium oxide, etc.), silicon nitride, silicon oxynitride, etc., and the like, which is not limited herein. The formation process includes, but is not limited to, electroplating, chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
In the embodiment of the present application, the first metal layer 12, the second metal layer 22, the third metal layer 32, the first via 14, the second via 24, and the third via 34 may be made of any suitable conductive material, such as metal, metal alloy, metal silicide, or highly doped semiconductor (e.g., tungsten (W), tungsten silicide (WSiX), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), doped polysilicon, etc.), and formed by a process including, but not limited to, electroplating, chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
Specifically, the first conductive via 4 and the second conductive via 5 may use a Through Silicon Via (TSV) structure, and may be made of metal, metal alloy, metal silicide, or any suitable conductive material such as highly doped semiconductor (e.g., tungsten (W), tungsten silicide (WSiX), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), doped polysilicon, etc.
In the embodiment of the application, the three-dimensional heterogeneous integrated chip transmits data by using metal, through holes or Through Silicon Vias (TSV) in the chip, and compared with an off-chip wiring, the three-dimensional heterogeneous integrated chip is low in wire parasitic capacitance and high in data exchange speed. When data is input, the data flow direction is the first conductive channel 4, the first chip 1, the second chip 2, the second conductive channel 5 and the third chip 3. The first chip 1 is logic for computation, the second chip 2 is a new type of memory for hot data storage, and the third chip 3 may be a flash memory for cold data storage. The whole computing and storing framework is designed according to the speed from fast to slow and the data capacity from small to large, so that the system is high in energy efficiency and low in cost;
and the three-dimensional heterogeneous integrated chip has no exposed wires, data can be processed internally, a relatively closed computing system is formed, the difficulty of obtaining a secret key is increased, and the security risk is reduced.
In the embodiment of the present application, the first chip 1, the second chip 2, and the third chip 3 may adopt different manufacturing processes, so as to increase the speed, reduce the cost, and reduce the mutual influence in the manufacturing process. This advantage covers computing components, hot data storage components and cold data storage components.
The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
Claims (10)
1. A three-dimensional heterogeneous integrated chip, comprising:
a first chip (1); the first chip (1) comprises: a first substrate (10), a first active region layer (11), a first metal layer (12), a first dielectric layer (13) and at least one first via (14); the first substrate (10), the first active region layer (11), the first metal layer (12) and the first dielectric layer (13) are sequentially connected in a stacked manner, the at least one first through hole (14) is connected with the first metal layer (12) and the outside of the first dielectric layer (13), and the at least one first through hole (14) is an input end or an output end of the first chip (1);
a second chip (2), the second chip (2) comprising a second substrate (20), a first memory layer (21), a second dielectric layer (23) and at least one second via (24); the first storage layer (21) is connected to the second substrate (20), the second dielectric layer (23) is connected to the first storage layer (21), the at least one second via (24) connects the second storage layer (31) and the outside of the second dielectric layer (23), the at least one second via (24) is an input or output of the second chip (2);
the first dielectric layer (13) is connected with the second dielectric layer (23) in a stacking mode, and the at least one first through hole (14) corresponds to the at least one second through hole (24) in a one-to-one mode;
a first conductive path (4); one end of the first conductive channel (4) is connected with the first metal layer (12), the other end of the first conductive channel (4) is connected with the outside of the first substrate (10), and the first conductive channel (4) is used as an input end or an output end of the three-dimensional heterogeneous integrated chip.
2. The three-dimensional heterogeneous integrated chip of claim 1, further comprising:
a third chip (3); the third chip (3) comprises a third substrate (30), a second memory layer (31) and a third dielectric layer (33); the second storage layer (31) is connected to the third substrate (30), and the third dielectric layer (33) is connected to the second storage layer (31); at least one third through hole (34) is formed in the third dielectric layer (33), the at least one third through hole (34) is connected with the second storage layer (31) and the outside of the third dielectric layer (33), and the at least one third through hole (34) is used as the input and the output of the third chip (3);
the third dielectric layer (33) is connected with the second substrate (20) to realize the stacking of the first chip (1), the second chip (2) and the third chip (3);
a second conductive channel (5) is arranged in the second chip (2), one end of the second conductive channel (5) is connected with the inside of the second chip (2), and the other end of the second conductive channel (5) is connected with the at least one third through hole (34);
when data are input into the three-dimensional heterogeneous integrated chip, the data flow direction sequentially comprises the first conductive channel (4), the first chip (1), the second chip (2), the second conductive channel (5) and the third chip (3); the first chip (1) is used for computing, the second chip (2) is used for hot data storage, and the third chip (3) is used for cold data storage;
when the three-dimensional heterogeneous integrated chip outputs data, the data flow direction sequentially comprises the third chip (3), the second conductive channel (5), the second chip (2), the first chip (1) and the first conductive channel (4), the first chip (1) is used for calculation, the second chip (2) is used for hot data exchange, and the third chip (3) is used for cold data reading.
3. The three-dimensional heterogeneous integrated chip of claim 2, further comprising:
a second metal layer (22), the second metal layer (22) being located between the first storage layer (21) and the second dielectric layer (23);
and/or;
a third metal layer (32), the third metal layer (32) being located between the second storage layer (31) and the third dielectric layer (33).
4. The three-dimensional heterogeneous integrated chip according to claim 1, further comprising a conductive bump (6), wherein the conductive bump (6) is disposed at one end of the first conductive via (4), and the conductive bump (6) is connected to the first conductive via (4).
5. The three-dimensional heterogeneous integrated chip of claim 2,
the first active region (11) comprises at least one of a storage peripheral circuit, a central processing unit, an image processor, a field programmable logic array, an application specific integrated circuit, a digital signal processor, an artificial intelligence chip and a modem;
the first storage layer (21) comprises at least one of a phase change storage array, a resistance change storage array, a magnetic storage array, a static random access storage array, a dynamic random access storage array or a flash memory storage array;
the second memory layer (31) comprises at least one of a phase change memory array, a resistive memory array, a magnetic memory array, a static random access memory array, a dynamic random access memory array or a flash memory array.
6. A preparation method of a three-dimensional heterogeneous integrated chip is characterized by comprising the following steps:
preparing a first chip (1); the method comprises the following steps: obtaining a first substrate (10), forming a first active region layer (11) on the surface of the first substrate (10), and forming a first metal layer (12) on the surface of the first active region (11); forming a first dielectric layer (13) on the surface of the first metal layer (12); forming at least one first through hole (14) inside the first dielectric layer (13), wherein the at least one first through hole (14) is connected with the first metal layer (12) and the outside of the first dielectric layer (13), and the at least one first through hole (14) is an input end or an output end of the first chip (1);
preparing a second chip (2); the method comprises the following steps: obtaining a second substrate (20), and forming a first storage layer (21) on the surface of the second substrate (20); forming a second dielectric layer (23) on the surface of the first storage layer (21); forming at least one second via (24) inside the second dielectric layer (23), the at least one second via (24) connecting the first storage layer (21) and the outside of the second dielectric layer (23), the at least one second via (24) being an input or an output of the second chip (2);
connecting the first dielectric layer (13) and the second dielectric layer (23) in a layer-by-layer manner, wherein the at least one first via (14) and the at least one second via (24) are connected in a bonding manner;
preparing a first conductive channel (4) inside the first chip (1), wherein one end of the first conductive channel (4) is connected with the first metal layer (12), the other end of the first conductive channel (4) is connected with the outside of the first substrate (10), and the first conductive channel (4) is an input end or an output end of the three-dimensional heterogeneous integrated chip.
7. The method for preparing the three-dimensional heterogeneous integrated chip according to claim 6, further comprising the following steps:
preparing a third chip (3); the method comprises the following steps: obtaining a third substrate (30), and forming a second storage layer (31) on the surface of the third substrate (30); forming a third dielectric layer (33) on the surface of the second storage layer (31); forming at least one third via inside the third dielectric layer (33), the at least one third via (34) connecting the second memory layer (31) and the outside of the third dielectric layer (33), the at least one third via serving as an input and an output of the third chip (3);
connecting the third dielectric layer (33) and the second substrate (20) to realize the lamination of the first chip (1), the second chip (2) and the third chip (3);
preparing a second conductive channel (5) in the second chip (2), wherein one end of the second conductive channel (5) is connected with the inside of the second chip (2), and the other end of the second conductive channel (5) is connected with the at least one third through hole (34).
8. The method for preparing the three-dimensional heterogeneous integrated chip according to claim 7, further comprising the following steps:
preparing a second metal layer (22) on the surface of the first storage layer (21), and then preparing a second dielectric layer (23) on the upper surface of the second metal layer (22);
and/or;
-preparing a third metal layer (32) on the surface of the second storage layer (31), followed by preparing the third dielectric layer (33) on the surface of the third metal layer (32).
9. The method of claim 7,
the first active area layer (11) comprises at least one of a storage peripheral circuit, a central processing unit, an image processor, a field programmable logic array, an application specific integrated circuit, a digital signal processor, an artificial intelligence chip and a modem;
the first storage layer (21) comprises at least one of a phase change storage array, a resistance change storage array, a magnetic storage array, a static random access storage array, a dynamic random access storage array or a flash memory storage array;
the second memory layer (31) comprises at least one of a phase change memory array, a resistive memory array, a magnetic memory array, a static random access memory array, a dynamic random access memory array or a flash memory array.
10. The method for preparing the three-dimensional heterogeneous integrated chip according to claim 6, further comprising the following steps: preparing and forming a conductive bump (6) on the surface of the first conductive channel (4), wherein the conductive bump (6) is connected with the first conductive channel (4).
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