KR101637583B1 - Light emitting device and fabrication method thereof - Google Patents

Abstract

The embodiments relate to a light emitting device and a manufacturing method thereof.
A light emitting device according to an embodiment includes a substrate; A plurality of metal layers below the substrate; A plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on the substrate; A first connecting member electrically connected to one of the first conductive semiconductor layer and the plurality of metal layers; And a second connecting member electrically connected to the second conductive type semiconductor layer and another metal layer of the plurality of metal layers.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a light emitting device,

The embodiments relate to a light emitting device and a manufacturing method thereof.

BACKGROUND ART Light emitting diodes (LEDs) are a kind of semiconductor devices that convert the electric power to infrared rays or light using the characteristics of compound semiconductors, exchange signals, or use as a light source.

 Light emitting diodes (LEDs) or light emitting diodes (LD) using the nitride semiconductor materials, and are used as light sources for various products such as a keypad light emitting portion of a cellular phone, an electric sign board, and a lighting device.

Embodiments provide a light emitting device in which a substrate on which a semiconductor layer is grown and a semiconductor layer thereon are packaged, and a method of manufacturing the same.

Embodiments provide a light emitting device in which a plurality of electrode layers and a semiconductor layer are packaged on a substrate, and a method of manufacturing the same.

 A light emitting device according to an embodiment includes a substrate; A plurality of metal layers below the substrate; A plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on the substrate; A first connecting member electrically connected to one of the first conductive semiconductor layer and the plurality of metal layers; And a second connecting member electrically connected to the second conductive type semiconductor layer and another metal layer of the plurality of metal layers.

A method of manufacturing a light emitting device according to an embodiment of the present invention includes: forming first and second metal layers on a substrate; Forming a plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on the substrate; Electrically connecting the first conductive type semiconductor layer and the first metal layer; Electrically connecting the second conductive type semiconductor layer and the second metal layer; And forming a resin layer covering the plurality of compound semiconductor layers on the substrate.

In this embodiment, since the substrate and the semiconductor layer thereon are packaged, there is no need to perform a separate packaging process.

Embodiments can provide a package of a light emitting device in which a growth substrate is disposed on a bottom surface.

Embodiments can provide a light emitting device package in which a semiconductor layer and an electrode layer are disposed on a growth substrate.

Embodiments provide a light emitting device that can be packaged as a unit chip and then separated into individual packages.

The embodiment can improve the reliability of the light emitting device.

1 is a side sectional view showing a light emitting device according to a first embodiment.
FIGS. 2 to 9 are views illustrating a manufacturing process of the light emitting device of FIG.
10 and 11 are side cross-sectional views illustrating a light emitting device according to the second embodiment.
12 is a side sectional view showing a light emitting device according to the third embodiment.
13 is a side sectional view showing a light emitting device according to the fourth embodiment.
14 is a side sectional view showing a light emitting device according to a fifth embodiment.

In describing the above embodiments, it is to be understood that each layer (film), area, pattern or structure may be referred to as being "on" or "under" a substrate, each layer Quot; on "and" under "include both the meaning of" directly "and" indirectly ". In addition, the criteria for above or below each layer will be described with reference to the drawings. The thickness and size of each layer in the drawings are exaggerated, omitted, or schematically shown for convenience and clarity of explanation. Also, the size of each component does not entirely reflect the actual size. The technical features of the embodiments are not limited to the embodiments, but can be selectively applied to other embodiments.

Hereinafter, embodiments will be described with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a light emitting device according to a first embodiment.

1, a light emitting device 100 includes a substrate 110, a plurality of compound semiconductor layers 121 to 124, a current diffusion layer 125, a first electrode 126, a second electrode 127, The first metal layer 112, the second metal layer 113, the first insulating layer 114, the second insulating layer 128, the first through hole 116, the second through hole 117, the third metal layer 118, A fourth metal layer 119, a first wire 131, a second wire 132, and a resin layer 140.

The light emitting device 100 is implemented by an LED including a compound semiconductor of a plurality of compound semiconductor layers 121 to 124, for example, a group III-V element, and the LED may emit light such as blue, green, It can be a colored LED or a UV LED. The emitted light of the LED may be implemented using various semiconductors within the technical scope of the embodiment.

The substrate 110 is a growth substrate on which a compound semiconductor can be grown. For example, the substrate 110 may be formed of an insulating material or a conductive material, and may be used as a material having a small difference in lattice constant or a small difference in thermal expansion coefficient . The substrate 110 may be selected from the group consisting of Al ₂ O ₃ , SiC, Si, GaAs, GaN, ZnO, Si, GaP, InP, Ga ₂ O ₃ and LiGaO ₃ . Hereinafter, a growth substrate will be described as an example of the substrate 110 in the embodiment. The thickness of the substrate 110 is about 100 to 400 μm, and may vary depending on the lapping and / or polishing of the substrate.

A concavo-convex pattern may be formed on the top surface or the top surface of the substrate 110, and the concavo-convex pattern may be periodically or irregularly spaced to change the critical angle of incident light. By changing the critical angle of the proceeding light, the light extraction efficiency can be improved.

A plurality of compound semiconductor layers 121 to 124 may be formed on the substrate 110. The plurality of compound semiconductor layers 121 to 124 may include a layer or a pattern using a compound semiconductor of Group 2 to Group 6 elements. The material may be ZnO, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN , AlGaAs, GaP, GaAs, GaAsP, AlGaInP, or the like. The plurality of compound semiconductor layers 121 to 124 may include a buffer layer 121, a first conductivity type semiconductor layer 122, an active layer 123, and a second conductivity type semiconductor layer 124, for example.

The buffer layer 121 is formed on the substrate 110 and reduces the difference in lattice constant and / or thermal expansion coefficient between the substrate 110 and the semiconductor. An undoped semiconductor layer (not shown) is formed on the buffer layer 121, and the undoped semiconductor layer may be formed of undoped GaN based semiconductor that is intentionally not doped. The buffer layer 121 and the undoped semiconductor layer may not be formed.

A DBR (Distributed Bragg reflector) structure having a light extraction structure or having different refractive indexes, for example, a low refractive index layer and a high refractive index layer may be alternately arranged above and / or below the buffer layer 121 to improve light reflection efficiency By stacking the stacked semiconductor layers (for example, GaN / AlN) over two or more cycles, light traveling in the direction of the substrate can be efficiently reflected.

A first conductive semiconductor layer 122 is formed on the buffer layer 121. An active layer 123 is formed on the first conductive semiconductor layer 122 and a second conductive semiconductor layer 122 is formed on the active layer 123. [ (124) are formed. Other semiconductor layers may be disposed above or below the respective layers, but the present invention is not limited thereto.

The first conductive semiconductor layer 122 may be a compound semiconductor of a group III-V element doped with a first conductive type dopant such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like. When the first conductive type is an N type semiconductor, the first conductive type dopant includes N type dopants such as Si, Ge, Sn, Se, and Te. The first conductive semiconductor layer 122 may be formed as a single layer or a multilayer, but the present invention is not limited thereto. The first conductive semiconductor layer 122 may have the same or different area as the active layer 123, but the present invention is not limited thereto.

An active layer 123 may be formed on the first conductive semiconductor layer 122 and the active layer 123 may have a single quantum well structure or a multiple quantum well structure. The active layer 123 may be formed of a Group III-V compound semiconductor material, such as a period of a well layer and a barrier layer, for example, a period of an InGaN well layer / a GaN barrier layer, a period of an InGaN well layer / And a period of the InGaN well layer / InGaN barrier layer.

A conductive clad layer may be formed on and / or below the active layer 123, and the conductive clad layer may be formed of a GaN-based semiconductor.

The second conductivity type semiconductor layer 124 is formed on the active layer 123 and the second conductivity type semiconductor layer 124 is formed of a compound semiconductor of a group III-V element doped with a second conductivity type dopant, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and the like. When the second conductivity type is a P-type semiconductor, the second conductivity type dopant includes a P-type dopant such as Mg, Zn, or the like. The second conductive semiconductor layer 124 may be formed as a single layer or a multilayer, but is not limited thereto.

A third conductive type semiconductor layer, for example, a semiconductor layer having a polarity opposite to that of the second conductive type may be formed on the second conductive type semiconductor layer 124. Accordingly, the compound semiconductor layers 121-124 may include at least one of an N-P junction, a P-N junction, an N-P-N junction, and a P-N-P junction structure. In the following description, the structure in which the second conductivity type semiconductor layer 124 is disposed on the uppermost layer of the plurality of compound semiconductor layers 121 to 124 will be described as an example.

A current diffusion layer 125 is formed on the second conductive semiconductor layer 124. The current diffusion layer 125 diffuses current on the second conductive semiconductor layer 124 and functions as a light transmitting layer. The current diffusion layer 125 may not be formed and may be changed within the technical scope of the embodiment.

The current diffusion layer 125 may include a transparent oxide or a transparent nitride and may be formed of one selected from the group consisting of ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc oxide), IAZO (indium aluminum zinc oxide), IGZO gallium zinc oxide, indium gallium tin oxide (IGTO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), and gallium zinc oxide (GZO). The current diffusion layer 125 may not be formed, but the present invention is not limited thereto.

The second electrode 127 may be in contact with at least one of the second conductive semiconductor layer 124 and the current diffusion layer 125 and may be formed in a predetermined pattern such as a radial pattern, A pattern, a straight pattern, a polygonal pattern, a circular pattern, or the like, or a plurality of patterns may be selectively mixed. However, the present invention is not limited thereto. The second electrode 127 may be formed of one or more of Ti, Al, Al alloy, In, Ta, Pd, Co, Ni, Si, Ge, Ag, Ag alloy, Hf, Pt, And may be formed as a single layer or multiple layers.

The first electrode 126 may be formed on the first conductive semiconductor layer 122. The first electrode 126 may include a pad or a predetermined pattern and may be formed of any one or more of Cu, Ti, Cr, Ta, Al, In, Pd, Co, Ni, Ge, Ag, The present invention is not limited thereto. The exposed area of the first conductivity type semiconductor layer 122 may be several times smaller than the top side area of the second conductivity type semiconductor layer 124.

Here, the plurality of compound semiconductor layers 121 to 124, the first electrode 126, the second electrode 127, the current diffusion layer 125, and the second insulating layer 128 are defined as individual chips 120 .

A first metal layer 112 and a second metal layer 113 may be formed on the upper surface of the substrate 110. The first metal layer 112 may be disposed on one side of the upper surface of the substrate and on one side of the plurality of compound semiconductor layers 121-124. The second metal layer 113 is formed on the upper surface of the substrate and is disposed on the other side of the plurality of compound semiconductor layers 121-124. Here, the lower surfaces of the plurality of compound semiconductor layers 121 to 124 and the lower surfaces of the first metal layer 112 and the second metal layer 113 may be disposed on the same plane. The first metal layer 112 and the second metal layer 113 may be disposed between the plurality of compound semiconductor layers 121-124.

The first metal layer 112 and the second metal layer 113 may be made of any one material selected from among Cu, Ti, Cr, Ta, Al, In, Pd, Co, Ni, Ge, Ag, But it is not limited thereto.

The buffer layer 121 of the plurality of compound semiconductor layers 121-124 may or may not be in contact with the first metal layer 112 and the second metal layer 113. The first metal layer 112 and the second metal layer 113 may prevent electrical contact with the first conductive type semiconductor layer 122 or prevent electrical contact with the second metal layer 113 .

A second insulating layer 128 is formed on the upper surface and side surfaces of the plurality of compound semiconductor layers 121 to 124 and a portion of the upper surface of the second metal layer 113. The second insulating layer 128 may include a plurality of Layer short-circuiting of the compound semiconductor layers 121-124, protects the chip, and improves the light extraction efficiency to the surface of the semiconductor layer.

The second metal layer 113 and the second electrode 127 are electrically connected by a second connecting member and the first metal layer 112 and the first electrode 126 are electrically connected to each other by a first connecting member. Lt; / RTI > The connecting member functions as an electrical connecting means such as a wire or a metal layer.

The second connecting member may be a wire 131 connected to the second metal layer 113 and the second electrode 127. The first connecting member may connect the first metal layer 112 and the first electrode 127, And a second wire 131 connected to the second wire 126. The second connecting member and the first connecting member may pattern the metal layer without using the wires 131 and 132 to connect the metal layer and the electrodes to each other. That is, at least one of the first wire 131 and the second wire 132 can be used as a metal layer, and technical modifications of this embodiment can be implemented within the scope of the embodiments.

The first insulating layer 114 may be formed around the upper surface of the substrate 110, and the outer surface of the first insulating layer 114 may be exposed to the outside of the unit package. A part of the first insulating layer 114 is disposed on the upper surfaces of the first metal layer 112 and the second metal layer 113 and the first metal layer 112 and the second metal layer 113 Exposed to the outside of the unit package. The first insulating layer 114 may be formed along the upper side of the substrate 110.

A third metal layer 118 and a fourth metal layer 119 are formed on a lower surface of the substrate 110 and a portion of the third metal layer 118 corresponds to the first metal layer 112, And a part of the second metal layer 119 corresponds to the second metal layer 113. [ That is, the first metal layer 112 and the third metal layer 118 are disposed on both sides of the substrate 110, and the second metal layer 113 and the fourth metal layer 119 are disposed on both sides of the substrate 110 .

At least one first through hole 116 is disposed on one side of the substrate 110 and at least one second through hole 117 is disposed on the other side. The first through hole 116 penetrates the first metal layer 112, the substrate 110 and the third metal layer 118 vertically, and the first metal layer 112 and the third metal layer 118 ). The second through hole 117 vertically penetrates the second metal layer 113, the substrate 110 and the fourth metal layer 119, and the second metal layer 113 and the fourth metal layer 119 ).

The first through hole 116 and the second through hole 117 may be formed of a conductive via including a metal and a height equal to or greater than the thickness of the substrate 110. The first through holes 116 and the second through holes 117 may be formed of any one of Cu, Cr, Ti, Al, Al alloy, In, Ta, Pd, Co, Ni, Si, Ge, Ag, Pt, Ru, and Au.

The diameter of the first through hole 116 and the diameter of the second through hole 117 may be 0.5 to 50 μm and may be a straight line or a non-straight line perpendicular to the bottom surface of the substrate.

A resin layer 140 is formed on the plurality of compound semiconductor layers 121-124 and the resin layer 140 may be formed of a resin material such as silicon or epoxy or a light transmitting insulating material, Of the refractive index of the light-transmissive material.

The resin layer 140 may include at least one of a fluorescent material such as a yellow fluorescent material, a red fluorescent material, a green fluorescent material, and a blue fluorescent material,

The resin layer 140 may be formed on the substrate 110 in a predetermined shape such as hemispherical or polyhedral shape and the height of the resin layer 140 may be higher than the upper ends of the wires 131 and 132 . The lower part of the resin layer 140 is formed to cover the entire upper surface of the substrate 110. This is because when the resin layer 140 is viewed from the top side of the resin layer 140, But may not be protruded from the region.

FIGS. 2 to 9 are views illustrating a manufacturing process of the light emitting device of FIG.

Referring to FIGS. 2 and 3, a metal layer 111 is formed on both sides of the first region A1 on the substrate 110. FIG. The metal layer 111 may be disposed in a boundary region of the unit package.

Here, the formation time of the metal layer 111 may be formed after the growth of the compound semiconductor layer. In this case, the metal layer may be formed after the compound semiconductor layer is formed after the metal layer region is masked.

3 and 4, a plurality of compound semiconductor layers 121 to 124 are formed on a first region A1 of the substrate 110, and a plurality of compound semiconductor layers 121 to 124 are formed on the plurality of compound semiconductor layers 121 to 124, (125) may be formed.

The plurality of compound semiconductor layers 121 to 124 may be grown using an electron beam evaporator, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual- Sputtering, metal organic chemical vapor deposition (MOCVD), or the like, and the present invention is not limited thereto.

The plurality of compound semiconductor layers 121 to 124 include a buffer layer 121, a first conductivity type semiconductor layer 122, an active layer 123 and a second conductivity type semiconductor layer 124. The buffer layer 121, The first conductive semiconductor layer 122, the active layer 123, and the second conductive semiconductor layer 124 may be formed using Group III-V compound semiconductors. . The first conductive semiconductor layer 122 may include an n-type semiconductor layer and the second conductive semiconductor layer 124 may include a p-type semiconductor layer. The first conductive semiconductor layer 122 may include a p- And the second conductive semiconductor layer 124 may be formed of an n-type semiconductor layer. A semiconductor having a polarity opposite to that of the first conductivity type may be formed on the second conductivity type semiconductor layer 124. Accordingly, the plurality of compound semiconductor layers 121 to 124 may include at least one of an n-p junction, a p-n junction, an n-p-n junction, and a p-n-p junction. Hereinafter, for convenience of description of the embodiments, the uppermost layer of the plurality of compound semiconductor layers 121 to 124 is described as an example in which the second conductivity type semiconductor layer 124 is disposed.

The current diffusion layer 125 may be formed on the upper surface of the second conductive semiconductor layer 124, but the present invention is not limited thereto. The current diffusion layer 125 may be formed of a transparent electrode material, but the present invention is not limited thereto.

A part of the first conductive type semiconductor layer 122 may be exposed by performing the mesa etching.

A first electrode 126 is formed on a part of the first conductivity type semiconductor layer 122 and a second electrode 127 is formed on the current diffusion layer 125 and / . The second electrode 127 may be in contact with the second conductive semiconductor layer 124 directly or indirectly.

Here, the plurality of compound semiconductor layers 121 to 124, the first electrode 126, the second electrode 127, the current diffusion layer 125, and the second insulating layer 128 may be formed of the individual chips 120, Can be defined as a structure.

The first insulating layer 114 may be formed at the boundary of the unit package 1P. The first insulating layer 114 is formed on the upper side of the substrate 110 and around the metal layer 111. The first insulating layer 114 may be formed at a boundary portion of the unit package to enhance adhesion with the resin layer 140. The first insulating layer 114 may be disposed in the center region of the metal layer 111 under the first insulating layer 114, but the present invention is not limited thereto.

The first insulating layer 114 may be formed on the surface of the plurality of compound semiconductor layers 121-124. The first insulating layer 114 may be formed in a region excluding the metal layer 111 and the bonding portions of the first electrode 126 and the second electrode 127.

Referring to FIGS. 5 and 6, a third metal layer 118 and a fourth metal layer 119 may be formed under the substrate 110. The third metal layer 118 and the fourth metal layer 119 are disposed on both sides of the unit package and are electrically separated. The third metal layer 118 and the fourth metal layer 119 may be used as external terminals.

Holes are formed through the metal layer 111, the third metal layer 118, and the fourth metal layer 119 using a device such as a drill or a laser. By forming a conductive via using a metal in these holes, the first through hole 116 and the second through hole 117 can be formed. The first through hole 116 and the second through hole 117 may be formed by a plating method and / or a filling method, but the present invention is not limited thereto.

The first through hole 116 connects the first metal layer 112 disposed on one side of the substrate 110 with the third metal layer 118 and the second through hole 117 connects the substrate 110 ) Between the second metal layer 113 and the fourth metal layer 119 disposed on the other side.

6 and 7, one side of the first electrode 126 and one side of the metal layer 111 are connected to each other by a first connecting member, and the other side of the second electrode 127 and the metal layer 111 is connected to the second side And are connected to each other by a connecting member. The first connecting member is bonded to the first electrode and the metal layer 111 as a first wire 131 and the second connecting member is bonded to the second electrode 127 as the second wire 132, And is bonded to the other side of the metal layer 111.

The first connecting member may be formed by connecting the first electrode 126 or the first conductive type semiconductor layer 122 and one side of the metal layer 111 with a patterned metal layer instead of the first wire 131, . The second electrode 127 or the second conductivity type semiconductor layer 124 and the opposite side of the metal layer 111 may be connected to each other by a patterned metal layer instead of the second wire 132 as the second connecting member. have.

Referring to FIGS. 7 and 8, a resin layer 140 is formed on the substrate 110. The resin layer 140 may be formed of a material such as silicon or epoxy to have a hemispherical shape or a polyhedral shape, but the present invention is not limited thereto. The resin layer 140 may be formed by injection molding or transfer molding, but the present invention is not limited thereto.

A phosphor may be added to the resin layer 140. The fluorescent material may be a colored fluorescent material such as yellow, red, green, blue, etc., but is not limited thereto.

Referring to FIGS. 8 and 9, the unit package is cut. The package cutting method can be cut using a cutting device, a laser, and a braking device, but is not limited thereto.

10 and 11 are views illustrating a process of manufacturing a light emitting device according to the second embodiment. The second embodiment will refer to the embodiments disclosed above.

Referring to FIGS. 10 and 11, a reflective layer 130 is formed under the substrate 110 in the light emitting device 100A. The reflective layer 130 may be formed on the opposite side of the plurality of compound semiconductor layers 121-124 and may be formed to have a larger area than the plurality of compound semiconductor layers 121-124.

The reflective layer 130 may effectively reflect light emitted from the plurality of compound semiconductor layers 121 to 124 toward the substrate 110, which may improve the light extraction efficiency.

The reflective layer 130 may be separated from the third metal layer 118 and the fourth metal layer 119 or may be in electrical contact with any metal layer. The reflective layer 130 may be used as a heat dissipating member, but the present invention is not limited thereto. Also, as the heat dissipating member, a concave-convex pattern may be formed under the substrate 110 to increase the heat radiation area.

Embodiments may provide a relief pattern on at least one of the substrate 110 and the substrate 110 to improve the light extraction efficiency.

12 is a side sectional view showing a light emitting device according to the third embodiment. The third embodiment will refer to the embodiments disclosed above.

Referring to FIG. 12, the light emitting device 100B includes a phosphor layer 135 on a chip. The phosphor layer 135 may be coated on the current diffusion layer 125 or may be attached in a film form. The phosphor layer 135 may selectively include a yellow phosphor, a red phosphor, a green phosphor, and a blue phosphor. However, the present invention is not limited thereto.

The phosphor layer 135 may be formed before or after the second insulating layer 128 is formed, but the present invention is not limited thereto.

The phosphor layer 135 converts part of the first light passing through the current diffusion layer 125 into second light having a long wavelength. The mixed light of the first light and the second light is emitted from the light emitting element 100B The light is emitted by the target light.

13 is a side sectional view showing a light emitting device according to the fourth embodiment. The fourth embodiment will refer to the embodiments disclosed above.

Referring to FIG. 13, the light emitting device 100C does not expose a part of the first conductivity type semiconductor layer 122. Accordingly, it is possible to prevent the area of the active layer 123 from being reduced by the mesa etching.

The first through hole 116A electrically connects the first conductive type semiconductor layer 122 and the fourth metal layer 118A. One or a plurality of the first through holes 116A may be disposed, and the hole diameter, the hole pattern, and the like may be changed for the current injection efficiency into the first conductive type semiconductor layer 122. [

Here, the first through hole 116A may be formed to have a lower height than the upper surface of the first conductive type semiconductor layer 122.

The third metal layer 118A may serve as a reflection electrode and is not limited thereto. Accordingly, the first metal layer (112 in FIG. 1) may not be formed on the substrate 110. Further, by removing the first wire, the wire bonding process can be omitted. The embodiment is not limited to the first insulating layer, but may be disposed for adhesion with the resin layer 140, but is not limited thereto.

14 is a side sectional view showing a light emitting device according to a fifth embodiment. The fifth embodiment will refer to the embodiments disclosed above.

14, the light emitting device 100D includes a roughness 105 between the substrate 110 and the reflective layer 130. The roughness 105 is formed in the rough surface of the substrate, Since the reflective layer 130 is formed on the surface of the reflective layer 130, the roughness 105 of the reflective layer 130 can reflect and change the critical angle of the incident light, thereby improving the light extraction efficiency.

In an embodiment, after disposing a plurality of metal layers separated from each other below the substrate, the plurality of metal layers may be electrically connected to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer by a plurality of connection members separated from each other . The connecting member may be a patterned metal

The light emitting device according to the embodiment (s) may be packaged with a chip on the substrate and die-bonded on the module substrate. At least one of the light emitting devices may be arrayed to form an indicator, a lighting device, a display device As shown in FIG. The above-described embodiments are not limited to the embodiments, but can be selectively applied to other embodiments described above, and the present invention is not limited to these embodiments.

The features, structures, effects and the like described in the embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to one embodiment. Furthermore, the features, structures, effects and the like illustrated in the embodiments can be combined and modified by other persons skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

A semiconductor light emitting device includes a first conductive semiconductor layer and a second conductive semiconductor layer, wherein the first conductive semiconductor layer is formed on the first conductive semiconductor layer, and the second conductive semiconductor layer is formed on the first conductive semiconductor layer. Wherein the first metal layer comprises a first metal layer and a second metal layer is formed on the first metal layer and the second metal layer is formed on the first metal layer. A fourth metal layer, 131: a first wire, 132: a second wire, 140: a resin layer

Claims (26)

Board;
A plurality of metal layers below the substrate;
A plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on the substrate;
A first connecting member electrically connected to one of the first conductive semiconductor layer and the plurality of metal layers; And
And a second connecting member electrically connected to the second conductive type semiconductor layer and another metal layer of the plurality of metal layers,
And a reflective layer formed on the opposite side of the plurality of compound semiconductor layers under the substrate. The light emitting device according to claim 1, wherein the substrate is a growth substrate and comprises any one of Al ₂ O ₃ , SiC, Si, GaAs, GaN, ZnO, Si, GaP, InP, Ga ₂ O ₃ , and LiGaO ₃ . The light emitting device of claim 1, further comprising a first metal layer disposed on one side of the substrate and electrically connected to a metal layer connected to the first conductivity type semiconductor layer. The light emitting device of claim 3, further comprising a second metal layer disposed on the other surface of the substrate and electrically connected to the metal layer connected to the second conductivity type semiconductor layer. The semiconductor light emitting device of claim 4, further comprising: a first through hole for connecting the first metal layer and the metal layer connected to the first conductive type semiconductor layer to each other; And a second through hole connecting the second metal layer and the metal layer connected to the second conductivity type semiconductor layer to each other. The method of claim 5, further comprising: a first connecting member including at least one of a metal pattern and a wire connecting the first metal layer and the metal layer connected to the first conductive type semiconductor layer to each other; And a second connecting member including at least one of a metal pattern and a wire connecting the second metal layer and the second conductive type semiconductor layer. The plasma display panel of claim 1, further comprising: a second metal layer disposed on the other side of the upper surface of the substrate; A second through hole for connecting a metal layer electrically connected to the second conductive type semiconductor layer to the second metal layer under the substrate; And a second wire or metal pattern connecting the second metal layer and the second conductive type semiconductor layer. The light emitting device of claim 1 or 7, further comprising: a first through hole for connecting a metal layer electrically connected to the first conductivity type semiconductor layer and the first conductivity type semiconductor layer. The organic electroluminescent device according to claim 1, wherein the plurality of compound semiconductor layers are formed of a Group 2 to Group 6 compound semiconductor layer on the substrate; A first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, and a second conductive semiconductor layer on the second conductive semiconductor layer, . 7. The light emitting device of claim 6, further comprising: a first electrode formed on the first conductive semiconductor layer; And a second electrode formed on the second conductive semiconductor layer. The light emitting device of claim 6, further comprising a current diffusion layer including a transparent electrode formed on the second conductivity type semiconductor layer. The light emitting device according to claim 1, wherein the reflective layer is larger than the bottom area of the plurality of compound semiconductor layers. The light emitting device according to claim 1, further comprising a roughness between the reflective layer and the substrate. The semiconductor light emitting device of claim 6, further comprising: a first electrode connected to the first connection member on the first conductive type semiconductor layer; And a second electrode connected to the second connection member on the second conductive type semiconductor layer. The light emitting device of claim 1, further comprising a first insulating layer disposed on an upper surface of the substrate. The light emitting device according to claim 1 or 15, comprising a resin layer covering the plurality of compound semiconductor layers on the substrate. The light emitting device according to claim 16, wherein the resin layer has a hemispherical or polyhedral shape and covers the entire upper side of the substrate. The light emitting device according to claim 16, further comprising a phosphor layer between the plurality of compound semiconductor layers and the resin layer. Forming first and second metal layers on the substrate;
Forming a plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on the substrate;
Electrically connecting the first conductive type semiconductor layer and the first metal layer;
Electrically connecting the second conductive type semiconductor layer and the second metal layer; And
And forming a resin layer covering the plurality of compound semiconductor layers on the substrate,
And a reflective layer formed on the opposite side of the plurality of compound semiconductor layers under the substrate. delete delete delete delete The light emitting device according to claim 19, wherein a third metal layer electrically connected to the first conductivity type semiconductor layer is formed under the substrate, and a fourth metal layer electrically connected to the second conductivity type semiconductor layer is formed under the substrate Lt; / RTI > delete delete

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