KR101617374B1 - 에러 검출 기법들에 의거한 메모리 쓰기 타이밍의 조정 - Google Patents

에러 검출 기법들에 의거한 메모리 쓰기 타이밍의 조정 Download PDF

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KR101617374B1
KR101617374B1 KR1020127008686A KR20127008686A KR101617374B1 KR 101617374 B1 KR101617374 B1 KR 101617374B1 KR 1020127008686 A KR1020127008686 A KR 1020127008686A KR 20127008686 A KR20127008686 A KR 20127008686A KR 101617374 B1 KR101617374 B1 KR 101617374B1
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result
timing
clock signal
data bits
write
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KR20120062870A (ko
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아론 제이. 니그렌
밍-주 이. 리
샤디 엠. 바라캇
지아오링 수
토안 디. 팜
워렌 프릿츠 크루거
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Information Transfer Systems (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
  • Debugging And Monitoring (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
KR1020127008686A 2009-09-09 2010-09-09 에러 검출 기법들에 의거한 메모리 쓰기 타이밍의 조정 Active KR101617374B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US24069909P 2009-09-09 2009-09-09
US61/240,699 2009-09-09
US12/846,958 2010-07-30
US12/846,958 US8862966B2 (en) 2009-09-09 2010-07-30 Adjustment of write timing based on error detection techniques

Publications (2)

Publication Number Publication Date
KR20120062870A KR20120062870A (ko) 2012-06-14
KR101617374B1 true KR101617374B1 (ko) 2016-05-02

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KR1020127008686A Active KR101617374B1 (ko) 2009-09-09 2010-09-09 에러 검출 기법들에 의거한 메모리 쓰기 타이밍의 조정

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Country Link
US (1) US8862966B2 (https=)
EP (1) EP2476062B1 (https=)
JP (1) JP5805643B2 (https=)
KR (1) KR101617374B1 (https=)
CN (1) CN102576342B (https=)
IN (1) IN2012DN02970A (https=)
WO (1) WO2011031847A1 (https=)

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US10756847B2 (en) 2016-12-22 2020-08-25 Samsung Electronics Co., Ltd. Electronic device and method for detecting error thereof

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KR20120011491A (ko) * 2010-07-29 2012-02-08 주식회사 하이닉스반도체 반도체 시스템 및 그 데이터 트래이닝 방법
US8930776B2 (en) * 2012-08-29 2015-01-06 International Business Machines Corporation Implementing DRAM command timing adjustments to alleviate DRAM failures
TWI522772B (zh) * 2012-10-17 2016-02-21 Automatic transmission interface device and method for correcting transmission frequency
BR122016006764B1 (pt) 2013-03-15 2022-02-01 Intel Corporation Aparelhos e métodos de memória
US10163508B2 (en) 2016-02-26 2018-12-25 Intel Corporation Supporting multiple memory types in a memory slot
US10459855B2 (en) 2016-07-01 2019-10-29 Intel Corporation Load reduced nonvolatile memory interface
DE102018115100A1 (de) * 2018-06-22 2019-12-24 Krohne Messtechnik Gmbh Verfahren zur Fehlerbehandlung bei Buskommunikation und Buskommunikationssystem
US11601825B2 (en) * 2018-08-08 2023-03-07 Faraday&Future Inc. Connected vehicle network data transfer optimization
KR102685470B1 (ko) * 2018-12-24 2024-07-17 에스케이하이닉스 주식회사 트래이닝 기능을 갖는 반도체 장치 및 반도체 시스템
CN113227925B (zh) * 2018-12-27 2022-07-29 三菱电机株式会社 数据收集装置、方法及记录有程序的计算机可读取的记录介质

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WO2009108562A2 (en) 2008-02-25 2009-09-03 Rambus Inc. Code-assisted error-detection technique

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US6198688B1 (en) * 1998-04-02 2001-03-06 Hyundai Electronics Industries, Co., Ltd. Interface for synchronous semiconductor memories
US6801989B2 (en) * 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US6877103B2 (en) * 2001-10-05 2005-04-05 Via Technologies, Inc. Bus interface timing adjustment device, method and application chip
SE524201C2 (sv) 2002-12-17 2004-07-06 Lars-Berno Fredriksson Anordning vid distribuerat styr- och övervakningssystem
US6920524B2 (en) * 2003-02-03 2005-07-19 Micron Technology, Inc. Detection circuit for mixed asynchronous and synchronous memory operation
US7000170B2 (en) * 2003-02-04 2006-02-14 Lsi Logic Corporation Method and apparatus for generating CRC/parity error in network environment
JP2005141725A (ja) 2003-10-16 2005-06-02 Pioneer Plasma Display Corp メモリアクセス回路、そのメモリアクセス回路の動作方法およびそのメモリアクセス回路を用いる表示装置
DE102005019041B4 (de) * 2005-04-23 2009-04-16 Qimonda Ag Halbleiterspeicher und Verfahren zur Anpassung der Phasenbeziehung zwischen einem Taktsignal und Strobe-Signal bei der Übernahme von zu übertragenden Schreibdaten
JP2008152315A (ja) * 2006-12-14 2008-07-03 Sanyo Electric Co Ltd 信号処理回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009055103A2 (en) 2007-10-22 2009-04-30 Rambus, Inc. Low-power source-synchronous signaling
WO2009108562A2 (en) 2008-02-25 2009-09-03 Rambus Inc. Code-assisted error-detection technique

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10756847B2 (en) 2016-12-22 2020-08-25 Samsung Electronics Co., Ltd. Electronic device and method for detecting error thereof

Also Published As

Publication number Publication date
EP2476062B1 (en) 2014-02-26
JP2013504817A (ja) 2013-02-07
IN2012DN02970A (https=) 2015-07-31
US8862966B2 (en) 2014-10-14
KR20120062870A (ko) 2012-06-14
US20110185256A1 (en) 2011-07-28
CN102576342B (zh) 2015-07-01
CN102576342A (zh) 2012-07-11
EP2476062A1 (en) 2012-07-18
WO2011031847A1 (en) 2011-03-17
JP5805643B2 (ja) 2015-11-04

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