KR101585252B1 - Method for driving liquid crystal display device - Google Patents

Abstract

The present invention discloses a liquid crystal display device driving method. The disclosed invention includes a plurality of stages in which a display-ON period in which a liquid crystal display is displayed and a power-up period in which a liquid crystal display is not displayed are defined and a gate driving signal is sequentially output from the display ON period, A scan control unit which receives a gate start pulse signal and a gate scan direction signal from the scan control unit and controls the current stage to output no gate drive signal in the power up period, And an output unit for sequentially outputting a clock signal as a gate driving signal in accordance with the control of the scan control unit and the internal circuit, the gate driving driver comprising: a gate driver for supplying a gate start pulse signal to the scan control unit,The scan start signal is supplied with a low level voltage and the gate start pulse signal supplied to the scan control unit is supplied with a high level voltage having the same period as the clock signal supplied to the output unit, And the gate scan direction signal is supplied at a high level during the display-on period.

Description

[0001] The present invention relates to a method of driving a liquid crystal display device,

The present invention relates to a liquid crystal display device, in particular, to prevent an initial abnormal operation of a gate driver.

[0003] In the information society, a flat panel display device capable of displaying information has been widely developed. The flat panel display includes a liquid crystal display, an organic electro-luminescence display device, a plasma display device, and a field emission display device.

Such display devices may include a drive driver for driving the panel. The driving driver includes a gate driver and a data driver.

FIG. 1 is a block diagram showing a general liquid crystal display device, and FIG. 2 is a block diagram showing the gate driver of FIG.

1, the liquid crystal display includes a liquid crystal display panel 13, a gate driver 11, a data driver 12, and a timing controller 10.

The gate driver 11 drives the liquid crystal display panel 13 line by line and the data driver 12 supplies the data voltage for each line of the liquid crystal display panel 13 And the timing controller 10 controls the gate driver 11 and the data driver 12.

The timing controller 10 generates a control signal for controlling the gate driver 11 and the data driver 12.

For example, the timing controller 10 generates the start signal Vst and the first to fourth gate clock signals GCLK1 to GCLK4 to control the gate driver 11. However, it can use only two GCL1 and GCL2 depending on the circuit diagram.

The timing controller 10 generates a source start pulse (SSP), a source shift clock (SSC), a source output enable (SOE), and a POL to control the data driver 12.

The gate driver 11 is formed directly on the liquid crystal display panel 13. [ This structure is called a gate in panel. The gate driver 11 is manufactured at the same time when the liquid crystal display panel 13 is manufactured.

As shown in Fig. 2, the gate driver 11 is provided with a plurality of stages ST1 to STn. The stages ST1 to STn are connected to each other in a dependent manner. Each of the stages ST1 to STn receives three gate clock signals among the first to fourth gate clock signals GCLK1 to GCLK4 sequentially supplied thereto and an output signal of the previous stage. In the first stage ST1, since there is no stage in the previous stage, a separate start signal Vst is input.

Each of the stages ST1 to STn receives the output signal of the previous stage and three gate clock signals among the first to fourth gate clock signals GCLK1 to GCLK4 and outputs the output signals Vg1 to Vgn. The output signals Vg1 to Vgn output from the stages ST1 to STn are supplied to the gate lines of the liquid crystal panel 130. [

The internal circuit configurations of the stages ST1 to STn are the same.

3 is a diagram showing an output waveform of a gate signal due to an initial abnormal operation of a gate driver according to the related art. As shown in FIG. 3, it can be seen that the gate driving signal is generated in the form of a multi-gate driving signal.

This is because, when the first stage is driven, the gate start pulse GSP is input to the stage in the state that the gate scan direction signal is "high ", and the gate low voltage VGL, which serves as a ground in the stage, (-5 V at -7 V).

This is because when the gate low voltage VGL rises, it becomes larger than the "low" level voltage of the clock (CLK) signal, and the transistor of the stage output terminal is turned on by the gate low voltage VGL. As described above, even if the transistor is turned on, the present stage is not internally applied with the gate low voltage applied by the previous single stage to the gate terminal of the transistor of the stage output stage.

Further, since the gate driving circuit of the conventional liquid crystal display device as described above consumes current even during the blank display period, there is a problem in power loss.

It is an object of the present invention to provide a method of driving a liquid crystal display device in which a gate scanning direction signal is added so that a gate driver does not generate a multi-gate driving signal from the first frame.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device including a display-on period during which a liquid crystal display device is displayed and a power-up period during which a display is not performed, Wherein each stage includes a scan control unit for receiving a gate start pulse signal and a gate scan direction signal from the front stage and controlling the current stage not to output a gate driving signal in the power up period, An internal circuit for controlling an output of a gate driving signal together with a scan control unit and an output unit for sequentially outputting a clock signal as a gate driving signal under the control of the scan control unit and the internal circuit, In the interval, The gate start pulse signal and the gate scan direction signal supplied to the control unit are supplied with a low level voltage. When the display on period starts, the gate start pulse signal supplied to the scan control unit is supplied to the output unit Signal is supplied with a high level voltage of the same cycle as the signal, and the gate scan direction signal is supplied with a high level during the display-on period.

The present invention is effective in preventing a multi-gate driving signal from being generated in each stage of the gate driver.

In addition, the present invention has an effect of reducing power consumption by preventing a driving signal abnormally generated in each stage of the gate driver.

In addition, the scan control unit and the gate scan direction signal of the present invention are applied to each stage of a gate driver having various circuit configurations, thereby preventing generation of a multi-gate drive signal.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of an apparatus may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a circuit diagram showing a stage of a gate driving driver according to the present invention.

A plurality of stages are cascade-connected to the gate drive driver, and output signals can be sequentially output from each stage.

The output signals output from the gate driving driver may be sequentially supplied to the respective gate lines of the liquid crystal display panel.

In the present embodiment, for convenience of explanation, the first stage ST1 of the gate drive driver is limited to the first stage ST1, but the remaining stages have the same circuit configuration as the first stage ST1.

4, the ST 100 includes an internal circuit 110 including a plurality of transistors, a scan controller 130 for controlling a gate start pulse GSP and a gate scan direction signal GSD, And an output unit 120 for outputting a gate driving signal by the operation of the internal circuit 110 and the scan control unit 130.

The stage 100 of the gate driver of the present invention uses the two first and second clock signals CLK1 and CLK2, the gate low voltage VGL, the gate start pulse GSP and the gate scan direction signal GSD And outputs a gate driving signal. However, although not shown in the drawing, voltage sources VDD and VSS may be supplied to the internal circuit 110 and two first and second gate clock signals CLK1 and CLK2 may be supplied to the stage 100, However, this is not fixed but may use the first to fourth gate clock signals GCLK1 to GCLK4. Which depends on the configuration of the transistors disposed in the internal circuit 110.

4, the N-MOS transistors are used in the internal circuit 110, the scan control unit 130, and the output unit 120. However, the present invention can be applied to the case where the P-MOS transistor is used. In the case of using a P-MOS transistor, the signal waveforms shown in FIG. 5 have a "high" section as a "low" section and a "low" section as a "high" section.

Hereinafter, a stage of a gate drive driver using an N-MOS transistor will be mainly described.

The scan controller 130 included in the stage 100 of the present invention includes a first switching device T1 and a second switching device T2. The first switching device T1 of the scan controller 130 is turned on / off by a gate start pulse GSP supplied from a system (not shown) of the liquid crystal display device (in the case of the n-th stage, Gate drive signal) and a gate start pulse (GSP) supply line and the first common node N1. To this end, the gate terminal and the drain terminal of the first switching device T1 provided in the stage 100 are connected to the gate start pulse supply line, and the source terminal is connected to the first common node N1.

The second switching element T2 provided on the stage 100 is turned on / off according to the state of the gate scan direction signal and is connected to the first common node N1 and the first set node Q. To this end, the gate terminal of the second switching element T2 provided in the stage 100 is connected to the gate signal line for supplying the gate scan signal, the drain terminal is connected to the first common node N1, Is connected to the first set node (Q).

The output unit 120 provided in the stage 100 includes a third switching device T3 and a fourth switching device T4. The third switching element T3 of the output unit 120 is turned on and off according to a signal supplied from the first set node Q. The third switching element T3 of the output unit 120 is controlled by the first clock signal line CLK1 and the gate output terminal, Respectively. The gate terminal of the third switching element T3 provided at the output part 120 of the stage 100 is connected to the first set node Q and the drain terminal is connected to the first clock signal line CLK1 ), And the source terminal is connected to the gate output terminal.

The fourth switching element T4 of the output unit 120 is turned on and off according to a signal supplied from the second set node QB and has a gate output terminal and a discharge power supply line VGL . To this end, the gate terminal of the fourth switching element T4 provided in the output part 120 of the stage 100 is connected to the second set node QB, the drain terminal is connected to the gate output terminal, The source terminal is connected to the discharge power supply line (VGL).

The internal circuit 110 included in the stage includes a plurality of transistors and includes a second clock signal line CLK2, a first set node Q, a discharge power source line VGL, and an output unit 120, And the gate terminal of the fourth switching device T4.

The internal circuit 110 may be variously implemented with a plurality of transistors, and the circuit used in the stage of the gate drive driver may be used as it is.

The first set node Q is connected to the second common node N2 and the second common node N2 is connected to the first capacitor C1 between the discharge power supply line VGL, A second capacitor C2 is connected between the second common node N2 and the gate output terminal (Gate OutPut) of the output unit 120. [

The first and second capacitors C1 and C2 may be switching elements. That is, the capacitor of the switching element is equalized.

FIG. 5 is a view showing signals supplied to the gate driving driver according to the present invention, and FIG. 6 is a view showing gate driving signals outputted from each stage of the gate driving driver according to the present invention.

The stage operation of the gate driving driver of the present invention will be described with reference to FIGS. 4, 5 and 6. FIG.

A period in which a gate driving signal of the liquid crystal display device is outputted and displayed is referred to as a display on period and a blanking period in a preceding stage is defined as a power up period. The display period is a period during which a gate driving signal is output. That is, a section in which a screen is implemented in the liquid crystal display device is referred to as a power-up section, and a section in the power-up section is a section before the display.

The operation of the internal circuit 110 of the stage 100 by the second gate clock signal CLK2 is the same as the operation of the stage of a general gate drive driver, and is omitted.

In the present invention, the scan control unit 130 is disposed between the gate start pulse supply line to which the gate start pulse GSP is supplied and the first set node Q of the stage 100.

The scan controller 130 includes a terminal to which a gate start pulse (GSP) is supplied and a terminal to which a gate scan direction signal is supplied. Since the gate-start pulse signal is not supplied to the scan controller 130 in the power-up period, the second switch T2 of the scan controller 130 is turned on / off by the gate scan direction signal. In the present invention, the gate scan direction signal is maintained at the "low" level voltage in the power-up period to prevent the second switching device T2 from being turned on.

Here, the gate start pulse signal is a gate driving signal of the (N-1) th stage when the stage of the gate driving driver is the N-th stage.

Therefore, no "high" or "low" signal is supplied to the first set node Q through the gate-start pulse line in the power-up period. Therefore, the first set node Q can maintain the gate low voltage of the discharging power supply line in the uncharged state.

In the conventional gate drive circuit stage, the gate scan direction signal is maintained at the "high" state even during the power-up period. If the gate scan direction signal is maintained at the "high" state at the display- do.

5, in the power-up period, the gate start pulse (or gate driving signal of the previous single stage), the first clock signal GCLK1, and the second clock signal GCLK2 all have a "low" level voltage When the gate scan direction signal becomes "High ", the second switching device T2 is turned on and the first switching device T1 changes the" low " level of the gate start pulse (or the previous single stage gate driving signal) Quot; level can not be delivered to the first set node Q and therefore can not maintain a "low" level.

However, due to the coupling effect of the first capacitor C1 and the second capacitor C2, the first set node (" L ") of the clock signal input to the third switching element T3 of the output unit 120 Q) so that the third switching element T3 is turned on. That is, there arises a problem that a plurality of gate driving signals are outputted in a section where the gate driving signal should not be outputted.

However, if the gate scan direction signal of the present invention is maintained at a low level during the power-up period, the second switching device T2 of the scan control unit 130 is not turned on. Therefore, the third switching device of the output unit 120 T3 to prevent the first set node Q from maintaining the "low " level voltage supplied from the discharge voltage supply line.

Therefore, as shown in FIG. 6, only one gate driving signal is outputted for each frame in the stage of the gate driving driver of the present invention.

1 is a block diagram showing a general liquid crystal display device.

2 is a block diagram illustrating the gate driver of FIG.

3 is a diagram showing an output waveform of a gate signal due to an initial abnormal operation of a gate driver according to the related art.

4 is a circuit diagram showing a stage of a gate driving driver according to the present invention.

5 is a diagram showing signals supplied to the gate driving driver according to the present invention.

6 is a diagram showing gate drive signals output from each stage of the gate drive driver according to the present invention.

 (Description of Reference Numbers to Main Parts of the Drawings)

10: timing controller 11: gate driver

12: data driver 13: liquid crystal display panel

130: scan control unit 120: output unit

Claims (10)

A display on period in which the liquid crystal display is displayed and a power up period in which the liquid crystal display is not displayed are defined, And a plurality of stages sequentially outputting a gate driving signal from the display ON period, A scan control unit for receiving a gate start pulse signal and a gate scan direction signal from the front stage and controlling the current stage not to output a gate drive signal in the power up period; And a gate driving driver for sequentially outputting a clock signal as a gate driving signal according to control of the scan control unit and the internal circuit, Wherein the gate-start pulse signal and the gate scan direction signal supplied to the scan control unit are supplied with a low-level voltage in the power-up period, The gate-on pulse signal supplied to the scan control unit is supplied with a high-level voltage having the same cycle as that of the clock signal supplied to the output unit when the display-on period starts, and the gate- And a high level is supplied, Wherein the gate scan direction signal is at a low level during the power-up period to block the gate start pulse signal from flowing into the output section. The driving method of a liquid crystal display device according to claim 1, wherein the gate start pulse signal is a gate driving signal of a front stage. The driving method of a liquid crystal display device according to claim 1, wherein in the power-up period, a gate driving signal of a low level is outputted in the stage by the gate scanning direction signal. The method of claim 1, wherein the gate scan direction signal, the gate start pulse signal, and the clock signal are all at a low level in the power-up period. The method of claim 1, wherein the scan control unit comprises a first switching device and an second switching device, each of which includes an NMOS transistor. And stages for sequentially outputting the clock signal to the gate line, Each of the stages includes: A first switching device of a diode connection structure for providing a gate start pulse signal provided from a front end stage to a first node; A second switching element whose on / off is controlled by a gate scan direction signal and is connected between the first node and the Q node; And And a third switching element, which is turned on / off by a voltage on the Q node and is connected between the clock signal line to which the clock signal is input and the gate line, Wherein the second switching element is turned off by the gate scan direction signal during a power up period before a display period and the second switching element is turned on by the gate scan direction signal in the display period. The method according to claim 6, The logic level of the gate scan direction signal fluctuates when the clock signal becomes high level, and the second switching element is turned on. The method according to claim 6, Each of the stages includes: And a fourth switching element controlled by a voltage on the QB node and discharging the gate line. 9. The method of claim 8, Each of the stages includes: A first capacitor connected between the Q node and a power supply line to which power is supplied for discharging the gate line; And And a second capacitor connected between the Q node and the gate line. The method according to claim 6, Wherein a logic level of the gate scan direction signal varies when the gate start pulse signal becomes a high logic level, thereby turning on the second switching device.

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