KR101527941B1 - The Repairing Method of Multilayer Test Board for Semiconductor Device - Google Patents

The Repairing Method of Multilayer Test Board for Semiconductor Device Download PDF

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Publication number
KR101527941B1
KR101527941B1 KR1020150036958A KR20150036958A KR101527941B1 KR 101527941 B1 KR101527941 B1 KR 101527941B1 KR 1020150036958 A KR1020150036958 A KR 1020150036958A KR 20150036958 A KR20150036958 A KR 20150036958A KR 101527941 B1 KR101527941 B1 KR 101527941B1
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South Korea
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semiconductor device
test board
circuit
silver paste
hole
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KR1020150036958A
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Korean (ko)
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김창열
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김창열
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G01R31/02—
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

The present invention relates to a method for repairing a semiconductor device test board of a multilayer structure. The method for repairing the semiconductor device test board of the multilayer structure according to the embodiment of the present invention includes a failure position checking step, a masking step of attaching a silicon tape on a preset region, a hole processing step of processing a hole on the checked failure position, a sliver paste injecting step of connecting and recovering the damaged pattern, a curing step of removing the silicon tape and curing the inner side of the hole filled with the silver paste, a polishing step of polishing the upper side of the silver paste, a copper plating step, a nickel plating step, and a gold plating step. The present invention precisely forms a resistance value between circuit patterns on the test board.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a repair method of a multilayered semiconductor device test board,

The present invention relates to a method for repairing a semiconductor device test board having a multilayered structure in which circuits are provided on the upper surface, the lower surface and the inner layer, and more particularly, A test socket in which an upper probe for inspection and a lower probe are protruded by a predetermined length is used on an upper surface and a lower surface, respectively, for testing whether the device operates normally or not. In a long time repeated test, Or damage caused by breakage of the connection between the upper surface circuit and the inner layer circuit due to delamination of the multilayer structure test board generated by moisture or the like, the damaged semiconductor device test board can be reproduced, A method of repairing a semiconductor device test board of a multilayer structure The.

Recently, the technology development of various industries such as the electronic industry such as the computer industry, the information communication industry, the aerospace industry, and the machinery industry is rapidly proceeding, And the performance of high-performance, highly integrated semiconductor devices having industrially essential functions such as internal processing and storage of more data per unit area.

Semiconductor devices that play such an important role are fabricated on a pure silicon substrate by a very complicated and precise semiconductor thin film process to produce highly integrated semiconductor chips and to protect the semiconductor chip from the harsh external environments and to prevent external devices and signal input / The semiconductor device is supplied to a customer who needs the semiconductor device only after a predetermined fixing is performed. At this time, it is very important to fix the semiconductor chip process and the packaging process, which are the process of manufacturing the semiconductor device, but the test process which is the process of verifying the reliability of the semiconductor device manufacturing process and the fixing of the packaging is more important.

1, the upper and lower probes 12 and 13 are provided on the upper and lower surfaces of the board 11, respectively, in order to proceed with the testing process of the semiconductor device, The semiconductor device 20 to be tested is placed on the upper surface of the upper probe 12 of the test socket 10 so that the upper probe 12 and the upper probe 12 And the test board 30 is placed on the lower side of the lower probe 13 of the test socket 10 so that the target semiconductor device 20 is brought into contact with the lower probe 13, The test process is carried out.

As described above, the upper side pattern of the test board 30 contacting the lower probe 13 of the test socket 10 during the process of testing the semiconductor device, The patterns formed on the upper side of the test board 30 are worn or damaged due to frequent contact with the lower probes 13 so that the test process can be further accurately performed I will not. The test boards worn or damaged by the patterns are no longer used in the test process, and the entire amount of the test board is replaced and discarded, thereby causing environmental pollution and causing economic loss due to the replacement cost.

Accordingly, in the case of Patent No. 10-0891076 (entitled " method for regenerating a printed circuit board "), when defects of a pattern and a pad occur in the process of mounting a SMT (Surface Mounter Technology) There is a printed circuit board regeneration method for repairing and reusing a PCB substrate without discarding the PCB substrate. However, in general, in the process of inserting electronic components into a PCB substrate, It is difficult to repair and regenerate a damaged portion caused by abrasion caused by frequent contact with a lower probe of a test socket such as a semiconductor device test board, In addition, there is a problem in that a conventional PCB substrate in which a circuit pattern is formed by copper lines The repaired reproducing method as was the precise resistance value is difficult to form between the circuit patterns on the test required to proceed with the fine semiconductor device testing process board.

In order to solve this problem, Japanese Patent Application No. 10-1398180 (entitled " Method of Repairing a Semiconductor Device Test Board "), in which a patent application and a patent registration are filed by the present applicant, A method for repairing a semiconductor device test board capable of precisely forming a resistance value between circuit patterns on a test board required in a semiconductor device test process can be used for a test board which is reinforced and reproduced for a long time in a semiconductor device test process have. In the repair method of the test board proposed by the applicant of the present invention, circuit damage caused on the upper or lower board surface of the test board can easily be repaired and repaired. However, In the case of a semiconductor device test board having a multilayer structure, the connection portion between the inner layer circuit and the upper surface or the lower surface circuit is broken due to an interlayer crack in the test board due to external factors such as external impact or temperature or humidity, There is a problem that it is difficult to repair and repair the damage site located inside the test board.

Registered Patent No. 10-1398180 (entitled " Method of repairing semiconductor device test board ")

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a method of testing a semiconductor device, The semiconductor device can be used for a long time in the device testing process and the resistance value between the circuit patterns on the test board required in the semiconductor device testing process can be precisely formed,

Further, a multi-layered semiconductor device test board in which a circuit is provided on each of the upper surface, the lower surface and the inner layer is formed by the interlayer spreading of the multi-layer test board generated by impact, room temperature change, moisture or the like in a long time repeated test , It is possible to regenerate and repair the damaged semiconductor device test board without disposing the damaged semiconductor device test board when the connection between the upper surface circuit and the inner layer circuit is broken, Thereby reducing costs.

According to an aspect of the present invention for solving the above problems, an upper probe for inspection and a lower probe are protruded by a predetermined length on an upper surface and a lower surface, respectively, so that a lower surface of a semiconductor device A method for repairing a semiconductor device test board of a multilayer structure in which the lower probe of the test socket to be seated is brought into contact with the upper surface and the circuits are provided on the upper surface, the lower surface and the inner layer, A defective position determining step of determining a defective circuit position of the semiconductor device test board of the structure; A masking step of attaching a silicon tape to a predetermined area including an identified defective position; A hole machining step of forming a hole having a predetermined diameter and a depth in an identified defective position; A silver paste applying step of filling a hole formed in the processed hole with a silver paste to connect and recover broken and damaged patterns between the inner layer circuit and the upper surface circuit; A step of removing the silicon tape adhered in the masking step and holding the silicon tape at a predetermined temperature for a predetermined period of time in a curing machine by raising the temperature stepwise and repeatedly a predetermined number of times to cure the inside of the hole filled with the silver paste; A polishing step of polishing the upper surface of the silver paste filled in the holes formed after the curing step; A copper plating step of removing foreign substances generated in the polishing step and copper plating the upper surface of the hole at a predetermined height; A nickel plating step of nickel plating the upper surface of the copper-plated part to a predetermined height; And a gold plating step of gold plating the upper surface of the nickel plated part to a predetermined height.

A method of repairing a semiconductor device test board of a multilayer structure according to an embodiment of the present invention includes: a first testing step of inspecting a circuit connection between an inner layer circuit and an upper side circuit after the silver paste applying step; And a second test step of inspecting the circuit connection of the gold-plated part after the gold plating step,

Further, the method may further include a hot air drying step of blowing hot air into the holes formed after the hole processing step, before the silver paste is introduced, to remove foreign substances in the holes.

A method for repairing a semiconductor device test board of a multilayer structure according to the present invention is a method for repairing a semiconductor device test board of a multi-layered structure, comprising: a step of repairing a damaged portion by frequent contact with a lower probe of a test socket during a test process of the semiconductor device, The semiconductor device test process can be used for a long time and the resistance value between the circuit patterns on the test board required in the semiconductor device test process can be precisely formed,

Further, a multi-layered semiconductor device test board in which a circuit is provided on each of the upper surface, the lower surface and the inner layer is formed by the interlayer spreading of the multi-layer test board generated by impact, room temperature change, moisture or the like in a long time repeated test , It is possible to regenerate and repair the damaged semiconductor device test board without disposing of the damaged semiconductor device test board when the connection between the upper surface circuit and the inner layer circuit is broken and the reuse can be done. . ≪ / RTI >

1 is a cross-sectional view showing that a semiconductor device and a test board contact each other on the upper and lower probes of a test socket used for a conventional semiconductor device testing process;
2 is a block diagram illustrating steps of a repair method of a semiconductor device test board of a multi-layer structure according to the present invention;
FIG. 3A is a cross-sectional view illustrating a repair method of a semiconductor device test board having a multilayer structure according to the present invention, in which an internal circuit of a test board is damaged; FIG.
FIG. 3B is a test board cross-sectional view showing a method of repairing a multilayered semiconductor device test board according to the present invention, in which masking with a silicon tape is followed by filling a hole formed inside the test board at an internal damaged position with silver paste;
FIG. 4A is a view of a Teddo board showing a method of repairing a multilayered semiconductor device test board according to the present invention, in which a silicon tape for masking is removed, the upper surface of the silver paste is polished, and copper plating is performed;
FIG. 4B is a test board cross-sectional view showing a method of repairing a semiconductor device test board of a multilayer structure according to the present invention, wherein nickel plating and gold plating are respectively formed on the upper surface of the copper plating portion; FIG.
5 is a block diagram illustrating steps of a repair method of a semiconductor device test board according to another embodiment of the present invention;
FIG. 6A is a test board cross-sectional view showing another example of a repair method of a semiconductor device test board having a multilayer structure according to the present invention, in which an internal pattern connecting a top surface circuit and a bottom surface circuit is damaged; FIG. And
6B is a cross-sectional view illustrating a method of repairing a semiconductor device test board of a multilayer structure according to another embodiment of the present invention. Referring to FIG. 6B, a method of repairing a semiconductor device test board according to another embodiment of the present invention includes applying a silver paste, copper plating, And Fig.

Hereinafter, embodiments of the present invention in which the above object can be specifically realized will be described with reference to the accompanying drawings. In describing the embodiments, the same names are denoted by the same reference numerals, and further description thereof will be omitted below.

FIG. 2 is a block diagram showing steps of a repair method of a semiconductor device test board 30 of a multilayer structure according to the present invention. FIG. 2 is a block diagram showing steps of a repair method of a semiconductor device test board 30 according to the present invention. A masking step, a hole processing step S130, a silver paste applying step S140, a hardening step S150, a polishing step S160, a copper plating step S170, A nickel plating step S180, and a gold plating step S190.

The defective position determining step S110 is a test board 30 having a multilayer structure in which a circuit 32 is formed as an inner layer as well as an upper surface and a lower surface. In the test board 30, The connection between the upper surface circuit 31 and the inner layer circuit 32 is cut off when an interlayer expansion of the test board 30 of a multilayer structure occurs due to changes in the room temperature or moisture or the like, In the method of repairing the device test board 30, a damaged portion is checked by an electron microscope for the protruding portion of the surface of the test board 30 due to the interlayer widening phenomenon, or a defective position where the circuit connection is disconnected is checked through a contact tester or the like .

3A is a cross-sectional view illustrating a method of repairing a semiconductor device test board 30 having a multilayer structure according to the present invention, in which an internal circuit of the test board 30 is damaged, and FIG. 3B is a cross- A method of repairing a test board (30) comprising the steps of: masking with a silicon tape (36); and inserting a test board (30) The masking step S120 is performed between the upper surface circuit 31 and the inner layer circuit 32 identified through the defective positioning step S110, as shown in FIGS. 3A and 3B. A silicon tape 36 is attached to a predetermined region on the upper surface pattern 31 of the connection cut portion and the silver paste 37 injected into the hole 33 in the silver paste applying step 33) to the outside of the hole (33) Side is masked (masking) from being attached to the other pattern 31 of the mask.

3B, the upper surface of the portion where the connection between the upper surface circuit 31 and the inner layer circuit 32 is broken may be formed by using CNC (Computerized Numerically Controlled Machine Tools) or the like A hole 33 is formed in the test board 30 at a predetermined depth on the test board 30 with a predetermined diameter enough to remove the broken portion of the inner layer and a depth corresponding to the depth of the inner layer circuit 32 formed therein.

3B, the inside of the hole 33 formed up to the inner layer circuit 32 on the tester 30 is filled with the silver paste 37, The silver paste 37 is inserted into the hole 33 at a height enough to touch the upper surface circuit pattern 31 through the air pressurized syringe or the like do.

The curing step S150 is a step for curing the silver paste 37 injected into the hole 33. The silicon tape 36 adhered in the masking step S120 is removed, The temperature is maintained at a predetermined temperature for a predetermined time, and the temperature is elevated stepwise to maintain the temperature at 70 ° C to 150 ° C for 30 minutes.

4A shows a method of repairing a multilayered semiconductor device test board 30 according to the present invention. In the method of repairing a semiconductor device test board 30 according to the present invention, the masking silicon tape 36 is removed and the upper surface of the silver paste 37 is polished, 38, and FIG. 4B is a cross-sectional view illustrating a method of repairing a semiconductor device test board 30 having a multilayer structure according to the present invention, wherein nickel plating The polishing step S160 is a step of cutting the test board 30 into a hole 33 formed in the test board 30 so as to be connected to the test board 30 The upper surface of the cured silver paste 37 is polished and shaved so that when the copper plating 38 is laminated on the silver paste 37 side, (31) so that the height of the peripheral pattern Point is polished with a hand piece attached to the end portion, and the entire upper surface of the silver paste 37 is polished in a concave shape.

As shown in FIG. 4A, the copper plating step S170 removes foreign substances generated in the polishing step S160 and copper plating 38 at a predetermined height on the silver paste 37 side Preferably by means of an electroless copper plating 38 using a plating machine in conformity with the height of the left and right pattern 31 portions broken by the machining of the holes 33, Copper plating 38 using copper having high conductivity is used to densify the silver paste 37 in the silver paste 37 to make the side surface of the silver paste 37 more flat and to make frequent contact with the lower probe of the test socket So that the contact failure due to the separation can be prevented in advance.

The nickel plating step S180 is performed to prevent the wear of the pattern 31 due to frequent contact with the test socket bottom probe of the semiconductor device test board 30 as shown in FIG. 38) nickel plating (39) to be laminated on the upper side of the region. Preferably, a current is applied through a plating machine to a voltage of 4.5 V for 2 minutes to nickel plated 39, washed with alcohol, and then plated with a nickel plating 39 to a thickness of 1 to 3 μm And the cleaning process are repeatedly performed to enhance the abrasion resistance while maintaining the current conductivity of the pattern 31 region. When the voltage value of the plating machine is less than 4.5V, the thickness of the plated nickel is thin, so that the plating process may be repeated several times. If the voltage exceeds 4.5V, the thickness of the nickel plating 39 is excessively thick And the current application time of the current can be maintained for 2 minutes for the same reasons as the above-mentioned 4.5V voltage value maintenance.

When the thickness of the nickel plating 39 is less than 1 탆, wear resistance is weak and abrasion damage due to repetitive contact of the lower probe of the test socket may easily occur. When the thickness is more than 3 탆, The thickness of the entire plating is thickened together with the gold plating 40 to be plated so that the lower probe pressure input and the frictional force are largely affected when the test socket is brought into contact with the lower probe to cause re-damage.

The gold plating step S190 is a step of forming a gold plating layer having excellent electrical conductivity of gold on the surface of the nickel plating layer 39 as shown in FIG. 4B in order to form a precise resistance value of the test board 30 during a test process of the semiconductor device. The gold plating 40 is performed so as to be stacked on the side surface. Preferably, a current is applied by a plating machine at a voltage of 4 V for 3 minutes to perform gold plating (40), followed by washing with alcohol, and until the thickness of the gold plating (40) The plating and the washing process are repeatedly performed so that the resistance value of the pattern 31 region can be precisely formed to the original value before the damage. When the voltage value of the plating machine is less than 4V, there is a possibility that the plating and washing process is repeated several times because the thickness of the plated gold is thin. On the other hand, when the voltage is more than 4V, It may be thicker than 3 m, and the current application time of the current can be maintained for 3 minutes for the same reasons as the above-mentioned maintenance of the 4V voltage value.

If the thickness of the gold plating 40 is less than 1 袖 m, the resistance value may be higher than the original value before the damage. If the thickness exceeds 3 袖 m, the thickness of the gold plating 40 may increase, The cost is increased, and when the probe is brought into contact with the lower probe of the test socket, the lower probe pressure input and the frictional force are increased to cause re-damage.

5 is a block diagram illustrating steps of a method of repairing a semiconductor device test board 30 according to another embodiment of the present invention. As shown in FIG. 5, after the hole machining step S 130 , Hot air is blown into the holes 33 formed through the hot air drying step S131 before the silver paste injecting step S140 to remove foreign substances in the holes 33 and the silver paste 37, So that it can be easily inserted into the hole 33.

After the silver paste applying step S140, a first test step S141 may be performed to check whether or not the electrical connection between the inner layer circuit 32 and the upper surface circuit 31 is good, After conducting the gold plating step S190, a second test step S191 for inspecting the circuit connection of one part of the gold plating 40 is performed to test the electrical performance such as the current value and the resistance value of the gold plating part .

6A is a cross-sectional view of a test board 30 showing an internal pattern connecting a top surface circuit and a bottom surface circuit is damaged in another embodiment of the repair method of the semiconductor device test board 30 according to the present invention 6B shows another embodiment of the repair method of the multilayered semiconductor device test board 30 according to the present invention. After the epoxy 35 is applied to the inner surface of the through hole 34 formed in the damaged position , A silver paste 37, copper plating 38, nickel plating 39 and gold plating 40 in this order. In the semiconductor device test board 30 of the multilayer structure according to the present invention, In another embodiment of the repair method, as shown in Figs. 6A and 6B, in a state in which the circuit 32 is formed in the inner layer, the inner pattern connecting the upper surface and the lower surface circuit 31 is damaged If broken, A through hole 34 penetrating the upper and lower side surfaces of the inner layer damaged portion is formed and the inner layer circuit 32 is exposed to the inner surface of the through hole 34, The side surface is coated with the epoxy 35 to insulate the inner layer circuit 32 exposed through the through hole 34. The through hole 34 whose inner surface is insulated by the epoxy 35 is filled with the silver paste 37 to electrically connect the broken top surface and the bottom surface circuit.

The top and bottom surfaces of the through hole 34 filled with the silver paste 37 are subjected to a polishing step S160, a copper plating step S170, a nickel plating step S180, And the plating step (S190).

As described above, the method of repairing a semiconductor device test board 30 of a multilayer structure according to the present invention is a method of repairing a semiconductor device test board 30 having a multilayered structure in which circuits 31 and 32 are provided on an upper surface, The connection between the upper surface circuit 31 and the inner layer circuit 32 is prevented by the interlayer spreading of the multilayer structure test board 30 which is generated by the impact or the room temperature change or moisture or the like in the long time repeated test process of the board 30 The damaged semiconductor device test board 30 can be regenerated, repaired and reused without discarding the damaged semiconductor device test board 30, thereby reducing the cost of discharging and replacing the foreign substances of the anti-fouling agent according to the disposal of the test board 30 having a multilayer structure However,

It is possible to use the regenerated test board 30 for a long period of time in the semiconductor device test process by enhancing the wear resistance by repairing and regenerating the damaged and damaged part by frequent contact with the lower probe of the test socket during the test process of the semiconductor device, It is possible to precisely form the resistance value between the circuit patterns 31 on the test board 30 required in the process.

It is to be understood by those skilled in the art that the present invention may be embodied in many other forms without departing from the spirit and scope of the invention,

Accordingly, the above-described embodiments are to be considered illustrative and not restrictive, and all embodiments within the scope of the appended claims and their equivalents are intended to be included within the scope of the present invention.

30: Multilayer semiconductor device test board
31: upper surface, lower surface circuit 32: inner layer circuit
33: Hole 34: Through hole
35: Epoxy 36: Silicone tape
37: silver paste 38: copper plating
39: Nickel plated 40: Gold plated

Claims (3)

The upper probe and the lower probe are protruded from the upper surface and the lower surface by a predetermined length so that the lower surface of the semiconductor device is contacted with the upper probe, A method of repairing a semiconductor device test board of a multi-layer structure in which a circuit is provided on an upper surface, a lower surface, and an inner layer,
A defective position checking step of confirming a defective circuit position of a semiconductor device test board of a multilayer structure through an appearance inspection or a test instrument;
A masking step of attaching a silicon tape to a predetermined area including an identified defective position;
A hole machining step of forming a hole having a predetermined diameter and a depth in an identified defective position;
A silver paste applying step of filling a hole formed in the processed hole with a silver paste to connect and recover broken and damaged patterns between the inner layer circuit and the upper surface circuit;
A step of removing the silicon tape adhered in the masking step and holding the silicon tape at a predetermined temperature for a predetermined period of time in a curing machine by raising the temperature stepwise and repeatedly a predetermined number of times to cure the inside of the hole filled with the silver paste;
A polishing step of polishing the upper surface of the silver paste filled in the holes formed after the curing step;
A copper plating step of removing foreign substances generated in the polishing step and copper plating the upper surface of the hole at a predetermined height;
A nickel plating step of nickel plating the upper surface of the copper-plated part to a predetermined height; And
And a gold plating step of gold plating the upper surface of the nickel plated part to a predetermined height.
The method according to claim 1,
A first test step of inspecting a circuit connection between the inner layer circuit and the upper side circuit after the silver paste injecting step;
And a second test step of inspecting the circuit connection of the gold-plated part after the gold plating step.
3. The method according to claim 1 or 2,
After the hole processing step, before the silver paste applying step,
And a hot air drying step of blowing hot air into the holes to remove foreign substances in the holes.
KR1020150036958A 2015-03-17 2015-03-17 The Repairing Method of Multilayer Test Board for Semiconductor Device KR101527941B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102528957B1 (en) 2022-05-06 2023-05-03 주식회사 알테크투 The Repairing Method of Multilayer Test Board for Semiconductor Device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060006998A (en) * 2003-12-26 2006-01-23 마쯔시다덴기산교 가부시키가이샤 Method and apparatus for manufacturing circuit board
KR20070030424A (en) * 2005-09-13 2007-03-16 엘지.필립스 엘시디 주식회사 Method of repair an Liquid Crystal Cell, method of manufacturing Liquid Crystal Display Device using the same, and Liquid Crystal Display repaired using the same
KR101141385B1 (en) * 2010-08-13 2012-05-03 삼성전기주식회사 Repairing method of probe board and probe board using thereof
KR101398180B1 (en) * 2014-01-29 2014-05-30 김창열 The repairing method of test board for semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060006998A (en) * 2003-12-26 2006-01-23 마쯔시다덴기산교 가부시키가이샤 Method and apparatus for manufacturing circuit board
KR20070030424A (en) * 2005-09-13 2007-03-16 엘지.필립스 엘시디 주식회사 Method of repair an Liquid Crystal Cell, method of manufacturing Liquid Crystal Display Device using the same, and Liquid Crystal Display repaired using the same
KR101141385B1 (en) * 2010-08-13 2012-05-03 삼성전기주식회사 Repairing method of probe board and probe board using thereof
KR101398180B1 (en) * 2014-01-29 2014-05-30 김창열 The repairing method of test board for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102528957B1 (en) 2022-05-06 2023-05-03 주식회사 알테크투 The Repairing Method of Multilayer Test Board for Semiconductor Device

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