KR101514171B1 - 메모리 시스템 및 메모리를 위한 모듈러 커맨드 스트럭처 - Google Patents

메모리 시스템 및 메모리를 위한 모듈러 커맨드 스트럭처 Download PDF

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Publication number
KR101514171B1
KR101514171B1 KR1020137030396A KR20137030396A KR101514171B1 KR 101514171 B1 KR101514171 B1 KR 101514171B1 KR 1020137030396 A KR1020137030396 A KR 1020137030396A KR 20137030396 A KR20137030396 A KR 20137030396A KR 101514171 B1 KR101514171 B1 KR 101514171B1
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KR
South Korea
Prior art keywords
memory
command
flash
page
address
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KR1020137030396A
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English (en)
Korean (ko)
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KR20130136004A (ko
Inventor
진기 김
학준 오
홍범 편
Original Assignee
컨버전트 인텔렉츄얼 프로퍼티 매니지먼트 인코포레이티드
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Publication of KR20130136004A publication Critical patent/KR20130136004A/ko
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
KR1020137030396A 2006-08-22 2007-08-20 메모리 시스템 및 메모리를 위한 모듈러 커맨드 스트럭처 KR101514171B1 (ko)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US83932906P 2006-08-22 2006-08-22
US60/839,329 2006-08-22
US90200307P 2007-02-16 2007-02-16
US60/902,003 2007-02-16
US89270507P 2007-03-02 2007-03-02
US60/892,705 2007-03-02
PCT/CA2007/001428 WO2008022434A1 (en) 2006-08-22 2007-08-20 Modular command structure for memory and memory system

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR1020097005563A Division KR101397229B1 (ko) 2006-08-22 2007-08-20 메모리 시스템 및 메모리를 위한 모듈러 커맨드 스트럭처

Publications (2)

Publication Number Publication Date
KR20130136004A KR20130136004A (ko) 2013-12-11
KR101514171B1 true KR101514171B1 (ko) 2015-04-21

Family

ID=39106428

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1020097005563A KR101397229B1 (ko) 2006-08-22 2007-08-20 메모리 시스템 및 메모리를 위한 모듈러 커맨드 스트럭처
KR1020137030396A KR101514171B1 (ko) 2006-08-22 2007-08-20 메모리 시스템 및 메모리를 위한 모듈러 커맨드 스트럭처

Family Applications Before (1)

Application Number Title Priority Date Filing Date
KR1020097005563A KR101397229B1 (ko) 2006-08-22 2007-08-20 메모리 시스템 및 메모리를 위한 모듈러 커맨드 스트럭처

Country Status (5)

Country Link
EP (1) EP2074623A4 (ja)
JP (1) JP2010501915A (ja)
KR (2) KR101397229B1 (ja)
TW (1) TW200826104A (ja)
WO (1) WO2008022434A1 (ja)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7904639B2 (en) 2006-08-22 2011-03-08 Mosaid Technologies Incorporated Modular command structure for memory and memory system
EP2109862A4 (en) 2007-02-16 2010-08-04 Mosaid Technologies Inc SEMICONDUCTOR DEVICE AND METHOD FOR REDUCING ELECTRICAL CONSUMPTION IN AN INTERCONNECTED DEVICE SYSTEM
US7957173B2 (en) * 2008-10-14 2011-06-07 Mosaid Technologies Incorporated Composite memory having a bridging device for connecting discrete memory devices to a system
US8037235B2 (en) 2008-12-18 2011-10-11 Mosaid Technologies Incorporated Device and method for transferring data to a non-volatile memory device
KR20110104477A (ko) 2008-12-18 2011-09-22 모사이드 테크놀로지스 인코퍼레이티드 프리셋 동작을 필요로 하는 메인 메모리 유닛 및 보조 메모리 유닛을 갖는 반도체 장치
US8194481B2 (en) 2008-12-18 2012-06-05 Mosaid Technologies Incorporated Semiconductor device with main memory unit and auxiliary memory unit requiring preset operation
US20110258366A1 (en) * 2010-04-19 2011-10-20 Mosaid Technologies Incorporated Status indication in a system having a plurality of memory devices
TWI477966B (zh) * 2012-05-31 2015-03-21 Silicon Motion Inc 資料儲存裝置與快閃記憶體操作方法
JP6541998B2 (ja) * 2015-03-24 2019-07-10 東芝メモリ株式会社 メモリデバイス、半導体装置および情報処理装置
KR102514388B1 (ko) 2016-03-25 2023-03-28 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
KR102651425B1 (ko) 2016-06-30 2024-03-28 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
JP7458740B2 (ja) * 2019-10-21 2024-04-01 キオクシア株式会社 メモリシステム及び制御方法
US11822793B2 (en) 2022-04-04 2023-11-21 Western Digital Technologies, Inc. Complete and fast protection against CID conflict

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US20040148482A1 (en) * 2003-01-13 2004-07-29 Grundy Kevin P. Memory chain
US20060031593A1 (en) * 2004-08-09 2006-02-09 Sinclair Alan W Ring bus structure and its use in flash memory systems

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US5729683A (en) * 1995-05-18 1998-03-17 Compaq Computer Corporation Programming memory devices through the parallel port of a computer system
US6453365B1 (en) * 1998-02-11 2002-09-17 Globespanvirata, Inc. Direct memory access controller having decode circuit for compact instruction format
US7130958B2 (en) * 2003-12-02 2006-10-31 Super Talent Electronics, Inc. Serial interface to flash-memory chip using PCI-express-like packets and packed data for partial-page writes
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
JP3973337B2 (ja) * 2000-02-08 2007-09-12 株式会社日立製作所 記憶素子及びそれを用いた記憶装置
US20020161941A1 (en) * 2001-04-30 2002-10-31 Sony Corporation And Electronics, Inc System and method for efficiently performing a data transfer operation
US7073010B2 (en) * 2003-12-02 2006-07-04 Super Talent Electronics, Inc. USB smart switch with packet re-ordering for interleaving among multiple flash-memory endpoints aggregated as a single virtual USB endpoint
DE102005015828A1 (de) * 2004-06-11 2006-01-05 Samsung Electronics Co., Ltd., Suwon Hub, Speichermodul, Speichersystem, sowie dazugehörige Schreib- und Leseverfahren

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040148482A1 (en) * 2003-01-13 2004-07-29 Grundy Kevin P. Memory chain
US20060031593A1 (en) * 2004-08-09 2006-02-09 Sinclair Alan W Ring bus structure and its use in flash memory systems

Also Published As

Publication number Publication date
KR101397229B1 (ko) 2014-05-20
TW200826104A (en) 2008-06-16
EP2074623A4 (en) 2010-01-06
EP2074623A1 (en) 2009-07-01
WO2008022434A1 (en) 2008-02-28
KR20090046944A (ko) 2009-05-11
JP2010501915A (ja) 2010-01-21
KR20130136004A (ko) 2013-12-11

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