KR101475389B1 - Display device, driving method of the same and electronic equipment incorporating the same - Google Patents

Abstract

A pixel section arranged so as to form a matrix of at least a plurality of columns, and at least one scan line arranged to correspond to a row arrangement of the pixel circuits and controlling conduction of the switching elements, A plurality of signal lines arranged to correspond to the column arrangement of the pixel circuits and propagating the pixel data; a plurality of signal lines corresponding to the plurality of groups in which the signal lines are divided, And a horizontal driver circuit having a signal driver of the horizontal driver circuit.

Pixels, Circuits, Displays, Transistors

Description

TECHNICAL FIELD [0001] The present invention relates to a display device, a driving method thereof, and an electronic device having the same. BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

The present invention includes Japanese Patent JP 2007-171691 filed on June 29, 2007, Japanese Patent Office, and Japanese Patent JP 2008-119201 filed on April 30, 2008, all contents Are hereby incorporated by reference.

TECHNICAL FIELD The present invention relates to a display device in which a thin film transistor as a switching element is formed on a transparent insulating substrate, a driving method thereof, and an electronic device, and more particularly to improvement of a signal line driving technique.

A liquid crystal display (liquid crystal display) using a display device, for example, a liquid crystal cell as a display element (electro-optical element) of a pixel is an active matrix type image display. This kind of display device is designed to display an output image through a liquid crystal display surface.

The liquid crystal display device is applied to a wide range of electronic devices, such as a portable digital assistant (PDA), a mobile phone, a digital camera, a video camcorder, and a display device for a personal computer come.

However, in general, the flicker of the screen called flicker is not perceived by the human eye if the frame frequency of the image is 60 Hz or more.

However, in this frequency, not only the display on the still image but also the display on the moving image, the blur of the moving image is recognized to the human being.

In order to solve this problem, for example, as disclosed in Japanese Unexamined Patent Application Publication No. 2006-78505 (hereinafter referred to as Patent Document 1), a frame frequency of 240 Hz is required to quadruple the blur of moving images .

In the display method disclosed in Patent Document 1, in a recording method using a thin film transistor (TFT), one frame image is recorded for 1/240 second by setting pixel display sequentially from the left. Alternatively, the time is shifted to rewrite the display at 1/240 second and to record the liquid crystal for 1/60 second (FIG. 21 of Patent Document 1).

On the other hand, a technique for recording video data at a data transfer rate of about 200 MHz is disclosed in Japanese Patent Application Laid-Open No. 11-338438 (hereinafter referred to as Patent Document 2).

In this liquid crystal display device, as shown in Fig. 1, one line of data is stored in the memory circuit 2 via the switch 1. Fig. Then, during the next one-line period, the apparatus stores data in the memory circuit 3 and supplies the red (R), green (G), and blue (B) (R) image data is selected.

And the device reads R data from the memory circuit by one driver IC through the switch 5-1 (or 5-2, or 5-3). The switches 5-1 to 5-3 are switched in conjunction with the switch 1. The device writes data to the driver IC 6-1 (or 6-2, or 6-3) and writes data to another driver IC at the same time. The apparatus records green (G) and blue (B) in the same manner. Thus, different image data can be simultaneously written to each driver IC. The liquid crystal display panel 7 displays an image based on the image data of the driver IC that has been written.

However, the above-described Patent Document 1 does not describe the input timing (input method) of the image signal data to the data line driving circuit. A specific data recording system at an image frame frequency of 240 Hz is not established.

On the other hand, in the technique disclosed in Patent Document 2, image data is recorded in a synchronous manner in the driver ICs 6-1 to 6-3. The data supplied to the three driver ICs are also synchronized with each other.

In this state, the noise of image data and clock rising and falling between adjacent wirings is increased, causing fluctuation of the voltage of the image data and the clock signal itself, which is unstable.

For this reason, by inputting the deformed image data, an error occurs in the image data of the driver IC, and the image quality is remarkably impaired. The waveform after the waveform shaping by the buffer circuit becomes a waveform likely to cause a data error.

Particularly, in a state where the frequency exceeds 100 MHz, it is difficult to ignore the noise in the cable or the adjacent wiring in the printed board.

Presently, a clock frequency of 27 MHz is required for VGA (800 x 600 pixels), and 108 MHz is required for a high frame rate of quadruple speed.

In UXGA (1600 x 1400 pixels), the lowest frame frequency is 135 MHz. Its quadruple speed is 540MHz, and this frequency can not be controlled by a general printed board.

For this reason, division driving is required. However, it is considered to be the limit to divide the panel system by 4 or 5 from the scale of the panel system.

In this state, a potential is generated due to a high frequency component due to parasitic capacitance between adjacent wirings for supplying signals to the driver IC. This potential appears as a clock and noise to the image data, which causes errors in the clock signal and the image data, which in turn impairs the image quality of the panel.

An object of an embodiment of the present invention is to provide a display device, a driving method thereof, and an electronic apparatus having the same that enable loading of image data of high frequency without deteriorating image quality.

A display device according to a first aspect of an embodiment of the present invention includes a pixel portion in which a pixel circuit is arranged to form a matrix of at least a plurality of columns. Pixel data is written to each pixel circuit through a switching element. The display device further includes at least one scan line arranged to correspond to the row arrangement of the pixel circuits and controlling conduction of the switching elements. The display device further includes a plurality of signal lines arranged corresponding to the column arrangement of the pixel circuits and propagating the pixel data. The display device further includes a horizontal driving circuit having a plurality of signal drivers. The signal driver corresponds to a plurality of groups in which the signal lines are divided, and propagates the image data supplied to the signal lines. Each of the plurality of signal drivers propagates image data to a corresponding signal line in accordance with each drive pulse. The drive pulses supplied to the respective signal drivers are shifted in phase with respect to each other.

Preferably, the signal driver is divided into signal drivers adjacent to each other and data is input. Preferably, the image data is input to each of the signal drivers at a timing synchronized with the drive pulse.

Preferably, the display device includes a multiphase clock data generator. Preferably, the generator divides drive pulses having frequencies higher than the normal frequency, and supplies drive pulses whose phases are mutually shifted to the respective signal drivers. Also preferably, the generator divides the image data, rearranges the divided data appropriately for input to the respective signal drivers, and supplies these data.

Preferably, the multi-phase clock data generator supplies respective independent drive pulses shifted in phase with respect to each signal driver. Also preferably, the drive pulses include a clock pulse and a start pulse, respectively.

Preferably, the shift period? Of the phase of the drive pulse is set so as to satisfy the relationship?? (T / 2) / N, where (T / 2) is a half period of the image clock and N is a frequency division number.

Preferably, a selector switch is provided between each signal driver and a corresponding signal line. Preferably, the selector switch selects image data by time division.

A driving method of a display device according to a second aspect of an embodiment of the present invention is a driving method of a display device including a pixel portion in which a pixel circuit is arranged so as to form a matrix of at least a plurality of columns. Pixel data is written to each pixel circuit through a switching element. The display device further includes at least one scan line arranged to correspond to the row arrangement of the pixel circuits and controlling conduction of the switching elements. The display device further includes a plurality of signal lines arranged corresponding to the column arrangement of the pixel circuits and propagating the pixel data. The display device further includes a horizontal driving circuit having a plurality of signal drivers. The signal driver corresponds to a plurality of groups in which the signal lines are divided, and propagates the image data supplied to the signal lines. In the driving method, each of the driving pulses whose phases are shifted from each other is supplied to the plurality of signal drivers, whereby each of the signal drivers spreads image data on a corresponding signal line according to a received driving pulse.

A third aspect of the embodiment of the present invention is an electronic apparatus having a display device. The display device includes a pixel portion in which the pixel circuits are arranged so as to form a matrix of at least a plurality of columns. Pixel data is written to each pixel circuit through a switching element. The display device further includes at least one scan line arranged to correspond to the row arrangement of the pixel circuits and controlling conduction of the switching elements. The display device further includes a plurality of signal lines arranged corresponding to the column arrangement of the pixel circuits and propagating the pixel data. The display device further includes a horizontal driving circuit having a plurality of signal drivers. The signal driver corresponds to a plurality of groups in which the signal lines are divided, and propagates the image data supplied to the signal lines. Each of the plurality of signal drivers propagates image data to a corresponding signal line in accordance with each drive pulse. The drive pulses supplied to the respective signal drivers are shifted in phase with respect to each other.

According to the embodiment of the present invention, a plurality of signal drivers are supplied with respective drive pulses whose phases are shifted from each other.

Each signal driver propagates image data to a corresponding signal line in accordance with a received drive pulse.

According to the embodiment of the present invention, by multiplexing and multiplexing the frequency of the start pulse and the image data as the control clock and the synchronizing signal, it is possible to load image data of high frequency which does not impair image quality.

Before describing an embodiment of the present invention, a general horizontal driving circuit will be described.

2 shows an example of a driving pulse supplied to the signal driver of the general horizontal driving circuit 130 as a comparative example of this embodiment. In this case, the signal driver is divided into four horizontal display areas, and image data is input at a frequency of four times.

In this example, as can be seen from Fig. 2, image signal data is loaded with one control clock. Therefore, the signal driver needs to process the control clock as an input pulse with a data frequency synchronized with the motion picture clock.

In this state, when image data is input at a frequency four times as high as that for high frame rate display, image data can not be input to the liquid crystal display device. This is because the followability of the signal driver IC and the impedance of the cable line carrying the image data are not suitable for high frequencies.

Further, as shown in Fig. 3, noise generated due to interference due to the parasitic capacitance between signal lines at high frequencies adversely affects the image data as well as the clock pulse itself, and normal image display can not be performed.

That is, the data supplied to the respective driver ICs are synchronized with each other. In this state, the noise NIS of image data and clock rising and falling between adjacent wirings is increased, causing fluctuation of the voltage of the image data and the clock signal itself, which is unstable. In the example shown in Fig. 3, the potentials of the noise NIS of the horizontal clock pulses HCK1, HCK2, HCK3, and HCK4 are mutually increased as indicated by X in Fig. At this time, in the image data IMD shown in Fig. 3, the regular waveform is indicated by a broken line, and the error portion is indicated by a solid line.

As a solution to this, lower the frequency supplied to the signal driver. It is necessary to shift the phases of the clock pulses HCK 1, HCK 2, HCK 3, and HCK 4 so as not to increase the noise. Incidentally, the VGA has a clock frequency of 27 MHz at a frame frequency of 60 Hz, and a clock frequency of 108 MHz at a frame frequency of 240 Hz, which is four times thereof.

In this embodiment, in order to cope with the above problem, the frequency of the start pulse and the image data as the control clock and the synchronizing signal are multiplexed and multiplexed to enable the image data of the high frequency to be loaded as described above.

Hereinafter, this embodiment will be described in detail with reference to the drawings.

4 is a block diagram showing an example of a configuration of a liquid crystal display device according to an embodiment of the present invention.

4, the liquid crystal display 100 includes an effective pixel portion 110, a vertical driving circuit (VDRV) 120, a horizontal driving circuit (HDRV) 130A, and a multiphase clock data generator 140. [ Lt; / RTI >

In the effective pixel portion 110, a plurality of pixel circuits 111 are arranged in a matrix.

Each pixel circuit 111 has a thin film transistor (TFT) 112, a liquid crystal cell 113, and a storage capacitor (storage capacitor) 114 as switching elements. In the liquid crystal cell 113, the pixel electrode is connected to the drain electrode (or the source electrode) of the TFT 112. [ One electrode of the storage capacitor 114 is connected to the drain electrode of the TFT 112. [

The gate (scan) lines 115-1 to 115-m are wired along the pixel circuit 111 for each row of the pixel circuit 111. [ The signal lines 116-1 to 116-n are wired along the pixel circuit 111 for each column of the pixel circuit 111. [ The gate electrodes of the TF T 112 of the pixel circuits 111 in each row are all connected to the same gate (scan) lines 115-1 to 115-m. The source electrodes (or drain electrodes) of the TFTs 112 of the pixel circuits 111 in each column are all connected to the same signal lines 116-1 to 116-n.

In the liquid crystal cell 113, the pixel electrode is connected to the drain electrode of the TFT 112, and the counter electrode is connected to the common line 117. The storage capacitor 114 is connected between the drain electrode of the thin film transistor TFT and the common line 117.

In the common line 117, a predetermined AC voltage is given as a common voltage Vcom from a VCOM circuit (not shown) formed integrally with the glass substrate and a drive circuit or the like.

Each pixel circuit 111 writes pixel data to the storage capacitor 114 through the TFT 112 serving as a switching element. The liquid crystal cell 113 is modulated by the voltage based on the pixel data recorded in the storage capacitor 114. [ The liquid crystal display device 100 displays an image by controlling the transmittance of light passing through a pair of polarizing plates (not shown) arranged before and after the liquid crystal cell 113.

Each of the gate lines 115-1 to 115-m is driven by the vertical driving circuit 120 and each of the signal lines 116-1 to 116-n is driven by the horizontal driving circuit 130A.

The vertical drive circuit 120 receives the vertical start signal VST, the vertical clock VCK, and the enable signal ENAB and scans in the vertical direction for each field period to drive the pixel circuits connected to the scan lines 115-1 to 115- 111) on a row-by-row basis.

That is, when a gate pulse GP1 is given to the gate line 115-1 from the vertical driving circuit 120, pixels of each column in the first row are selected. When the scanning pulse GP2 is given to the gate line 115-2, the pixels of the respective columns of the second row are selected. The gate pulses GP3, ..., and 115-m are applied to the gate lines 115-3, ..., and 115-m in the following manner. , And GPm are sequentially given.

At this time, the vertical start signal VST, the vertical clock VCK, and the enable signal ENAB are generated by a second timing controller (not shown) different from the timing controller of the polyphase data generating circuit 140.

The second timing controller operates in synchronization with the signals hst, hck1, hck2, hck3, hck4 and data d0 of the level system supplied to the polyphase data generating circuit 140.

The vertical driving circuit 120 operates in synchronization with an output enable signal OTEN that allows the horizontal driving circuit 130A to output data to the signal lines 116-1 to 116-n.

The horizontal drive circuit 130A divides the signal lines into a plurality of groups (in this embodiment, four groups are provided for simplicity of description). Signal drivers 131 to 134 are provided corresponding to each group.

6 shows an example of drive pulses supplied to the signal drivers 131 to 134 of the horizontal drive circuit 130A.

In this embodiment, the drive pulses are supplied to the signal drivers 131 to 134 individually. Each drive pulse includes a horizontal start pulse HST and a horizontal clock pulse HCK. The horizontal start pulse HST is used to instruct the start of horizontal scanning. The horizontal clock pulse HCK becomes a reference for horizontal scanning.

The horizontal start pulse HST2 supplied to the signal driver 132 is shifted (delayed) by 1/4 of the clock period from the horizontal start pulse HST1 supplied to the signal driver 131. [

Likewise, the horizontal start pulse HST3 supplied to the signal driver 133 is shifted (delayed) by 1/4 of the clock period from the horizontal start pulse HST2 supplied to the signal driver 132.

The horizontal start pulse HST4 supplied to the signal driver 134 is shifted (delayed) by 1/4 of the clock period from the horizontal start pulse HST3 supplied to the signal driver 133. [

The horizontal clock pulse HCK2 supplied to the signal driver 132 is shifted (delayed) by 1/4 of the clock period from the horizontal clock pulse HCK1 supplied to the signal driver 131.

Similarly, the horizontal clock pulse HCK3 supplied to the signal driver 133 is shifted (delayed) by ¼ of the clock period from the horizontal clock pulse HCK2 supplied to the signal driver 132. [

The horizontal clock pulse HCK4 supplied to the signal driver 134 is shifted (delayed) by ¼ of the clock period from the horizontal clock pulse HCK3 supplied to the signal driver 133.

In the examples of Figs. 4 and 6, the signal driver 131 receives the horizontal start pulse HST1 for instructing the start of horizontal scanning and the horizontal clock pulse HCK1 for the horizontal scanning, and generates a sampling pulse. The horizontal start pulse HST1 and the horizontal clock pulse HCK1 are supplied from the polyphase clock data generator 140. [

The signal driver 131 successively samples input image data R (red), G (green), and B (blue) in response to the generated sampling pulses and writes the data to each pixel circuit 111 And supplies them as data signals to the signal lines 116-1 to 116-3.

The signal driver 132 receives the horizontal start pulse HST2 for instructing the start of the horizontal scanning and the horizontal clock pulse HCK2 for the horizontal scanning to generate the sampling pulse. The horizontal start pulse HST2 and the horizontal clock pulse HCK2 are supplied from the polyphase clock data generator 140. [

The signal driver 132 successively samples input image data R (red), G (green), and B (blue) in response to the generated sampling pulses and records the data in each pixel circuit 111 And supplies them to the signal lines 116-4 to 116-6 as data signals.

The signal driver 133 receives the horizontal start pulse HST3 instructing the start of horizontal scanning and the horizontal clock pulse HCK3 serving as a reference of horizontal scanning to generate a sampling pulse. The horizontal start pulse HST3 and the horizontal clock pulse HCK3 are supplied from the polyphase clock data generator 140. [

The signal driver 133 successively samples input image data R (red), G (green), and B (blue) in response to the generated sampling pulses and writes the data to each pixel circuit 111 And supplies them as data signals to the respective signal lines 116-7 to 116-9.

The signal driver 134 receives the horizontal start pulse HS T4 for instructing the start of the horizontal scanning and the horizontal clock pulse HCK4 for the horizontal scanning to generate the sampling pulse. The horizontal start pulse HST4 and the horizontal clock pulse HCK4 are supplied from the polyphase clock data generator 140. [

The signal driver 134 successively samples input image data R (red), G (green), and B (blue) in response to the generated sampling pulses and writes the data to each pixel circuit 111 And supplies them as data signals to the respective signal lines 116-10 to 116-12.

In this way, in this embodiment, in the horizontal driving circuit 130A, a plurality of signal lines are divided into a plurality of groups. A plurality of (four in this embodiment) signal drivers 131 to 134 are provided corresponding to each group of signal lines and propagate the image data.

The phases of the horizontal start pulses HST 1, HST 2, HST 3, and HST 4 and the horizontal clock pulses HCK 1, HCK 2, HCK 3, and HCK 4 are mutually shifted. These pulses serve as drive pulses for driving and controlling the plurality of signal drivers 131 to 134.

More specifically, the signal drivers 131 to 134 are divided into signal drivers adjacent to each other and data is input.

Each of the signal drivers 131 to 134 is controlled by independent horizontal phase clock pulses HCK1 to HCK4 and horizontal start pulses HST1 to HST4. The image data is input at the timing synchronized with the independent clock pulse and the start pulse.

4 and 6, the signal drivers 131 to 134 arbitrarily shift the phase of the horizontal clock pulse HST and the horizontal clock pulse HCK (in this embodiment, 1/4 of the clock cycle) ). The final image signal is output in synchronization with the output enable signal OTEN.

As a result, the signal driver can be driven with clock pulses, start pulses, and image data that are lower in frequency than the original.

The reason why the horizontal driving circuit 130A is driven in this embodiment will be described below.

Generally, the human eye does not recognize flicker on the screen when the frame frequency of the image is 60 Hz or more.

At this frequency, however, not only the still image but also the blurring of the moving image is perceived by humans.

To improve this, a frame frequency of 240 Hz is required in order to eliminate the blur of moving images.

Therefore, in the active matrix display device, when the moving picture characteristic is a current problem, the number of frames to be displayed per second and the frame frequency are quadrupled to display an image, thereby improving such characteristics. Usually the frame frequency is 60Hz. Therefore, the frame frequency of 4 times is 240 Hz.

Usually, in UXGA (1600 x RGB x 1200), the clock frequency is 135 MHz. A typical silicon IC can operate at this frequency.

However, the clock frequency becomes 540MHz when the frame frequency is four times higher than the frequency. At these high frequencies, silicon ICs are difficult to operate.

Also, an image signal generated at this frequency can not be easily transmitted to a liquid crystal display through a cable due to interference between signal lines. To overcome this, the frequency should be lower than this.

In this embodiment, the clock of the image data is maintained while lowering the frequency.

Next, the multiphase clock data generator 140 will be described.

The multi-phase clock data generator 140 receives the horizontal start pulse hst and the horizontal clock pulses hck1 to hck4, and divides these pulses by 1/4. The horizontal start pulse hst and the horizontal clock pulses hck1 to hck4 are supplied from a graphic IC (not shown), for example, four times the normal frequency.

The multiphase clock data generator 140 supplies the frequency-divided horizontal start pulse HST1 and the horizontal clock pulse HCK1 to the signal driver 131 of the horizontal driving circuit 130A. The horizontal clock pulse HCK1 is shifted (delayed) from the horizontal start pulse HST1 by one fourth of the clock period.

The multi-phase clock data generator 140 also generates a horizontal start pulse HST2 whose phase is shifted by 1/4 of the clock period from the horizontal start pulse HST1. The multiphase clock data generator 140 supplies the horizontal start pulse HST2 and the divided horizontal clock pulse HCK2 to the signal driver 132 of the horizontal driving circuit 130A. The horizontal clock pulse HCK2 is shifted (delayed) from the horizontal start pulse HST2 by a quarter of the clock period.

The multi-phase clock data generator 140 also generates a horizontal start pulse HST3 whose phase is shifted from the horizontal start pulse HST2 by 1/4 of the clock period. The multiphase clock data generator 140 supplies the horizontal start pulse HST3 and the divided horizontal clock pulse HCK3 to the signal driver 133 of the horizontal driving circuit 130A. The horizontal clock pulse HCK3 is shifted (delayed) from the horizontal start pulse HST3 by a quarter of the clock period.

The multi-phase clock data generator 140 also generates a horizontal start pulse HST4 whose phase is shifted by 1/4 of the clock period from the horizontal start pulse HST3. The multiphase clock data generator 140 supplies the horizontal start pulse HST4 and the divided horizontal clock pulse HCK4 to the signal driver 134 of the horizontal driving circuit 130A. The horizontal clock pulse HCK4 is shifted (delayed) by 1/4 of the clock period from the horizontal start pulse HST4.

At this time, the shift period? Of the phase of the clock pulse is set so as to satisfy the relationship?? (T / 2) / N, where (T / 2) is the half period of the image clock and N is the number to be divided.

The multi-phase clock data generator 140 also arranges the supplied image data d0 in the line buffer. The multi-phase clock data generator 140 rearranges the image data into a plurality of (four in this embodiment) independent line memory buffers from the division processing and the arrangement in the line memory buffer, And supplies it to the signal driver side from the buffer circuit.

7 is a diagram showing a specific configuration example of the multi-phase clock data generator 140 according to the present embodiment.

8 is a diagram for explaining timing control by the multi-phase clock data generator according to the present embodiment and an example of recording data after division.

The multiphase clock data generator 140 includes a timing controller (TC) 141, a data memory buffer and counter 142, a first counter and a flip flop (CT / FF) 143, a second CNT / A third CNT / FF 145, and a fourth CNT / FF 146.

The timing controller 141 receives the horizontal start pulse hst1 and the horizontal clock pulses hck1 to hck4 having the normal fourfold frequency and supplies the trigger point signals a1 to a4 to the first to fourth CNT / FFs 143 to 146 do. The trigger point signals a1 to a4 are shifted in phase by phi.

More specifically, the timing controller 141 supplies the trigger point signal a1 to the first CNT / FF 143. The timing controller 141 supplies the trigger point signal a1 and the trigger point signal a2 shifted in phase by? To the second CNT / FF 144.

In addition, the timing controller 141 supplies the trigger point signal a3 and the trigger point signal a3 shifted in phase by? To the third CNT / FF 145. The timing controller 141 supplies the trigger point signal a3 and the trigger point signal a4 shifted in phase by? To the fourth CNT / FF 146.

The timing controller 141 also receives the horizontal start pulse hst1 and the horizontal clock pulses hck1 to hck4 of the normal fourfold frequency and supplies the trigger point signals b1 to b4 to the data memory buffer and the counter 142. [ The trigger point signals b1 to b4 are shifted in phase by phi.

More specifically, the timing controller 141 supplies the trigger point signals b 1 and b 2 to the data memory buffer and the counter 142. The trigger point signal b2 is shifted in phase from the trigger point signal b1 by?.

The timing controller 141 supplies the trigger point signals b3 and b4 to the data memory buffer and the counter 142. [ The trigger point signal b3 is shifted in phase with the trigger point signal b2 by?. The trigger point signal b4 is shifted in phase from the trigger point signal b3 by?.

At this time, the timing controller 141 generates the trigger point signals a1 to a4 and b1 to b4 so that they are kept synchronized with each other.

The timing controller 141 generates an output enable signal OT EN, which is a control signal of the horizontal period, and outputs the signal to the horizontal driving circuit 130A and the vertical driving circuit.

The data memory buffer and counter 142 receive the input data d0 and extend the period four times in synchronization with the trigger point signals b1 to b4 from the timing controller 141. [ The data memory buffer and counter 142 rearrange the data d0 into data D1, D2, D3, D4, ..., and output. The data D1, D2, D3, D4, ... are shifted in phase by phi. The rearranged data D1, D2, D3, D4, ... are formed of data of R (red), G (green), and B (blue).

The first CNT / FF 143 receives the trigger point signal a1 and divides the horizontal start pulse hst and the horizontal clock pulse hck1.

The first CNT / FF 143 supplies the divided horizontal start pulse HST1 and the horizontal clock pulse HCK1 to the signal driver 131 of the horizontal driving circuit 130A. The horizontal clock pulse HCK1 is shifted (delayed) from the horizontal start pulse HST1 by one fourth of the clock period.

The second CNT / FF 144 receives the trigger point signal a2 and divides the horizontal start pulse hst and the horizontal clock pulse hck2. Also, the second CNT / FF 144 generates a horizontal start pulse HST2 whose phase is shifted by 1/4 of the clock period from the horizontal start pulse HST1.

The second CNT / FF 144 supplies the horizontal start pulse HST2 and the horizontal clock pulse HCK2 to the signal driver 132 of the horizontal driving circuit 130A. The divided horizontal clock pulse HCK2 is shifted (delayed) from the horizontal start pulse HST2 by a quarter of the clock period.

The third CNT / FF 145 receives the trigger point signal a3 and divides the horizontal start pulse hst and the horizontal clock pulse hck3. Further, the third CNT / FF 145 generates a horizontal start pulse HST3 whose phase is shifted (delayed) by 1/4 of the clock period from the horizontal start pulse HST2.

The third CNT / FF 145 supplies the horizontal start pulse HST3 and the horizontal clock pulse HCK3 to the signal driver 133 of the horizontal driving circuit 130A. The horizontal clock pulse HCK3 after the division is shifted (delayed) by 1/4 of the clock period from the horizontal start pulse HST3.

The fourth CNT / FF 146 receives the trigger point signal a4 and divides the horizontal start pulse hst and the horizontal clock pulse hck4. Further, the fourth CNT / FF 146 generates a horizontal start pulse HST4 whose phase is shifted by 1/4 of the clock period from the horizontal start pulse HST3.

The fourth CNT / FF 146 supplies the horizontal start pulse HST4 and the horizontal clock pulse HCK4 to the signal driver 134 of the horizontal driving circuit 130A. The divided horizontal clock pulse HCK4 is shifted (delayed) from the horizontal start pulse HST4 by 1/4 of the clock period.

8, the multiphase clock data generator 140 generates the horizontal clock pulses hck1 to hck4 having the normal fourfold frequency and the horizontal start horizontal driving synchronous with the horizontal clock pulses hck1 to hck4, The pulse hst is input.

The timing controller 141 generates the trigger point signals b1 to b4 from the horizontal clock pulses hck1 to hck4 and the start pulse hst. The data memory buffer and counter 142 receive the trigger point signals b1 to b4 to accumulate image data in the horizontal direction within one horizontal period and store the data in a manner suitable for the signal drivers 131 to 134 arranged independently of each other .

Here, the input and output data periods of one horizontal period are shown. This makes it possible to process the data.

Here, T is the period of the horizontal clock pulse HCK, which is the control clock of the signal driver (IC), T1 is the data period of one horizontal period after quadrupling, T2 is the data period of one horizontal period, T3 Quot; 1 horizontal period ", respectively.

In the above period, the following relationship is established.

T3? T1? T2

In other words, for example, the data period T1 of one horizontal period after the quadrant is longer than the data period T2 of one horizontal period of the original high frequency before division, and is shorter than one horizontal period T3.

Satisfying this relationship is a condition satisfying the timing chart for realizing the characteristic function of this embodiment.

7 and 8, the phase shifted horizontal clock pulses HCK1 to HCK4 and the horizontal start pulses HST1 to HST4, which are supplied to the signal drivers 131 to 134 of the present embodiment, Are generated by the FFs (143 to 146).

In each of the CNT / FFs 143 to 146, an image clock pulse hck and a start pulse hst for a synchronization signal are input from an original image source.

These pulses are divided under the control of the timing controller 141. The image data d0 simultaneously input is also divided and arranged in the data memory buffer and counter 142. [ Then, the image data d0 is rearranged into four independent data D1 to D4.

As a result, the first to fourth CNT / FFs 143 to 146, that is, the line memory buffers 143, 144, 145 and 146, can supply independent outputs to the respective signal drivers.

Further, by using the divided clock, the phase of the data can be shifted in the form of division.

In addition, as indicated by reference character Y in Fig. 9, the horizontal clock pulse HCK1 is shifted in phase from the horizontal clock pulse HCK2. Thus, the horizontal clock pulse HCK1 is only affected by the noise NIS of the horizontal clock pulse HCK2.

The horizontal clock pulse HCK2 is similarly affected only by the noise NIS of the horizontal clock pulse HCK3.

That is, the noise due to the overlap of the potentials of the horizontal clock pulses HCK 1, HCK 2, HCK 3, and HCK 4 due to the synchronization signal is reduced.

Therefore, the waveform of the image data IMD after the waveform shaping by the buffer circuit (not shown) of each of the signal drivers 131 to 134 becomes a regular rectangular waveform having no error portion as indicated by Z in Fig.

The shift period? Of the phase of the clock pulse is equal to or smaller than a value obtained by dividing the half cycle of the image clock by the number N divided by N (N is an integer).

When this relationship is expressed,? (T / 2) / N is satisfied.

Next, the operation of the liquid crystal display device 100 according to the above configuration will be described with reference to Figs. 4 and 8. Fig.

The vertical drive circuit 120 receives the vertical start signal VST, the vertical clock VCK, and the enable signal ENAB as shown in Fig. 4, and performs a process of successively selecting each pixel circuit 111 on a row-by-row basis. The vertical drive circuit 120 receives each signal and sequentially scans each pixel circuit 111 connected to the scan lines 115-1 to 115-m in the vertical direction every field period .

The multi-phase clock data generator 140 receives the horizontal start pulse hst and the horizontal clock pulses hck1 to hck4, and divides these pulses by 1/4. The horizontal start pulse hst and the horizontal clock pulses hck1 to hck4 are supplied from a graphic IC (not shown) at, for example, four times the normal frequency.

The multi-phase clock data generator 140 supplies the divided horizontal start pulse HST1 and the horizontal clock pulse HCK1 to the signal driver 131 of the horizontal driving circuit 130A. The horizontal clock pulse HCK1 is shifted (delayed) from the horizontal start pulse HST1 by one fourth of the clock period.

In the same way, the multi-phase clock data generator 140 generates a horizontal start pulse HST2 whose phase is shifted (delayed) by 1/4 of the clock period from the horizontal start pulse HST1.

The multiphase clock data generator 140 supplies the horizontal start pulse HST2 and the divided horizontal clock pulse HCK2 to the signal driver 132 of the horizontal driving circuit 130A. The horizontal clock pulse HCK2 is shifted (delayed) from the horizontal start pulse HST2 by a quarter of the clock period.

The multi-phase clock data generator 140 also generates a horizontal start pulse HST3 whose phase is shifted from the horizontal start pulse HST2 by 1/4 of the clock period.

The multiphase clock data generator 140 supplies the horizontal start pulse HST3 and the divided horizontal clock pulse HCK3 to the signal driver 133 of the horizontal driving circuit 130A. The horizontal clock pulse HCK3 is shifted (delayed) from the horizontal start pulse HST3 by one fourth of the clock period.

Further, the multi-phase clock data generator 140 generates a horizontal start pulse HST4 whose phase is shifted by 1/4 of the clock period from the horizontal start pulse HST3.

The multiphase clock data generator 140 supplies the horizontal start pulse HST4 and the divided horizontal clock pulse HCK4 to the signal driver 134 of the horizontal driving circuit 130A. The horizontal clock pulse HCK4 is shifted (delayed) by 1/4 of the clock period from the horizontal start pulse HST4.

The multi-phase clock data generator 140 also arranges the supplied image data D0 in the line buffer. The multiphase clock data generator 140 rearranges the image data into a plurality of (four in this embodiment) independent line memory buffers from the division processing and the arrangement in the line memory buffer, And supplies it to the signal driver side from the circuit (Fig. 8).

The signal driver 131 receives the horizontal start pulse HST1 instructing the start of horizontal scanning and the horizontal clock pulse HCK1 serving as a reference of horizontal scanning to generate a sampling pulse. The horizontal start pulse HST1 and the horizontal clock pulse HCK1 are supplied from the polyphase clock data generator 140. [

Further, the signal driver 131 sequentially samples the input image data R (red), G (green), and B (blue) in response to the generated sampling pulse.

The signal driver 131 supplies the data to each of the signal lines 116-1 to 116-3 as a data signal to be written in each pixel circuit 111 in synchronization with the output enable signal OTEN.

Similarly, the signal driver 132 receives the horizontal start pulse HST2 for instructing the start of the horizontal scanning and the horizontal clock pulse HCK2 for the horizontal scanning, and generates a sampling pulse. The horizontal start pulse HST2 and the horizontal clock pulse HCK2 are phase-shifted with the horizontal start pulse HST1 and the horizontal clock pulse HCK1, respectively.

The signal driver 132 sequentially samples the input image data R (red), G (green), and B (blue) in response to the generated sampling pulses.

The signal driver 132 supplies the data to each of the signal lines 116-4 to 116-6 as a data signal to be written to each pixel circuit 111 in synchronization with the output enable signal OTEN.

The signal driver 133 receives the horizontal start pulse HST3 instructing the start of horizontal scanning and the horizontal clock pulse HCK3 serving as a reference of horizontal scanning to generate a sampling pulse. The horizontal start pulse HST3 and the horizontal clock pulse HCK3 are phase-shifted with the horizontal start pulse HST2 and the horizontal clock pulse HCK2, respectively.

Further, the signal driver 133 sequentially samples the input image data R (red), G (green), and B (blue) in response to the generated sampling pulses.

The signal driver 133 supplies the data to each of the signal lines 116-7 to 116-9 as a data signal to be written to each pixel circuit 111 in synchronization with the output enable signal OTEN.

The signal driver 134 receives the horizontal start pulse HST4 instructing the start of horizontal scanning and the horizontal clock pulse HCK4 serving as a reference of horizontal scanning to generate a sampling pulse. The horizontal start pulse HST4 and the horizontal clock pulse HCK4 are phase-shifted with the horizontal start pulse HST3 and the horizontal clock pulse HCK3, respectively.

Further, the signal driver 134 sequentially samples the input image data R (red), G (green), and B (blue) in response to the generated sampling pulse.

The signal driver 133 supplies the data to each of the signal lines 116-10 to 116-12 as a data signal to be written into each pixel circuit 111 in synchronization with the output enable signal OTEN.

At this time, the vertical driving circuit 120 receives the output enable signal OTEN and can output the gate pulse at the timing at which the output enable signal OTEN falls from the active high level to the inactive low level. The output enable signal OTEN allows the horizontal driving circuit 130A to output the data to the signal lines 116-1 to 116-n.

As described above, according to the present embodiment, a plurality of signal lines are divided into a plurality of groups. A plurality of signal drivers 131 to 134 for propagating the image data supplied to the signal lines are provided corresponding to the divided groups.

The phases of the horizontal start pulses HST 1, HST 2, HST 3, and HST 4 and the horizontal clock pulses HCK 1, HCK 2, HCK 3, and HCK 4 are mutually shifted. These pulses serve as drive pulses for driving and controlling the plurality of signal drivers 131 to 134.

Each of the signal drivers 131 to 134 is controlled by independent horizontal phase clock pulses HCK1 to HCK4 and horizontal start pulses HST1 to HST4. The image data is input at the timing synchronized with the independent clock pulse and the start pulse.

In the present embodiment, the signal drivers 131 to 134 arbitrarily shift the phases of the horizontal start pulse HST and the horizontal clock pulse HCK to operate. The final image signal is output in synchronization with the output enable signal OTEN.

Thus, the signal driver can be driven with clock pulses, start pulses, and image data that are lower in frequency than originally.

As a result, a high-quality image can be transmitted at high speed without deteriorating image quality.

Also, with the image of the high frame rate, the moving image characteristic of the display device is remarkably improved as compared with the image of the existing frame frequency, and the image rolling is eliminated.

In addition, since a driver for an image signal which can operate at a common clock frequency can be used, a display device can be produced at a low cost. There is no need to use a particularly high speed image signal driver.

At this time, the embodiment of the present invention is also effective in a method of recording image data in a time-divisional panel. Particularly, even when the time-divisional switch is used as shown in Fig. 10, the embodiment of the present invention is applied when the time-division number does not sufficiently satisfy the electric characteristic and the image characteristic within the horizontal selection period.

In this case, the signal driver divides the input frequency of the clock pulse (control clock), the start pulse, and the image data in the same manner as described above.

In Fig. 10, the signal SV from the signal drivers 131 to 134 is transferred to the signal lines 116 (116-1 to 116-12) through a selector SEL having a plurality of transfer gates TMG.

Each of the transmission gates TGM is controlled in conduction state by the selection signal S1 and its inverse signal XS1, the selection signal S2 and its inverse signal XS2, the selection signal S3 and its inverse signal XS3.

In this way, a selector time division driving system can be employed, which reduces the number of connection terminals and improves the mechanical reliability of connection by using an active matrix display device of high image quality (UXGA) and high frame rate.

In this case, CMOS signaling, Low Voltage Differential Signaling (LVDS), or Transition Minimized Differential Signaling (TMDS) can be applied to transmit digital data used in the present embodiment. These transmission schemes are used on the input side and the output side of the multi-phase clock data generator 140.

An active matrix type display device represented by an active matrix type liquid crystal display device is used for an OA device such as a PC, a word processor, or a display such as a television receiver. Further, the display device is particularly suitable for use as a display portion of an electronic device such as a cellular phone or a PDA in which the size and compactness of the apparatus main body are increasing.

That is, the display device 100 in this embodiment can be applied to various electronic apparatuses shown in Figs. 11A to 11G.

For example, the present invention can be applied to display devices of electronic devices of all kinds, such as a digital camera, a notebook PC, a mobile phone, and a video camcorder. These electronic apparatuses are designed to display the image signals inputted to the electronic apparatus or generated in the electronic apparatus as images or images.

Hereinafter, an example of an electronic apparatus to which such a display apparatus is applied will be described below.

FIG. 11A shows an example of a television 300 to which an embodiment of the present invention is applied. The television 300 includes an image display screen 303 composed of a front panel 301, a filter glass 302, and the like. The television is produced by using the display device according to the embodiment of the present invention in its video display screen 303. [

11B and 11C show an example of a digital camera 310 to which an embodiment of the present invention is applied. The digital camera 310 includes a photographing lens 311, a flash light emitting unit 312, a display unit 313, a control switch 314, and the like. The digital camera is manufactured by using the display device according to the embodiment of the present invention in its display portion 313. [

11D shows a video camcorder 320 to which an embodiment of the present invention is applied. The video camcorder 320 includes a body portion 321, a subject photographing lens 322 on the side facing forward, a start / stop switch 323 at the time of photographing, a display portion 324, and the like. The video camcorder is manufactured by using the display device according to the embodiment of the present invention in its display portion 324. [

11E and 11F show a portable terminal device 330 to which an embodiment of the present invention is applied. The portable terminal device 330 includes an upper casing 331, a lower casing 332, a connecting portion (here, a hinge portion) 333, a display 334, a subdisplay 335, a picture light 336, 337). The portable terminal apparatus is manufactured by using the display apparatus according to the embodiment of the present invention in the display 334 or the sub display 335.

11G shows a notebook PC 340 to which an embodiment of the present invention is applied. The notebook PC 340 includes a keyboard 342 operated to input information such as characters and the like, a display section 343 for displaying an image, and the like in the main body 341. [ The note-type PC is manufactured by using the display device according to the embodiment of the present invention in the display portion 343 thereof.

Here, the above embodiment has been described taking an example in which the present invention is applied to an active matrix type liquid crystal display device. However, the present invention is not limited to this, and it is also applicable to other active matrix type display devices such as an EL display device using an electroluminescence (EL) element as an electro-optical element of each pixel.

It will be understood by those skilled in the art that various changes, combinations, subcombinations, and alterations may be made in accordance with design requirements or other elements as long as they are within the scope of the appended claims or their equivalents.

FIG. 1 is a diagram for explaining a conventional technique for enabling video data to be recorded at a data transfer rate of about 200 MHz.

2 is a diagram showing an example of a drive pulse supplied to a signal driver of a general horizontal drive circuit as a comparative example of the present embodiment.

Fig. 3 is a diagram for explaining the problem of drive pulses in Fig. 2. Fig.

4 is a block diagram showing an example of a configuration of a liquid crystal display device according to an embodiment of the present invention.

5 is a waveform chart showing the relationship between the output enable signal and the gate pulse.

6 is a diagram showing an example of drive pulses supplied to the respective signal drivers of the horizontal drive circuit.

7 is a diagram showing a specific configuration example of the multiphase clock data generator according to the present embodiment.

8 is a diagram for explaining timing control by the multiphase clock data generator according to the present embodiment and an example of data recording after division.

Fig. 9 is a diagram for explaining the effect of this embodiment.

10 is a block diagram showing an example of a configuration of a liquid crystal display device according to an embodiment of the present invention using a time-divisional switch.

11A to 11G are views showing examples of an electronic device in which the display device according to the present embodiment is used.

Claims (11)

A pixel portion in which a pixel circuit for writing image data through a switching element is arranged to form a matrix of at least a plurality of columns, At least one scanning line arranged to correspond to a row arrangement of the pixel circuits and controlling conduction of the switching elements, A plurality of signal lines arranged corresponding to the column arrangement of the pixel circuits and propagating the image data, A horizontal driver circuit having a plurality of signal drivers corresponding to the plurality of groups in which the signal lines are divided and which propagate the image data supplied to the signal lines; And a multiphase clock data generator for dividing a drive pulse having a frequency higher than a normal frequency and supplying a drive pulse shifted in phase to each of the signal drivers, Each of the plurality of signal drivers receives each drive pulse and propagates the image data to a corresponding signal line, Wherein the multi-phase clock data generator supplies the drive pulses each including a clock pulse and a start pulse which are independent of each other, Wherein the clock pulses are phase shifted with respect to each of the signal drivers, Wherein the start pulse is phase-shifted with respect to each of the signal drivers, And the rise and fall of the start pulse do not overlap with the rise and fall of the clock pulse in each drive pulse. The method according to claim 1, Wherein the signal driver is divided into signal drivers adjacent to each other, Wherein each of the signal drivers receives the image data at a timing synchronized with the drive pulse. The method according to claim 1, The multi-phase clock data generator comprises: The image data is divided and rearranged into a data array for input to the signal driver. delete delete delete The method according to claim 1, The shift period? Of the phase of the drive pulse is set so as to satisfy the relationship?? (T / 2) / N, where (T / 2) is a half period of an image clock and N is a number / RTI > delete The method according to any one of claims 1, 2, 3, and 7, Further comprising a selector switch for selecting image data in a time division manner between each signal driver and a signal line corresponding thereto. A pixel circuit for writing image data through a switching element includes a pixel portion forming a matrix of at least a plurality of columns, Disposing at least one scanning line for controlling conduction of the switching element corresponding to the row arrangement of the pixel circuits; Disposing a plurality of signal lines for propagating the image data corresponding to the column arrangement of the pixel circuits; Disposing a horizontal driver circuit having a plurality of signal drivers for propagating the image data supplied to the signal lines corresponding to the plurality of groups in which the signal lines are divided; Dividing a drive pulse having a frequency higher than a normal frequency and supplying a drive pulse whose phase is shifted to each of the signal drivers; And causing each of the plurality of signal drivers to propagate the image data to a corresponding signal line in response to a received drive pulse, Each of said drive pulses being supplied to a signal driver comprising clock pulses independent of each other and a start pulse, Wherein the clock pulses are phase shifted with respect to each of the signal drivers, Wherein the start pulse is phase-shifted with respect to each of the signal drivers, Wherein the rise and fall of the start pulse do not overlap the rise and fall of the clock pulse in each drive pulse. With a display device, The display device includes: A pixel portion in which a pixel circuit for writing image data through a switching element is arranged to form a matrix of at least a plurality of columns, At least one scanning line arranged to correspond to a row arrangement of the pixel circuits and controlling conduction of the switching elements, A plurality of signal lines arranged corresponding to the column arrangement of the pixel circuits and propagating the image data, A horizontal driver circuit having a plurality of signal drivers corresponding to the plurality of groups in which the signal lines are divided and which propagate the image data supplied to the signal lines; And a multiphase clock data generator for dividing a drive pulse having a frequency higher than a normal frequency and supplying a drive pulse shifted in phase to each of the signal drivers, Each of the plurality of signal drivers receives each drive pulse and propagates the image data to a corresponding signal line, Wherein the multi-phase clock data generator supplies the drive pulses each including a clock pulse and a start pulse which are independent of each other, Wherein the clock pulses are phase shifted with respect to each of the signal drivers, Wherein the start pulse is phase-shifted with respect to each of the signal drivers, Wherein the rise and fall of the start pulse do not overlap with the rise and fall of the clock pulse in each drive pulse.

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