JP2007102219A - Integrated circuit for image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily perform signal processing to high-frequency image signals. <P>SOLUTION: Digital image signals are latched in four latches respectively in response to four latch clock signals, which have a quarter frequency of a dot clock signal and have phases mutually shifted by every period of the dot dock signal. The four latched digital image signals are further latched by a common latch in response to a common latch signal, and are then output as one set of digital image signals to four consecutive pixels. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an integrated circuit for an image processing apparatus having AD conversion and DA conversion functions, and more particularly to a technique for processing a high-frequency image signal.

  In an image processing apparatus, an input analog image signal is converted into a digital image signal by an AD converter, and various processes are performed on the converted digital image signal, and then DA conversion is performed to return the analog image signal to a display. An image is displayed on the device.

  The frequency of an image signal that must be handled in this image processing apparatus tends to gradually increase with the progress of video technology in recent years. Therefore, it is necessary to increase the processing speed of the hardware circuit for realizing the image processing apparatus in accordance with the increase in the frequency of the image signal. However, in general, the processing speed of the hardware circuit depends on the performance of a device for configuring the hardware circuit, and thus there is a problem that it is difficult to handle a high-frequency image signal.

  The present invention has been made to solve the above-described problems in the prior art, and an object thereof is to provide a technique capable of easily processing a signal with respect to an image signal having a high frequency.

In order to solve at least a part of the problems described above, an image processing apparatus according to the present invention includes:
A first dot clock generation circuit that generates a first dot clock signal having a frequency for sampling the first analog image signal in synchronization with a first synchronization signal of the input first analog image signal When,
An AD converter that quantizes and converts the first analog image signal into a digital image signal and sequentially outputs the digital image signal of each pixel sampled in synchronization with the first dot clock signal;
Mw (Mw is an integer greater than or equal to 2) Mw pixel signal holding circuits that sequentially hold the digital image signal for each pixel, and Nw (Nw is an integer between 1 and Mw; A serial-to-parallel converter that outputs a digital image signal of consecutive pixels (indicating the number of pixel signal holding circuits used) in parallel as a set of digital image signals;
A first sampling clock generation circuit that generates a first sampling clock signal having a second frequency that is 1 / Nw of the frequency of the first dot clock signal in synchronization with the first synchronization signal;
Nw second sampling clock signals having the frequency of the first sampling clock signal and having different phases sequentially for each cycle of the first dot clock signal according to the number Nw of the pixel signal holding circuits used. A second sampling clock generation circuit for generating;
The operation of the first and second sampling clock generation circuits is controlled according to the value of the used number Nw, and the Nw second sampling clock signals are supplied to the used Nw pixel signal holding circuits. Write control signal adjusting means for outputting digital image signals of Nw consecutive pixels from the serial-parallel converter as a set of digital image signals by
It is characterized by providing.

  In this image processing apparatus, digital image signals of Nw consecutive pixels quantized and output by the AD converter are held one by one in the Nw pixel signal holding circuits in the series-parallel converter, Since each Nw pixel digital image signal is output in parallel as a set of digital image signals, the digital image signal can be processed at a frequency of 1 / Nw of the relatively low frequency of the first dot clock signal. it can. Further, in this image processing apparatus, even when the frequency of the first dot clock signal is high by adjusting the number Nw of pixel signal holding circuits according to the frequency of the first analog image signal, the comparison is performed. Since the digital image signal can be handled at the frequency of the first sampling clock signal that is low, the first analog image signal from a relatively low frequency to a very high frequency can be handled.

In the image processing apparatus,
A selection control circuit for stopping the operation of the unused (Mw-Nw) pixel signal holding circuits;
The write control signal adjusting means includes
It is preferable to control the selection control circuit according to the value of the used number Nw.

  In this way, the operation of the unused (Mw−Nw) pixel signal holding circuits can be stopped, so that power consumption can be reduced.

In the image processing apparatus,
It is preferable to provide a number determining circuit that determines the number Nw of the pixel signal holding circuits to be used according to the frequency of the first dot clock signal.

  The number determining circuit is configured to select a signal frequency that can process a digital image signal output from a serial-parallel converter in the image processing apparatus and a first dot clock signal according to the frequency of the first dot clock signal. The number Nw of pixel signal holding circuits can be determined (from the relationship with the frequency of the pixel). Thereby, it is possible to automatically cope with the first analog image signal from a relatively low frequency to a very high frequency.

In the image processing apparatus,
The Nw second sampling clock signals having different sequential phases are preferably output from the image processing apparatus together with the one set of digital image signals.

  In this way, it is possible to reliably sample a set of digital image signals using the Nw second sampling clock signals having different sequential phases used in the Nw pixel signal holding circuits.

In the image processing apparatus,
The second sampling clock generation circuit includes:
The Nw second sampling clock signals having sequentially different phases may be generated in accordance with the first sampling clock signal and the first dot clock signal.

Alternatively, the second sampling clock generation circuit includes:
The Nw second sampling clock signals having different phases may be generated by sequentially delaying the first sampling clock signals.

The first sampling clock generation circuit includes:
Further, a 90-degree phase difference clock signal having a phase difference of 90 degrees from the first sampling clock signal is generated,
The second sampling clock generation circuit includes:
The Nw second sampling clock signals having different phases may be sequentially generated from the first sampling clock signal and the 90-degree phase difference clock signal.

  In any case, the second sampling clock generation circuit can easily generate Nw second sampling clock signals having sequentially different phases. Among the three types of second sampling clock generation circuits, the second and third second sampling clock generation circuits in particular do not use the first dot clock signal having a high frequency, but the second sampling clock signal. Can be generated. Therefore, the configuration of the second sampling clock generation circuit is easy.

Further, the second sampling clock generation circuit includes:
The sequential phase differs according to the pulse of the first synchronization signal so that the first synchronization signal and each of the Nw second sampling clock signals having different sequential phases have a certain phase relationship. It is preferable to initialize the Nw second sampling clock signals.

  In this way, since each of the Nw second sampling clock signals always has the same phase relationship as the first synchronization signal, the time series of the first analog image signal included between the first synchronization signals is increased. Each of the aligned pixels can always be sampled with the same constant phase relationship.

In the image processing apparatus,
A third sampling clock generation circuit for generating a third sampling clock signal having a phase suitable for sampling the set of digital image signals;
The third sampling clock signal is preferably output from the image processing apparatus together with the one set of digital image signals.

  In this way, a set of digital image signals can be reliably sampled using the third sampling clock signal.

In the image processing apparatus,
Further, a fourth sampling clock that generates a fourth sampling clock signal having a frequency Nx (Nx is an integer of 2 or more) times the frequency of the first dot clock signal in synchronization with the first synchronization signal. A generation circuit,
The AD converter includes a ΔΣ modulation circuit and a digital filter, quantizes the first analog image signal according to the fourth sampling clock signal, and synchronizes with the first dot clock signal. You may make it output the sampled digital image signal of each pixel in order.

  An AD converter including a ΔΣ modulation circuit and a digital filter can realize high-speed and high-precision processing with a relatively small configuration.

In the image processing apparatus,
The first analog image signal includes a plurality of color signals,
The AD converter includes a plurality of AD conversion elements corresponding to the respective color signals,
The serial-parallel converter may include a plurality of conversion elements corresponding to the respective color signals.

In the image processing apparatus,
The serial-to-parallel converter is:
A multi-stage digital image signal phase adjustment circuit group for outputting Nw digital image signals as the same phase,
The multi-stage digital image signal phase adjustment circuit group has a hierarchical structure in which the number of circuits included in each stage gradually decreases toward the final stage,
Each of the plurality of digital image signal phase adjustment circuits included in each stage other than the final stage holds the input digital image signals at a constant phase different from that of the other digital image signal phase adjustment circuits of the stage. To the next stage digital image signal phase adjustment circuit,
The final stage digital image signal phase adjustment circuit may hold the Nw digital image signals supplied from the previous stage in the same phase.

  In this way, each stage of the digital image signal phase adjustment circuit can perform sampling with relatively sufficient timing, so that Nw digital image signals having different phases can be easily converted into digital image signals having the same phase. be able to.

In the image processing apparatus,
An image memory for storing digital image signals;
Write control means for writing digital image signals of the Nw consecutive pixels into a continuous storage area in the image memory;
It is preferable to provide.

  The writing control means writes the Nw digital image signals for the obtained Nw pixels in a continuous storage area of the image memory, so that the image signals are stored in the image memory as in the original pixel array. Is done.

Here, the writing control means
A plurality of stages of digital image signal phase adjustment circuits for outputting Nw digital image signals output in parallel from the serial-parallel converter as the same phase;
The multi-stage digital image signal phase adjustment circuit group has a hierarchical structure in which the number of circuits included in each stage gradually decreases toward the final stage,
Each of the plurality of digital image signal phase adjustment circuits included in each stage other than the final stage holds the input digital image signals at a constant phase different from that of the other digital image signal phase adjustment circuits of the stage. To the next stage digital image signal phase adjustment circuit,
The final stage digital image signal phase adjustment circuit may hold the Nw digital image signals supplied from the previous stage in the same phase.

In the image processing apparatus,
Mr DA (Mr is an integer of 2 or more) DA converter, a second dot clock generation circuit for generating a second dot clock signal having a frequency for sampling the output second analog image signal, and The second analog image signal having a frequency of 1 / Nr of the frequency of the second dot clock signal (Nr is an integer not less than 1 and not more than Mr, indicating the number of DA converters to be used) A fifth sampling clock generation circuit for generating a fifth sampling clock signal synchronized with the second synchronization signal;
A sixth sampling clock signal for generating Nr sixth sampling clock signals having the frequency of the fifth sampling clock signal and having different phases sequentially for each cycle of the second dot clock signal is generated from the second dot clock signal. A sampling clock generation circuit,
Read control means for reading out digital image signals of Nr consecutive pixels from the image memory in synchronization with the fifth sampling clock signal;
A DA conversion selection control circuit for stopping the operation of (Mr−Nr) DA converters that are not used according to the value of the used number Nr;
The DA converter usage number Nr is determined in accordance with the frequency of the second dot clock signal, the DA conversion selection control circuit is controlled, and the operations of the fifth and sixth sampling clock generation circuits are controlled by the usage number. The digital image signals of the Nr consecutive pixels are sequentially DA-converted by the Nr DA converters in accordance with the Nr fifth sampling clock signals, respectively, so that the phases are mutually phased. Reading control signal adjusting means for generating Nr partial analog image signals having different
A video switch that generates the second analog image signal by sequentially switching the Nr partial analog image signals output from the Nr DA converters in synchronization with the second dot clock signal; ,
You may make it provide.

  In the image processing apparatus, since the DA converter only needs to perform DA conversion at a frequency 1 / Nr of the second dot clock signal, the digital image signal is converted to a high-frequency analog image signal at a relatively low frequency. be able to. Further, the video switch can generate an analog image signal representing an image according to the original pixel arrangement by simply switching Nr partial analog image signals sequentially. Note that the number Nw of pixel signal holding circuits and the number Nr of DA converters may be different from each other or may be the same value. In the first image processing apparatus, the second analog signal from a relatively low frequency to a very high frequency is further adjusted by adjusting the number Nr of DA converters used in accordance with the frequency of the second analog image signal. It can correspond to an image signal. In addition, since the operations of the (Mr-Nr) DA converters that are not used can be stopped, there is an effect that power consumption can be reduced.

An integrated circuit of the present invention generates a first dot clock signal having a frequency for sampling the first analog image signal in synchronization with a first synchronization signal of the input first analog image signal A first dot clock generation circuit that quantizes the first analog image signal to convert it to a digital image signal, and sequentially outputs the digital image signal of each pixel sampled in synchronization with the first dot clock signal. An output AD converter;
Mw (Mw is an integer greater than or equal to 2) Mw pixel signal holding circuits that sequentially hold the digital image signal for each pixel, and Nw (Nw is an integer between 1 and Mw; A serial-to-parallel converter that outputs a digital image signal of consecutive pixels (indicating the number of pixel signal holding circuits used) in parallel as a set of digital image signals;
A first sampling clock generation circuit that generates a first sampling clock signal having a frequency of 1 / Nw of the frequency of the first dot clock signal in synchronization with the first synchronization signal;
One period of the first dot clock signal having the frequency of the first sampling clock signal according to the number Nw of the pixel signal holding circuits set according to the frequency of the first dot clock signal. A second sampling clock generation circuit for generating Nw second sampling clock signals having different phases one by one,
The operations of the first and second sampling clock generation circuits are controlled according to the value of the number Nw of pixel signal holding circuits used, and the Nw second sampling clocks are used in the Nw pixel signal holding circuits to be used. When the signal is supplied, digital image signals of Nw consecutive pixels are output from the serial-parallel converter as a set of digital image signals.

  When this integrated circuit is applied to an image processing apparatus, the same operation and effect as the image processing apparatus of the present invention can be obtained. Further, since the frequency of the digital image signal output from the integrated circuit of the present invention is relatively low, which is 1 / Nw of the frequency of the first dot clock signal, it is affected by noise generated by the presence of a high frequency signal. Can be relatively reduced.

In the above integrated circuit,
A selection control circuit for stopping the operation of the unused (Mw-Nw) pixel signal holding circuits;
It is preferable that the operation of the selection control circuit is controlled according to the value of the number Nw of pixel signal holding circuits.

  In this way, the operation of the unused (Mw−Nw) pixel signal holding circuits can be stopped, so that power consumption can be reduced.

In the above integrated circuit,
It is preferable that the Nw second sampling clock signals having different sequential phases are output from the integrated circuit together with the one set of digital image signals.

  In this way, a set of digital image signals output from the integrated circuit can be reliably sampled using the Nw second sampling clock signals having different sequential phases.

In the above integrated circuit,
The second sampling clock generation circuit includes:
The Nw second sampling clock signals having sequentially different phases may be generated in accordance with the first sampling clock signal and the first dot clock signal.

Alternatively, the second sampling clock generation circuit includes:
The Nw second sampling clock signals having different phases may be generated by sequentially delaying the first sampling clock signals.

The first sampling clock generation circuit includes:
Further, a 90-degree phase difference clock signal having a phase difference of 90 degrees from the first sampling clock signal is generated,
The second sampling clock generation circuit includes:
The Nw second sampling clock signals having different phases may be sequentially generated from the first sampling clock signal and the 90-degree phase difference clock signal.
Further, the second sampling clock generation circuit includes:
The sequential phase differs according to the pulse of the first synchronization signal so that the first synchronization signal and each of the Nw second sampling clock signals having different sequential phases have a certain phase relationship. Nw second sampling clock signals may be initialized.

In the above integrated circuit,
A third sampling clock generation circuit for generating a third sampling clock signal having a phase suitable for sampling the set of digital image signals;
The third sampling clock signal may be output from the image integration circuit together with the set of digital image signals.

The integrated circuit further includes:
Further, a fourth sampling clock that generates a fourth sampling clock signal having a frequency Nx (Nx is an integer of 2 or more) times the frequency of the first dot clock signal in synchronization with the first synchronization signal. A generation circuit,
The AD conversion circuit includes a ΔΣ modulation circuit and a digital filter, quantizes the first analog image signal according to the fourth sampling clock signal, and synchronizes with the first dot clock signal. You may make it output the sampled digital image signal of each pixel in order.

  An AD converter including a ΔΣ modulation circuit and a digital filter is suitable for the integrated circuit of the present invention because it can realize high-speed and high-precision processing with a relatively small configuration.

A. First embodiment:
Next, embodiments of the present invention will be described based on examples. FIG. 1 is a block diagram showing the overall configuration of an image processing apparatus as a first embodiment of the present invention. The image processing apparatus includes a synchronization separation circuit 20, a write sampling clock generation unit 30, three AD conversion units 40 corresponding to RGB three-color image signals, a frame memory 50, a video processor 60, and a read sampling. The computer includes a clock generation unit 70, three DA conversion units 80 respectively corresponding to RGB three-color image signals, a display control circuit 90, a display device 100, a CPU 110, a number determination circuit 140, and a RAM 120. . The video processor 60, the CPU 110, the RAM 120, and the number determination circuit 140 are connected to each other by a bus 130. The two sampling clock generation units 30 and 70 and the display control circuit 90 are also connected to the bus 130, but their connection is omitted in FIG.

  The synchronization separation circuit 20 separates a synchronization signal (horizontal synchronization signal HSYNC1 and vertical synchronization signal VSYNC1) from the input composite image signal CV, and the synchronization signal and a component image signal (analog image signal not including a synchronization signal). Output. The component image signal AV1 is composed of three color signals representing RGB three-color images. The horizontal synchronization signal HSYNC1 separated by the synchronization separation circuit 20 is supplied to the write sampling clock generation unit 30.

  The component image signal AV1 output from the synchronization separation circuit 20 is converted into a digital image signal for each color signal by the three AD converters 40. Detailed operation of the AD converter 40 will be described later.

  The video processor 60 is a microprocessor for performing image writing control and reading control on the frame memory 50. Digital image signals obtained by the three AD converters 40 are once written in the frame memory 50 and read out from the frame memory 50 as necessary. In the present embodiment, although not specifically described, various image processing, for example, image enlargement / reduction processing, is usually performed in the process of writing or reading an image signal to / from the frame memory 50. The digital image signals read from the frame memory 50 are converted into three analog color signals by the three DA converters 80, respectively. This conversion operation will be described later. An analog image signal AV2 composed of these three color signals is supplied to the display apparatus 100. The display device 100 displays an image according to the analog image signal AV2 and the synchronization signals (vertical synchronization signal VSYNC2 and horizontal synchronization signal HSYNC2) supplied from the display control circuit 90.

  The AD conversion operation and the image signal writing operation to the frame memory 50 are performed in synchronization with the synchronization signal output from the synchronization separation circuit 20. The write sampling clock generation unit 30 generates a plurality of clock signals used by the AD conversion unit 40 based on the horizontal synchronization signal HSYNC1, supplies the clock signals to the AD conversion unit 40, and is executed via the video processor 60. A write sampling clock signal Sw used for various operations such as a write operation to the frame memory 50 is generated and supplied to the video processor 60.

  The reading operation of the image signal from the frame memory 50 and the DA conversion operation of the read image signal are performed in synchronization with the synchronization signal output from the display control circuit 90. The readout sampling clock generation unit 70 generates a plurality of clock signals used by the DA conversion unit 80 based on the horizontal synchronization signal HSYNC2, supplies the clock signals to the DA conversion unit 80, and is executed via the video processor 60. A read sampling clock signal Sr used for various image processing, for example, a read operation from the frame memory 50 is generated and supplied to the video processor 60.

  The RAM 120 stores a computer program that functions as the write control signal adjustment unit 122 and a computer program that functions as the read control signal adjustment unit 124. The write control signal adjusting unit 122 sets parameters (described later) for adjusting the frequency of various clock signals used at the time of writing in the write sampling clock generation unit 30. Further, the read control signal adjusting unit 124 sets parameters (described later) for adjusting the frequencies of various clock signals used at the time of reading in the read sampling clock generation unit 70. The function of each of these means will be described later.

  Note that the computer program that realizes the functions of these means is provided in a form recorded on a computer-readable recording medium such as a floppy disk or a CD-ROM. The computer (image processing apparatus) reads the computer program from the recording medium and transfers it to the internal storage device or the external storage device. Or you may make it supply a computer program to a computer from a program supply apparatus via a communication path. When realizing the functions of a computer, a computer program stored in an internal storage device is executed by the CPU 110 (microprocessor) of the computer. The computer program recorded on the recording medium may be directly executed by the computer.

  In this specification, the computer is a concept including a hardware device and an operation system, and means a hardware device that operates under the control of the operation system. Further, when an operation system is unnecessary and a hardware device is operated by an application program alone, the hardware device itself corresponds to a computer. The hardware device includes at least a microprocessor such as a CPU and means for reading a computer program recorded on a recording medium. The computer program includes program code for causing such a computer to realize the functions of the above-described means. Note that some of the functions described above may be realized by an operation system instead of an application program.

  The “recording medium” in the present invention includes a flexible disk, a CD-ROM, a magneto-optical disk, an IC card, a ROM cartridge, a punch card, a printed matter on which a code such as a bar code is printed, an internal storage device (RAM) of a computer. And various media that can be read by a computer such as an external storage device.

  FIG. 2 is a block diagram showing the internal configuration of the write sampling clock generator 30 and one AD converter 40. The write sampling clock generation unit 30 includes three PLL circuits 31, 32, and 33, a sampling clock selection generation circuit 34, a selection control circuit 35, a delay adjustment circuit 36, and a CPU interface circuit 38. The AD conversion unit 40 includes an AD converter 43 having a ΔΣ modulation circuit 41 and a digital filter 42, and four latches 44 to 47 and a common latch 48 that latches signals supplied from the four latches 44 to 47 at the same timing. And a serial-to-parallel converter 49.

  FIG. 3A to FIG. 3O are timing charts of main signals related to the image signal writing operation. In the following, the operation of the circuit of FIG. 2 will be described with reference to the timing charts of FIGS. 3 (a) to 3 (o).

  The first PLL circuit 31 of the write sampling clock generation unit 30 multiplies the horizontal synchronization signal HSYNC1 provided from the synchronization separation circuit 20 (FIG. 1) by Ns1 times, thereby providing a reference for the write operation of the image processing apparatus. The write reference clock signal SDCLK1 is generated. The second PLL circuit 32 generates the dot clock signal DCLK1 by multiplying the write reference clock signal SDCLK1 by Nw times. The third PLL circuit 33 generates the quantized sampling signal SADC used for the AD conversion operation of the AD converter 43 by multiplying the dot clock signal DCLK1 by Nx. 3A to 3D, the analog image signal AV1, the write reference clock signal SDCLK1, the dot clock signal DCLK1, and the AD-converted digital image signal DV1 input to the AD converter 43 are shown. The waveform is shown. The signal level of the analog image signal AV1 shown in FIG. 3A has one peak for each pixel. Reference numerals # 1 to # 4 indicate four pixels existing on one horizontal line. The dot clock signal DCLK1 shown in FIG. 3C has a frequency and phase suitable for sampling the analog image signal AV1. The AD converter 43 (FIG. 2) oversamples the analog image signal AV1 by the ΔΣ modulation circuit 41 using the quantized sampling signal SADC obtained by multiplying the dot clock signal DCLK1 by Nx. Then, the oversampled quantized data is processed by the digital filter 42 to be converted into a digital pixel signal of each pixel corresponding to the pixels # 1, # 2, # 3, # 4,..., And the dot clock signal DCLK1 The digital image signal DV1 synchronized with the rising edge is output. Here, “oversampling” refers to sampling a signal using a clock signal having a frequency higher than the frequency of the dot clock signal.

  Since this digital image signal DV1 is a signal in which the digital pixel signals of each pixel are arranged in time series in the order of pixels # 1, # 2, # 3, # 4,..., The dot clock signal DCLK1 has a very high frequency. If so, various processing systems (circuits) that perform image processing such as writing operations performed via the video processor 60 (FIG. 1) must also be accelerated. However, since the processing speed of the circuit depends on the performance of the devices constituting the circuit, it may be difficult to realize. On the other hand, in this embodiment, as will be described below, even when the dot clock signal DCLK1 has a very high frequency, the image processing executed through the video processor 60 is performed by the dot clock signal DCLK1. Realized at a fraction of the frequency.

  The frequency of the dot clock signal DCLK1 is determined according to the resolution of the input image signal. However, the frequency is not necessarily limited to the frequency determined according to the resolution of the input image. For example, if the resolution of the image handled by the image processing apparatus is ½ of the resolution of the input image, the frequency of the dot clock signal DCLK1 may be ½ of the frequency determined by the resolution of the input image.

  The write reference clock signal SDCLK1 shown in FIG. 3B is synchronized with the synchronization signal HSYNC1 of the input analog image signal AV1, and 1 / Nw (Nw is the second PLL) of the frequency of the dot clock signal DCLK1. Frequency of circuit 32). Normally, the multiplication number Nw of the second PLL circuit 32 is set equal to the total number of latches 44 to 47. That is, the value of the multiplication number Nw is set to 4 in the case of FIG.

  The sampling clock selection generation circuit 34 receives four latch clock signals SLT1 to SLT4 to be supplied to the four latches 44 to 47 from the dot clock signal DCLK1 and the write reference clock signal SDCLK1, and a common to be supplied to the common latch 48. A latch clock signal CLT is generated. 3 (e), 3 (g), 3 (i), and 3 (k) show waveforms of four latch clock signals SLT1 to SLT4. The four latch clock signals SLT1 to SLT4 have the same frequency as that of the write reference clock signal SDCLK1, and sequentially differ in phase by 1/4 of one cycle of the write reference clock signal SDCLK1 (one cycle of the dot clock signal DCLK1). Signal. The sampling clock selection generation circuit 34 generates four latch clock signals SLT1 to SLT4 by sequentially selecting and outputting pulses from the dot clock signal DCLK1 at a ratio of one pulse to four pulses. FIG. 3 (m) shows the waveform of the common latch clock signal CLT. The common latch clock signal CLT is equal to the frequency of the write reference clock signal SDCLK1, and has a rising edge in a period between the rising edge of the fourth latch clock signal SLT4 and the rising edge of the first latch clock signal SLT1. Signal. As the common latch clock signal CLT, the write reference clock signal SDCLK1 may be used as it is. Also, the write reference clock signal SDCLK1 is delayed and adjusted so as to have a rising edge in a period between the rising edge of the fourth latch clock signal SLT4 and the rising edge of the first latch clock signal SLT1. Can be generated.

  As shown in FIG. 2, the digital image signal DV1 is commonly input to the four latches 44 to 47, and the four latch clock signals SLT1 to SLT4 are respectively supplied thereto. The first latch 44 latches the digital image signal DV1 at the rising edge of the first latch clock signal SLT1. In FIG. 3F, as the digital image signal D1 output from the first latch 44, the digital pixel signal of the first pixel # 1 is latched and output at the rising edge of the first latch clock signal SLT1. The state is shown. Similarly, in FIG. 3H, as the digital image signal D2 output from the second latch 45, the digital pixel signal of the second pixel # 2 is latched at the rising edge of the second latch clock signal SLT2. The output status is shown. In FIG. 3J, the digital pixel signal of the third pixel # 3 is latched at the rising edge of the third latch clock signal SLT3 as the digital image signal D3 output from the third latch 46. The output status is shown. Further, in FIG. 3L, as the digital image signal D4 output from the fourth latch 47, the digital pixel signal of the fourth pixel # 4 is latched at the rising edge of the fourth latch clock signal SLT4. The output status is shown.

  The digital image signals D1 to D4 for four pixels obtained in this way are input to the common latch 48. The common latch 48 latches the digital image signals D1 to D4 for four pixels at the rising edge of the common latch signal CLT. In FIG. 3 (n), a digital image signal Dcom including a set of digital image signals D1 to D4 (each 8 bits × 4) for 4 pixels (8 bits for one pixel digital pixel signal) is output from the common latch 48. The output status is shown.

  As described above, the serial-parallel converter 49 converts the digital image signal DV1 supplied by the four latches 44 to 47 and the common latch 48 in synchronization with the rising edge of the dot clock signal DCLK1 to 1 / of the dot clock signal DCLK1. In synchronization with the write reference clock signal SDCLK1 having a frequency of 4, the signal is converted into a 32-bit digital image signal Dcom in which four pixels are set as one set.

  As shown in FIGS. 3K and 3N, the delay adjustment circuit 36 sets the phase of the rising edge of the common latch signal CLT (or write reference clock signal SDCLK1) from the rising edge of the latch clock signal SLT4. The write sampling clock signal Sw for reliably sampling the digital image signal Dcom is generated via the video processor 60 and supplied to the video processor 60. Thus, the video processor 60 can reliably sample the digital image signal Dcom using the write sampling clock signal Sw.

  As shown in FIG. 1, the image processing apparatus of this embodiment includes three AD conversion units 40 so as to correspond to three color signals. The operation of each AD converter 40 is exactly the same. Accordingly, each AD conversion unit 40 outputs a 32-bit digital image signal Dcom, which is a set of four pixels of each color signal.

  The digital image signal Dcom is written in a continuous storage area in the frame memory 50. This write operation is performed in synchronization with the write sampling clock signal Sw (FIG. 3 (o)). The digital image signal Dcom, which is a set of four pixels, is 32 bits per color signal, the total is 96 bits, and corresponds to 12 bytes. Therefore, the video processor 60 performs one write operation. Each time the write address (pixel address) given to the frame memory 50 is increased by 12. When the writing of the digital image signal for one line is completed, the line address is incremented by 1, and the pixel address is initialized. As a result, the digital image signals of all the pixels on each line are written in continuous storage areas in the frame memory 50. That is, in the frame memory 50, 24-bit image signals for one pixel including the three color components of RGB are arranged and stored according to the pixel arrangement in the original image. As described above, since the digital image signals of all the pixels on the same line are stored in continuous addresses in the frame memory 50, when reading the digital image signals from the frame memory 50, an arbitrary position is obtained. The digital image signal can be easily read out. The frame memory 50 may be composed of three memories for writing each of the three color image signals separately. In this case, the three color image signals are respectively written in the continuous storage areas in the respective memories.

  In the write sampling clock generator 30 shown in FIG. 2, the first PLL circuit 31 and the second PLL circuit 32 generate a dot clock signal DCLK1 suitable for sampling the analog image signal AV1. Further, the first PLL circuit 31 generates the write reference clock signal SDCLK1 having a frequency that is 1/4 of the dot clock signal DCLK1. In addition, the sampling clock selection generation circuit 34 generates four latch clock signals SLT1 to SLT4 having a frequency that is ¼ of the dot clock signal DCLK1 and having phases sequentially shifted by one period of the dot clock signal DCLK1. is doing. As can be understood from this description, the first PLL circuit 31 and the second PLL circuit 32 of FIG. 2 correspond to the first dot clock generation circuit in the present invention. The first PLL circuit 31 corresponds to a first sampling clock generation circuit, and the sampling clock selection generation circuit 34 corresponds to a second sampling clock generation circuit. The delay adjustment circuit 36 corresponds to a third sampling clock generation circuit, and the third PLL circuit 33 corresponds to a fourth sampling clock generation circuit.

  The latches 44 to 47 and the common latch 48 in FIG. 2 only need to repeat the latches at the frequencies of the latch clock signals SLT1 to SLT4 and the common latch clock signal CLT, that is, the frequency of the write reference clock signal SDCLK1, and thus are synchronized with the dot clock signal DCLK1 As compared with the case where latching is performed, there is an advantage that the conversion may be performed at a relatively low speed of 1/4. Also, image processing executed via the video processor 60 (FIG. 1), for example, writing to the frame memory 50 is performed by using a set of digital image signals Dcom output from the serial-parallel converter 49 in the frame memory 50. This is done by writing to successive storage areas. Therefore, such image processing may be executed at a frequency that is 1/4 of the dot clock signal DCLK1. In other words, in this embodiment, since the processing operation of the image signal after AD conversion may be performed at a frequency that is ¼ of the frequency of the dot clock signal DCLK1, a relatively low-speed hardware circuit is used. There is an advantage that analog image signals can be handled.

  In the circuit of FIG. 2, only the sampling clock selection / generation circuit 34 and the AD converter 43 operate with the high-frequency dot clock signal DCLK1 and the quantized sampling signal SADC. In other words, the circuit of this embodiment has an advantage that the circuit configuration is relatively simple and the power consumption is small because circuit elements operating at a high frequency are minimized.

  The write sampling clock generation unit 30 and at least one AD conversion unit 40 shown in FIG. 2 are preferably integrated circuits mounted in one package. If these blocks are mounted as an integrated circuit in one package, high frequency signals such as the dot clock signal DCLK1 and the quantized sampling signal SADC exist only in one integrated circuit. It is possible to reduce noise and malfunctions generated in the image processing apparatus due to the above. In addition, the image processing apparatus can be mounted with high density, and the apparatus can be downsized.

  In the AD converter 40, as an example of the AD converter 43, an AD converter having a ΔΣ modulator and a digital filter and oversampling with a quantized sampling signal SADC having a frequency higher than that of the dot clock signal DCLK1 is taken as an example. However, it may be a general AD converter that performs AD conversion using the dot clock signal DCLK1. However, an oversampling AD converter is advantageous in realizing an integrated circuit because it can realize high-speed and high-accuracy AD conversion with a smaller configuration than a general AD converter.

  In a register (not shown) in the CPU interface circuit 38, parameters such as the multiplication numbers Ns1, Nw, Nx of the PLL circuits 31, 32, 33 are set by the write control signal adjusting means 122. The frequency Nw of the second PLL circuit 32 is determined based on the relationship between the frequency of the dot clock signal DCLK1 and the processing speed at which writing to the frame memory 50 is possible, for example. It is set to a frequency that is equal to or lower than the processing speed at which writing to 50 is possible. For example, if the frequency of the dot clock signal DCLK1 is 300 MHz and the frequency of the write reference clock signal SDCLK1 must be 80 MHz or less, the multiplication number Nw is set equal to the number of latches 44 to 47 mounted ( Nw = 4). However, if the frequency of the dot clock signal DCLK1 is sufficiently low and sufficient processing can be performed with one to three latches, it is not always necessary to use all four latches 44 to 47. In such a case, by operating a circuit that is not necessarily required, an amount of power that is not necessarily required in the AD conversion unit 40 is increased, which is not preferable.

  Therefore, in this embodiment, when the frequencies of the latch clock signals SLT1 to SLT4 when using the four latches 44 to 47 are equal to or lower than a predetermined value (for example, 20 MHz), the selection control circuit 35 is connected to the CPU interface circuit 38. The sleep signals SLP1 to SLP4 for pausing some of the four latches 44 to 47 are output in accordance with the conditions set by. For example, when only three latches 44, 45, 46 are used, the sleep signal SLP4 is supplied to the fourth latch 47 to stop its operation. At this time, the multiplication number Nw of the second PLL circuit 32 is set equal to the number of latches used (= 3), and the multiplication number Ns1 of the first PLL circuit 31 is Nw0 / Nw (= 4) of the original value. / 3) (where Nw0 is the total number of latches). As a result, the first PLL circuit 31 generates the write reference clock signal SDCLK1 having a frequency Nw0 / Nw (= 4/3) times the original, and the second PLL circuit 32 has the same frequency as the original. A dot clock signal DCLK1 is generated.

  Note that the horizontal synchronization signal HSYNC1 and vertical synchronization signal VSYNC1 of the input analog image signal AV1 have a specific frequency, phase relationship, signal polarity, and the like depending on the resolution of the image. Therefore, information regarding the synchronization signal for each resolution of the main image is stored in advance as a table in a memory or the like, and the synchronization signal separated by the synchronization separation circuit 20 (FIG. 1) is analyzed by the number determination circuit 140, and the memory The frequency of the corresponding analog image signal AV1 (that is, the dot clock signal DCLK1) can be obtained from the table stored in FIG. The number Nw of latches can be determined from the relationship between the signal frequency at which the digital image signal Dcom output from the serial-parallel conversion circuit can be processed in the image processing apparatus and the frequency of the dot clock signal DCLK1. Thereby, it is possible to automatically cope with the first analog image signal from a relatively low frequency to a very high frequency.

  4A to 4O are timing charts of main signals related to the write operation when the operation of the latch 47 is stopped. 4 (a) to 4 (o) show the same signals as those in FIGS. 3 (a) to 3 (o), so only the main part will be described below. As shown in FIG. 4B, the write reference clock signal SDCLK1 has a frequency that is 1/3 of the dot clock signal DCLK1 shown in FIG. As shown in FIGS. 4E, 4G, and 4I, the three latch clock signals SLT1 to SLT3 have the same frequency as the write reference clock signal SDCLK1, and the write reference clock signal SDCLK1 The signals are sequentially different in phase by 1/3 of one cycle (one cycle of the dot clock signal DCLK1). On the other hand, the generation of the pulse signal is stopped in the latch clock signal SLT4 as shown in FIG. As a result, the operation of the latch 47 is stopped, and the serial-parallel converter 49 sets the digital image signal DV1 output from the AD converter 43 to a set of three pixels as shown in FIG. 4 (n). It is converted into a set of digital image signals Dcom of 24 bits (8 bits × 3).

  The write control signal adjusting means 122 has a frequency of the latch clock signals SLT1 to SLT4 supplied to the latches 44 to 47 via the CPU interface circuit 38 within a predetermined range (for example, about 20 MHz to about 100 MHz). As described above, the number Nw (Nw is 1 to 4) of the latches 44 to 47 determined by the number determination circuit 140 is adjusted. By doing so, there is an advantage that it is possible to process analog image signals from a relatively low frequency to a very high frequency, and to select an operation mode that reduces power consumption. There are various methods for stopping the operation of the latch. For example, the supply of the latch clock signal supplied to the latch may be stopped as described above, and the power supply to the latch is stopped. May be.

  The digital image signal stored in the frame memory 50 is read by the video processor 60 and then converted into an analog image signal by the three DA converters 80 corresponding to the RGB three-color signals. FIG. 5 is a block diagram showing the internal configuration of the read sampling clock generator 70 and one DA converter 80. The read sampling clock generation unit 70 includes two PLL circuits 71 and 72, a sampling clock selection generation circuit 74, a selection control circuit 75, and a CPU interface circuit 78. The read sampling clock generator 70 has substantially the same configuration as the write sampling clock generator 30 shown in FIG. The difference is that a PLL circuit corresponding to the third PLL circuit 33 is not provided. The DA conversion unit 80 includes four DA converters 81 to 84.

  The first PLL circuit 71 of the read sampling clock generation unit 70 generates the read reference clock signal SDCLK2 by multiplying the horizontal synchronization signal HSYNC2 given from the display control circuit 90 (FIG. 1) by Ns2. The second PLL circuit 72 generates the dot clock signal DCLK2 by multiplying the read reference clock signal SDCLK2 by Nr times. Further, the sampling clock selection / generation circuit 74 generates four sampling clock signals SDA1 to SDA4 to be supplied to the four DA converters 81 to 84 from the dot clock signal DCLK2 and the read reference clock signal SDCLK2.

  The relationship between the frequency and phase of the four types of signals SDCLK2, DCLK2, SDA1 to SDA4 generated in the read sampling clock generation unit 70 is the same as the four types of signals SDCLK1 generated by the write sampling clock generation unit 30 (FIG. 2). , DCLK1, and SLT1 to SLT4 are substantially the same in frequency and phase. That is, the dot clock signal DCLK2 has a frequency and phase suitable for sampling the analog image signal AV2 supplied to the display device 100. The frequency of the dot clock signal DCLK2 is determined by the type of the display device 100. The frequency of the read reference clock signal SDCLK2 is 1 / Nr of the frequency of the dot clock signal DCLK2. This value Nr (multiplier of the PLL circuit 72) is normally set equal to the total number of DA converters 81 to 84 mounted. Further, the four sampling clock signals SDA1 to SDA4 have a frequency of 1 / Nr of the dot clock signal DCLK2, and sequentially phase by 1/4 of one period of the read reference clock signal SDCLK2 (one period of the dot clock signal DCLK2). Are different signals. As can be understood from this description, the first PLL circuit 71 and the second PLL circuit 72 in FIG. 5 correspond to the second dot clock generation circuit in the present invention. The first PLL circuit 71 corresponds to a fifth sampling clock generation circuit, and the sampling clock selection generation circuit 74 corresponds to a sixth sampling clock generation circuit.

  The four DA converters 81 to 84 DA convert the digital image signals D1 to D4 at the rising edges of the four sampling clock signals SDA1 to SDA4, respectively. In this DA conversion, the digital image signals D1 to D4 input at the rising edges of the input sampling clock signals SDA1 to SDA4 are converted into voltages having a weight for a predetermined reference voltage. By this DA conversion, for example, digital image signals D1 to D4 for four consecutive pixels are converted into four analog image signals A1 to A4 having different phases, respectively. These four analog image signals A1 to A4 are input to the video switch 85. The video switch 85 performs a switching operation so that the four analog image signals A1 to A4 are sequentially selected and output by the switch signal VSW synchronized with the dot clock signal DCLK2. This switch signal VSW is generated in the sampling clock selection generation circuit 74. As a result, an analog image signal AV2 representing an image with the pixel arrangement in the original order is output from the video switch 85. The analog image signals A1 to A4 output from the DA converters 81 to 84 constitute part of the finally output analog image signal AV2, and are also referred to as “partial analog image signals”.

  As described above, in the image processing apparatus according to the embodiment, the reading operation from the frame memory 50 and the DA conversion operation may be performed at a frequency of 1 / Nr of the frequency of the dot clock signal DCLK2. There is an advantage that a high-frequency analog image signal AV2 can be output using a circuit. Further, since only the sampling clock selection / generation circuit 74 and the video switch 85 operate with the high-frequency dot clock signal DCLK2, circuit elements that operate at a high frequency are minimized, and the circuit configuration is relatively simple. In addition, there is an advantage of low power consumption.

  The read control signal adjustment means 124 (FIG. 1) sets the number of DA converters used Nr (this is also equal to the multiplication number of the PLL circuit 72) in the CPU interface circuit 78 of the read sampling clock generation unit 70. Is possible. The CPU interface circuit 78 sets the multiplication numbers Ns2 and Nr of the PLL circuits 71 and 72 according to the number Nr of DA converters used, and performs some operations of the DA converters 81 to 84 as necessary. A condition for stopping is set in the selection control circuit 75. The selection control circuit 75 generates sleep signals SLP5 to 8 based on the set conditions. For example, when the operation of the DA converter 84 is stopped, the sleep signal SLP8 can be supplied to the DA converter 84 to exhibit the operation. Further, the generation of the pulse of the sampling clock signal SDA4 may be stopped. As a result, it is possible to reduce power consumption by DA conversion that is not always necessary.

  As described above, in the frame memory 50, digital image signals of all the pixels on the same line are stored at consecutive addresses. Therefore, when reading a digital image signal from the frame memory 50, a digital image signal at an arbitrary position can be read. Therefore, the number of used latches Nw (FIG. 2) in the serial-parallel converter 49 and the number of used DA converters Nr can be set independently of each other. Also, the number of latches to be mounted and the number of DA converters to be mounted can be determined independently of each other.

B. Second embodiment:
FIG. 6 is a block diagram showing the internal configuration of the write sampling clock generation unit 30 and the AD conversion unit 40A in the second embodiment. The overall configuration of the image processing apparatus according to the second embodiment is substantially the same except that the AD conversion unit 40 in FIG. 1 is replaced with the AD conversion unit 40A, and thus detailed description thereof is omitted.

  The AD conversion unit 40A shows a configuration in which the serial / parallel converter 49 of the AD conversion unit 40 shown in FIG. 2 is replaced with a serial / parallel converter 49A. The common latch 48 of the serial / parallel converter 49 is not necessarily provided in the AD conversion unit 40. For example, it may be provided on the input side of the video processor 60 (FIG. 1). Therefore, the serial / parallel converter 49A shows a configuration in which the common latch 48 of the serial / parallel converter 49 is not provided. Hereinafter, only the delay adjustment of the delay adjustment circuit 36, which is changed by removing the common latch 48, will be described, and description of other functions will be omitted.

  FIGS. 7A to 7O are timing charts of main signals related to the image signal writing operation in the AD conversion unit 40A. The digital image signals D1 to D4 (FIGS. 7 (f), 7 (h), 7 (j), and 7 (l)) for four pixels output from the AD conversion unit 40A are digital image signals DV1 (FIG. d) is an image signal latched by four latch clock signals SLT1 to SLT4 (FIGS. 7 (e), 7 (g), 7 (i), and 7 (k)). These four latch clock signals SLT1 to SLT4 have the same frequency as the write reference clock signal SDCLK1, and are sequentially phased by 1/4 of one cycle of the write reference clock signal SDCLK1 (one cycle of the dot clock signal DCLK1). It is a different signal. Accordingly, the digital image signals D1 to D4 for four pixels output from the AD conversion unit 40A are updated every signal cycle of the latch clock signals SLT1 to SLT4, respectively. In this case, the digital image signals D1 to D4 are latched by the latch clock signals SLT1 to SLT4 in order to securely process the digital image signals D1 to D4 for four pixels via the video processor 60 (FIG. 1). After that, it is necessary to sample the digital image signal for four pixels before the next digital image signal D1 is latched. That is, as shown in FIG. 7 (n), the phase of the rising edge of the write sampling clock signal Sw is preferably adjusted between the rising edge of the latch clock signal SLT4 and the rising edge of the latch clock signal SLT1. The delay adjustment circuit 36 (FIG. 6) adjusts the rising edge of the common latch signal CLT (or write reference clock signal SDCLK1) to generate the write sampling clock signal Sw. Accordingly, the digital image signals D1 to D4 for four pixels can be reliably sampled in the common latch 48 provided on the input side of the video processor 60 using the write sampling clock signal Sw.

C. Third embodiment:
FIG. 8 is a block diagram showing the overall configuration of an image processing apparatus as a third embodiment of the present invention. The configuration of this image processing apparatus is substantially the same as that of the first embodiment shown in FIG. 1, except that the AD conversion unit 40 is replaced with the AD conversion unit 40A shown in FIG. The difference is that the SLT 4 is also supplied to the video processor 60.

  As described in the second embodiment, the digital image signals D1 to D4 output from the AD converter 40A (FIG. 6) are output from the latch clock signals SLT1 to SLT4 in the four latches 44 to 47 of the serial-parallel converter 49A. Latched on rising edge. Therefore, if the video processor 60 uses the latch clock signals SLT1 to SLT4 for sampling the digital image signals D1 to D4, stable sampling can be realized.

D. Fourth embodiment:
FIG. 9 is a block diagram showing the internal configuration of the write sampling clock generator 30A and the AD converter 40A in the fourth embodiment. The overall configuration of the image processing apparatus in the fourth embodiment is substantially the same except that the write sampling clock generation unit 30 in FIG. 8 is replaced with a write sampling clock generation unit 30A. Is omitted.

  The write sampling clock generation unit 30A has substantially the same configuration as the write sampling clock generation unit 30 shown in FIG. 2, except that the sampling clock selection generation circuit 34 is replaced with a sampling clock selection generation circuit 34A. The AD conversion unit 40A has the same configuration as that shown in FIG.

  In addition to the dot clock signal DCLK1, the write reference clock signal SDCLK1 and the horizontal synchronization signal HSYNC1 are input to the sampling clock selection generation circuit 34A of the present embodiment.

  FIG. 10 is a circuit diagram showing an example of the sampling clock selection generation circuit 34A. The sampling clock selection generation circuit 34A includes a shift register composed of four D flip-flops 226a to 226d, and a delay circuit 226e. The write reference clock signal SDCLK1 is input to the data input terminal of the first D flip-flop 226a. The dot clock signal DCLK1 is input to the delay circuit 226e. The dot clock signal DCLK1 'output from the delay circuit 226e is input in common to the clock terminals of the four D flip-flops 226a to 226d. The horizontal synchronization signal HSYNC1 is input in common to the reset terminals of the four D flip-flops 226a to 226d.

  FIGS. 11A to 11G are timing charts showing the operation of the sampling clock selection generation circuit 34A. Hereinafter, the operation of the sampling clock selection generation circuit 34A will be described according to the timing chart of FIG. The first D flip-flop 226a (FIG. 10) samples the write reference clock signal SDCLK1 input from the data input terminal at the rising edge of the dot clock signal DCLK1 ′, and outputs the first latch clock signal SLT1. . 11A to 11C show waveforms of the write reference clock signal SDCLK1, the dot clock signal DCLK1 ', and the first latch clock signal SLT1. The second D flip-flop 226b samples the first latch clock signal SLT1 (FIG. 11C) output from the D flip-flop 226a with the dot clock signal DCLK1 ′, and outputs the second latch clock signal SLT2. To do. Similarly, the D flip-flops 226c and 226d output a third latch clock signal SLT3 and a fourth latch clock signal SLT4, respectively. 11D to 11F show the waveforms of the latch clock signals SLT2 to SLT4. In this way, the sampling clock selection generation circuit 34A outputs four latch clock signals SLT1 to SLT4 (FIGS. 11 (c) to (f)) whose phases are sequentially different by 90 degrees.

  The D flip-flops 226a to 226d change the output signals SLT1 to SLT4 to the L level when the L level is input to their reset terminals. On the other hand, when the H level is input to the reset terminal, the reset state is released, the above operation is started again, and the latch clock signals SLT1 to SLT4 are output. Therefore, if the horizontal synchronization signal HSYNC1 as shown in FIG. 11G is used as the reset signal for the D flip-flop, the phase relationship between the horizontal synchronization signal HSYNC1 and the four latch clock signals SLT1 to SLT4 is always kept in the same phase relationship. It becomes possible.

  When the latch clock signals SLT1 to SLT4 are supplied to the latches 44 to 47 (FIG. 9), the image signal of the first pixel of each horizontal line can always be sampled by the first latch 44. On the other hand, when the reset operation by the horizontal synchronization signal HSYNC1 as described above is not performed, the latch for sampling the image signal of the first pixel existing on one horizontal line is not fixed, and any latch is There is a possibility that it is used for each horizontal line. On the other hand, in the present embodiment, the first pixel signal is always sampled by the first latch 44. The reset signal is not limited to the horizontal synchronization signal HSYNC1 shown in FIG. 11 (g). For example, another signal having a pulse that always occurs in a constant phase relationship with the pulse of the horizontal synchronization signal HSYNC1 is used. Also good.

  FIG. 12 is a timing chart showing the output of the digital image signals D1 to D4 in the present embodiment. 12A to 12C show the waveforms of the horizontal synchronization signal HSYNC1, the write reference clock signal SDCLK1, and the dot clock signal DCLK1. FIG. 12D shows the waveform of the digital image signal DV1 output from the AD converter 43 (FIG. 9). The analog image signal AV1 input to the AD converter 43 is converted into a digital image signal DV1, and is output in synchronization with the rising edge of the dot clock signal DCLK1 (FIG. 12 (c)). The digital image signal DV1 is input in common to the four latches 44 to 47, and is held according to the latch clock signals SLT1 to SLT4. The four digital image signals D1 to D4 held by the latches 44 to 47 are sequentially output as data having different phases by 90 degrees. 12E to 12H show the waveforms of the latch clock signals SLT1 to SLT4. FIGS. 12I to 12L show the digital image signals D1 to D1 output in accordance with the latch clock signals SLT1 to SLT4. D4 is shown.

  FIG. 12 shows a case where each of the latch clock signals SLT1 to SLT4 is supplied to the latches 44 to 47 and the sampling operation (latch operation) is performed in the order of the latches 44, 45, 46 and 47. The operation order of the latches may be changed by changing the latch that supplies each of the latch clock signals SLT1 to SLT4.

  Although the present embodiment shows a case where the waveforms of the latch clock signals SLT1 to SLT4 are substantially equal in the high level and low level periods, the present invention is not limited to this. As shown in the first embodiment, the ratio between the high level and low level periods may be different as 1: 7. That is, it is only necessary that the phases of the rising edges of the latch clock signals SLT1 to SLT4 indicating the sampling (latching) timing of the latches 44 to 47 are sequentially shifted by 90 degrees. Such deformation of the waveforms of the latch clock signals SLT1 to SLT4 can be easily performed using the dot clock signal DCLK1, the write reference clock signal SDCLK1, and the like. Further, such waveform deformation can be similarly performed in the other embodiments.

  In this embodiment, the internal configuration of the write sampling clock generation unit 30A has been described. However, the above configuration can be similarly applied to the read sampling clock generation unit 70.

E. Example 5:
FIG. 13 is a block diagram showing the internal configuration of the write sampling clock generator 30B and the AD converter 40A in the fifth embodiment. The overall configuration of the image processing apparatus in the fifth embodiment is substantially the same except that the write sampling clock generator 30 in FIG. 8 is replaced with a write sampling clock generator 30B. Is omitted.

  The write sampling clock generation unit 30B has substantially the same configuration as the write sampling clock generation unit 30 shown in FIG. 2, except that the sampling clock selection generation circuit 34 is replaced with a sampling clock selection generation circuit 34B. The AD conversion unit 40A has the same configuration as that shown in FIG.

  FIG. 14 is a block diagram showing an internal configuration of the sampling clock selection generation circuit 34B. The sampling clock selection / generation circuit 34B includes a phase comparator 367 and four delay circuits 368a to 368d. Each of the delay circuits 368a to 368d includes an Up / Down counter and a delay adjustment circuit (not shown). As the delay adjustment circuit, for example, a circuit in which a plurality of delay adjustment buffers are arranged in series can be used.

  The phase comparator 367 is a circuit that compares the phases of two input signals and outputs an Up / Down signal corresponding to the phase difference. To the phase comparator 367, the write reference clock signal SDCLK1 output from the PLL circuit 31 (FIG. 13) and the feedback signal FB output from the delay circuit 368d are input.

  Up / Down counters provided in the delay circuits 368a to 368d change the output value of the counter according to the Up / Down signal output from the phase comparator 367. The output value of the counter is used for adjusting the delay amount by the delay adjustment circuit. For example, when the counter output value is increased by the Up signal, the number of delay adjustment buffers used is increased to increase the delay amount, and when the counter output value is decreased by the Down signal, the delay adjustment buffer is used. Reduce the number of buffers used to reduce the amount of delay. In this manner, the delay amounts in the four delay circuits 368a to 368d are adjusted.

  The write reference clock signal SDCLK1 input to the delay circuit 368a passes through the four delay circuits 368a to 368d, thereby becoming a feedback signal FB that is delayed by about one cycle from the write reference clock signal SDCLK1, and the phase comparator 367. Is input. The phase comparator 367 again outputs an Up / Down signal corresponding to the phase difference between the two signals SDCLK1 and FB. In this way, the phases of the two signals SDCLK1 and FB are adjusted, and the write reference clock signal SDCLK1 and the three signals output from the delay circuits 368a to 368c are used as the latch clock signals SLT1 to SLT4 as the sampling clock selection generation circuit. 34B. The latch clock signals SLT1 to SLT4 are signals whose phases are shifted by 90 degrees.

  In FIG. 14, the write reference clock signal SDCLK1 is used as it is as the latch clock signal SLT1, but signals output from the four delay circuits 368a to 368d may be used as the sampling clock signals SLT1 to SLT4. .

  In this embodiment, the Up / Down counter is provided in each of the delay circuits 368a to 368d, but may be provided in the phase comparator 367. In this case, there is an advantage that only one Up / Down counter is required.

  Even when the latch clock signals SLT1 to SLT4 generated in this way are used, the same processing as in the fourth embodiment can be performed. In this embodiment, unlike the first to third embodiments, since the dot clock signal DCLK1 having a high frequency is not used, the power consumption of the sampling clock selection generation circuit 34B can be made relatively small.

  In the present embodiment, the internal configuration of the write sampling clock generation unit 30B has been described, but the above configuration can be similarly applied to the read sampling clock generation unit 70.

F. Example 6:
FIG. 15 is a block diagram showing an internal configuration of the write sampling clock generation unit 30C and the AD conversion unit 40A in the sixth embodiment. The overall configuration of the image processing apparatus in the sixth embodiment is substantially the same except that the write sampling clock generation unit 30 in FIG. 8 is replaced with a write sampling clock generation unit 30C. Is omitted.

  The write sampling clock generation unit 30C has substantially the same configuration as the write sampling clock generation unit 30 shown in FIG. 2, but the PLL circuit 31 and the sampling clock selection generation circuit 34 are replaced with the PLL circuit 31A and the sampling clock selection generation circuit 34C. The point of replacement is different. The AD conversion unit 40A has the same configuration as that shown in FIG.

  The first PLL circuit 31A can output the write reference clock signal SDCLK1 from the horizontal synchronization signal HSYNC1 and can output the clock signal SDCLK1Q that is 90 degrees out of phase with the write reference clock signal SDCLK1. As the first PLL circuit 31A, for example, an ICS1522 manufactured by ICS can be used.

  The sampling clock selection generation circuit 34C generates latch clock signals SLT1 to SLT4 from the input write reference clock signals SDCLK1 and SDCLK1Q. The two write reference clock signals SDCLK1 and SDCLK1Q input to the sampling clock selection generation circuit 34C are signals that are 90 degrees out of phase with each other. Therefore, if the signal obtained by inverting the two signals SDCLK1 and SDCLK1Q is generated inside the sampling clock selection generation circuit 34C, the four latch clock signals SLT1 to SLT4 having phases different by 90 degrees can be easily generated.

  When this circuit configuration is used, the sampling clock selection / generation circuit 34C can be configured by an inverting circuit, so that the configuration of the sampling clock selection / generation circuit 34C can be simplified. Moreover, power consumption can be made relatively small.

  In the present embodiment, the internal configuration of the write sampling clock generation unit 30C has been described. However, the above configuration can be similarly applied to the read sampling clock generation unit 70.

G. Seventh embodiment:
FIG. 16 is a block diagram showing a group of digital image signal phase adjustment circuits provided in an interface portion inside the video processor 60 of FIG. This digital image signal phase adjustment circuit group is provided for each digital image signal output from each of the three AD conversion units 40A. The digital image signal phase adjustment circuit group is composed of a plurality of stages of digital image signal phase adjustment circuits, and has a hierarchical structure in which the number of circuits included in each stage gradually decreases toward the final stage. Each of the plurality of digital image signal phase adjustment circuits included in each stage other than the final stage holds the input digital image signals at a constant phase different from that of the other digital image signal phase adjustment circuits of the stage. And a function of supplying the digital image signal phase adjustment circuit in the next stage. The final stage digital image signal phase adjustment circuit has a function of holding Nw digital image signals supplied from the previous stage in the same phase.

  The digital image signal phase adjustment circuit at each stage is configured by a latch. Each latch receives one of the latch clock signals SLT1 to SLT4 generated by the sampling clock selection circuit 30A of FIG.

  The four latches 230a to 230d in the first stage are latches for taking the digital image signals D1 to D4 having different sequential phases output from the AD converter 40A into the video processor 60. The two latches 232a and 232b in the second stage collectively output every four digital image signals D1 to D4 having different sequential phases output from the four latches in the first stage, and output them. It is a latch for doing. The third-stage latch 234 further combines two sets of digital image signals having different phases, which are collected by the two latches 232a and 232b of the second stage, into one, and the digital image signals Dcom having the same phase are combined. It is a circuit for outputting.

  FIGS. 17A to 17P are timing charts of the digital image signals D1 to D4 when the digital image signal phase adjustment circuit group of FIG. 16 is used. FIGS. 17A to 17D show four digital image signals D1 to D4 having different sequential phases output from the AD converter 40A shown in FIG. FIGS. 17E to 17H show waveforms of latch clock signals SLT1 to SLT4 input to the video processor 60. FIG.

  Digital image signals D1, D3, D2, and D4 are input to the first-stage latches 230a to 230d in FIG. The latch 230a samples the digital image signal D1 with the latch clock signal SLT3, and outputs a digital image signal LD1 that is 180 degrees out of phase with the digital image signal D1. Similarly, digital image signals LD3, LD2, and LD4 are output from the latches 230b to 230d in accordance with the latch clock signals SLT1, SLT4, and SLT2, respectively. FIGS. 17 (i) to 17 (l) show digital image signals LD1, LD3, LD2, and LD4 output from the latches 230a to 230d.

  The second stage latch 232a receives every other digital image signal LD1 and LD3 among the four digital image signals LD1 to LD4 having different phases. The latch 232a samples the digital image signals LD1 and LD3 at the rising edge of the latch clock signal SLT2, and outputs a digital image signal LD5 including data of the digital image signals LD1 and LD3. Similarly, the latch 232b samples the digital image signals LD2 and LD4 with the latch clock signal SLT3, and outputs a digital image signal LD6 including data of the digital image signals LD2 and LD4. 17 (m) and 17 (n) show digital image signals LD5 and LD6 output from the latches 232a and 232b.

  Two digital image signals LD5 and LD6 having different phases are input to the third-stage latch 234. The latch 234 samples the digital image signals LD5 and LD6 with the latch clock signal SLT4, and outputs a digital image signal Dcom (FIG. 17 (o)) including data of the digital image signals LD1 to LD4. As described above, the digital image signals D1 to D4 can be output as the digital image signals Dcom having the same phase by using a plurality of stages of latches.

  In this way, stable sampling can be realized if a plurality of stages of latches are used, and every other signal having different phases is gathered into a signal having the same phase. That is, in this case, each latch can ensure a relatively large interval between the data change point of each digital image signal to be collected and the sampling point (the rising edge of the latch clock signal) to be collected. The possibility of sampling at the data change point of each digital image signal can be reduced. For example, as shown in FIG. 17, when four digital image signals D1 to D4 (FIGS. 17A to 17D) having different sequential phases are input, the phase is delayed by 90 degrees from the latch clock signal SLT4. It is also possible to sample all the signals D1 to D4 at a time using the signal SLT4 ′ (FIG. 17 (p)) and output it as the same phase. However, in this case, the interval between the sampling point (the rising edge of the latch clock signal SLT4 ') and the data change point of the digital image signals D1 and D4 is each reduced to 1/8 of one cycle. On the other hand, when every other signal having different phases is sampled using a plurality of stages of latches as shown in FIG. 16, for example, digital image signals LD1, LD3 (FIG. 17 (i), (j )) Is sampled with the latch clock signal SLT2, the interval between the sampling point (the rising edge of the latch clock signal SLT2) and the change point of the two signals LD1 and LD3 is compared with 1/4 of one period of each signal. Can be increased.

  In the present embodiment, as described above, the latch clock signals SLT1 to SLT4 are supplied to the latches 44 to 47 and also to the video processor 60. Therefore, the digital image signal D1 output from the AD conversion unit 40A is supplied. It is possible to sample at a timing suitable for .about.D4. In this way, even when there is a variation in the delay of each clock signal depending on the operating temperature, it is possible to avoid a malfunction due to the variation.

  The digital image signal phase adjustment circuit is provided in the video processor 60 in this embodiment, but may be provided in the AD converter 40A (FIG. 9). In this case, as in the first embodiment, the digital image signals D1 to D4 can be output from the AD conversion unit 40A as digital image signals Dcom having the same phase. In this case, it is not necessary to supply all of the latch clock signals SLT1 to SLT4 to the video processor 60. However, in order to sample the digital image signal Dcom within the video processor 60, at least one of the latch clock signals SLT1 to SLT4 is used. It is preferable to supply.

  Thus, the digital image signal Dcom captured in the video processor 60 is stored in the frame memory 50 as described in the first embodiment.

H. Other Embodiments The present invention is not limited to the above-described embodiments and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are also possible. Is possible.
(1) In each of the above embodiments, a signal having a relatively high frequency such as the dot clock signal DCLK1 and the quantized sampling signal SADC is generated in the sampling clock generation unit. When signals having a relatively high frequency such as these are transmitted through a wiring formed on a printed circuit board, waveform disturbance or delay that cannot be ignored may occur. Therefore, it is preferable that the dot clock signal DCLK1, the quantized sampling signal SADC, and the like are generated and used inside one integrated chip and not output outside the chip.

Accordingly, in each of the above embodiments, it is assumed that the sampling clock generation unit and at least one AD conversion unit are integrated on one chip, so that the above problem can be reduced. Further, even when the sampling clock generation unit and at least one AD conversion unit are not integrated into one chip, the PLL circuits 32 and 33 do not need to output the dot clock signal DCLK1 and the quantized sampling signal SADC to the outside of the chip. The sampling clock selection / generation circuit 34 (or 34A, 34B) and one AD conversion unit 40 are preferably integrated in one chip.
(2) The write sampling clock generation unit 30 shown in FIG. 2 generates the write reference clock signal SDCLK1 by multiplying the horizontal synchronization signal HSYNC1 by Ns1 times by the first PLL circuit 31. Alternatively, the write reference clock signal SDCLK1 may be generated by dividing the dot clock signal DCLK1 by 1 / Nw (Nw is the number of latches used). In this case, the dot clock signal DCLK1 can be generated by multiplying the horizontal synchronization signal HSYNC1 by one PLL circuit. In other words, as a circuit for generating the write reference clock signal SDCLK1, various circuit configurations such as a PLL circuit and a frequency divider can be employed.

The above-described modification can also be applied to a circuit related to generation of the read reference clock signal SDCLK2 and the dot clock signal DCLK2 in the read sampling clock generation unit 70 shown in FIG.
(3) In each of the above embodiments, a part of the configuration realized by hardware may be replaced with software. Conversely, a part of the configuration realized by software is replaced with hardware. May be.

(4) The present invention can be applied to various image processing apparatuses having AD conversion and DA conversion functions, and can be applied to a projection display apparatus such as a liquid crystal projector. Further, the present invention is not limited to an image display device using a liquid crystal panel, and can be applied to an image display device using display means such as a CRT or a plasma display, and various electronic devices including them.

1 is a block diagram showing an overall configuration of an image processing apparatus as a first embodiment of the present invention. 3 is a block diagram showing an internal configuration of a write sampling clock generation unit 30 and one AD conversion unit 40. FIG. It is a timing chart which shows the main signals relevant to the writing operation of an image signal. 7 is a timing chart of main signals related to a write operation when the operation of a latch 47 is stopped. 3 is a block diagram showing an internal configuration of a read sampling clock generation unit 70 and one DA conversion unit 80. FIG. It is a block diagram which shows the internal structure of the write sampling clock production | generation part 30 and AD conversion part 40A in 2nd Example. It is a timing chart of main signals related to the image signal writing operation in the AD conversion unit 40A. It is a block diagram which shows the whole structure of the image treatment apparatus as 3rd Example of this invention. It is a block diagram which shows the internal structure of the write sampling clock generation part 30A and AD conversion part 40A in 4th Example. It is a circuit diagram showing an example of a sampling clock selection generation circuit 34A. It is a timing chart which shows operation | movement of the sampling clock selection production | generation circuit 34A. It is a timing chart which shows the output of the digital image signal D1-D4 in a present Example. It is a block diagram which shows the internal structure of the write sampling clock generation part 30B and AD conversion part 40A in 5th Example. It is a block diagram which shows the internal structure of the sampling clock selection production | generation circuit 34B. It is a block diagram which shows the internal structure of the write sampling clock generation part 30C and AD conversion part 40A in 6th Example. FIG. 9 is a block diagram showing a digital image signal phase adjustment circuit group provided in an interface portion inside the video processor 60 of FIG. 8. FIG. 17 is a timing chart of digital image signals D1 to D4 when the digital image signal phase adjustment circuit group of FIG. 16 is used.

Explanation of symbols

DESCRIPTION OF SYMBOLS 20 ... Synchronization separation circuit 30 ... Write sampling clock generation part 30A ... Write sampling clock generation part 30B ... Write sampling clock generation part 30C ... Write sampling clock generation part 31 ... PLL
32 ... PLL
33 ... PLL
34 ... Sampling clock selection generation circuit 34A ... Sampling clock selection generation circuit 34B ... Sampling clock selection generation circuit 34C ... Sampling clock selection generation circuit 35 ... Selection control circuit 36 ... Delay adjustment circuit 38 ... CPU interface circuit 40 ... AD converter 40A ... AD converter 41 ... ΔΣ modulation circuit 42 ... digital filter 43 ... AD converter 44-47 ... latch 48 ... common latch 49 ... serial / parallel converter 49A ... serial / parallel converter 50 ... frame memory 60 ... video processor 70 ... read sampling clock Generator 71 ... PLL
72 ... PLL
73 ... PLL
74: Sampling clock selection generation circuit 75 ... Selection control circuit 78 ... CPU interface circuit 80 ... DA converter 81 ... DA converter 85 ... Video switch 90 ... Display control circuit 100 ... Display device 110 ... CPU
120 ... RAM
122 ... Write control signal adjusting means 124 ... Reading control signal adjusting means 130 ... Bus 140 ... Number determination circuit 226e ... Delay circuit 226a-226d ... D flip-flop 230a-230d ... Latch 232a, 232b ... Latch 234 ... Latch 367 ... Phase Comparators 368a to 368d ... delay circuits

Claims (9)

An integrated circuit that generates a first dot clock signal having a frequency for sampling the first analog image signal in synchronization with a first synchronization signal of the input first analog image signal A first dot clock generation circuit; and the first analog image signal is quantized and converted into a digital image signal, and the digital image signal of each pixel sampled in synchronization with the first dot clock signal is sequentially output. An AD converter that
Mw (Mw is an integer greater than or equal to 2) Mw pixel signal holding circuits that sequentially hold the digital image signal for each pixel, and Nw (Nw is an integer between 1 and Mw; A serial-to-parallel converter that outputs a digital image signal of consecutive pixels (indicating the number of pixel signal holding circuits used) in parallel as a set of digital image signals;
A first sampling clock generation circuit that generates a first sampling clock signal having a frequency of 1 / Nw of the frequency of the first dot clock signal in synchronization with the first synchronization signal;
One period of the first dot clock signal having the frequency of the first sampling clock signal according to the number Nw of the pixel signal holding circuits set according to the frequency of the first dot clock signal. A second sampling clock generation circuit for generating Nw second sampling clock signals having different phases one by one,
The operations of the first and second sampling clock generation circuits are controlled according to the value of the number Nw of pixel signal holding circuits used, and the Nw second sampling clocks are used in the Nw pixel signal holding circuits to be used. By supplying a signal, a digital image signal of Nw consecutive pixels is output from the serial-parallel converter as a set of digital image signals.
Integrated circuit. An integrated circuit according to claim 1, comprising:
A selection control circuit for stopping the operation of the unused (Mw-Nw) pixel signal holding circuits;
The operation of the selection control circuit is controlled according to the value of the number Nw of pixel signal holding circuits used.
Integrated circuit. An integrated circuit according to claim 1 or claim 2, wherein
The Nw second sampling clock signals having different sequential phases are output from the integrated circuit together with the one set of digital image signals.
Integrated circuit. An integrated circuit according to any one of claims 1 to 3,
The second sampling clock generation circuit includes:
According to the first sampling clock signal and the first dot clock signal, the Nw second sampling clock signals having different phases are sequentially generated.
Integrated circuit. An integrated circuit according to any one of claims 1 to 13,
The second sampling clock generation circuit includes:
Sequentially generating the Nw second sampling clock signals having different phases by sequentially delaying the first sampling clock signals;
Integrated circuit. An integrated circuit according to any one of claims 1 to 3,
The first sampling clock generation circuit includes:
Further, a 90-degree phase difference clock signal having a phase difference of 90 degrees from the first sampling clock signal is generated,
The second sampling clock generation circuit includes:
The Nw second sampling clock signals having different phases are sequentially generated from the first sampling clock signal and the 90-degree phase difference clock signal.
Integrated circuit. An integrated circuit according to any one of claims 1 to 6,
The second sampling clock generation circuit includes:
The sequential phase differs according to the pulse of the first synchronization signal so that the first synchronization signal and each of the Nw second sampling clock signals having different sequential phases have a certain phase relationship. Initialize Nw second sampling clock signals;
Integrated circuit. An integrated circuit according to any one of claims 1 to 7,
A third sampling clock generation circuit for generating a third sampling clock signal having a phase suitable for sampling the set of digital image signals;
The integrated circuit, wherein the third sampling clock signal is output from the image integrated circuit together with the set of digital image signals. An integrated circuit according to any one of claims 1 to 9,
Further, a fourth sampling clock that generates a fourth sampling clock signal having a frequency Nx (Nx is an integer of 2 or more) times the frequency of the first dot clock signal in synchronization with the first synchronization signal. A generation circuit,
The AD conversion circuit includes a ΔΣ modulation circuit and a digital filter, quantizes the first analog image signal according to the fourth sampling clock signal, and synchronizes with the first dot clock signal. Sequentially output the digital image signal of each sampled pixel,
Integrated circuit.

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