KR101468511B1 - ESD protection system and X-ray flat panel detector - Google Patents

Abstract

An ESD protection system and an X-ray flat panel detector are disclosed. An ESD protection system includes an ESD reliability bus and one of the terminals is an ESD protection circuit connected to the ESD reliability bus. The ESD protection circuit includes at least a pair of amorphous silicon thin film transistors connected in a back-to-back manner, and the first light shield layer is provided on the channel of the pair of amorphous silicon thin film transistors . When an ESD protection system is applied to an X-ray flat panel detector, no photocurrent is generated during use of the X-ray platelet detector and the effect of the photocurrent on the voltage of the scan line is reduced, Noise and driving force loss are reduced. Further, when the first light-shielding layer is connected to the negative fixed potential, it is possible to ensure that the ESD protection circuit has a small threshold voltage while reducing the leakage current in the ESD protection circuit, The driving force is prevented from being wasted.

Description

An ESD protection system and an X-ray flat panel detector,

The present invention relates to an ESD protection system, and more particularly to an ESD protection system for protecting an X-ray flat panel detector. Furthermore, the present invention relates to an X-ray flat panel detector with an ESD protection system.

This application claims priority to Chinese patent application No. 201210225073.1 (titled "ESD protection system and X-ray flat panel detector") submitted to the Chinese Intellectual Property Office on June 29, 2012, and all contents of Chinese patent application No. 201210225073.1 It is incorporated into the application.

Currently, there are two types of X-ray flat panel detectors in the domestic market and the external market: one is the indirect energy conversion type and the other is the direct energy conversion type. . Due to advantages such as high conversion efficiency, wide operating range, high spatial resolution, and enhanced environmental adaptability, X-ray flat panel detectors of indirect energy conversion type correspond to the most popular detectors in the X-ray flat panel detector market do.

As shown in FIG. 1, an indirect energy conversion type X-ray flat panel detector (abbreviated to X-ray flat panel detector in the present invention) is a multi-scan line formed on a substrate ) 2 and a plurality of data lines 3 in which the scan lines 2 and the data lines 3 are arranged in an intersecting manner to form a multi-pixel region, and each pixel region includes a pixel unit 4) are provided; A flicker layer or a phosphor layer (not shown) is formed on the substrate to cover the pixel region. Each pixel unit 4 includes a photodiode 5 and a switch 6 having a terminal connected to the photodiode 5. The photodiode 5 is adjusted to convert visible light into charge. The photodiode 5 is typically made of amorphous silicon because it has a complete photo-electric conversion function within the wavelength of the visible light, such as amorphous silicon and its alloys (such as amorphous silicon doped with germanium) And also because it has an anti-radiation performance against radiation having a high energy, and can also be made on a large scale. The pixel switch 6 is an amorphous silicon thin film transistor or diode, which is adjusted to control the pixel unit 4 to be switched on or off. The pixel switches 6 in each row of pixel units 4 are connected to the same data line 3. The pixel switches 6 in each column of the pixel unit 4 are connected to the same corresponding scan line 2. The data line 3 is connected to a data processing unit (also called a read unit) 7, and the scan line 2 is connected to an address control unit (also called a gate drive unit)

The operation principle of the X-ray flat panel detector is as follows. The X-rays generate visible light after passing through the flicker layer or fluorescent layer, the visible light is converted into charge by the photodiode 5 of the pixel unit 4, and the charge is stored in the photodiode 5, The address control unit 8 applies the line-by-line voltage on the scan line 2 in the pixel arrangement 1 such that the pixel switch 6 is switched on line by line and the charge stored in the photodiode 5 is applied to the data line 3 to the data processing unit 7, and the data processing unit 7 finally obtains the image information by further performing processing such as amplification and analog-to-digital conversion on the received electrical signal.

In the X-ray flat panel detector, the thin film in the photodiode and the TFT (i.e., the pixel switch) occupies a very large and large area, so the design, fabrication, assembly and testing process for the X-ray flat panel detector proceeds The electrostatic discharge (ESD) is apt to occur during the process. Almost all of the microelectronic circuits are very sensitive to such ESD, and thus electro-static protection must be provided for X-ray flat panel detectors in order to improve productivity and reduce manufacturing costs.

ESD protection systems for existing X-ray flat panel detectors include shorting buses and metal-insulator-metal diodes (MIMs). However, such ESD protection systems have many problems, such as not meeting the test and maintenance requirements for X-ray flat panel detectors.

In order to solve the above problems, as shown in FIG. 1, an ESD protection system for providing ESD protection for an X-ray flat panel detector is disclosed. ≪ / RTI > US2006 / 0092591A1 ("on-substrate ESD protection for array based image sensors"). 2, the ESD protection system includes an ESD leakage bus 10 and an ESD protection circuit 11 on a substrate (not shown), where the ESD leaky bus is grounded . The ESD protection circuit 11 includes a first wiring terminal 12 connected to the ESD reliable bus 10 and a second wiring terminal 13 connected to the scan line 2 of the X-ray flat panel detector .

3 is a schematic diagram illustrating an equivalent circuit for the ESD protection system of FIG. As shown in FIG. 3, the ESD protection circuit 11 includes a pair of amorphous silicon thin film transistors, that is, a first amorphous silicon thin film transistor 15 connected in a back-to-back manner, And a second amorphous silicon thin film transistor 16. When ESD is generated on the scan line 2 of the X-ray flat panel detector, a voltage between the first wiring terminal 12 and the second wiring terminal 13 of the ESD protection circuit is set to a threshold voltage The first amorphous silicon thin film 15 and the second amorphous silicon thin film 16 in the ESD protection system can prevent the ESD from flowing from the scan line 2 to the ESD leak bus 10 in a short period of time Thereby preventing a portion of the detector from being completely destroyed by the ESD voltage, or preventing the occurrence of a threshold voltage drift or other damage to the TFT.

4 is a cross-sectional view of a first amorphous silicon thin film transistor in the ESD protection circuit. 4, a first amorphous silicon thin film transistor 15 is formed on top of a substrate 17, which includes a gate 18, and an active layer 19 Is located at the top of the gate. The source 20 and the drain 21 are located on top of the active layer 19 where the active layer 19 is formed of an amorphous silicon layer 19a and an N ⁺ And an amorphous silicon layer 19b. As shown in FIG. 3, in the ESD protection circuit 11, the second amorphous silicon thin film transistor 16 has the same structure as the first amorphous silicon thin film transistor 15.

As shown in FIGS. 3 and 4, in the typical use of an X-ray flat panel detector, the X-ray irradiates a flickering layer or a fluorescent layer on a pixel unit, Ray is converted into a ray of light from the operation principle of the X-ray flat panel detector. Since the pixel unit of the X-ray flat panel detector and the ESD protection circuit are formed on the same substrate, the visible light is also illuminated by the ESD protection circuit while illuminating the pixel unit. This means that the first amorphous silicon thin film transistor 15 and the second amorphous silicon thin film transistor 16 in the ESD protection circuit will also be exposed to the visible light 22. However, since the first amorphous silicon thin film transistor 15 and the second amorphous silicon thin film transistor 16 include amorphous silicon capable of converting visible light into electric charge, the ESD protection during the operation of the X-ray flat panel detector A large photocurrent is generated in the circuit.

Since the ESD protection circuit is connected to the scan line of the X-ray flat panel detector, the photocurrent will affect the voltage on the scan line such that the actual voltage value on the scan line deviates from the ideal voltage value. This leads to variations in the final electronic image (horizontal and vertical stripes will be generated in the image) and increased noise. In order to ensure that the voltage on the scan line meets the requirements, the voltage on the scan line can be corrected or compensated by an external circuit for the X-ray flat panel detector, which leads to waste of drive power consumption.

Moreover, when the pixel switch of the pixel unit corresponds to an amorphous silicon thin film transistor, the amorphous silicon thin film transistor of the ESD protection circuit and the amorphous silicon thin film transistor of the pixel unit are formed in the same manufacturing step, whereby the two thin film transistors have the same threshold voltage . The thin film transistor of the ESD protection circuit and the thin film transistor of the pixel unit are commonly used in order to reduce driving power consumption for the thin film transistor of the pixel unit and to ensure that the thin film transistor of the ESD protection circuit can be switched on even under a relatively low ESD voltage Lt; RTI ID = 0.0 > 1V < / RTI > However, when the X-ray flat panel detector is normally driven, the voltage applied on the scan line is typically -10V to + 25V. Since the ESD protection circuit is connected to the scan line of the X-ray flat panel detector, the voltage applied on the thin film transistor of the ESD protection circuit is also -10V to + 25V. If so, a large amount of leakage current will be generated in the ESD protection circuit, and regardless of whether the voltage applied on the scan line is a positive voltage or a negative voltage, this causes a large amount of leakage current on the scan line, Causing a large waste. Therefore, in the X-ray flat panel detector equipped with the ESD protection system, it can not be achieved that the ESD protection circuit has a small threshold voltage while avoiding waste of driving power consumption in the X-ray flat panel detector.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an X-ray flat panel detector which can provide ESD protection for an X-ray flat panel detector, reduce a photocurrent effect on a voltage of a scan line, It is an object of the present invention to provide an ESD protection system capable of avoiding photocurrent in the use of X-ray flat panel detectors in order to reduce the loss of image fluctuation, noise and driving power consumption.

It is another object of the present invention to provide an ESD protection circuit that ensures that the ESD protection circuit has a small threshold voltage while reducing the leakage current in the ESD protection circuit and thus prevents wasted driving power consumption in the X- Ray flat panel detector equipped with the ESD protection system.

In order to solve the above-mentioned problems, there is provided an ESD protection system according to the present invention, including:

An ESD leak bus formed on a substrate; And

An ESD protection circuit formed on the substrate and having a first wiring terminal and a second wiring terminal, wherein the first wiring terminal is connected to an ESD leak bus, and the ESD protection circuit includes at least a pair of amorphous silicon thin film transistors Wherein the pair of amorphous silicon thin film transistors includes a first amorphous silicon thin film transistor and a second amorphous silicon thin film transistor connected in a back-to-back manner, and the first amorphous silicon thin film transistor And a first shading layer is provided on the channel of the second amorphous silicon thin film transistor).

Optionally, the ESD protection circuit may comprise a plurality of pairs of amorphous silicon thin film transistors connected in series, parallel, or series-parallel.

Alternatively, the area of the first light-shielding layer may be equal to or larger than an area of the channel of the first amorphous silicon thin film transistor and a channel of the second amorphous silicon thin film transistor.

Optionally, the ESD latency bus may be grounded or connected to a first fixed potential.

Alternatively, the first light-shielding layer may be made of a conductive material and may be connected to a second fixing potential.

Optionally, the conductive material may comprise at least one of Mo, W and Al.

Optionally, the second fixed potential may correspond to a negative fixed potential or a zero potential.

Optionally, the second fixed potential may be provided by an external power supply.

Alternatively, the ESD protection circuit may further include a first conductive layer provided on the channel of the first amorphous silicon thin film transistor and the channel of the second amorphous silicon thin film transistor and in contact with the first light shield layer, The first conductive layer is provided on the upper or lower portion of the first light shielding layer and overlaps at least a portion of the first light shielding layer, the first light shielding layer is made of a conductive material, and the first conductive layer is connected to the second fixed potential) .

Optionally, the conductive material may comprise at least one of Mo, W and Al.

Optionally, the second fixed potential may be a negative fixed potential or a zero potential.

Optionally, the second fixed potential may be provided by an external power supply.

Alternatively, the ESD protection circuit may include a first conductive layer provided on the channel of the first amorphous silicon thin film transistor and on the channel of the second amorphous silicon thin film transistor and in contact with the first light shield layer, 1 conductive layer is provided on the upper or lower portion of the first light shielding layer and overlaps at least a part of the first light shielding layer, the first light shielding layer is made of a nonconductive material, and the first conductive layer is connected to the second fixing potential ).

Optionally, the second fixed potential may be a negative fixed potential or a zero potential.

Optionally, the second fixed potential may be provided by an external power supply.

According to the present invention there is further provided an X-ray flat panel detector comprising:

A plurality of scan lines and a plurality of data lines formed on a substrate, wherein a plurality of scan lines and a plurality of data lines are arranged in such a manner as to intersect so as to form a plurality of pixel regions, the pixel units include a photosensitive unit, The switch being provided in each of the plurality of pixel regions); And

Wherein the ESD protection system is one or more ESD protection circuits within the ESD protection system and at least one of the plurality of scan lines is connected to a second wiring terminal of one of the ESD protection circuits.

Alternatively, the photosensitive unit may be a photodiode, the pixel switch is an amorphous silicon thin film transistor, the photodiode comprises a lower electrode, a photoelectric conversion layer provided on the lower electrode, and a photoelectric conversion layer The lower electrode of the photodiode may be connected to the pixel switch and the upper electrode of the photodiode may be connected to the externally biased second conductive layer, A source coupled to the lower electrode of the photosensitive unit, a drain coupled to the data line, and a gate coupled to one of the scan lines.

Alternatively, the second light shielding layer may be provided above the channel of the pixel switch.

Alternatively, the second light-shielding layer may overlap at least part of the second conductive layer, and may be in contact with the second conductive layer, and the second light-shielding layer may be provided at the upper portion or the lower portion of the second conductive layer .

Optionally, the number of ESD protection circuits in the ESD protection system may be two or more, the first wiring terminal of one of the ESD protection circuits may be connected to the ESD leak bus, and one of the ESD protection circuits The wiring terminal may be connected to one of the plurality of scan lines (where the first wiring terminal of another ESD protection circuit may be connected to the ESD leak bus and the second wiring terminal may be grounded).

According to the present invention there is further provided another X-ray flat panel detector comprising:

A plurality of scan lines formed on a substrate; and a plurality of data lines formed on the substrate, wherein the plurality of scan lines and the plurality of data lines are arranged in such a manner as to intersect so as to form a plurality of pixel regions, Wherein the pixel switch corresponds to the photodiode, the pixel switch corresponds to the amorphous silicon thin film transistor, the photodiode corresponds to the lower electrode, and the photoelectric converter provided on the lower electrode. Wherein the lower electrode of the photodiode is connected to a pixel switch and the upper electrode of the photodiode is connected to an externally biased second conductive layer, A source connected to the lower electrode of the photosensitive unit, a drain connected to one of the data lines, One including a gate connected to one; And

The ESD protection system described above wherein the number of ESD protection circuits is one or more, at least one of the plurality of scan lines is connected to a second wiring terminal of one of the ESD protection circuits, and the second fixed potential is negative fixed Potential, and an externally biased second conductive layer or ESD lead bus is connected to the first conductive layer to provide a second fixed potential).

Accordingly, in accordance with the present invention there is further provided another X-ray flat panel detector comprising:

 A plurality of scan lines and a plurality of data lines formed on a substrate, wherein a plurality of scan lines and a plurality of data lines are arranged in a manner of intersecting to form a plurality of pixel regions, the pixel units including a photosensitive unit, The pixel switch corresponds to the photodiode, the pixel switch corresponds to the amorphous silicon thin film transistor, the photodiode includes the lower electrode, the photoelectric conversion layer provided on the lower electrode, and the photoelectric conversion Wherein the lower electrode of the photodiode is connected to the pixel switch, the upper electrode of the photodiode is connected to the externally biased second conductive layer, and the pixel switch is connected to the lower electrode of the photosensitive unit A drain coupled to one of the data lines, and a scan line. Lt; / RTI > And

The ESD protection system described above wherein the number of ESD protection circuits is one or more, at least one of the plurality of scan lines is connected to a second wiring terminal of one of the ESD protection circuits, and the second fixed potential is negative fixed Potential, and the ESD leak bus is connected to the first shield layer of the ESD protection circuit to provide a second fixed potential).

Compared with the prior art, the present invention has the following advantages.

An ESD protection system according to the present invention includes an ESD leak bus and an ESD protection circuit, wherein the ESD protection circuit has a first wiring terminal connected to an ESD leak bus and a first wiring terminal, Wherein the pair of amorphous silicon thin film transistors includes a first amorphous silicon thin film transistor and a second amorphous silicon thin film transistor connected in a back-to-back manner, The first light-shielding layer is provided on the channel of the first amorphous silicon thin film transistor and on the channel of the second amorphous silicon thin film transistor. This ESD protection system not only provides ESD protection for an X-ray flat panel detector when applied to an X-ray flat panel detector, but also allows for the generation of photocurrent during use of the X-ray flat panel detector . Thus, the influence of the photocurrent on the voltage on the scan line is reduced, and the fluctuation of the electronic image, the noise, and the waste of driving force are reduced.

Furthermore, when the first light-shielding layer in the ESD protection system is connected to the fixed potential, it is possible to ensure that the ESD protection circuit has a relatively small threshold voltage while suppressing the leakage current in the ESD protection circuit, It is possible to prevent the driving force from being wasted in the flat panel detector.

In addition, all parts of the ESD protection system, except for the shading layer, are formed during the existing manufacturing process for the X-ray flat panel detector, thereby adding little new process.

According to one aspect of the present invention, when applied to an X-ray flat panel detector, it is possible not only to provide ESD protection for an X-ray flat panel detector, but also to reduce the photocurrent effect on the voltage of the scan line, An ESD protection system that avoids photocurrent in the use of X-ray flat panel detectors can be obtained to reduce losses to fluctuations, noise and driving power consumption.

According to another aspect of the present invention, there is provided an ESD protection circuit, which ensures that the ESD protection circuit has a small threshold voltage while reducing the leakage current in the ESD protection circuit, and thus, in order to prevent waste of driving power consumption in the X- An X-ray flat panel detector with an ESD protection system can be obtained.

1 is a schematic diagram showing an equivalent circuit for an existing X-ray flat panel detector;
2 is a schematic diagram illustrating an equivalent circuit for an X-ray flat panel detector with an ESD protection system, wherein the ESD protection system includes an ESD leaky bus and an ESD protection circuit, the ESD protection circuit comprises a first amorphous A silicon thin film transistor and a second amorphous silicon thin film transistor);
3 is a schematic diagram illustrating an equivalent circuit for the ESD protection system shown in FIG. 2;
4 is a cross-sectional view of the first amorphous silicon thin film transistor of the ESD protection system shown in FIG. 2;
5 is a schematic diagram illustrating an equivalent circuit for an ESD protection system in one embodiment of an ESD protection system in accordance with the present invention;
FIG. 6 is a cross-sectional view of a first amorphous silicon thin film transistor in an embodiment of the first amorphous silicon thin film transistor of the ESD protection system shown in FIG. 5; FIG.
7 is a schematic diagram illustrating an equivalent circuit for an X-ray flat panel detector in an embodiment of an X-ray flat panel detector with an ESD protection system according to the present invention;
8 is an enlarged view of the ESD protection circuit shown in FIG. 7 connected between the scan line and the ESD latency bus.
9 is a cross-sectional view of a pixel unit in an embodiment of an X-ray flat panel detector according to the present invention;
10 is a structural view showing a configuration in which a first amorphous silicon thin film transistor and a second amorphous silicon thin film transistor are connected between an ESD leak bus and a scan line;
FIG. 11 is a first structural diagram relating to the arrangement shown in FIG. 10 (where the first light-shielding layer and the first conductive layer are provided on the channel of the first amorphous silicon thin film transistor and the channel of the second amorphous silicon thin film transistor) ;
FIG. 12 is a second structural diagram relating to the arrangement shown in FIG. 10 (wherein the first light-shielding layer and the first conductive layer are provided on the channel of the first amorphous silicon thin film transistor and the channel of the second amorphous silicon thin film transistor) ;
FIG. 13 is a third structural diagram relating to the arrangement shown in FIG. 10 (wherein the first light-shielding layer and the first conductive layer are provided on the channel of the first amorphous silicon thin film transistor and the channel of the second amorphous silicon thin film transistor) ;
14 is a _{graph showing the relationship} between the input voltage _Vbias and the ESD protection when the first light shielding layer connected to the negative fixed potential is provided on the ESD protection circuit and the first light shielding layer connected to the zero potential is provided on the ESD protection circuit, The leakage current I _esd of the circuit;
15 is a schematic diagram showing an equivalent circuit for providing a negative fixed potential for a first light-shielding layer of an ESD protection system according to the present invention; And
16 is a schematic diagram showing another equivalent circuit for providing a negative fixed potential for the first light-shielding layer of the ESD protection system according to the present invention.

It is an object of the present invention to provide an X-ray flat panel detector capable of providing ESD protection for an X-ray flat panel detector and also capable of providing a photocurrent in the process of using the X-ray flat panel detector And to provide an ESD protection system that reduces the effect of photocurrent on the voltage of the scan lines, thereby reducing the loss of electronic image changes, noise, and driving forces.

In order to solve this problem, an ESD protection system according to the present invention includes an ESD leak bus and an ESD protection circuit, wherein the ESD protection circuit includes a first wiring terminal and a second wiring terminal and includes at least a pair of amorphous silicon thin films Transistors (a-Si TFTs). Here, the ESD protection circuit includes a first amorphous silicon thin film transistor and a second amorphous silicon thin film transistor connected in a back-to-back manner, wherein the first wiring terminal is an ESD protection circuit, And the ESD leak bus is grounded or connected to the first fixed potential. When the ESD protection system is applied to an X-ray flat panel detector, at least one scan line is connected to the second wiring terminal of the ESD protection circuit. The ESD leak bus is grounded or connected to the first fixed potential, whereby when the ESD is generated on the scan line, the first amorphous silicon thin film transistor and the second amorphous silicon thin film transistor in the ESD protection circuit connected to the scan line The ESD is quickly turned on to escape to the ESD recki bus.

In order to ensure that no photocurrent is generated in the ESD protection circuit during the use of the X-ray flat panel detector, the present inventors propose providing a first light-shielding layer made of a material having a low light transmittance, The light shielding layer is provided on the channel of the first amorphous silicon thin film transistor and the channel of the second amorphous silicon thin film transistor to prevent light from being irradiated to the channel of the first amorphous silicon thin film transistor and the second amorphous silicon thin film transistor, Thereby preventing photocurrent.

When the first light-shielding layer is electrically fired, ESD protection systems with a variety of adopted process and environmental conditions and some effects not controlled with respect to the X-ray flat panel detector will be introduced, The electrical characteristics of the X-ray flat panel detector may be affected. For example, the electrically floated first light-shielding layer can affect the characteristics of the circuit such as RC delay property and capacitive coupling property; Furthermore, the electrically-floated first light-shielding layer may cause an unstable potential of the circuit because the first amorphous silicon thin film transistor and the second amorphous silicon thin film transistor under the first light shielding layer are normally switched on ) Or can not be turned off, and the ESD protection system may not operate normally. From this point of view, the present inventors propose to connect the first light-shielding layer to the fixed potential so as to prevent the drawbacks from occurring.

A further object of the present invention is to provide an X-ray flat panel detector comprising the ESD system to ensure that the ESD protection circuit has a small threshold voltage while reducing the leakage current of the ESD protection circuit, And to prevent a large amount of driving force loss in the ray flat panel detector.

In order to solve this problem, the present inventors propose to connect the first light-shielding layer to the negative fixed potential in the ESD protection system. By doing so, a small threshold voltage of the ESD protection circuit is assured, and when the X-ray flat panel detector operates normally, the leakage current in the ESD protection circuit is reduced and the driving power loss in the X- So that an electric field can be applied to the TFTs inside the channels of the first amorphous silicon thin film transistor and the second amorphous silicon thin film transistor.

When the first light-shielding layer is provided on the channel of the first amorphous silicon thin film transistor and the second amorphous silicon thin film transistor for the ESD protection circuit and the first light shielding layer is connected to the negative fixed potential, the above two problems are solved It can be said that.

BRIEF DESCRIPTION OF THE DRAWINGS In the following, technical solutions of embodiments of the present invention will be explained clearly and completely by using one embodiment of the present invention together with the drawings related to the embodiments of the present invention. Of course, the described embodiments are only a few of the embodiments of the present invention and are not exhaustive. On the basis of these embodiments, all other embodiments which a person skilled in the art obtains without inventive effort fall within the scope of protection of the present invention.

5 is a schematic diagram of an equivalent circuit for an ESD protection system in one embodiment of an ESD protection system in accordance with the present invention. As shown in FIG. 5, the ESD protection system includes an ESD latency bus 120 formed on a substrate (not shown); And an ESD protection circuit 130 formed on the substrate, wherein the ESD protection circuit 130 includes a first wiring terminal 131 connected to the ESD reliability bus 120 and a second wiring terminal 131 connected to the circuit provided with ESD protection And the number of ESD protection circuits 130 is one or more, which is the number of applications of the ESD protection system to provide optimal ESD protection for circuits that are provided with ESD protection. . ≪ / RTI >

The ESD protection circuit 130 includes at least a pair of amorphous silicon thin film transistors (a-Si TFTs). In particular, the pair of amorphous silicon thin film transistors including the first amorphous silicon thin film transistor 140 and the second amorphous silicon thin film transistor 150 are connected in a back-to-back manner. The so-called back-to-back method is a method in which the gate 141 and the source 142 of the first amorphous silicon thin film transistor 140 are connected to the drain 153 of the second amorphous silicon thin film transistor 150, And the drain 143 of the first amorphous silicon thin film transistor 140 is connected to the gate 151 and the source 152 of the second amorphous silicon thin film transistor 150. [ The connection terminal of the gate 141 and the source 142 of the first amorphous silicon thin film transistor 140 and the drain 153 of the second amorphous silicon thin film transistor 150 is connected to the first wiring terminal of the ESD protection circuit 130 And the drain 143 of the first amorphous silicon thin film transistor 140 and the gate 151 and the source 152 of the second amorphous silicon thin film transistor 150 function as the ESD protection circuit 130 And serves as a second wiring terminal 132. Thus, the gate 141 and the source 142 of the first amorphous silicon thin film transistor 140 and the drain 153 of the second amorphous silicon thin film transistor 150 are connected to the ESD latency bus 120, The drain 143 of the amorphous silicon thin film transistor 140 and the gate 151 and the source 152 of the second amorphous silicon thin film transistor 150 are connected to a circuit which is provided with ESD protection.

In a preferred embodiment of the present invention, the ESD protection circuit 130 includes a plurality of (two or more) pairs of amorphous silicon thin film transistors (the first amorphous silicon thin film transistor 140 and a second amorphous silicon thin film transistor 150). When multiple pairs of amorphous silicon thin film transistors are connected in series, the ESD protection system may withstand higher ESD voltages; Also, the number of ESD leaky passages for ESD protection increases when multiple pairs of amorphous silicon thin film transistors are connected in parallel.

In this embodiment, the ESD protection circuit 130 includes two pairs of amorphous silicon thin film transistors connected in series. If the voltage across the first wiring terminal 131 and the second wiring terminal 132 of the ESD protection circuit 130 is less than twice the threshold voltage of the TFT, Only a small amount of current flows through the TFT. On the other hand, if the voltage across the first wiring terminal 131 and the second wiring terminal 132 of the ESD protection circuit 130 is greater than two times the threshold voltage of the TFT, the low resistance of the ESD protection circuit 130 The first amorphous silicon thin film transistor 140 and the second amorphous silicon thin film transistor 150 are switched on. In this case, a large amount of current will flow into the ESD recki bus 120 within a short time, and the current can escape because the ESD recki bus 120 can be grounded or connected to the first fixed potential.

The visible light is irradiated to the channels of the first amorphous silicon thin film transistor 140 and the second amorphous silicon thin film transistor 150 to the ESD protection circuit 130 to cause generation of photocurrent in the ESD protection circuit 130 Shielding layer 146 may be provided on the channel of the first amorphous silicon thin film transistor 140 and the second amorphous silicon thin film transistor 150. [ The first light-shielding layer 146 is made of a metal, a non-organic thin film or an organic thin film (including opaque ceramics or metal oxides), and the first light-shielding layer 146 is made of a conductive material, It may be made of a conductive material. The area of the first light-shielding layer 146 is set so that the area of the first amorphous silicon thin film transistor 140 and the second amorphous silicon thin film transistor 150 can be controlled so that visible light can not be irradiated to the channels of the first amorphous silicon thin film transistor 140 and the second amorphous silicon thin film transistor 150. [ Is equal to or larger than the area of the channel of the second amorphous silicon thin film transistor (140) and the area of the channel of the second amorphous silicon thin film transistor (150).

When the first light-shielding layer 146 provided over the channels of the first amorphous silicon thin film transistor 140 and the second amorphous silicon thin film transistor 150 is electrically floated, the ESD protection system and the circuit provided with ESD protection Some uncontrolled effects can be introduced, so that the electrical characteristics of the ESD protection system and the circuit under ESD protection can be affected. For example, the electrically shielded first light-shroud layer 146 may affect the characteristics of the circuit such as the RC delay property and the capacitive coupling property. Further, the electrically-floated first light-shielding layer 146 may cause an unstable potential of the circuit because the channel of the amorphous silicon thin film transistor under the first light-shielding layer 146 is normally switched on or off The ESD system will not be able to operate normally. From this point of view, it is proposed to connect the first light-shielding layer 146 to the second fixed potential 16 in order to prevent the occurrence of the defect.

In particular, connecting the first light-shielding layer 146 to the second fixed potential 160 includes the following case:

If the first light-shielding layer 146 is made of a conductive material, the first light-shielding layer 146 may be directly connected to the second fixing potential 16 or the first light-shielding layer 146 may be connected to the second fixing potential 160 Lt; RTI ID = 0.0 > a < / RTI > other conductive structure; And

Shielding layer 146 is connected to another conductive structure connected to the second fixed potential 160 if the first light-shielding layer 146 is made of a nonconductive material.

FIG. 6 is a cross-sectional view of a first amorphous silicon thin film transistor in one embodiment of the first amorphous silicon thin film transistor of the ESD protection system shown in FIG. 5; FIG. 6, a first amorphous silicon thin film transistor 140 is formed on a substrate 110 and includes a gate 141, an active layer 144 provided on top of the gate 141, And a source 142 and a drain 143 provided on top of the active layer 144. The gate 141 may be made of a metal material such as Ti, Al, or Mo. [ The active layer 144 includes an a-Si layer 144a and an N ⁺ a-Si layer 144b provided on the a-Si layer 144a. The source 142 and the drain 143 may be made of a metal material such as Al or Mo. [ The insulating layer 145 is made of SiN _x, SiO _x , or the like, and is provided on top of the first amorphous silicon thin film transistor 140. The first light-shielding layer 146 is formed on the insulating layer 145 and is provided on the channel of the first amorphous silicon thin film transistor 140. The area of the first light-shielding layer 146 is larger than the area of the first amorphous silicon thin film transistor 140 so that the first light-shielding layer 146 can prevent visible light from being irradiated to the channel of the first amorphous silicon thin- And the area of the channel of the second antenna. As shown in FIG. 5, the second amorphous silicon thin film transistor 150 in the ESD protection circuit 130 is the same as the first amorphous silicon thin film transistor 140 shown in FIG. 6, .

As shown in FIGS. 5 and 6, in one embodiment, the channel of the first amorphous silicon thin film transistor 140 and the channel of the second amorphous silicon thin film transistor 150 first light shield layer 146 are provided The first light-shielding layer 146 is made of a conductive material and is also directly connected to the second fixing potential 160. In one embodiment, the conductive material comprises at least one of Mo, W, and Al, and may also include other metals. The second fixed potential 160 may correspond to a zero potential, a positive fixed potential or a negative fixed potential; The second fixed potential 160 may also be provided by an external power supply, and may also be provided by a structure having a fixed potential in a circuit that is provided with ESD protection.

5 and 6, in one embodiment, the ESD protection circuit 130 is provided on the channel of the first amorphous silicon thin film transistor 140 and on the top of the second amorphous silicon thin film transistor 150 And further includes a first conductive layer 147. The first conductive layer 147 may be provided on the top or bottom of the first light shielding layer 146 (the first conductive layer 147 is shown as being provided under the first light shielding layer 146) The first conductive layer 147 is in contact with the first light-shielding layer 146, so that the first conductive layer 147 at least overlaps with a part of the first light-shielding layer 146. That is, the first conductive layer 147 may be provided on the upper portion or the lower portion of the first light-shielding layer 146. In addition, the first conductive layer 147 may be provided on the upper right side or the lower right side of the first light shielding layer 146, or on the upper left side or the lower left side. The first light-shielding layer 146 is made of a conductive material, and the first conductive layer 147 is connected to a second fixing potential 160. In one embodiment, the conductive material comprises less than one of Mo, W, and Al, and may also include other materials. The second fixed potential 160 may correspond to a zero potential, a positive fixed potential, or a negative fixed potential. The second fixed potential 160 may be provided by an external power supply and may be provided by a structure with a fixed potential in a circuit subject to ESD protection. In one embodiment, the conductive layer 147 may be made of indium tin oxide (ITO). In other embodiments, the first conductive layer 147 may be made of any other suitable conductive material. It should be noted that the first conductive layer 147 may be formed using a separate manufacturing process and may also be formed using the same manufacturing process as the corresponding layer in a circuit subject to ESD protection. In this way, the manufacturing cost of the ESD protection system can be reduced, and the manufacturing time can be shortened.

As shown in FIGS. 5 and 6, in one embodiment, the ESD protection circuit 130 includes a first amorphous silicon thin film transistor 140 and a second amorphous silicon thin film transistor 150 provided on the channel of the second amorphous silicon thin film transistor 150. 1 < / RTI > conductive layer (147). The first conductive layer 147 may be provided on the top or bottom of the first light shielding layer 146 (the case where the first conductive layer 147 is provided below the first light shielding layer 146) ) And also contacts the first light-shielding layer 146. Accordingly, the first conductive layer 147 overlaps at least a part of the first light-shielding layer 146. That is, the first conductive layer 147 may be provided on the upper or lower portion of the first light shielding layer 146, and the first incidence layer 147 may be provided on the upper right or lower right side of the first light shielding layer 146 It may be provided on the upper left side or the lower side. The first light-shielding layer 146 is made of a non-conductive material, and the first conductive layer 147 is connected to the second fixed potential 160. The second fixed potential 160 may correspond to a zero potential, a positive fixed potential, or a negative fixed potential. The second fixed potential 160 may be provided by an external power supply and may also be provided by a corresponding structure with a fixed potential in the circuit to which ESD protection is provided. In one embodiment, the conductive layer 147 may be made of ITO. In other embodiments, the first conductive layer 147 may be made of any other suitable conductive material. It should be noted that the first conductive layer 147 may be formed using a separate fabrication process and may also be formed using the same fabrication process as the corresponding layer in the circuit where ESD protection is provided. In this way, the manufacturing cost of the ESD protection system can be reduced, and the manufacturing period can be shortened.

After the first light-shielding layer 146 is provided above the channels of the first amorphous silicon thin film transistor 140 and the second amorphous silicon thin film transistor 150, the ESD protection system (not shown) 130 are not generated. The ESD protection system according to the present invention is typically provided in the outer area of the circuit where ESD protection is provided, the location of the ESD protection system needs to be determined according to the specific structure of the circuit to which ESD protection is provided, It will not affect.

7 is a schematic diagram illustrating an equivalent circuit for an X-ray flat panel detector in an embodiment of an X-ray flat panel detector with an ESD protection system according to the present invention. 8 is an enlarged view of the ESD protection circuit shown in FIG. 7 connected between the scan line and the ESD latency bus. 7 and 8, the X-ray flat panel detector includes a plurality (two or more) of scan lines (or gate lines) 220 formed on a substrate 110 and a plurality (two or more Wherein the plurality of scan lines 220 and the plurality of data lines 210 are arranged in an intersecting manner to form a plurality of pixel regions and the pixel unit 200 includes a plurality of data lines 210, Pixel region. The pixel units 200 in the same row are connected by a data line 210 and the pixel units 200 in the same column are connected to the scan line 220, One terminal for the data line 200 is connected to one of the data lines 210. [ The pixel unit 200 includes a photosensitive unit 230 and a pixel switch 240. One terminal for the photosensitive unit 230 is connected to the externally biased second conductive layer 250 to receive a bias signal; The other terminal of the photosensitive unit is also connected to the pixel switch 240. The substrate 110 may be a general semiconductor substrate or a glass substrate. Only two pixel units 200, one data line 210 and two scan lines 220 are shown in FIG. However, those skilled in the art will appreciate that the present invention includes an NxN pixel unit 200, each of which is provided within a pixel region consisting of N data lines 210 and N scan lines 220 arranged in such a way that the X- (Where N corresponds to an integral number greater than zero). ≪ RTI ID = 0.0 > The second conductive layer 250 needs to be made of a transparent conductive material. In one embodiment, the transparent conductive material may be ITO.

9 is a cross-sectional view showing a pixel unit in an embodiment of the X-ray flat panel detector according to the present invention. In this embodiment, the photosensitive unit 230 is a photodiode, and the pixel unit 240 is an amorphous silicon thin film transistor (a-Si TFT). The pixel switch 240 includes a gate 241 formed on the substrate 110, an active layer 244 provided over the gate 241, and a source 242 and drain (not shown) provided over the active layer 244. [ 243). The gate 241 is made of a metal material such as Ti, Al or Mo and the active layer 244 is formed of an N ⁺ a-Si layer 244a provided on the a-Si layer 244a and an a- And the source 242 and the drain 243 may be made of a metal material such as Al or Mo or the like. A source 242 of the pixel switch 240 extends to a region where the photosensitive unit 230 is located and functions as a lower electrode of the photosensitive unit 230. [ The PIN-type photoelectric conversion layer 231 is formed on the source 242 located on the region of the photosensitive unit 230. The PIN-type photoelectric conversion layer 231 includes a P ⁺ a-Si layer, an Ia-Si layer, and an N ⁺ a-Si layer, which are sequentially arranged in order from bottom to top. The upper electrode 232 is formed on the PIN-type photosensitive switching layer 231 to always apply a negative fixing potential to the second conductive layer 250 and is formed on the externally biased second conductive layer 250 Thereby enabling the photosensitive unit 230 when the X-ray flat panel detector is activated.

In fact, the photosensitive unit 230 is not limited to a photodiode, and may be another type of photosensitive unit; The pixel switch 240 is not limited to an amorphous silicon thin film transistor, and may be another type of switch element.

The gating, X-ray flat panel detector as shown in Figs. 7 and 8 further includes the ESD protection system mentioned in any of the above embodiments. The ESD protection system includes an ESD reliability bus 120 and an ESD protection circuit 130. If the ESD protection system is applied to an X-ray flat panel detector, the number of ESD protection circuits 130 may be one or more. The ESD protection circuit 130 includes a first wiring terminal 131 connected to the ESD latency bus 120 and a second wiring terminal 132 connected to the scan line 220. An X-ray flat panel detector typically includes two or more scan lines 220. Preferably, each scan line 22 in the X-ray flat panel detector is coupled to an ESD protection circuit 130. That is, in the X-ray flat panel detector, the number of the ESD protection circuits 130 is the same as that of the scan lines 220.

10 is a structural view showing the arrangement in which the first amorphous silicon thin film transistor and the second amorphous silicon thin film transistor are connected between the ESD leak bus and the scan line. As shown in FIGS. 8 and 10, the ESD protection circuit 130 includes at least a pair of amorphous silicon thin film transistors. The pair of amorphous silicon thin film transistors includes a first amorphous silicon thin film transistor 140 and a second amorphous silicon thin film transistor 150 connected in a back-to-back manner. Particularly, the gate 141 and the source 142 of the first amorphous silicon thin film transistor 140 and the drain 153 of the second amorphous silicon thin film transistor 150 are connected to the ESD latency bus 120, The drain 143 of the first amorphous silicon thin film transistor 140 and the gate 151 and the source 152 of the second amorphous silicon are connected to the scan line 22. [ The source 142 and the drain 143 of the first amorphous silicon thin film transistor 140 and the source 152 and the drain 153 of the second amorphous silicon thin film transistor 150 and the ESD recki bus 120 The same layer made of metal to achieve the connection between the source 142 of the first amorphous silicon thin film transistor 140 and the drain 153 of the second amorphous silicon thin film transistor 150 and the ESD reliable bus 120 (Indicated by the same shade). The scan line 220, the gate 141 of the first amorphous silicon thin film transistor 140 and the gate 151 of the second amorphous silicon thin film transistor 150 may be made of the same metal layer ).

In this embodiment, the ESD protection circuit 130 includes two pairs of amorphous silicon thin film transistors connected in series. In the X-ray flat panel detector, when ESD is generated on the scan line 220, a current between the first wiring terminal 131 and the second wiring terminal 132 of the ESD protection circuit 130 is reduced to the threshold voltage of the TFT The first amorphous silicon thin film transistor 140 and the second amorphous silicon thin film transistor 150 in the ESD protection circuit 130 are arranged such that the ESD is transferred from the scan line 220 to the ESD leaky bus 200. [ Is automatically switched on so that it can flow quickly toward the main body (120). By doing so, some of the detectors are prevented from being completely destroyed by the ESD voltage, causing TFT voltage drift or causing other damage.

FIG. 11 is a first structural diagram relating to the arrangement shown in FIG. 10 (where the first light-shielding layer and the first conductive layer are provided on the channel of the first amorphous silicon thin film transistor and the channel of the second amorphous silicon thin film transistor) . FIG. 12 is a second structural diagram relating to the arrangement shown in FIG. 10 (wherein the first light-shielding layer and the first conductive layer are provided on the channel of the first amorphous silicon thin film transistor and the channel of the second amorphous silicon thin film transistor) . FIG. 13 is a third structural diagram relating to the arrangement shown in FIG. 10 (wherein the first light-shielding layer and the first conductive layer are provided on the channel of the first amorphous silicon thin film transistor and the channel of the second amorphous silicon thin film transistor) . As shown in FIGS. 10, 11, 12 and 13, in the process of using the X-ray flat panel detector, the first amorphous silicon thin film transistor 140 and the second amorphous silicon thin film 140 of the ESD protection circuit 130 The first light shielding layer 146 may be provided in the ESD protection system to prevent the visible light from being irradiated to the channel of the transistor 150 and generating a photocurrent in the ESD protection circuit 130, (146) is provided on the channel of the first amorphous silicon thin film transistor (140) and on the channel of the second amorphous silicon thin film transistor (150). In one embodiment, in the ESD protection circuit 130, the first light-shielding layer 146 provided on the channel of the first amorphous silicon thin film transistor 140 is connected to the channel upper portion of the second amorphous silicon thin film transistor 150 (As shown in Figs. 11 and 12) independent of the first light-shielding layer 146 provided in the light-shielding layer. In another embodiment, in the ESD protection circuit 130, the first light-shielding layer 146 provided on the channel of the first amorphous silicon thin film transistor 140 is connected to the channel of the second amorphous silicon thin film transistor 150 And is entirely connected to the light-shielding layer 146 provided on the upper side (as shown in Fig. 13). The ESD protection circuit 130 includes a plurality of pairs of amorphous silicon thin film transistors (the first amorphous silicon thin film transistor 140 and the second amorphous silicon thin film transistor 150) The first light-shielding layers 146 provided on top of the plural pairs of amorphous silicon thin film transistors are connected as a whole (as shown in FIG. 13). In another embodiment, to simplify the manufacturing process of the first light-shielding layer 146, all of the first light-shielding layer 146 of the ESD protection circuit 130 in the ESD protection system may be connected (not shown) as a whole have.

After the first light-shielding layer 146 is provided on the channel of the first amorphous silicon thin film transistor 140 and the channel of the second amorphous silicon thin film transistor 150 in the ESD protection circuit 130, No photocurrent is generated in the ESD protection circuit 130 during the use of the detector and the scan line voltage of the X-ray flat panel detector is not affected, thereby reducing variations in the electronic image, noise, do.

7 and 8, when the channel of the first amorphous silicon thin film transistor 140 and the light shield layer 146 provided on the channel of the second amorphous silicon thin film transistor 150 are electrically floated, Some uncontrolled effects may be introduced into the ESD protection system and the X-ray flat panel detector, which may affect the electrical characteristics of the ESD protection system and the X-ray flat panel detector. In this regard, the first light-shielding layer 146 may be connected to the second fixed potential 160 to prevent the above-mentioned defects from being generated.

As described above and as shown in Figs. 5, 7, and 8, connecting the first light-shielding layer 146 to the second fixed potential 160 includes the following cases:

If the first light-shielding layer 146 is made of a conductive material, the first light-shielding layer 146 may be directly connected to the second fixing potential 160 or the first light-shielding layer 146 may be connected to the second fixing potential 160 160 to another conductive structure connected thereto; And

If the first light-shielding layer 146 is made of a non-conductive material, the first light-shielding layer 146 is connected to another conductive structure connected to the second potential 160.

In this way, when the first conductive layer 147 is provided in the ESD protection circuit 130 in contact with the first light shielding layer 146, even if the first light shielding layer 146 is made of a conductive material, Layer 147 is connected to second fixed potential 160; Or the first light-shielding layer 146 is made of a non-conductive material, the first conductive layer 147 is connected to the second fixed potential 160. [ Shielding layer 146 is formed of a conductive material in the case where no first conductive layer 147 is provided in the ESD protection circuit 130, 160, respectively.

If an ESD protection circuit 130 is provided with a first conductive layer 147 as shown in FIGS. 8, 11, 12 and 13, the ESD protection circuit 130 connected on the same scan line 220, All of the first light-shielding layer 146 of the first light-shielding layer 146 may be connected by the first conductive layer 147, and they are connected to the second fixing potential 160. [ In the circuit of this structure, the first conductive layer 147 of one ESD protection circuit 130 is separated from the first conductive layer 147 of another ESD protection circuit 130 (as shown in FIG. 11 equivalence). 12 and 13, all of the first conductive layer 147 of the ESD protection circuit 130 may be fabricated at one time by a conductive layer, And is connected to the fixed potential 160. That is, all of the first conductive layer 147 of the ESD protection circuit 130 is connected as a whole. 13, in the ESD protection circuit 130, the first light-shielding layer 146 provided on the channel of the first amorphous silicon thin film transistor 140 is connected to the second amorphous silicon thin film transistor 140. In this embodiment, The first light-shielding layer 146 provided on the channel of the first light-shielding layer 150; The first conductive layer 147 of the ESD protection circuit 130 is also generally connected to the first conductive layer 147 of another ESD protection circuit 130. In this way, the first light-shielding layer 146 and the first conductive layer 146 of the plurality of ESD protection circuits in the ESD protection system can be made of the same material layer, thereby simplifying the manufacturing process of the ESD system.

The second fixed potential 160 may be a zero potential, a positive fixed potential, or a negative fixed potential. The second fixed potential 160 may be provided in various ways, such as by an external power supply, or by a corresponding layer already present in the X-ray flat panel detector and having a fixed potential.

7, when the pixel switch 240 in the X-ray flat panel detector corresponds to the amorphous silicon thin film transistor, the amorphous silicon thin film transistor (the first amorphous silicon thin film transistor (Including the second amorphous silicon thin film transistor 140 and the second amorphous silicon thin film transistor 150) and the pixel switch 240 of the amorphous silicon thin film transistor are formed according to the same manufacturing step, whereby the two types of TFTs have the same threshold voltage. In order that the first amorphous silicon thin film transistor 140 and the second amorphous silicon thin film transistor 150 in the ESD protection circuit 130 can be surely switched on under a relatively low ESD voltage to allow the electric charge to flow, The amorphous silicon thin film transistor in the ESD protection circuit 130 and the pixel switch 240 of the amorphous silicon thin film transistor typically have a threshold voltage of 1V to 3V. However, when the X-ray flat panel detector is operating normally, the voltage applied on the scan line 220 typically ranges from -10V to + 25V. By connecting the ESD protection circuit 130 to the scan line, the voltage applied on the TFT of the ESD protection circuit 130 also exhibits a range of -10V to + 25V. Thereby, a very large amount of leakage current is generated in the ESD protection circuit 130, and regardless of whether the voltage applied on the scan line 220 is a positive voltage or a negative voltage, Causing a large amount of leakage current, and a large amount of driving power loss.

In order to solve this problem, the second fixed potential 160 to which the first light-shielding layer 146 is connected may correspond to a negative fixed potential. In this way, when the X-ray flat panel detector operates normally, an electric field can be applied to the TFTs in the channel of the first amorphous silicon thin film transistor 140 and the channel of the second amorphous silicon thin film transistor 150, The leakage current in the TFT is reduced, and the driving force loss in the X-ray flat panel detector is reduced.

14 is a _{graph showing the relationship} between the input voltage _Vbias and the ESD protection when the first light shielding layer connected to the negative fixed potential is provided on the ESD protection circuit and the first light shielding layer connected to the zero potential is provided on the ESD protection circuit, And the leakage current I _esd of the circuit. 14, when the first light-shielding layer connected to the zero potential is provided on the ESD protection circuit, a graph of the relationship between the input voltage _Vbias of the ESD protection circuit and the leakage current I _esd is represented by S ₁ . When the input voltage V _bias of the ESD protection circuit is V, the leakage current I _esd corresponds to I ₁ . When a first light-shielding layer connected to a negative fixed potential is provided on the ESD protection circuit, a graph of the relationship between the input voltage V _bias and the leakage current I _esd of the ESD protection circuit is represented by S ₂ . When the input voltage V _bias is V, the leakage current I _esd of the ESD protection circuit corresponds to I ₂ . The comparison shows that I ₁ >> I ₂ . Thus, when the first light-shielding layer is connected to the negative fixed potential, the leakage current I _esd of the ESD protection circuit can be reduced by one digit, thereby reducing the driving power loss.

15 is a schematic diagram showing an equivalent circuit for providing a negative fixed potential for the first light-shielding layer of the ESD protection system according to the present invention. 7 and 15, the first wiring terminal 131 of the ESD protection circuit 130 is connected to the ESD leak bus 120 and the second wiring terminal 132 of the ESD protection circuit 130 Is connected to the scan line 220, the first light-shielding layer is connected to the external voltage source 170, and the positive terminal of the external voltage source 170 is grounded. That is, a negative fixed potential may be provided for the first light-shielding layer 146. When the driving voltage for the scan line 220 of the X-ray flat panel detector is changed, an external voltage source (not shown) is used to adjust the negative fixed potential to another fixed value so that the leakage current in the ESD protection circuit 130 can be minimized 170 can be adjusted. Connecting the first light-shielding layer 146 to the external voltage source 170 includes the following cases:

If the first light-shielding layer 146 is made of a conductive material, the first light-shielding layer 146 may be directly connected to the external voltage source 170, or the first light-shielding layer 146 may be connected to the external voltage source 170, With a first conductive layer (147) connected to the first conductive layer (147); And

If the first light-shielding layer 146 is made of a non-conductive material, the first light-shielding layer 146 is brought into contact with the first conductive layer 147 connected to the external voltage source 170.

As described above and as shown in FIGS. 6 and 9, when the pixel unit 200 in the X-ray flat panel detector includes the photodiode 230 and the amorphous silicon thin film transistor 240 , The negative fixed potential is always applied to the second conductive layer 250 to enable the photosensitive unit 230 when the X-ray flat panel detector is driven. Accordingly, the first light-shielding layer 146 provided on the upper part of the ESD protection circuit may be connected to the second conductive layer 250 to provide a negative fixed potential. Connecting the first light-shielding layer 146 to the second conductive layer 250 includes the following case:

The first light-shielding layer 146 is brought into contact with the first conductive layer 147 connected to the second conductive layer 250;

In addition, when the first conductive layer 147 is made of a transparent conductive material (such as ITO), the first conductive layer 147 and the second conductive layer 250 may be formed according to the same manufacturing steps, do.

16 is a schematic diagram showing another equivalent circuit for providing a negative fixed potential for the first light-shielding layer of the ESD protection system according to the present invention. 9 and 16, the pixel unit 200 includes a photodiode 230 and an amorphous silicon thin film transistor 240, and the scan line 220 is connected to a pixel switch (not shown) Such as -10V or even -20V for most of the time, so that one scan line 220 is at a high level at a particular instant. An X-ray flap-panel radiator typically includes thousands of scan lines 220. When one scan line 220 is applied at a high level, the other scan lines 220 are at a low level. The ESD protection circuit 130 connected to the scan line 220 having a high level is activated and the generated current is supplied to the scan line 220 at a low level such that the level of the ESD latched bus 120 is almost equal to the low level of the scan line 220 To the ESD protection circuit 130 connected to the thousands of scan lines 220 having the scan lines 220. [ Thus, the first light-shielding layer 146 provided on the top of the ESD protection circuit 130 may be connected to the ESD reliable bus 120 to provide a negative fixed potential. Connecting the first light-blocking layer 146 to the ESD reliability bus 120 includes the following cases:

If the first light-shielding layer 146 is made of a conductive material, the first light-shielding layer 146 may be directly connected to the ESD leak bus 120, or the first light-shielding layer 146 may be connected to the ESD leak bus 120. [ With a first conductive layer (147) connected to the first conductive layer (120);

If the first light-shielding layer 146 is made of a nonconductive material, the first light-shielding layer 146 is brought into contact with the first conductive layer 147 connected to the ESD reliable bus 120.

Compared to this approach, which provides a negative fixed potential by an external voltage source, this approach can greatly simplify the circuit structure.

Referring again to FIG. 16, based on all embodiments of the above-described X-ray flat panel detector, the ESD protection system may include at least two or more ESD protection systems in order to increase the ESD voltage that the ESD protection system can tolerate. And an ESD protection circuit accordingly. 16, four ESD protection circuits are shown as an example. In this embodiment, the first wiring terminal 131 of one ESD protection circuit 130 (the fourth ESD protection circuit 130 in Fig. 16) is connected to the ESD leak bus 120, Terminal 132 is grounded. In this embodiment, the first wiring terminal 131 of another ESD protection circuit 130 (any of the three further ESD protection circuits 130 in Figure 16) is connected to the ESD leak bus 120 And the second wiring terminal 132 is connected to the scan line 220. That is, in the X-ray flat panel detector, each scan line 220 is connected to the ESD protection circuit 130, and the number of the ESD protection circuits 130 is one more than the number of the scan lines 220.

Referring again to FIG. 9, when the X-ray flat panel detector is operating normally, it can be seen that visible light is applied to the channel of the pixel switch 240 to reduce the photocurrent in the pixel switch 240 of the amorphous silicon thin film transistor The second light shielding layer 148 may be provided on the channel of the pixel switch 240. [ The second light-shielding layer 148 is made of a material having a low light transmittance such as a metal, an inorganic thin film, or an organic thin film (including a light-shielding ceramic or a metal oxide). The second light-shielding layer 148 may be made of a conductive material or a non-conductive material. The area of the second light shielding layer 148 should be larger than the area of the channel of the pixel switch 240 in order to completely prevent the visible light from being irradiated onto the channel of the pixel switch 240. [ When the second light-shielding layer 148 is electrically floated, a number of uncontrolled effects can be introduced into the X-ray flat panel detector. Accordingly, the second light-shielding layer 148 can be in contact with the second conductive layer 250 to provide a negative fixing potential with respect to the second light-shielding layer 148. The second light shielding layer 148 overlaps at least a part of the second conductive layer 250 and the second light shielding layer 148 is provided at the upper portion or the lower portion of the second conductive layer 250. [ (The case where the second light-shielding layer 148 is provided under the second conductive layer 250 is shown in Fig. 9).

According to the present invention, the pixel units of the ESD protection system and the X-ray flat panel detector can be manufactured on the same substrate. Moreover, all components of the ESD protection system, except for the light-shielding layer, are formed in the existing manufacturing process for the X-ray flat panel detector and thus little new manufacturing process is added. In addition, when the ESD system is applied to an X-ray flat panel detector, the ESD protection system must be provided in the area of the X-ray flat panel detector, specifically in the area of the X-ray flat panel detector except the pixel unit area do.

Compared with the prior art, the present invention has the following advantages.

An ESD protection system according to the present invention comprises an ESD leak bus and an ESD protection circuit, wherein the ESD protection circuit includes a first wiring terminal and a second wiring terminal connected to the ESD leak bus, (A-Si TFTs) including a first amorphous silicon thin film transistor and a second amorphous silicon thin film transistor connected in a back-to-back manner, wherein the first light shielding layer comprises a first amorphous silicon thin film transistor The channel of the transistor and the channel of the second amorphous silicon thin film transistor. When such an ESD protection system is applied to an X-ray flat panel detector, ESD protection can be provided for the X-ray flat panel detector and a photocurrent can be prevented from being generated during the use of the X-ray flat panel detector have. Thus, the influence of the photocurrent on the voltage on the scan line is reduced, and electronic image fluctuation, noise, and driving power loss are reduced.

Further, when the first light-shielding layer in the ESD protection system is connected to the fixed potential, the ESD protection circuit apparently has a relatively small threshold voltage while the leakage current in the ESD protection circuit is suppressed, whereby the X-ray flat panel detector A large waste of the driving force can be prevented.

In addition, all the components of the ESD protection system except for the light-shielding layer are formed in the existing manufacturing process for the X-ray flat panel detector, so that little new manufacturing process is added.

Throughout the description of the embodiments, the invention will be better understood and may be resorted to by those skilled in the art. Obviously, those skilled in the art will be able to make various modifications and alterations to the described embodiments based on the principles described herein without departing from the spirit and scope of the invention. Accordingly, the present invention should not be construed as being limited to the embodiments described herein, but the scope of protection of the present invention should be determined by the appended claims.

Claims (26)

An ESD leak bus formed on a substrate; And
And an ESD protection circuit formed on the substrate and having a first wiring terminal and a second wiring terminal,
Wherein the first wiring terminal is connected to an ESD leak bus, the ESD protection circuit includes at least a pair of amorphous silicon thin film transistors, and the pair of amorphous silicon thin film transistors are back-to- The first amorphous silicon thin film transistor and the second amorphous silicon thin film transistor are connected in such a manner that the channel of the first amorphous silicon thin film transistor and the channel of the second amorphous silicon thin film transistor are provided with a first light shielding layer,
Wherein the first light-shielding layer is provided with a negative fixed potential. The method according to claim 1,
The ESD protection circuit includes:
And a plurality of pairs of amorphous silicon thin film transistors connected in series, parallel, or series-parallel. The method according to claim 1,
The area of the first light-
Wherein an area of the channel of the first amorphous silicon thin film transistor and an area of the channel of the second amorphous silicon thin film transistor are equal to or larger than an area of the channel of the first amorphous silicon thin film transistor and an area of the channel of the second amorphous silicon thin film transistor. The method according to claim 1,
Wherein the latch bus is grounded or connected to a first fixed potential. The method according to claim 1,
The first light-
Wherein the first ESD protection device is made of a conductive material and is connected to a second ESD protection potential. delete delete 6. The method of claim 5,
Wherein the second fixed potential is a first fixed potential,
Wherein the ESD protection system is provided by an external power supply. The method according to claim 1,
The ESD protection system further includes a first conductive layer provided on the channel of the first amorphous silicon thin film transistor and the channel of the second amorphous silicon thin film transistor and in contact with the first light shield layer,
The first conductive layer is provided on an upper portion or a lower portion of the first light-shielding layer and overlaps at least a part of the first light-shielding layer. The first light-shielding layer is made of a conductive material or a nonconductive material, Lt; RTI ID = 0.0 > 2 < / RTI > fixed potential. delete delete 10. The method of claim 9,
Wherein the second fixed potential is a first fixed potential,
Wherein the ESD protection system is provided from an external power supply. delete delete delete A plurality of scan lines and a plurality of data lines formed on the substrate, wherein a plurality of scan lines and a plurality of data lines are arranged in such a manner as to intersect so as to form a plurality of pixel regions, the pixel units each include a photosensitive unit, The switch being provided in each of the plurality of pixel regions); And an ESD protection system,
The ESD protection system includes:
An ESD leak bus formed on a substrate; And
An ESD protection circuit formed on the substrate and including a first wiring terminal and a second wiring terminal, wherein the first wiring terminal is connected to an ESD leak bus, and the ESD protection circuit includes at least a pair of amorphous silicon thin film transistors Wherein the pair of amorphous silicon thin film transistors includes a first amorphous silicon thin film transistor and a second amorphous silicon thin film transistor connected in a back-to-back manner, and the first amorphous silicon thin film transistor And a first light-shielding layer is provided on a channel of the second amorphous silicon thin film transistor, and the first light-shielding layer is provided with a negative fixed potential,
Wherein at least one of the plurality of ESD protection circuits in the ESD protection system is connected to a second wiring terminal of one of the ESD protection circuits. 17. The method of claim 16,
Wherein the photodiode unit is a photodiode, the pixel switch is an amorphous silicon thin film transistor, the photodiode includes a lower electrode, a photoelectric conversion layer provided on the lower electrode, and an upper electrode provided on the photoelectric conversion layer, The lower electrode of the photodiode is connected to the pixel switch, the upper electrode of the photodiode is connected to the externally biased second conductive layer, the pixel switch includes a source connected to the lower electrode of the photosensitive unit, And the gate is connected to one of the scan lines. 17. The method of claim 16,
And a second light-shielding layer is provided on a channel of the pixel switch. 19. The method of claim 18,
Wherein the second light shielding layer overlaps with at least a portion of the second conductive layer and is also in contact with the second conductive layer and the second light shielding layer is provided on the top or bottom of the second conductive layer. Panel detector. 17. The method of claim 16,
Wherein a number of ESD protection circuits in the ESD protection system is more than two, a first wiring terminal of one of the ESD protection circuits is connected to an ESD leak bus, and a second wiring terminal of the ESD protection circuit is connected to a plurality of scan Ray flat panel is connected to one of the lines, a first wiring terminal of another ESD protection circuit is connected to an ESD leak bus, and a second wiring terminal of the another ESD protection circuit is grounded. Detector. A plurality of scan lines and a plurality of data lines formed on a substrate, wherein a plurality of scan lines and a plurality of data lines are arranged in such a manner as to intersect so as to form a plurality of pixel regions, the pixel units including a photosensitive unit, The pixel switch corresponds to the photodiode, the pixel switch corresponds to the amorphous silicon thin film transistor, the photodiode includes the lower electrode, the photoelectric conversion layer provided on the lower electrode, and the photoelectric conversion Wherein the lower electrode of the photodiode is connected to the pixel switch, the upper electrode of the photodiode is connected to the externally biased second conductive layer, and the pixel switch is connected to the lower electrode of the photosensitive unit A drain coupled to one of the data lines, and a gate coupled to one of the scan lines, ≪ / RTI > And
ESD protection system,
The ESD protection system includes:
An ESD leak bus formed on a substrate;
An ESD protection circuit formed on the substrate and including a first wiring terminal and a second wiring terminal, wherein the first wiring terminal is connected to an ESD leak bus, and the ESD protection circuit includes at least a pair of amorphous silicon thin film transistors Wherein the pair of amorphous silicon thin film transistors includes a first amorphous silicon thin film transistor and a second amorphous silicon thin film transistor connected in a back-to-back manner, and the first amorphous silicon thin film transistor And a first light-shielding layer is provided on a channel of the second amorphous silicon thin film transistor, and the first light-shielding layer is provided with a negative fixed potential; And
A first conductive layer provided on the channel of the first amorphous silicon thin film transistor and on the channel of the second amorphous silicon thin film transistor and in contact with the first light shielding layer And the first light-shielding layer is made of a conductive material or a nonconductive material, and the first conductive layer is connected to a second fixing potential,
Wherein the number of the ESD protection circuits is one or more, at least one of the plurality of scan lines is connected to a second wiring terminal of one of the ESD protection circuits, the second fixed potential corresponds to a negative fixed potential, Is coupled to the first conductive layer to provide a second fixed potential. ≪ RTI ID = 0.0 > 1 < / RTI > 22. The method of claim 21,
Wherein a number of ESD protection circuits in the ESD protection system is more than two, a first wiring terminal of one of the ESD protection circuits is connected to an ESD leak bus, and a second wiring terminal of the ESD protection circuit is connected to a plurality of scan Line, the first wiring terminal of another ESD protection circuit is connected to the ESD leak bus, the second wiring terminal of the another ESD protection circuit is grounded, and the ESD leaky bus is connected to the second fixed potential Wherein the first conductive layer of the ESD protection circuit is connected to the first conductive layer of the ESD protection circuit. delete delete A plurality of scan lines and a plurality of data lines formed on the substrate, wherein a plurality of scan lines and a plurality of data lines are arranged in such a manner as to intersect so as to form a plurality of pixel regions, The switch is provided in each of the plurality of pixel regions, the photosensitive unit is a photodiode, the pixel switch is an amorphous silicon thin film transistor, and the photodiode is provided on the lower electrode, the photoelectric conversion layer provided on the lower electrode and the photoelectric conversion layer A lower electrode of the photodiode is connected to the pixel switch, an upper electrode of the photodiode is connected to the externally biased second conductive layer, the pixel switch comprises a source connected to the lower electrode of the photosensitive unit, A drain coupled to one of the data lines and a gate coupled to one of the scan lines); And
ESD protection system,
The ESD protection system includes:
An ESD leak bus formed on a substrate; And
An ESD protection circuit formed on the substrate and having a first wiring terminal and a second wiring terminal, wherein the first wiring terminal is connected to the ESD leak bus, and the ESD protection circuit includes at least a pair of amorphous silicon thin film transistors Wherein the pair of amorphous silicon thin film transistors includes a first amorphous silicon thin film transistor and a second amorphous silicon thin film transistor connected in a back-to-back manner, and the first light shield layer comprises a first amorphous silicon thin film transistor A channel of the amorphous silicon thin film transistor and a channel of the second amorphous silicon thin film transistor, wherein the first light shield layer is provided with a negative fixed potential,
Wherein the first light-shielding layer is made of a conductive material and is connected to a second fixing potential,
Wherein at least one of the plurality of scan lines is connected to one of the second wiring terminals of the ESD protection circuit, the second fixed potential is a negative fixed potential, and the ESD leaky bus Wherein the first light-shielding layer of the ESD protection circuit is connected to the first light-shielding layer of the ESD protection circuit to provide a second fixed potential. 26. The method of claim 25,
Wherein a number of ESD protection circuits in the ESD protection system is more than two, a first wiring terminal of one of the ESD protection circuits is connected to an ESD leak bus, and a second wiring terminal of the ESD protection circuit is connected to a plurality of scan Line of the ESD protection circuit is connected to one of the lines, the first wiring terminal of another ESD protection circuit is connected to the ESD leak bus, and the second wiring terminal of the another ESD protection circuit is grounded. .

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