KR101465711B1 - Method for forming semiconductor structure - Google Patents

Abstract

1. A method for forming a semiconductor structure, comprising: forming a gate electrode on a semiconductor substrate on which ion implantation is performed; and forming a polycrystalline silicon layer on the semiconductor substrate; implanting ions into the polycrystalline silicon layer; Conducting a pre-annealing process so that the implanted ions are concentrated on the polycrystalline layer at the interface between the polycrystalline silicon layer and the semiconductor substrate; Wherein the temperature of the pre-annealing step is lower than the temperature of the annealing step. The ion implantation method according to claim 1, wherein the annealing step comprises: The pre-annealing causes the implanted ions to diffuse to the interface of the polycrystalline silicon and the semiconductor substrate so that the implanted ions are positioned on the same plane, and further annealing at a high temperature is performed to diffuse the implanted ions into the semiconductor substrate And ensures the uniformity of ion diffusion to form a doped region with boundaries aligned.

Description

[0001] METHOD FOR FORMING SEMICONDUCTOR STRUCTURE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor fabrication, and more particularly to a method of forming a semiconductor structure.

Static Random Access Memory (SRAM) is widely applied in the fields of PC, personal communication, consumer electronics (eg digital camera), and the like.

1 and 2 are a circuit diagram and a plan view of a memory unit in a SRAM memory having a 6T structure according to the prior art. Referring to FIGS. 1 and 2, the memory unit includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, A transistor N3 and a fourth NMOS transistor N4. The first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, and the second NMOS transistor N2 form a bistable circuit, and the bistable circuit maintains data information Thereby forming a latch. The first PMOS transistor P1 and the second PMOS transistor P2 are pull-up transistors. The first NMOS transistor N1 and the second NMOS transistor P2 are pull-down transistors. The third NMOS transistor N3 and the fourth NMOS transistor N4 are transfer transistors.

The gate electrode of the first PMOS transistor P1, the gate electrode of the first NMOS transistor N1, the drain electrode of the second PMOS transistor P2, the drain electrode of the second NMOS transistor N2, Are electrically connected to each other to form a first storage node 11. The gate electrode of the second PMOS transistor P2, the gate electrode of the second NMOS transistor N2, the drain electrode of the first PMOS transistor P1, the drain electrode of the first NMOS transistor N1, Are electrically connected to form a second storage node 12. The source electrode of the second storage node 12 is electrically connected to the second storage node 12. [ The gate electrodes of the third NMOS transistor N3 and the fourth NMOS transistor N4 are electrically connected to a word line WL. The drain electrode of the third NMOS transistor N3 is electrically connected to the first bit line BL and the drain electrode of the fourth NMOS transistor N4 is connected to the second bit line BLB And is electrically connected. The source electrode of the first PMOS transistor P1 and the source electrode of the second PMOS transistor P2 are electrically connected to the power source line Vdd. The source electrode of the first NMOS transistor N1 and the source electrode of the second NMOS transistor N2 are electrically connected to the ground line Vss.

The first bit line BL and the second bit line BLB are connected to the first storage node 11 or the second storage node 12 at a low level from the first bit line BL at a high level to the second storage node 12 at the time of performing a read operation with respect to the SRAM memory. Current flows. (BL) or a second bit line (BLB) from a first storage node (11) or a second storage node (12) of a high level to the first bit line Current flows.

In order to realize the connection of the gate electrode, the source electrode or the drain electrode of the transistor in the related art, a gate electrode, a source electrode, or a connection connecting the drain electrode to the other element by drawing out the gate electrode, Install the plug. The U. S. Patent No. US2007 / 0241411A1 discloses an SRAM memory, and Figure 3 is a cross-sectional view of a transistor in a prior art SRAM memory. Referring to FIG. 3, the transistor includes a semiconductor substrate 10; And a gate electrode formed on the semiconductor substrate 10. The gate electrode includes a gate dielectric layer 116B, a gate electrode layer 118B and a contact layer 119B sequentially positioned on the semiconductor substrate 10 And the gate electrode further includes side wirings 122B located on both sides of the gate dielectric layer 116B, the gate electrode layer 118B, and the contact layer 119B. The transistor further includes a connection plug G positioned above the gate electrode layer 118B and the connection plug G is formed in the interlayer dielectric layer 104 to draw the gate electrode layer 118B of the transistor do. However, since the connection plug G exists, the space between the transistors is relatively large, and the size of the SRAM memory is relatively large.

In order to solve such a problem, a solution (a patent application, not yet disclosed) provided by the applicant is to form a single conductive layer on the surfaces of gate electrodes adjacent to each other or adjacent gate electrodes and drain electrodes, (G), thereby realizing an electrical connection between the transistor and the transistor.

4, 5 and 6 are a plan view, an AA 'sectional view, and a BB' line of FIG. 4, FIG. 5, and FIG. 6, respectively, Fig.

The gate electrode of the first PMOS transistor P1, the gate electrode of the first NMOS transistor N1, the drain electrode of the second PMOS transistor P2, the drain electrode of the second NMOS transistor N2, 4, a first conductive layer 208 is provided to form the first storage node, and the first conductive layer 28 is electrically connected to the source electrode of the first conductive layer 28, Thereby realizing the electrical connection between the associated electrodes.

The gate electrode of the first PMOS transistor P1 and the gate electrode of the first NMOS transistor N1 are in contact with each other so that the gate electrode of the first PMOS transistor P1 and the gate electrode of the first NMOS transistor N1 Electrical connection is realized.

One end of the gate electrode of the first PMOS transistor P1, which is not in contact with the gate electrode of the first NMOS transistor N1, extends to a position intersecting the drain electrode of the second PMOS transistor P2.

5 is a schematic cross-sectional view showing a gate electrode of the first PMOS transistor P1 and a drain electrode of the second PMOS transistor P2. 5, the gate electrode of the first PMOS transistor P1 includes a gate dielectric layer 201, a gate electrode layer 202, an insulating layer 203, and a gate dielectric layer (not shown) 201, a gate electrode layer 202, and a side well 204 surrounding the insulating layer 203. The gate dielectric layer 201, the insulating layer 203, and the side wirings 204 are all formed of an insulating material. For example, the material of the gate dielectric layer 201 may be silicon oxide, and the material of the insulating layer 203, the sidewall 204 may be silicon nitride. The gate electrode layer 202 is a conductive material. For example, the material of the gate electrode layer 202 is polycrystalline silicon. The gate electrode layer 202 realizes the electrical connection of the gate electrode of the first PMOS transistor P1.

The drain electrode of the second PMOS transistor P2 is located at one side of the side wall 204 of the first PMOS transistor P1. Specifically, the drain electrode of the second PMOS transistor P2 is a P-type doped region 205 formed in the semiconductor substrate 100.

Among the gate electrodes of the first PMOS transistor P1, the insulating layer 203 covers only a part of the gate electrode layer 202 far away from the P-type doped region 205, and the P Type doped region 205 of the first conductivity type. The gate electrode layer 202 of the first PMOS transistor P1, the P-type doped region 205 of the second PMOS transistor P2, the gate electrode layer 202 of the first PMOS transistor P1, A gate electrode (not shown) of the second PMOS transistor P2 is surrounded to form an opening 210.

A first conductive layer 208 is coated on the bottom and sidewalls of the opening 210 and the first conductive layer 208 is connected to the drain electrode of the second PMOS transistor P2 ) And the first PMOS transistor P1 gate electrode (gate electrode layer 202). Specifically, the material 208 of the first conductive layer may be one or more of materials such as polycrystalline silicon, indium tin oxide and the like. Thus, the first conductive layer 208 realizes the electrical connection between the gate electrode of the first PMOS transistor P1 and the drain electrode of the second PMOS transistor P2.

It should be noted that in the above description of the embodiment, the first conductive layer 208 covers only a part of the P-type doped region 205, but the present invention is not limited thereto, Type doped region 205 may completely cover the P-type doped region 205. [ It should be further noted that in this embodiment the first conductive layer 208 not only covers the bottom and sidewalls of the opening 210 but also covers the top of the insulating layer 203, The first conductive layer 208 may cover only the side wall of the insulating layer 203 since the invention is not limited thereto.

Referring to FIG. 4, the first conductive layer 208 also extends between the drain electrode of the second NMOS transistor N2 and the source electrode of the fourth transistor N4. 6 is a cross-sectional view illustrating a second NMOS transistor N2 and a fourth transistor N4.

The second NMOS transistor N2 and the fourth transistor N4 are adjacent to each other on the semiconductor substrate 100. [ The second NMOS transistor N2 and the fourth transistor N4 both include a gate electrode and source electrode / drain electrodes formed on both sides of the gate electrode.

Specifically, the gate electrode of the second PMOS transistor N2 and the gate electrode of the fourth NMOS transistor N4 all have a gate dielectric layer 401, a gate electrode layer 402, an insulating layer 403 And side wirings 404 surrounding the gate dielectric layer 401, the gate electrode layer 402, and the insulating layer 403.

The source electrode / drain electrode of the second NMOS transistor N2 and the fourth NMOS transistor N4 are N-type doped regions. Specifically, the drain electrode 407 of the second NMOS transistor N2 and the source electrode 408 of the fourth NMOS transistor N4 are located between the two gate electrodes. In another embodiment, the N-type doped region constituting the drain electrode 407 of the second NMOS transistor N2 and the N-type doped region constituting the source electrode 408 of the fourth NMOS transistor N4 are formed in one N Type doping region.

A gate electrode of the second NMOS transistor N2 and a fourth NMOS transistor N4 and a semiconductor substrate 100 located between the second NMOS transistor N2 and the fourth NMOS transistor N4, (410). The first conductive layer 208 also covers the bottom and sidewalls of the second opening 410 to electrically connect the drain electrode 407 of the second NMOS transistor N2 and the source electrode of the fourth NMOS transistor N4 408 are electrically connected.

In this way, the gate electrode of the first PMOS transistor P1 and the gate electrode of the first NMOS transistor N1 of the SRAM memory unit of this embodiment realize electrical connection by direct contact, and the gate electrode of the first PMOS transistor P1 An electric connection is made between the gate electrode and the drain electrode of the second PMOS transistor P2, the drain electrode of the second NMOS transistor N2, and the source electrode of the fourth NMOS transistor N4 through the first conductive layer 208 Realization.

4, in this embodiment, the gate electrode of the second PMOS transistor P2, the gate electrode of the second NMOS transistor N2, the drain electrode of the first PMOS transistor P1, N1 and the source electrode of the third NMOS transistor N3 to realize the second storage node, the second conductive layer 211 is provided in this embodiment.

Specifically, the gate electrode of the second PMOS transistor P2 and the gate electrode of the second NMOS transistor N2 are opposed to each other to realize an electrical connection.

The insulating layer of the second PMOS transistor P2 exposes a portion of the gate electrode layer adjacent to the drain electrode of the first PMOS transistor P1, (Not shown) surrounded by the insulating layer, the exposed part of the gate electrode layer, the drain electrode of the first PMOS transistor P1, and the gate electrode of the first PMOS transistor P1, 211 electrically connects the gate electrode of the second PMOS transistor P2 and the drain electrode of the first PMOS transistor P1 by covering the bottom portion and the side wall of the third opening.

A first NMOS transistor N1 is disposed between the gate electrodes of the first NMOS transistor N1 and the third NMOS transistor N3 and between the gate electrodes of the first NMOS transistor N1 and the third NMOS transistor N3, The source electrode of the third NMOS transistor N3 is surrounded by a fourth opening (not shown), and the second conductive layer 211 further covers the bottom of the fourth opening and the sidewall , And the drain electrode of the first NMOS transistor N1 and the source electrode of the third NMOS transistor N3 are electrically connected.

By thus realizing the electrical connection of the corresponding electrode by the first conductive layer 208 and the second conductive layer 211, the first storage node and the second storage node can be formed to ensure the normal operation of the SRAM memory unit do. The present embodiment does not need to use a connection plug, so that the interval between different transistors can be reduced. In this embodiment, the interval between the gate electrodes of the transistors adjacent to each other can be reduced to within a range of 1500 ANGSTROM to 2500 ANGSTROM.

Although the SRAM memory unit has been described herein as an example, in other applications in the semiconductor field, there is a semiconductor structure that needs to realize the electrical connection between the gate electrode of one transistor and the doping region of the other transistor, When there is a semiconductor structure for realizing the electrical connection between the regions, those skilled in the art can respectively modify, modify and replace correspondingly to the semiconductor structure shown in Figs. 5 and 6, respectively.

Correspondingly, using this method, an SRAM memory comprising a plurality of said SRAM memory units can be provided. The SRAM memory has a relatively small area.

After forming the conductive layer 208, the forming process of the embodiment of the SRAM memory unit is performed by forming an opening surrounded by the semiconductor substrate between two adjacent gate electrodes and the gate electrode (e.g., the first opening 210 or the second opening 210) (P-type doped region 205) by implanting ions into the semiconductor substrate 100 at the bottom of the semiconductor substrate 100 (the source region 410).

However, the conductive layer (the first conductive layer 208 or the second conductive layer 211) that covers the bottom and side walls of the opening (e.g., the first opening 210 or the second opening 410) (The heights of the drain electrode of the second PMOS transistor P2 and the first conductive layer located on the sidewall of the gate electrode of the first PMOS transistor P1 are different from each other) and the ion implantation depths are different from each other, The uniformity of the doped region formed on the substrate 100 is not good, the boundaries are not aligned, and the ions adjacent to the gate electrode may not be diffused to the semiconductor substrate, so that the shape of the formed source / , Which affects the function of the formed device. If the thickness of the conductive layer is too large, it is likely to cause difficulty in forming a doped region through ion implantation. If the thickness of the conductive layer is too thin, the reliability of the electrical connection tends to be lowered.

The present invention has a problem in a method of realizing an electrical connection between a transistor and a transistor by using a conductive layer replacing the conventional connection plug G, that is, the thickness of the conductive layer is too thick and the thicknesses of the respective portions are different And a problem that the uniformity of the doped region formed by the ion implantation proceeding through the conductive layer is poor.

In order to solve the above problems,

At least two adjacent gate electrodes including a gate dielectric layer, a gate electrode layer, an insulating layer, and a gate dielectric layer, a gate electrode layer, and a sidewall surrounding the insulating layer in order from bottom to top in this order, Forming a semiconductor substrate on the semiconductor substrate such that the semiconductor substrate and the semiconductor substrate are surrounded by the semiconductor substrate;

Depositing a polycrystalline silicon on a semiconductor substrate not covered by the gate electrode and the gate electrode adjacent to each other to form a polycrystalline silicon layer;

Removing some of the polycrystalline silicon layer to cause the remaining polycrystalline silicon layer to cover the bottom and sidewalls of the opening;

Implanting ions into a semiconductor substrate located under the opening;

Conducting a pre-annealing process so that the implanted ions are concentrated on the polycrystalline silicon layer on the partial surface of the semiconductor substrate;

 And diffusing ions in the polycrystalline silicon concentrated on the minute interface into the semiconductor substrate to perform an annealing process so as to form a doped region,

The temperature of the pre-annealing process is lower than the temperature of the annealing process.

 The temperature of the pre-annealing step is preferably 690 ° C to 750 ° C.

The pre-annealing process is performed under a nitrogen gas atmosphere, and the ambient pressure is preferably set at atmospheric pressure.

The height of the polycrystalline silicon layer is preferably in the range of 500 ANGSTROM to 2000 ANGSTROM.

Preferably, the pre-annealing process is performed in an atmosphere of nitrogen gas, the ambient temperature is set to 690 ° C to 750 ° C, the pressure is set to atmospheric pressure, and the process is performed for 10min to 20min.

The present invention further provides a method of forming another semiconductor structure,

A first gate electrode including a gate dielectric layer, a gate electrode layer, an insulating layer, and a gate dielectric layer, a gate electrode layer and side wirings surrounding the insulating layer, and a second gate electrode on the semiconductor substrate ;

A portion of the gate electrode layer adjacent to the second gate electrode is removed so that the remaining insulating layer exposes a portion of the gate electrode layer adjacent to the second gate electrode and the remaining insulating layer, Forming an electrode layer, a semiconductor substrate between the first gate electrode and the second gate electrode, and a second gate electrode surrounding the opening;

Depositing polycrystalline silicon on a semiconductor substrate not covered by the first gate electrode, the second gate electrode, and the first gate electrode and the second gate electrode to form a polycrystalline silicon layer;

Removing some of the polycrystalline silicon layer to cause the remaining polycrystalline silicon layer to cover the bottom and sidewalls of the opening;

Implanting ions into a semiconductor substrate between a first gate electrode and a second gate electrode;

Conducting a pre-annealing process so that the implanted ions are concentrated on the polycrystalline silicon layer at the interface between the polycrystalline silicon layer and the semiconductor substrate;

And an annealing process is performed so that ions in the polycrystalline silicon layer concentrated on the minute interface are diffused into the semiconductor substrate to form a doped region,

The temperature of the pre-annealing process is lower than the temperature of the annealing process.

The temperature of the pre-annealing step is preferably 690 ° C to 750 ° C.

Preferably, the pre-annealing process is performed under a nitrogen gas atmosphere, and the ambient pressure is set to atmospheric pressure.

The height of the polycrystalline silicon layer is preferably in the range of 500 ANGSTROM to 2000 ANGSTROM.

Preferably, the pre-annealing process is performed in an atmosphere of nitrogen gas, the ambient temperature is set to 690 ° C to 750 ° C, the pressure is set to atmospheric pressure, and the process is performed for 10min to 20min.

Compared with the prior art, the present invention has the following advantages.

In the present invention, the polycrystalline silicon layer is replaced by a conductive layer for realizing the electrical connection between the transistor and the transistor by replacing the connection plug G. Then, after ion implantation through the conductive layer is performed, By conducting the pre-annealing, the implanted ions diffuse to the interface of the polycrystalline silicon and the semiconductor substrate (generally silicon), and are all located on the same plane. Then, annealing at a relatively high temperature is then performed again to ensure that the implanted ions are diffused into the semiconductor substrate, so that the thickness of the conductive layer is too thick to prevent ions from being injected into the semiconductor substrate, The problem that the depth of the implanted ions diffused in the semiconductor substrate is uneven due to the difference in the thickness of the conductive layer on the flat surface of the semiconductor substrate can be prevented and uniformity of the implanted ions diffused into the semiconductor substrate can be ensured, Thereby forming an aligned doped region.

FIG. 1 is a circuit diagram of a memory unit among SRAM memories of a conventional 6T structure.
2 is a plan view of a memory unit of a conventional 6T SRAM memory.
3 is a cross-sectional view of a transistor in a prior art SRAM memory.
4 is a plan view showing an embodiment of an SRAM memory unit according to a method of replacing a contact hole with a conductive layer of the present invention.
5 is a cross-sectional view taken along line AA 'of FIG.
6 is a cross-sectional view taken along line BB 'of FIG.
FIGS. 7 to 10 are schematic views showing a first embodiment of the semiconductor structure forming method of the present invention.
FIG. 11 is a schematic view showing a problem occurring in ion implantation into a semiconductor substrate through a conductive layer in the prior art. FIG.
FIGS. 12 to 14 are schematic views showing a second embodiment of the semiconductor structure forming method of the present invention.

In order to solve the problems of the prior art, Applicants have researched a semiconductor structure and a method for forming the same, an SRAM memory unit, and an SRAM memory through researches. The transistors in the semiconductor structure, the SRAM memory unit, and the SRAM memory, By realizing the electrical connection between one electrode, the connection plug can be omitted, which saves the space left between the transistors for the original connection plug, thereby reducing the area of the SRAM memory unit. However, in such a case, the conductive layer is too thick, the height at the sidewall of the gate electrode is different from the height at the semiconductor substrate, and it is difficult to inject ions into the semiconductor substrate through the conductive layer.

 In order to solve the above problems, the present invention provides a method of forming a semiconductor structure, wherein the conductive layer is made of polycrystalline silicon, and after the ion implantation, the preliminary annealing is performed at a temperature lower than the general annealing temperature, Is diffused up to the point of intersection of the polycrystalline silicon and the semiconductor substrate (generally silicon) so that they all lie on the same plane, and the annealing is performed at a relatively high temperature to diffuse the implanted ions into the semiconductor substrate, And forming a doped region with boundaries by ensuring uniformity of diffusion into the semiconductor substrate.

This method not only solves the problem that the conductive layer is too thick to inject ions into the semiconductor substrate but also differs in the height of the conductive layers at different positions on the semiconductor substrate, You can solve the problem that is not.

In order that the objects, features and advantages of the present invention can be more easily understood, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIGS. 7 to 10 are schematic views showing a first embodiment of the method for forming a semiconductor structure of the present invention, and FIG. 11 is a schematic diagram showing that the uniformity of a doped region formed by ion implantation in the conventional process is poor. This embodiment is for forming the semiconductor structure as shown in FIG.

As shown in Fig. 7, a semiconductor substrate 100 is provided. The semiconductor substrate 100 may be a silicon, germanium or other III-V semiconductor material. The semiconductor substrate 100 may be a silicon-on-insulator (SOI).

A first gate electrode and a second gate electrode (not shown) are formed on the semiconductor substrate 100 to form the first transistor P1 and the second transistor P2, respectively.

The first gate electrode includes a gate dielectric layer 201, a gate electrode layer 202, an insulating layer 203, and the gate dielectric layer 201, the gate electrode layer 202, And a side wil 204 surrounding the insulating layer 203. The material of the gate dielectric layer 201 may be silicon oxide and the material of the insulating layer 203 and side wirings 204 may be silicon nitride and the material of the gate electrode layer 202 may be polycrystalline silicon . Here, the method of forming the gate electrode is the same as that of the conventional art, and therefore will not be described in detail.

The semiconductor substrate 100 exposed between the first gate electrode and the second gate electrode is used to form a doped region 205 of the second transistor P2 in a subsequent process.

8, a part of the insulating layer 203 close to the second gate electrode of the first gate electrode is removed so that the remaining insulating layer 203 covers the part of the electrode layer 202 close to the second gate electrode The remaining insulating layer 203, a part of the gate electrode layer 202 exposed by the insulating layer 203, the semiconductor substrate 100 between the first gate electrode and the second gate electrode, and the second gate electrode are surrounded Thereby forming a first opening 210. The insulating layer 203 may be removed by photolithography and etching. More specifically, a photoresist pattern 206 may be formed on the first gate electrode and the second gate electrode, A portion of the insulating layer 203 in the gate electrode close to the second gate electrode is exposed and then a part of the insulating layer 203 exposed by the photoresist pattern 206 is removed by a plasma etching method. It should be pointed out that in this embodiment the material of the sidewall 204 is the same as the material of the insulating layer 203 and at the same time as removing some of the insulating layer 203, 204 are partially removed.

 As shown in Fig. 9, a conductive material is deposited on the semiconductor substrate 100 on which the first gate electrode, the second gate electrode, the first gate electrode, and the second gate electrode are exposed to form the conductive layer 207 do. Specifically, in this embodiment, the conductive material is polycrystalline silicon and can be formed through a chemical vapor deposition method.

It should be noted that the doping region 205 of the second transistor P2 must be formed between the first gate electrode and the second gate electrode in a subsequent process. If the thickness of the conductive layer 207 is too thick, it is difficult to form a doped region through ion implantation. If the thickness of the conductive layer 207 is too thin, the reliability of the electrical connection is lowered It is preferable that the thickness of the conductive layer 207 is in the range of 500 ANGSTROM to 800 ANGSTROM.

10, the conductive layer 207 is removed to allow the remaining conductive layer 207 to cover the bottom and sidewalls of the first opening 210 and the remaining conductive layer 207 A first conductive layer 208 is formed which realizes the electrical connection between the gate electrode of the first transistor P1 and the doped region of the second transistor P2 (in this case, the doped region is not yet formed). Specifically, a part of the conductive layer 207 can be removed by photolithography and etching.

After the first conductive layer 208 is formed, ions are implanted into the semiconductor substrate 100 between the first gate electrode and the second gate electrode to form a doped region 205. During the ion implantation, the doped ions may reach the semiconductor substrate 100 through the first conductive layer 208 to form the doped region 205.

10, the distance between the surface of the first conductive layer 208 at a flat position of the semiconductor substrate 100 and the distance H1 between the semiconductor substrate 100 and the first conductive layer The difference between the surface of the first conductive layer 208 and the distance H2 between the semiconductor substrate 100 is very large and can affect the shape of the ion implantation region formed through the first conductive layer 208. [ In this embodiment, the deposition thickness of the polycrystalline silicon layer is 500 ANGSTROM to 800 ANGSTROM. In the polycrystalline silicon layer located on the sidewall of the gate electrode, the difference between H1 and H2 reaches the height of one gate electrode and the height of the gate electrode is generally 1500 ANGSTROM, so that the height of the polycrystalline silicon layer ranges from 500 ANGSTROM to 2000 ANGSTROM . When the ions are injected through the polycrystalline silicon layer, ions near the sidewalls of the gate electrode have not yet diffused into the semiconductor substrate. However, there may arise a problem that ions in a flat portion of the semiconductor substrate are already diffused. Is similar to the displayed doped region 205 '.

In order to solve the above problem, the first conductive layer 208 used in the present embodiment is polycrystalline silicon, and the materials of the polycrystalline silicon and the semiconductor substrate (monocrystalline silicon substrate) are the same but have different lattice structures, And the minute interface has a certain blocking action against diffusion, but it is not clear. Since the materials of both are the same, ions are injected into the semiconductor substrate through the polycrystalline silicon layer due to the thermal diffusion action at a relatively high temperature, but the lattice structures are different from each other. And can be implanted into the semiconductor substrate from the polycrystalline silicon. If the high temperature annealing is directly used, the partial interface does not cause a blocking action when the ions to be implanted are diffused. Therefore, since the starting positions are different when the ions are diffused (the polycrystalline silicon thicknesses are different from each other) The position to be reached also changes, and the problem of poor doping uniformity occurs. However, if the pre-annealing is performed first at a lower temperature, the diffusion of ions having relatively low kinetic energy due to the low temperature can be effectively blocked, so that all of the implanted ions can stay at the minute interface. When annealing is performed again at a high temperature, all the implanted ions start to diffuse from the minute interface, so that all the implanted ions reach a uniform depth in the semiconductor substrate, thereby optimizing the uniformity of ion implantation.

The ion implantation in this step includes the following.

Ions are implanted into the first conductive layer 208. In this step, however, the ion implantation energy is controlled to prevent the first conductive layer 208 from penetrating. Otherwise, the ions are injected directly into the semiconductor substrate through the first conductive layer 208, and the uniformity of the ion implantation can not be guaranteed because the thicknesses of the respective positions of the first conductive layer 208 are different from each other.

The pre-annealing process is performed so that the implanted ions are concentrated on the polycrystalline silicon layer (the first conductive layer 208) and the polycrystalline silicon layer on the partial surface of the semiconductor substrate. In order to prevent the polycrystalline silicon from being oxidized, the pre-annealing process is performed under a nitrogen gas atmosphere, the ambient temperature is set to 690 ° C. to 750 ° C., the pressure is set to atmospheric pressure (760 Torr, standard atmospheric pressure) 10min to 20min. The ambient temperature affects the activity of the ions, and if the temperature is too low, the implanted ions do not have sufficient energy to diffuse to the interface, and if the temperature is too high, the implanted ions spread directly to the semiconductor substrate. The time for conducting the pre-annealing is determined by the thickness of the polycrystalline silicon, and as the thickness is increased, the time of the pre-annealing increases.

After the pre-annealing is completed, an annealing process is performed so that ions concentrated on the interface between the polycrystalline silicon and the semiconductor substrate are diffused into the semiconductor substrate 100. Generally, the annealing temperature is very high so that all the ions on the minute interface can be sufficiently diffused into the semiconductor substrate 100. Thus, a doped region 205 having a good uniformity is formed. In this embodiment, the annealing temperature is higher than 1000 deg.

In the semiconductor structure provided by this embodiment, since the electrical connection between the gate electrode of the first transistor P1 and the doped region of the second transistor P2 is realized by the first conductive layer 208, The interval between the first transistor P1 and the second transistor P2 can be reduced.

12 to 14 are schematic views showing a second embodiment of a method for forming a semiconductor structure of the present invention. This embodiment is for forming the semiconductor structure shown in Fig.

As shown in Fig. 12, a semiconductor substrate 100 is provided. The semiconductor substrate 100 may be a silicon, germanium or other III-V semiconductor material. The semiconductor substrate 100 may be a silicon-on-insulator (SOI).

Two adjacent gate electrodes are formed on the semiconductor substrate 100 and the two gate electrodes are for forming the second NMOS transistor N2 and the fourth NMOS transistor N4 connected to each other. Specifically, the gate electrode includes a gate dielectric layer 401, a gate electrode layer 402, an insulating layer 403, a gate dielectric layer 401, a gate electrode layer 402, And a side opening 404 surrounding the insulating layer 403 and a second opening 401 surrounded by the side wirings 404 of the adjacent gate electrodes and the semiconductor substrate.

 As shown in Fig. 13, a conductive material is deposited on the semiconductor substrate on which the two gate electrodes and the gate electrode are exposed to form the conductive layer 405. Next, as shown in Fig. In this embodiment, the conductive material is polycrystalline silicon and can be formed through a chemical vapor deposition method.

It should be noted that a doping region must be formed between the gate electrodes in a subsequent process. If the thickness of the conductive layer 405 is too thick, it is difficult to form a doped region through the ion implantation. If the thickness of the conductive layer 405 is too thin, It is easy to deteriorate. Therefore, the thickness of the conductive layer 405 is preferably in the range of 500 ANGSTROM to 800 ANGSTROM.

14, a part of the conductive layer 405 is removed so that the remaining conductive layer 405 covers the bottom portion and the side wall of the second opening 410 (as shown in Fig. 12).

The semiconductor substrate 100 located under the remaining conductive layer 405 is doped through ion implantation to form the doped regions of the second NMOS transistor N2 and the fourth NMOS transistor N4 And the second NMOS transistor N2 and the fourth NMOS transistor N4 may share one doping region. The remaining conductive layer 405 realizes the electrical connection of the doped regions of the second NMOS transistor N2 and the fourth transistor N4.

Similar to the above, ion implantation in this step includes:

Ions are implanted into the first conductive layer 405. In this step, the ion implantation energy is controlled to prevent penetration of the first conductive layer 208. Otherwise, the ions are injected directly into the semiconductor substrate through the first conductive layer 208, and the uniformity of the ion implantation can not be guaranteed because the thicknesses of the respective positions of the first conductive layer 208 are different from each other.

The pre-annealing process is performed so that the implanted ions are concentrated on the polycrystalline silicon layer (the first conductive layer 208) and the polycrystalline silicon layer on the partial surface of the semiconductor substrate. The pre-annealing process is performed under a nitrogen gas atmosphere, the ambient temperature is set to 690 ° C to 750 ° C, the pressure is set to normal pressure, and the process time is 10min to 20min. The ambient temperature affects the activity of the ions, and if the temperature is too low, the implanted ions do not have sufficient energy to diffuse over the surface, and if the temperature is too high, the implanted ions diffuse directly into the semiconductor substrate. The time for conducting the pre-annealing is determined by the thickness of the polycrystalline silicon, and as the thickness is increased, the time of the pre-annealing increases.

After the pre-annealing is completed, the annealing process is performed so that the ions concentrated on the interface between the polycrystalline silicon and the semiconductor substrate are diffused into the semiconductor substrate. In this embodiment, the annealing temperature is higher than 1000 deg.

Since the electrical connection between the doped regions of the second NMOS transistor N2 and the fourth NMOS transistor N4 in the semiconductor structure provided in this embodiment is realized by the remaining conductive layer 405, The interval between the second NMOS transistor N2 and the fourth NMOS transistor N4 can be reduced.

Although the present invention has been disclosed by way of preferred embodiments, it is not intended to limit the present invention. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Therefore, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

100: semiconductor substrate
201, 202: gate dielectric layer
203: insulating layer
204: Side Will
205: doped region
207: conductive layer

Claims (10)

At least two adjacent gate electrodes including a gate dielectric layer, a gate electrode layer, an insulating layer, and a gate dielectric layer, a gate electrode layer, and a sidewall surrounding the insulating layer in order from bottom to top in this order, Forming a shallow semiconductor substrate on the semiconductor substrate so as to surround the semiconductor substrate;
Depositing a polycrystalline silicon on a semiconductor substrate not covered by the gate electrode and the gate electrode adjacent to each other to form a polycrystalline silicon layer;
Removing some of the polycrystalline silicon layer to cause the remaining polycrystalline silicon layer to cover the bottom and sidewalls of the opening;
Implanting ions into a semiconductor substrate located under the opening;
Conducting a pre-annealing process such that the implanted ions are concentrated on a surface of the polycrystalline silicon layer and a partial interface of the semiconductor substrate on the side of the polycrystalline silicon layer; And
Conducting an annealing process so that ions in the polycrystalline silicon concentrated on the minute interface are diffused into the semiconductor substrate to form a doped region;
Lt; / RTI >
Wherein the temperature of the pre-annealing process is lower than the temperature of the annealing process,
A method of forming a semiconductor structure. The method according to claim 1,
Wherein the temperature of the pre-annealing step is 690 ° C to 750 ° C. 3. The method according to claim 1 or 2,
Wherein the pre-annealing process is performed under a nitrogen gas atmosphere, and the ambient pressure is set at atmospheric pressure. The method according to claim 1,
Wherein the height of the polycrystalline silicon layer is in the range of 500 ANGSTROM to 2000 ANGSTROM. 5. The method of claim 4,
Wherein the pre-annealing process is performed in a nitrogen gas atmosphere, the ambient temperature is set to 690 to 750 占 폚, the ambient pressure is set to atmospheric pressure, and the process is performed for 10 to 20 minutes. A first gate electrode comprising a gate dielectric layer, a gate electrode layer, an insulating layer, and a gate dielectric layer, a gate electrode layer, and a sidewall surrounding the insulating layer; and a second gate electrode on the semiconductor substrate ;
Removing a portion of the insulating layer adjacent to the second gate electrode of the first gate electrode so that the remaining insulating layer exposes a portion of the gate electrode layer adjacent to the second gate electrode; Forming a gate electrode layer, a semiconductor substrate between the first gate electrode and the second gate electrode, and a second gate electrode surrounded;
Depositing polycrystalline silicon on a semiconductor substrate not covered by the first gate electrode, the second gate electrode, and the first gate electrode and the second gate electrode to form a polycrystalline silicon layer;
Removing some of the polycrystalline silicon layer to cause the remaining polycrystalline silicon layer to cover the bottom and sidewalls of the opening;
Implanting ions into a semiconductor substrate between a first gate electrode and a second gate electrode;
Conducting a pre-annealing process so that the implanted ions are concentrated on the surface of the polycrystalline silicon layer and the surface of the semiconductor substrate on the side of the polycrystalline silicon layer, And
Conducting an annealing process so that ions in the polycrystalline silicon layer concentrated on the minute interface are diffused into the semiconductor substrate to form a doped region;
Lt; / RTI >
Wherein the temperature of the pre-annealing process is lower than the temperature of the annealing process,
A method of forming a semiconductor structure. The method according to claim 6,
Wherein the temperature of the pre-annealing step is 690 ° C to 750 ° C. 8. The method according to claim 6 or 7,
Wherein the pre-annealing process is performed under a nitrogen gas atmosphere, and the ambient pressure is set to an atmospheric pressure. 8. The method of claim 7,
Wherein the height of the polycrystalline silicon layer is in the range of 500 ANGSTROM to 2000 ANGSTROM. 10. The method of claim 9,
Wherein the pre-annealing process is performed under a nitrogen gas atmosphere, the ambient temperature is set to 690 to 750 占 폚, the ambient pressure is set to atmospheric pressure, and the process is performed for 10 to 20 minutes.

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