CN106935554B

CN106935554B - Semiconductor device, manufacturing method thereof and electronic device

Info

Publication number: CN106935554B
Application number: CN201511026807.3A
Authority: CN
Inventors: 李敏
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2015-12-31
Filing date: 2015-12-31
Publication date: 2020-08-21
Anticipated expiration: 2035-12-31
Also published as: CN106935554A

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the method comprises the following steps: providing a semiconductor substrate, and forming a plurality of grid structures comprising a grid dielectric layer, a grid material layer and a grid hard masking layer which are stacked from bottom to top on the semiconductor substrate; removing a gate hard mask layer in part of the gate structure; and forming an interconnection polysilicon layer electrically connected with the partial grid structure. According to the invention, before the interconnected polycrystalline silicon layer electrically connected with the grid structure is formed, the main side wall and the offset side wall positioned at two sides of the grid structure do not need to be removed, so that the damage to the grid dielectric layer in the grid structure is avoided, and the reliability of the grid dielectric layer is improved.

Description

Semiconductor device, manufacturing method thereof and electronic device

Technical Field

The invention relates to a semiconductor manufacturing process, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.

Background

Static Random Access Memory (SRAM) is a widely used memory device, and in order to increase the density of devices arranged on a chip and reduce the manufacturing cost, the feature size of the memory device needs to be reduced. However, due to the limitations of the dimensions of the contact region, the polysilicon gate, and the source region, it becomes very difficult to further reduce the feature size of the memory cell of the memory device.

Therefore, in the prior art, local interconnection between the gate structures or between the gate structures and the source/drain regions in the memory cells is realized by removing the side walls on the side walls of the gate structures and depositing an interconnection polysilicon layer, so that the number of contact holes to be formed can be reduced, and the area of the memory cells can be reduced. Before depositing the inter-polysilicon layer, a wet etching process is usually used to remove the sidewall on the sidewall of the gate structure, and during this process, an etching solution (e.g., hydrofluoric acid) used in the wet etching process easily attacks the exposed gate dielectric layer in the gate structure, thereby causing a decrease in device performance.

Therefore, a method is needed to solve the above problems.

Disclosure of Invention

In view of the shortcomings of the prior art, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, and forming a plurality of grid structures comprising a grid dielectric layer, a grid material layer and a grid hard masking layer which are stacked from bottom to top on the semiconductor substrate; removing a gate hard mask layer in part of the gate structure; and forming an interconnection polysilicon layer electrically connected with the partial grid structure.

In one example, before the removing, offset spacers are formed on two sides of the plurality of gate structures, and main spacers are formed on outer sides of the offset spacers.

In one example, after the removing, offset spacers are formed on two sides of the plurality of gate structures, and main spacers are formed on outer sides of the offset spacers.

In one example, the step of performing the removing comprises: forming a patterned photoetching mask on the semiconductor substrate to expose part of the gate structure; removing the gate hard masking layer in the partial gate structure by plasma dry etching by taking the photoetching mask as a mask; the photolithographic mask is removed by ashing or a stripping process.

In one example, the step of forming the interconnect polysilicon layer includes: forming a polysilicon layer by a deposition process to cover the plurality of gate structures; forming another patterned photoetching mask, and removing the part of the polycrystalline silicon layer which is not required to be electrically connected with the grid structure by dry etching by taking the other patterned photoetching mask as a mask; the further photolithographic mask is removed by an ashing or stripping process.

In one embodiment, the present invention also provides a semiconductor device manufactured by the above method.

In one embodiment, the present invention also provides an electronic apparatus including the semiconductor device.

According to the invention, before the interconnected polycrystalline silicon layer electrically connected with the grid structure is formed, the offset side walls positioned at two sides of the grid structure and the main side walls positioned at the outer sides of the offset side walls do not need to be removed, so that the damage to the grid dielectric layer in the grid structure is avoided, and the reliability of the grid dielectric layer is improved.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

fig. 1A to 1D are schematic cross-sectional views of devices respectively obtained by sequential steps of a method according to a first exemplary embodiment of the present invention;

FIGS. 2A-2D are schematic cross-sectional views of devices respectively obtained by sequential steps of a method according to an exemplary embodiment II of the present invention;

fig. 3 is a flow chart of steps performed in sequence by a method according to an exemplary embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

[ exemplary embodiment one ]

Referring to fig. 1A-1D, there are shown schematic cross-sectional views of devices respectively obtained by sequential steps of a method according to an exemplary embodiment one of the present invention.

First, as shown in fig. 1A, a semiconductor substrate 100 is provided, and the semiconductor substrate 100 may be formed of undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. As an example, in the present embodiment, the constituent material of the semiconductor substrate 100 is monocrystalline silicon. An isolation structure 102 is formed in the semiconductor substrate 100, and the isolation structure 102 is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. As an example, in the present embodiment, the isolation structure 102 is a shallow trench isolation structure. Various well structures are also formed in the semiconductor substrate 100, and are omitted from the drawings for simplicity.

A gate structure 101 is formed on the semiconductor substrate 100, and the gate structure 101 includes, as an example, a gate dielectric layer 101a, a gate material layer 101b, and a gate hard mask layer 101c, which are stacked from bottom to top. Gate dielectric layer 101a includes an oxide layer, such as silicon dioxide (SiO)₂) And (3) a layer. The gate material layer 101b includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer, wherein the constituent material of the metal layer may be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride layer includes a titanium nitride (TiN) layer; the conductive metal oxide layer comprises iridium oxide (IrO)₂) A layer; the metal silicide layer includes a titanium silicide (TiSi) layer. The gate hard mask layer 101c includes one or more of an oxide layer, a nitride layer, an oxynitride layer, and amorphous carbon, wherein the oxide layer is composed of a material including borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), Tetraethoxysilane (TEOS), Undoped Silicate Glass (USG), spin-on glass (SOG), high density plasma (hdp-cvd), and amorphous carbonDaughter (HDP) or spin-on dielectrics (SOD); the nitride layer comprises silicon nitride (Si)₃N₄) A layer; the oxynitride layer includes a silicon oxynitride (SiON) layer. In this embodiment, the gate dielectric layer 101a is formed of silicon dioxide, the gate material layer 101b is formed of polysilicon, and the gate hard mask layer 101c is formed of silicon nitride. The gate dielectric layer 101a, the gate material layer 101b and the gate hard mask layer 101c may be formed by any conventional technique known to those skilled in the art, and preferably by Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD) and Plasma Enhanced Chemical Vapor Deposition (PECVD).

Next, as shown in fig. 1B, a patterned photolithographic mask 103 is formed on the semiconductor substrate 100 to expose a portion of the gate structure 101, the exposed gate structure 101 serving as a pull-up transistor (PU) in the SRAM. The photolithography mask 103 is formed by a process such as spin coating, exposure, development, and the like, and then the gate hard mask layer 101c in the gate structure 101 is removed by plasma dry etching with the photolithography mask 103 as a mask. As an example, the etching gas of the plasma dry etching includes CF₄、CHF₃、CH₂F₂、CH₃F, and the like.

Next, as shown in fig. 1C, the photolithographic mask 103 is removed, which is carried out by ashing or a stripping process, as an example. Then, a pre-cleaning is performed on the semiconductor substrate 100 to remove etching residues and impurities.

Next, offset spacers 104 abutting against the gate structure 101 and main sidewalls 105 abutting against the offset spacers 104 are sequentially formed on both sides of the gate structure 101. As an example, the offset spacers 104 may be formed of silicon oxide, and the main sidewalls 105 may be formed of silicon nitride. After forming the offset spacers 104 and before forming the main sidewalls 105 next to the offset spacers 104, lightly doped ion implantation and annealing are performed to form LDD (lightly doped drain) regions in the semiconductor substrate 100 on both sides of the offset spacers 104. After the LDD regions are formed, pocket region ion implantation and annealing are performed to form pocket regions in the semiconductor substrate 100 on both sides of the offset spacers 104. Under the selected ion implantation angle, the rotation implantation is carried out, so that the shadow effect can be reduced, symmetrical impurity distribution is formed, the ion implantation energy, the dosage and the angle are correspondingly matched with those of the light doped ion implantation, and the implantation energy ensures that the formed bag-shaped region wraps the LDD region, so that the short channel effect caused by Drain Induced Barrier Lowering (DIBL) is effectively inhibited. After the main sidewalls 105 are formed, source/drain implantation is performed to form source/drain regions in the semiconductor substrate 100 on both sides of the main sidewalls 105.

Next, as shown in fig. 1D, an inter-polysilicon layer 106 is formed to implement local interconnections between gate structures or between a gate structure and a source/drain region in the SRAM memory cell. As an example, a polysilicon layer is formed by a conventional deposition process to cover the gate structure 101 formed on the semiconductor substrate 100, and then another patterned photolithography mask is formed, a portion of the polysilicon layer not required to be electrically connected to the gate structure 101 is removed by dry etching, the gate structure 101 required to be electrically connected to the polysilicon layer is a pull-up transistor in an SRAM, and then the another photolithography mask is removed by ashing or lift-off process.

To this end, the process steps performed by the method according to the first exemplary embodiment of the present invention are completed. Compared with the prior art, according to the method provided by the invention, before the internal polycrystalline silicon layer electrically connected with the grid structure is formed, the main side wall and the offset side wall positioned at two sides of the grid structure are not required to be removed, so that the damage to the grid dielectric layer in the grid structure is avoided, and the reliability of the grid dielectric layer is improved.

[ second exemplary embodiment ]

Referring to fig. 2A-2D, there are shown schematic cross-sectional views of devices respectively obtained by sequential steps of a method according to an exemplary embodiment two of the present invention.

First, as shown in fig. 2A, a semiconductor substrate 200 is provided, and the semiconductor substrate 200 may be formed of undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. As an example, in the present embodiment, the constituent material of the semiconductor substrate 200 is monocrystalline silicon. An isolation structure 202 is formed in the semiconductor substrate 200, and the isolation structure 202 is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. As an example, in the present embodiment, the isolation structure 202 is a shallow trench isolation structure. Various well structures are also formed in the semiconductor substrate 200, and are omitted from the drawing for simplicity.

A gate structure 201 is formed on the semiconductor substrate 200, and the gate structure 201 includes, as an example, a gate dielectric layer 201a, a gate material layer 201b, and a gate hard mask layer 201c, which are stacked from bottom to top. The constituent material of the gate dielectric layer 201a includes an oxide such as silicon dioxide (SiO)₂). The gate material layer 201b is made of one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal may be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO)₂) (ii) a The metal silicide includes titanium silicide (TiSi). The gate hard mask layer 201c is made of one or more of oxide, nitride, oxynitride, and amorphous carbon, wherein the oxide includes borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), Tetraethoxysilane (TEOS), Undoped Silicate Glass (USG), spin-on glass (SOG), High Density Plasma (HDP), or spin-on dielectric (SOD); the nitride includes silicon nitride (SiN); the oxynitride includes silicon oxynitride (SiON); in this embodiment, the gate dielectric layer 201a is made of silicon dioxide, the gate material layer 201b is made of polysilicon, and the gate hard mask layer 201c is made of silicon nitride. The gate dielectric layer 202a, the gate material layer 202b, and the gate hard mask layer 202c may be formed by any conventional technique known to those skilled in the art, preferably by Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD).

Next, as shown in fig. 2B, offset spacers 204 abutting against the gate structure 201 and main sidewalls 205 abutting against the offset spacers 204 are sequentially formed on both sides of the gate structure 201. As an example, the offset spacers 204 may be formed of silicon oxide, and the main sidewalls 205 may be formed of silicon nitride. After forming the offset spacers 204 and before forming the main sidewalls 205 next to the offset spacers 204, lightly doped ion implantation and annealing are performed to form LDD (lightly doped drain) regions in the semiconductor substrate 200 at both sides of the offset spacers 204. After the LDD regions are formed, pocket region ion implantation and annealing are performed to form pocket regions in the semiconductor substrate 200 on both sides of the offset spacers 204. Under the selected ion implantation angle, the rotation implantation is carried out, so that the shadow effect can be reduced, symmetrical impurity distribution is formed, the ion implantation energy, the dosage and the angle are correspondingly matched with those of the light doped ion implantation, and the implantation energy ensures that the formed bag-shaped region wraps the LDD region, so that the short channel effect caused by Drain Induced Barrier Lowering (DIBL) is effectively inhibited. After the main sidewalls 205 are formed, source/drain implantation is performed to form source/drain regions in the semiconductor substrate 200 at both sides of the main sidewalls 205.

Next, as shown in fig. 2C, a patterned photolithographic mask 203 is formed on the semiconductor substrate 200 to expose a portion of the gate structure 201, the exposed gate structure 101 acting as a pull-up transistor in the SRAM. The photolithography mask 203 is formed by a process such as spin coating, exposure, development, and the like, and then the gate hard mask layer 201c in the gate structure 201 is removed by plasma dry etching with the photolithography mask 203 as a mask. As an example, the etching gas of the plasma dry etching includes CF₄、CHF₃、CH₂F₂、CH₃F, and the like.

Next, as shown in fig. 2D, an inter-polysilicon layer 206 is formed to implement local interconnections between gate structures or between a gate structure and source/drain regions in the SRAM memory cell. As an example, a polysilicon layer is formed by a conventional deposition process to cover the gate structure 201 formed on the semiconductor substrate 200, and then another patterned photolithography mask is formed, a portion of the polysilicon layer not required to be electrically connected to the gate structure 201 is removed by dry etching, the gate structure 201 required to be electrically connected to the polysilicon layer is a pull-up transistor in an SRAM, and then the another photolithography mask is removed by ashing or lift-off process.

To this end, the process steps performed according to the method of the second exemplary embodiment of the present invention are completed. Compared with the prior art, according to the method provided by the invention, before the internal polycrystalline silicon layer electrically connected with the grid structure is formed, the main side wall and the offset side wall positioned at two sides of the grid structure are not required to be removed, so that the damage to the grid dielectric layer in the grid structure is avoided, and the reliability of the grid dielectric layer is improved.

Referring to fig. 3, a flow chart illustrating steps performed in sequence by a method according to an exemplary embodiment of the present invention is shown for schematically illustrating the flow of a manufacturing process.

In step 301, providing a semiconductor substrate on which a plurality of gate structures including a gate dielectric layer, a gate material layer and a gate hard mask layer are formed from bottom to top;

in step 302, removing a gate hard mask layer in a part of the gate structure;

in step 303, an interconnect polysilicon layer electrically connected to the portion of the gate structure is formed.

[ exemplary embodiment III ]

Next, the fabrication of the whole semiconductor device can be completed by the following processes, including: forming an interlayer dielectric layer on a semiconductor substrate, and forming a plurality of interconnected metal layers in the interlayer dielectric layer, wherein the formation is usually completed by adopting a dual damascene process; and forming a metal bonding pad for wire bonding in the subsequent device packaging process.

[ fourth exemplary embodiment ]

The present invention also provides an electronic device including a semiconductor device manufactured according to the method of the third exemplary embodiment of the present invention. The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, a PSP, or any intermediate product including the semiconductor device. The electronic device has better performance due to the use of the semiconductor device.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate, and forming a plurality of grid structures comprising a grid dielectric layer, a grid material layer and a grid hard masking layer which are stacked from bottom to top on the semiconductor substrate;

removing the grid hard masking layers in at least two grid structures, then forming offset side walls on two sides of the grid structures, and forming main side walls on the outer sides of the offset side walls;

and forming an interconnection polysilicon layer electrically connecting at least two of the gate structures.

2. The method of claim 1, wherein the step of performing the removing comprises: forming a patterned photoetching mask on the semiconductor substrate to expose part of the gate structure; removing the gate hard masking layer in the partial gate structure by plasma dry etching by taking the photoetching mask as a mask; the photolithographic mask is removed by ashing or a stripping process.

3. The method of claim 1, wherein the step of forming the interconnected polysilicon layer comprises: forming a polysilicon layer by a deposition process to cover the plurality of gate structures; forming another patterned photoetching mask, and removing the part of the polycrystalline silicon layer which is not required to be electrically connected with the grid structure by dry etching by taking the other patterned photoetching mask as a mask; the further photolithographic mask is removed by an ashing or stripping process.

4. A semiconductor device manufactured by the method of any one of claims 1 to 3.

5. An electronic device comprising the semiconductor device according to claim 4.