CN105514159A - Semiconductor device, formation method of the semiconductor device, formation method of static RAM - Google Patents
Semiconductor device, formation method of the semiconductor device, formation method of static RAM Download PDFInfo
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- CN105514159A CN105514159A CN201410494936.4A CN201410494936A CN105514159A CN 105514159 A CN105514159 A CN 105514159A CN 201410494936 A CN201410494936 A CN 201410494936A CN 105514159 A CN105514159 A CN 105514159A
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Abstract
The invention provides a semiconductor device, a formation method of the semiconductor device, a formation method of a RAM (static random access memory). An insulating layer in a grid structure of a transistor is a double-layer structure, that is, a silicon oxide insulating layer and a silicon nitride insulating layer. For the double insulating layers, the silicon nitride insulating layer is firstly prepared through dry etching, and then the silicon oxide insulating layer is prepared through wet etching. During the wet etching process of the silicon oxide insulating layer, the residual silicon nitride particles during the dry etching process of the silicon nitride insulating layer can be removed at the same time, so that the problem that the residual silicon nitride particles cause residual defects in the grid structure can be avoided and the yield rate of products can be improved.
Description
Technical field
The present invention relates to ic manufacturing technology field, particularly the formation method of a kind of semiconductor device and forming method thereof, static random access memory.
Background technology
Static random access memory (StaticRandomAccessMemory, SRAM) is widely used in the fields such as PC, personal communication, consumption electronic product (such as: digital camera).
In conjunction with reference to figure 1 and Fig. 2, respectively illustrate circuit diagram and the vertical view of memory cell in the SRAM memory of prior art 6T structure.Wherein, described memory cell comprises: the first PMOS transistor P1, the second PMOS transistor P2, the first nmos pass transistor N1, the second nmos pass transistor N2, the 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4.Described first PMOS transistor P1, the second PMOS transistor P2, the first nmos pass transistor N1, the second nmos pass transistor N2 form bistable circuit, and described bistable circuit forms a latch for latch data information.Described first PMOS transistor P1 and the second PMOS transistor P2 is for pulling up transistor; Described first nmos pass transistor N1 and the second nmos pass transistor N2 is pull-down transistor; Described 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4 is transmission transistor.
Concrete, the source electrode electrical connection of the drain electrode of the grid structure of the first PMOS transistor P1, the grid structure of the first nmos pass transistor N1, the second PMOS transistor P2, the drain electrode of the second nmos pass transistor N2, the 4th nmos pass transistor N4, forms the first memory node 11; The source electrode electrical connection of the drain electrode of the grid structure of the second PMOS transistor P2, the grid structure of the second nmos pass transistor N2, the first PMOS transistor P1, the drain electrode of the first nmos pass transistor N1, the 3rd nmos pass transistor N3, forms the second memory node 12.The grid structure of the 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4 is electrically connected with wordline WL; The drain electrode of the 3rd nmos pass transistor N3 is electrically connected with the first bit line BL, and the drain electrode of the 4th nmos pass transistor N4 is electrically connected with the second bit line (paratope line) BLB; The source electrode of the first PMOS transistor P1 and the source electrode of the second PMOS transistor P2 are electrically connected with power line Vdd; The source electrode of the first nmos pass transistor N1 and the source electrode of the second nmos pass transistor N2 are electrically connected with ground wire Vss.When carrying out read operation to described SRAM memory, having electric current and flowing to low level first memory node 11 or the second memory node 12 from the first bit line BL, the second bit line BLB of high level; When carrying out write operation to described SRAM memory, having electric current and flowing to low level first bit line BL or the second bit line BLB from the first memory node 11 of high level or the second memory node 12.
In order to realize the connection of transistor grid structure, source electrode or drain electrode in prior art, usually attachment plug is set above grid structure, source electrode or drain electrode, described attachment plug is used for grid structure, source electrode or drain electrode to draw, to realize the connection with other devices.Be disclose a kind of SRAM memory in the United States Patent (USP) of US2007/0241411A1 at publication number, with reference to figure 3, described transistor comprises: Semiconductor substrate 10; Be formed at the grid structure in described Semiconductor substrate 10, described grid structure comprises the gate dielectric layer 116B, gate electrode layer 118B, the contact layer 119B that are positioned at successively in described Semiconductor substrate 10, described grid structure also comprises the side wall 122B being positioned at described gate dielectric layer 116B, gate electrode layer 118B, contact layer 119B both sides, described transistor also comprises the attachment plug G be positioned at above described gate electrode layer 118B, described attachment plug G is formed in interlayer dielectric layer 104, is drawn by the gate electrode layer 118B of described transistor.But the existence of described attachment plug G occupies the space between more transistor, make the size of SRAM memory larger.
In order to solve the problem, those skilled in the art proposes a kind of solution, specifically please refer to Fig. 4, and this semiconductor device mainly comprises: Semiconductor substrate 200; Be formed at least two adjacent transistor in described Semiconductor substrate 200; The grid grid structure of described two adjacent transistor and the gap 210 that Semiconductor substrate 200 surrounds between the grid structure of described two adjacent transistor; The grid structure of described two adjacent transistor includes: be positioned at the gate dielectric layer 201 in described Semiconductor substrate 200, gate electrode layer 202, silicon nitride dielectric layer 203, and around the side wall 204 of gate electrode layer 202, silicon nitride dielectric layer 203; To be covered in bottom described gap and conductive layer 205 on side wall 204; Wherein said silicon nitride dielectric layer 203 is silicon nitride with the material of described side wall 204.Grid structure forming process is as follows: 200 deposit gate dielectric layer 201, gate electrode layer 202, silicon nitride dielectric layers 203 successively on a semiconductor substrate first successively; Afterwards by dry etching silicon nitride insulating barrier 203 to determine the shape of silicon nitride dielectric layer 203, be next that mask carries out dry etching to the gate electrode layer 202 below it with the silicon nitride dielectric layer 203 after dry etching; Next around the gate electrode layer 202 after dry etching and silicon nitride dielectric layer 203, side wall 204 is formed.Adopt in above-mentioned semiconductor device and to form one deck conductive layer 205 on the surface of the bottom in described gap 210 and the sidewall in described gap 210 and replace the electrical connection that attachment plug G realizes between transistor and transistor, thus reduce the size of SRAM memory.But the semiconductor device formed by this method can find to there is residual defects in its grid structure in actual applications, causes the problem that subsequent product yield declines.
Summary of the invention
The object of the present invention is to provide the formation method of a kind of semiconductor device and forming method thereof, static random access memory, there is residual defects in the grid structure of the semiconductor device formed with the method solving use prior art, cause the problem that subsequent product yield declines.
For solving the problems of the technologies described above, the invention provides a kind of formation method of semiconductor device, the formation method of described semiconductor device comprises the steps:
Semi-conductive substrate is provided;
Form gate dielectric layer, gate electrode layer, insulating layer of silicon oxide and silicon nitride dielectric layer successively on the semiconductor substrate;
Silicon nitride dielectric layer described in dry etching, insulating layer of silicon oxide described in wet etching, gate electrode layer described in dry etching is to form multiple stacked structure;
Form side wall at the sidewall of described multiple stacked structure, to form multiple grid structure, there is between adjacent grid structure a gap;
Depositing conducting layer on described gate dielectric layer and described multiple grid structure;
Remove the conductive layer at described grid structure top; And
Semiconductor substrate below described gap is adulterated, to form doped region.
Optionally, in the formation method of described semiconductor device, in the step of described wet etching insulating layer of silicon oxide, the etching solution of employing is hydrofluoric acid.
Optionally, in the formation method of described semiconductor device, in the step of silicon nitride dielectric layer described in described dry etching, the etching gas of employing is CF
4, CH
2f
2or He.
Optionally, in the formation method of described semiconductor device, in the step of gate electrode layer described in described dry etching, the etching gas of employing is C
2f
6, HBr, Cl
2or He.
Optionally, in the formation method of described semiconductor device, the thickness of described insulating layer of silicon oxide exists
between.
Optionally, in the formation method of described semiconductor device, the thickness of described silicon nitride dielectric layer exists
between.
Optionally, in the formation method of described semiconductor device, the material of described conductive layer is one or more in polysilicon, tin indium oxide.
Optionally, in the formation method of described semiconductor device, described conductive layer is deposited by the method for chemical vapour deposition (CVD).
The invention provides a kind of formation method of static random access memory, the formation method of described static random access memory adopts the formation method of semiconductor device as above.
The present invention also provides a kind of semiconductor device, and described semiconductor device comprises:
Semiconductor substrate;
Be formed at the multiple stacked structures in described Semiconductor substrate;
Be formed at the side wall of the sidewall of described multiple stacked structure, multiple grid structures that described side wall and described multiple stacked structure are formed;
The gap surrounded between adjacent grid structure;
Be covered in the conductive layer on described gate dielectric layer and described side wall.
Find through inventor's test of many times; residual defects is there is in grid structure; silicon nitride particle can be remained when mainly being formed the silicon nitride dielectric layer in grid structure by dry etching; and follow-up be that mask carries out in dry etching process to the gate dielectric layer below it with silicon nitride dielectric layer; residual silicon nitride particle is removed not yet; and then make this residual nitrogen silicon carbide particle can reside in the side wall of follow-up formation; cause the semiconductor device of formation to there is the problem of grid structure defect, and then cause product yield to decline.
At semiconductor device provided by the present invention and forming method thereof, in the formation method of static random access memory, insulating barrier in the grid structure of transistor is double-layer structure, i.e. insulating layer of silicon oxide and silicon nitride dielectric layer, this dielectric layers be silicon nitride dielectric layer described in first dry etching, then insulating layer of silicon oxide described in wet etching again, can also to get rid of while the process of insulating layer of silicon oxide described in wet etching in the process of dry etching silicon nitride insulating barrier the silicon nitride particle that remains, thus avoid residual silicon nitride particle and cause grid structure to there is the problem of residual defects, improve product yield.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of memory cell in the SRAM memory of prior art 6T structure;
Fig. 2 is the vertical view of memory cell in the SRAM memory of prior art 6T structure;
Fig. 3 is the cutaway view of transistor in prior art SRAM memory;
Fig. 4 is the schematic diagram that there is residual defects in the grid structure of semiconductor device in prior art;
Fig. 5 is the flow chart of the formation method of semiconductor device in one embodiment of the invention;
Fig. 6 is the dependency structure schematic diagram of step S20 in Fig. 5;
Fig. 7 A-Fig. 7 C is the dependency structure schematic diagram of step S30 in Fig. 5;
Fig. 8 is the dependency structure schematic diagram of step S40 in Fig. 5;
Fig. 9 is the dependency structure schematic diagram of step S50 in Fig. 5;
Figure 10 is the dependency structure schematic diagram of step S60 in Fig. 5.
Embodiment
Be described in further detail below in conjunction with the formation method of the drawings and specific embodiments to semiconductor device that the present invention proposes and forming method thereof, static random access memory.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Find through inventor's test of many times; residual defects is there is in grid structure; the particle of silicon nitride can be remained when mainly being formed the silicon nitride dielectric layer in grid structure by dry etching; and follow-up be that mask carries out in dry etching process to the gate dielectric layer below it with silicon nitride dielectric layer; residual silicon nitride particle is removed not yet; and then make this residual silicon nitride particle can reside in the side wall of follow-up formation; cause the semiconductor device of formation to there is the problem of grid structure defect, and then cause product yield to decline.
Fig. 5 is the flow chart of the formation method of semiconductor device in one embodiment of the invention; The dependency structure schematic diagram of Fig. 6-Figure 10 involved by the formation method of semiconductor device of the present invention.The formation method of described semiconductor device of the present invention is described in detail below in conjunction with Fig. 5-Figure 10.
First, perform step S10, semi-conductive substrate 100 is provided.
Please refer to Fig. 6, then, perform step S20, described Semiconductor substrate 100 is formed gate dielectric layer 401, gate electrode layer 402, insulating layer of silicon oxide 403 and silicon nitride dielectric layer 406 successively.
Wherein, the thickness of described insulating layer of silicon oxide 403 exists
between; The thickness of described silicon nitride dielectric layer 406 exists
between.
Please refer to Fig. 7 A-Fig. 7 C, then, perform step S30, silicon nitride dielectric layer 406 described in dry etching, insulating layer of silicon oxide 403 described in wet etching, gate electrode layer 402 described in dry etching is to form multiple stacked structure.
In the present embodiment, composition graphs 4 and Fig. 7-Figure 10, as shown in Figure 4, usually single layer structure is selected based on insulating barrier 203 of the prior art, namely one deck silicon nitride layer is formed, cause when forming insulating barrier 203 when removing unnecessary silicon nitride by dry etching, in the process due to dry etching silicon nitride layer, the phenomenon of residual silicon nitride particle can be there is; And next formed in the process of gate electrode layer 202, still cannot remove silicon nitride particle 211 residual after forming insulating barrier 203, cause the semiconductor device of formation to there is the problem of grid structure defect.Insulating barrier in the present invention in semiconductor device selects double-layer structure, i.e. insulating layer of silicon oxide 403 and silicon nitride dielectric layer 406, this dielectric layers be silicon nitride dielectric layer 406 described in first dry etching, then insulating layer of silicon oxide 403 described in wet etching again, can also to get rid of while the process of insulating layer of silicon oxide described in wet etching 403 in the process of dry etching silicon nitride insulating barrier 406 the silicon nitride particle 411 that remains, thus avoid residual silicon nitride particle 411 and cause grid structure to there is the problem of residual defects, improve product yield.
Preferably, in the step of silicon nitride dielectric layer 406 described in described dry etching, the etching gas of employing is CF
4, CH
2f
2or He; In the step of gate electrode layer 402 described in described dry etching, the etching gas of employing is C
2f
6, HBr, Cl
2or He; In the step of described wet etching insulating layer of silicon oxide 403, the etching solution of employing is hydrofluoric acid.Certainly the etching solution adopted in wet etching is including, but not limited to hydrofluoric acid, the hydrofluoric acid (DHF) such as diluted or buffered hydrofluoric acid solution (BOE), as long as etching solution can also remove the residual particles of silicon nitride while removing unnecessary silica.
Please refer to Fig. 8, then, perform step S40, form side wall 404 at the sidewall of described multiple stacked structure, to form multiple grid structure, there is between adjacent grid structure a gap 410.
Please refer to Fig. 9, then, perform step S50, depositing conducting layer 405 on described gate dielectric layer 401 and described multiple grid structure.
Further, the material of described conductive layer 405 is one or more in polysilicon, tin indium oxide.The material of conductive layer 405 described in the present embodiment is preferably as polysilicon, and described conductive layer 405 is formed by the method for chemical vapour deposition (CVD).
Please refer to Figure 10, then, perform step S60, remove the conductive layer 405 at described grid structure top.
Then, perform step S70, the Semiconductor substrate 100 below described gap 410 is adulterated, to form doped region.
In the present embodiment, need to illustrate that follow-up also needs forms doped region between grid structure.If the thickness of described conductive layer 405 is excessive, easily causes and be difficult to form the problem of doped region by ion implantation, and if the thickness of conductive layer 405 is too small, easily reduce the reliability of electrical connection, therefore, the thickness of described conductive layer 405 preferably exists
between.
The present embodiment additionally provides a kind of formation method of static random access memory, and the formation method of described static random access memory is the formation method adopting semiconductor device as above.
The present embodiment additionally provides a kind of semiconductor device, and described semiconductor device utilizes the formation method of above-mentioned semiconductor device to be formed, and specifically please continue to refer to Figure 10, described semiconductor device comprises: Semiconductor substrate 100; Be formed at the multiple stacked structures in described Semiconductor substrate 100; Be formed at the side wall 404 of the sidewall of described multiple stacked structure, multiple grid structures that described side wall 404 is formed with described multiple stacked structure; The gap 410 surrounded between adjacent grid structure; Be covered in the conductive layer 405 on described gate dielectric layer 401 and described side wall 404.
To sum up, at semiconductor device provided by the present invention and forming method thereof, in the formation method of static random access memory, insulating barrier in the grid structure of transistor is double-layer structure, i.e. insulating layer of silicon oxide and silicon nitride dielectric layer, this dielectric layers be silicon nitride dielectric layer described in first dry etching, then insulating layer of silicon oxide described in wet etching again, can also to get rid of while the process of insulating layer of silicon oxide described in wet etching in the process of dry etching silicon nitride insulating barrier the silicon nitride particle that remains, thus avoid residual silicon nitride particle and cause grid structure to there is the problem of residual defects, improve product yield.
Foregoing description is only the description to present pre-ferred embodiments, any restriction not to the scope of the invention, and any change that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, modification, all belong to the protection range of claims.
Claims (10)
1. a formation method for semiconductor device, is characterized in that, comprising:
Semi-conductive substrate is provided;
Form gate dielectric layer, gate electrode layer, insulating layer of silicon oxide and silicon nitride dielectric layer successively on the semiconductor substrate;
Silicon nitride dielectric layer described in dry etching, insulating layer of silicon oxide described in wet etching, gate electrode layer described in dry etching is to form multiple stacked structure;
Form side wall at the sidewall of described multiple stacked structure, to form multiple grid structure, there is between adjacent grid structure a gap;
Depositing conducting layer on described gate dielectric layer and described multiple grid structure;
Remove the conductive layer at described grid structure top; And
Semiconductor substrate below described gap is adulterated, to form doped region.
2. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, in the step of described wet etching insulating layer of silicon oxide, the etching solution of employing is hydrofluoric acid.
3. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, in the step of silicon nitride dielectric layer described in described dry etching, the etching gas of employing is CF
4, CH
2f
2or He.
4. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, in the step of gate electrode layer described in described dry etching, the etching gas of employing is C
2f
6, HBr, Cl
2or He.
5. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the thickness of described insulating layer of silicon oxide exists
between.
6. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the thickness of described silicon nitride dielectric layer exists
between.
7. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, the material of described conductive layer is one or more in polysilicon, tin indium oxide.
8. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, deposit described conductive layer by the method for chemical vapour deposition (CVD).
9. a formation method for static random access memory, is characterized in that, adopts the formation method of the semiconductor device according to any one of claim 1-8.
10. a semiconductor device, utilizes the method according to any one of claim 1-8 to be formed, it is characterized in that, comprising:
Semiconductor substrate;
Be formed at the multiple stacked structures in described Semiconductor substrate;
Be formed at the side wall of the sidewall of described multiple stacked structure, multiple grid structures that described side wall and described multiple stacked structure are formed;
The gap surrounded between adjacent grid structure;
Be covered in the conductive layer on described gate dielectric layer and described side wall.
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| CN201410494936.4A CN105514159B (en) | 2014-09-24 | 2014-09-24 | The forming method of semiconductor devices and forming method thereof, Static RAM |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5668065A (en) * | 1996-08-01 | 1997-09-16 | Winbond Electronics Corp. | Process for simultaneous formation of silicide-based self-aligned contacts and local interconnects |
| CN102446727A (en) * | 2011-08-29 | 2012-05-09 | 上海华力微电子有限公司 | Etching method of etching hard mask layer containing silicon nitride |
| CN103730468A (en) * | 2012-10-16 | 2014-04-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, forming method of semiconductor structure, SRAM memory unit and SRAM memorizer |
-
2014
- 2014-09-24 CN CN201410494936.4A patent/CN105514159B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5668065A (en) * | 1996-08-01 | 1997-09-16 | Winbond Electronics Corp. | Process for simultaneous formation of silicide-based self-aligned contacts and local interconnects |
| CN102446727A (en) * | 2011-08-29 | 2012-05-09 | 上海华力微电子有限公司 | Etching method of etching hard mask layer containing silicon nitride |
| CN103730468A (en) * | 2012-10-16 | 2014-04-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, forming method of semiconductor structure, SRAM memory unit and SRAM memorizer |
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