TW201630225A - Resistive random access memory and method for manufacturing the same - Google Patents

Abstract

A resistive random access memory (RRAM) including a resistive random access memory cell string. The resistive random access memory cell string includes a substrate, a first conductive type conductor layer and a plurality of stacked structures. The first conductive type conductor layer is disposed on the substrate. The stacked structures are separately disposed on the first conductive type conductor layer. Each of the stacked structures includes a second conductive type deposition layer, a RRAM cell and a first conductive line. The second conductive type deposition layer is disposed on the first conductive type conductor layer. The RRAM cell is disposed on the second conductive type deposition layer. The first conductive line is disposed on the RRAM cell.

Description

Resistive random access memory and manufacturing method thereof

The present invention relates to a memory and a method of fabricating the same, and more particularly to a resistive random access memory and a method of fabricating the same.

Since non-volatile memory has the advantage that the data will not disappear after power-off, many such electrical products must have such memory to maintain the normal operation of the electrical product when it is turned on. At present, a non-volatile memory component actively developed in the industry is a resistive random access memory (RRAM), which has a low write operation voltage, a short write erase time, a long memory time, and a non-volatile memory. Destructive reading, multi-state memory, simple structure and small required area make it one of the non-volatile memory components widely used in personal computers and electronic devices in the future.

However, current resistive random access memories have a problem of sneak current during operation, which in turn causes a decrease in reliability of the memory device.

The invention provides a resistive random access memory and a manufacturing method thereof, which can effectively improve the reliability of a memory component.

The invention provides a resistive random access memory comprising a resistive random access memory cell string. The resistive random access memory cell string includes a substrate, a first conductive type conductor layer, and a plurality of stacked structures. The first conductive type conductor layer is disposed on the substrate. The stacked structure is separately disposed on the first conductive type conductor layer. Each of the stacked structures includes a second conductive type deposition layer, a resistive random access memory cell, and a first wire. The second conductive type deposition layer is disposed on the first conductive type conductor layer. The resistive random access memory cell is disposed on the second conductive type deposition layer. The first wire is disposed on the resistive random access memory cell.

According to an embodiment of the invention, in the resistive random access memory, each of the resistive random access memory cells includes a variable resistance layer. The variable resistance layer is disposed on the second conductive type deposition layer.

According to an embodiment of the present invention, in the resistive random access memory, each of the resistive random access memory cells further includes a first electrode layer and a second electrode layer. The first electrode layer is disposed between the variable resistance layer and the second conductive type deposition layer. The second electrode layer is disposed between the variable resistance layer and the first wire.

According to an embodiment of the present invention, in the resistive random access memory, the resistive random access memory cell string further includes two second conductive type doped regions, which are disposed in the resistive random access memory. The first conductive type conductor layer at both ends of the cell string.

According to an embodiment of the invention, in the resistive random access memory, the resistive random access memory cell string further includes a second wire. The second wire is disposed on the stacked structure and disposed apart from the stacked structure. The second wire is electrically connected to the first conductive type conductor layer.

According to an embodiment of the present invention, in the resistive random access memory, the second conductive line and the first conductive type conductor layer are, for example, not adjacent to the last end of the resistive random access memory cell string. Connect between the stacked structures.

According to an embodiment of the present invention, in the resistive random access memory, the upper surface of the first conductive type conductor layer located between the second conductive type deposition layers is, for example, lower than the second conductive type sink. The lower surface of the laminate.

The invention provides a method for manufacturing a resistive random access memory, comprising forming a resistive random access memory cell string. The method of forming a resistive random access memory cell string includes the following steps. A first conductive type conductor layer is formed on the substrate. A plurality of stacked structures are separated on the first conductive type conductor layer. Each of the stacked structures includes a second conductive type deposition layer, a resistive random access memory cell, and a first wire. The second conductive type deposition layer is disposed on the first conductive type conductor layer. The resistive random access memory cell is disposed on the second conductive type deposition layer. The first wire is disposed on the resistive random access memory cell.

According to an embodiment of the present invention, in the method of fabricating a resistive random access memory, the method of forming the first conductive type conductor layer includes forming an ion implantation process on the substrate or by performing field doping. The deposition method is formed.

According to an embodiment of the invention, in the above resistive random access In the method of manufacturing a memory, the method of forming the stacked structure includes the following steps. A second conductive type deposition material layer is deposited on the first conductive type conductor layer. A resistive random access memory cell layer is formed on the second conductive type deposition material layer. Forming a first layer of conductive material on the resistive random access memory cell layer. The first conductive material layer, the resistive random access memory cell layer and the second conductive type deposition material layer are patterned.

According to an embodiment of the invention, in the method for fabricating a resistive random access memory, the method for depositing a second conductive type deposition material layer comprises directly forming by a field doping deposition method or by the following The method is formed. An undoped semiconductor layer is deposited on the first conductive type conductor layer. A second conductive type doped semiconductor layer is deposited on the undoped semiconductor layer. A plurality of second conductivity type dopants in the second conductivity type doped semiconductor layer are diffused into the undoped semiconductor layer.

According to an embodiment of the invention, in the method for fabricating a resistive random access memory, the method for forming a resistive random access memory cell layer includes the following steps. A first electrode material layer is formed on the second conductive type deposition material layer. A layer of variable resistance material is formed on the first electrode material layer. A second electrode material layer is formed on the variable resistance material layer.

According to an embodiment of the invention, in the method for manufacturing a resistive random access memory, the method further includes forming two in the first conductive type conductor layer at both ends of the resistive random access memory cell string. Two conductivity type doped regions.

According to an embodiment of the invention, in the method of manufacturing a resistive random access memory, the method further includes forming a second wire electrically connected to the first conductive type conductor layer on the stacked structure. The second wire is disposed apart from the stacked structure.

According to an embodiment of the invention, in the manufacturing method of the resistive random access memory, the second conductive line and the first conductive type conductor layer are not at the end of the resistive random access memory cell string, for example. A connection is made between two adjacent stacked structures.

Based on the above, in the resistive random access memory and the manufacturing method thereof according to the present invention, since the second conductive type deposition layer is formed by deposition, the adjacent stacked structure can be made in the manufacturing process. The second conductive type deposition layer is completely separated to avoid electrical interference, thereby effectively improving the reliability of the memory element. Further, since the second conductive type deposition layer and the first conductive type conductor layer can form a diode, leakage current of the memory element can be suppressed, and malfunction can be prevented, so that the reliability of the memory element can be effectively improved.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧Resistive random access memory

100‧‧‧Base

102‧‧‧Second Conductive Well Area

104‧‧‧First Conductive Conductor Layer

106‧‧‧Second conductive deposition material layer

106a‧‧‧Second conductive deposit

108, 112‧‧‧ electrode material layer

108a, 112a‧‧‧electrode layer

110‧‧‧Variable resistance material layer

110a‧‧‧variable resistance layer

113‧‧‧hard mask layer

113a‧‧‧ patterned hard mask layer

114‧‧‧Resistive random access memory cell layer

114a‧‧‧Resistive random access memory cells

115, 118, 122‧‧‧ patterned photoresist layer

116‧‧‧Wire material layer

116a‧‧‧Wire

117, 124‧‧‧ openings

119‧‧‧Isolation structure

120‧‧‧Stack structure

126‧‧‧Second conductive doped region

128‧‧‧ dielectric layer

130‧‧‧Contact window

132‧‧‧Wire

134‧‧‧Resistive random access memory cell string

1 is a top view of a resistive random access memory according to an embodiment of the present invention.

2A to 2D are cross-sectional views showing the manufacturing process of the resistive random access memory along the line I-I' in Fig. 1.

3A to 3D are cross-sectional views showing the manufacturing flow of the resistive random access memory along the line II-II' in Fig. 1.

1 is a top view of a resistive random access memory according to an embodiment of the present invention. For the sake of clarity, the depiction of the dielectric layer is omitted in FIG. 2A to 2D are cross-sectional views showing the manufacturing process of the resistive random access memory along the line I-I' in Fig. 1. 3A to 3D are cross-sectional views showing the manufacturing flow of the resistive random access memory along the line II-II' in Fig. 1.

In this embodiment, the "first conductivity type" and the "second conductivity type" referred to are different conductivity types. When the first conductivity type is an N type, the second conductivity type is a P type. When the first conductivity type is a P type, the second conductivity type is an N type.

First, referring to FIG. 1 and FIG. 2A simultaneously, the second conductive type well region 102 can be selectively formed in the substrate 100. The substrate 100 is, for example, a crucible substrate. The second conductive well region 102 is, for example, a P-type well region or an N-type well region. In this embodiment, the second conductive type well region 102 is described by taking a P-type well region as an example. The method of forming the second conductive type well region 102 is, for example, an ion implantation method.

Next, a first conductive type conductor layer 104 is formed on the substrate 100. The first conductive type conductor layer 104 can be used as a buried bit line. The first conductive type conductor layer 104 is, for example, an N-type conductor layer or a P-type conductor layer. In this embodiment, the first conductive type conductor layer 104 is described by taking an N-type conductor layer as an example. The method of forming the first conductive type conductor layer 104 can be formed by performing an ion implantation process on the substrate 100. In addition, the first conductive type conductor layer 104 can also be formed by a deposition method of field doping, such as a field doped chemical vapor deposition method. The material of the first conductive type conductor layer 104 formed by the deposition method of the field doping is, for example, a doped semiconductor such as doped polysilicon.

Then, referring to FIG. 1 and FIG. 2B, a second conductive type deposition material layer 106 is deposited on the first conductive type conductor layer 104. The second conductive type deposition material layer 106 is, for example, a P-type deposition material layer or an N-type deposition material layer. In this embodiment, the second conductive type deposition material layer 106 is exemplified by a P-type deposition material layer. The deposition method of the second conductive type deposition material layer 106 can be directly formed by a deposition method of on-site doping, such as a field-doped chemical vapor deposition method. The material of the second conductive type deposition material layer 106 is, for example, a doped semiconductor such as doped polysilicon.

Further, the second conductive type deposition material layer 106 can also be formed by the following method. An undoped semiconductor layer (not shown) is deposited on the first conductive type conductor layer 104. A second conductive type doped semiconductor layer (not shown) is deposited on the undoped semiconductor layer. Diffusion of the second conductivity type dopant in the second conductivity type doped semiconductor layer into the undoped semiconductor layer, so that the undoped semiconductor layer also becomes the second conductivity type doped semiconductor layer, thereby The second conductive type doped semiconductor layer forms the second conductive type deposition material layer 106. The method of diffusing the second conductivity type dopant in the second conductivity type doped semiconductor layer into the undoped semiconductor layer is, for example, a tempering process of the second conductivity type doped semiconductor layer.

Next, an electrode material layer 108 is formed on the second conductive type deposition material layer 106. The material of the electrode material layer 108 is, for example, a metal material such as titanium, nickel, ruthenium or copper. The method of forming the electrode material layer 108 is, for example, a physical vapor deposition method.

Thereafter, a variable resistance material layer 110 is formed on the electrode material layer 108. The material of the variable resistance material layer 110 is, for example, a metal oxide such as cerium oxide, magnesium oxide, nickel oxide, cerium oxide, titanium oxide, aluminum oxide, vanadium oxide, tungsten oxide, zinc oxide or Cobalt oxide. The method of forming the variable resistance material layer 110 is, for example, a chemical vapor deposition method.

Further, an electrode material layer 112 is formed on the variable resistance material layer 110. The material of the electrode material layer 112 is, for example, a metal material such as titanium, nickel, tantalum or copper. The method of forming the electrode material layer 112 is, for example, a physical vapor deposition method. Further, a resistive random access memory cell layer 114 on the second conductive type deposition material layer 106 is formed by the electrode material layer 108, the variable resistance material layer 110, and the electrode material layer 112.

Subsequently, a hard mask layer 113 may be selectively formed on the electrode material layer 112. The material of the hard mask layer 113 is, for example, tantalum nitride or tantalum oxide. The method of forming the hard mask layer 113 is, for example, a chemical vapor deposition method.

Next, a patterned photoresist layer 115 is formed on the hard mask layer 113. The method of forming the patterned photoresist layer 115 is formed, for example, by performing a lithography process.

Next, referring to FIG. 1 and FIG. 2C simultaneously, the patterned photoresist layer 115 is used as a mask to remove a portion of the hard mask layer 113 to form a patterned hard mask layer 113a. The method of removing the partial hard mask layer 113 is, for example, a dry etching method.

The patterned photoresist layer 115 can then be selectively removed. The method of removing the patterned photoresist layer 115 is, for example, a dry de-resisting method.

Next, using the patterned hard mask layer 113a as a mask, a portion of the resistive random access memory cell layer 114, a portion of the second conductive type deposition material layer 106, a portion of the first conductive type conductor layer 104, and a portion of the second portion are removed. The conductive well region 102 forms an opening 117 in the above-mentioned film layer. The removal method used in the above removal step is, for example, a dry etching method.

After that, please refer to FIG. 1 and FIG. 2D simultaneously to form isolation in the opening 117. Structure 119. The isolation structure 119 is, for example, a shallow trench isolation structure (STI). The material of the isolation structure 119 is, for example, ruthenium oxide. The forming method of the isolation structure 119 is formed, for example, by forming a layer of an insulating structural material (not shown) filling the opening 117 and then removing a layer of the insulating structural material other than the opening 117. The method for removing the layer of the isolation structural material other than the opening 117 is, for example, a chemical mechanical polishing method.

Furthermore, the patterned hard mask layer 113a is removed. The method of removing the patterned hard mask layer 113a is, for example, a dry etching method.

Subsequently, referring to FIG. 1 and FIG. 3A, a conductive material layer 116 is formed on the resistive random access memory cell layer 114. The material of the wire material layer 116 is, for example, a conductive material such as doped polysilicon or metal. The method of forming the electrode material layer 112 is, for example, a chemical vapor deposition method or a physical vapor deposition method.

Next, please refer to FIG. 1 and FIG. 3B simultaneously to form a patterned photoresist layer 118 on the conductive material layer 116. The method of forming the patterned photoresist layer 118 is formed, for example, by performing a lithography process.

Then, the patterned photoresist layer 118 is used as a mask to remove a portion of the conductive material layer 116, the partial resistive random access memory cell layer 114 and a portion of the second conductive type deposition material layer 106, thereby exposing the first conductive type conductor. The layer 104 and the stacked structure 120 are formed on the first conductive type conductor layer 104. In this embodiment, the stacked structure 120 is formed, for example, by performing the above self-aligned patterning process on the conductive material layer 116, the resistive random access memory cell layer 114, and the second conductive type deposition material layer 106. The removal method used in the above removal step is, for example, a dry etching method.

Each of the stacked structures 120 includes a second conductive type deposition layer 106a, and a resistive type The memory cell 114a is randomly accessed with the wire 116a. The second conductive type deposition layer 106a is disposed on the first conductive type conductor layer 104. The resistive random access memory cell 114a is disposed on the second conductive type deposition layer 106a. Each of the resistive random access memory cells 114a includes an electrode layer 108a, a variable resistance layer 110a, and an electrode layer 112a. The electrode layer 108a is disposed on the second conductive type deposition layer 106a. The variable resistance layer 110a is provided on the electrode layer 108a. The electrode layer 112a is provided on the variable resistance layer 110a. The wire 116a is disposed on the resistive random access memory cell 114a and can be used as a word line.

In the above removal step, since the second conductive type deposition material layer 106 is formed using deposition, the second conductive type deposition material layer 106 located between the stacked structures 120 can be easily removed. Therefore, the second conductive type deposition layer 106a in the adjacent stacked structure 120 can be completely separated to avoid electrical interference, thereby improving the reliability of the memory element.

In order to ensure complete removal of the second conductive type deposition material layer 106 between the stacked structures 120, the exposed portion of the first conductive type conductor layer 104 is more selectively removed. As a result, the upper surface of the first conductive type conductor layer 104 located between the second conductive type deposition layers 106a is, for example, lower than the lower surface of the second conductive type deposition layer 106a.

In addition, since the second conductive type deposition layer 106a and the first conductive type conductor layer 104 can form a diode, leakage current of the memory element can be suppressed, thereby preventing malfunction, thereby effectively improving the reliability of the memory element. .

Then, referring to FIG. 1 and FIG. 3C simultaneously, the patterned photoresist layer 118 is removed. The method of removing the patterned photoresist layer 118 is, for example, a dry de-resist method.

Next, a patterned photoresist layer 122 is formed. The opening 124 in the patterned photoresist layer 122 exposes the first conductive type conductor layer 104. The method of forming the patterned photoresist layer 122 is formed, for example, by performing a lithography process.

Thereafter, a second conductive type doped region 126 is formed in the first conductive type conductor layer 104 exposed by the opening, and the first conductive type conductor layer 104 at both ends of the predetermined formed resistive random access memory cell string is formed. Two second conductivity type doping regions 126 are formed in the middle. The second conductive type doped region 126 is, for example, a P-type doped region or an N-type doped region. In this embodiment, the second conductive type doped region 126 is exemplified by a P-type doped region. The method of forming the second conductive type doped region 126 is, for example, an ion implantation method. In addition, the second conductive type doping region 126 and the first conductive type conductor layer 104 can form a diode, so that the leakage current of the memory device can be further suppressed, thereby effectively improving the reliability of the memory device.

Furthermore, please refer to FIG. 1 and FIG. 3D simultaneously to remove the patterned photoresist layer 122. The method of removing the patterned photoresist layer 122 is, for example, a dry photoresist removal method.

Subsequently, a dielectric layer 128 covering the stacked structure 120 is formed. The material of the dielectric layer 128 is, for example, a dielectric material such as ruthenium oxide. The method of forming the dielectric layer 128 is, for example, a chemical vapor deposition method.

Next, a contact window 130 is formed in the dielectric layer 128. The material of the contact window 130 is, for example, copper or tungsten. The dielectric layer 128 can be formed by using a lithography process, an etching process, and a deposition process in combination or by a damascene process, such as a single damascene process.

Next, a wire 132 electrically connected to the first conductive type conductor layer 104 is formed on the stacked structure 120. The wire 132 can be electrically connected to the first through the contact window 130 A conductive type conductor layer 104. The wires 132 and the stacked structure 120 may be disposed apart by the dielectric layer 128. The material of the wire 132 is, for example, a metal material such as copper or aluminum. The method for forming the wire 132 is formed by first forming a wire material layer (not shown) by physical vapor deposition, and then patterning the wire material layer.

The fabrication of the resistive random access memory 10 has been completed by the above manufacturing method. The resistive random access memory 10 includes a resistive random access memory cell string 134. In this embodiment, a series of resistive random access memory cell strings 134 in the resistive random access memory 10 are illustrated as an example, but the invention is not limited thereto. As long as the resistive random access memory 10 includes a string or more of the resistive random access memory cell strings 134, it is within the scope of the present invention.

In this embodiment, the wires 132 and the first conductive type conductor layer 104 are, for example, not connected between the two adjacent stacked structures 120 at the end of the resistive random access memory cell string 134, but may have better Operational efficiency, but the invention is not limited thereto. Those skilled in the art can adjust the electrical connection position of the wire 132 and the first conductive type conductor layer 104 according to product design requirements.

Hereinafter, the configuration of the resistive random access memory 10 of the present embodiment will be described with reference to Fig. 3D.

Referring to FIG. 3D, the resistive random access memory 10 includes a resistive random access memory cell string 134. The resistive random access memory cell string 134 includes a substrate 100, a first conductive type conductor layer 104, and a plurality of stacked structures 120. The first conductive type conductor layer 104 is disposed on the substrate 100. The stacked structure 120 is separately disposed on the first conductive type conductor layer 104. Each of the stacked structures 120 includes a second conductive type deposition layer 106a, The resistive random access memory cell 114a is connected to the wire 116a. The second conductive type deposition layer 106a is disposed on the first conductive type conductor layer 104. The upper surface of the first conductive type conductor layer 104 located between the second conductive type deposition layers 106a is, for example, lower than the lower surface of the second conductive type deposition layer 106a. The resistive random access memory cell 114a is disposed on the second conductive type deposition layer 106a. Each of the resistive random access memory cells 114a includes a variable resistance layer 110a. The variable resistance layer 110a is disposed on the second conductive type deposition layer 106a. Each of the resistive random access memory cells 114a may further include an electrode layer 108a and an electrode layer 112a. The electrode layer 108a is disposed between the variable resistance layer 110a and the second conductive type deposition layer 106a. The electrode layer 112a is disposed between the variable resistance layer 110a and the wire 116a. The wire 116a is disposed on the resistive random access memory cell 114a.

In addition, the resistive random access memory cell string 134 further selectively includes at least one of the second conductive type well region 102, the two second conductive type doped regions 126, and the wires 132. The second conductive type well region 102 is disposed in the substrate 100 below the first conductive type conductor layer 104. The second conductive type doping region 126 is disposed in the first conductive type conductor layer 104 at both ends of the resistive random access memory cell string 134. The wires 132 are disposed on the stacked structure 120. The wires 132 and the stacked structure 120 may be disposed apart by the dielectric layer 128. The wire 132 can be electrically connected to the first conductive type conductor layer 104 by the contact window 130. The wire 132 and the first conductive type conductor layer 104 are not connected between the two adjacent stacked structures 120 at the end of the resistive random access memory cell string 134, but may have better operational efficiency, but the present invention Not limited to this.

Based on the above, in the resistive random access memory of the above embodiment and the method of fabricating the same, since the second conductive type deposition layer 106a is formed by deposition Therefore, the second conductive type deposition layer 106a in the adjacent stacked structure 120 can be completely separated during the manufacturing process to avoid electrical interference, thereby effectively improving the reliability of the memory element. Further, since the second conductive type deposition layer 106a and the first conductive type conductor layer 104 can form a diode, leakage current of the memory element can be suppressed, and malfunction can be prevented, so that the reliability of the memory element can be effectively improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Resistive random access memory

100‧‧‧Base

102‧‧‧Second Conductive Well Area

104‧‧‧First Conductive Conductor Layer

106a‧‧‧Second conductive deposit

108a, 112a‧‧‧electrode layer

110a‧‧‧variable resistance layer

114a‧‧‧Resistive random access memory cells

116a‧‧‧Wire

120‧‧‧Stack structure

126‧‧‧Second conductive doped region

128‧‧‧ dielectric layer

130‧‧‧Contact window

132‧‧‧Wire

134‧‧‧Resistive random access memory cell string

Claims (15)

A resistive random access memory, comprising a resistive random access memory cell string, wherein the resistive random access memory cell string comprises: a substrate; a first conductive type conductor layer disposed on the substrate; a plurality of stacked structures are disposed on the first conductive type conductor layer, wherein each of the stacked structures comprises: a second conductive type deposition layer disposed on the first conductive type conductor layer; and a resistive random access memory a cell disposed on the second conductivity type deposition layer; and a first wire disposed on the resistive random access memory cell. The resistive random access memory according to claim 1, wherein each of the resistive random access memory cells comprises a variable resistance layer disposed on the second conductive type deposition layer. The resistive random access memory according to claim 1, wherein each of the resistive random access memory cells further comprises: a first electrode layer disposed on the variable resistance layer and the second conductive type Between the deposited layers; and a second electrode layer disposed between the variable resistance layer and the first conductive line. The resistive random access memory of claim 1, wherein the resistive random access memory cell string further comprises two second conductive type doped regions disposed on the resistive random access memory cell string. In the first conductive type conductor layer at both ends. The resistive random access memory of claim 1, wherein the resistive random access memory cell string further comprises a second wire disposed on the stacked structure and isolated from the stacked structures The device is electrically connected to the first conductive type conductor layer. The resistive random access memory according to claim 5, wherein the second conductive line and the first conductive type conductor layer are not adjacent to the last two of the resistive random access memory cell strings. Connect between the stacked structures. The resistive random access memory according to claim 1, wherein an upper surface of the first conductive type conductor layer between the second conductive type deposition layers is lower than the second conductive type sinks The lower surface of the laminate. A method of manufacturing a resistive random access memory, comprising forming a resistive random access memory cell string, wherein the resistive random access memory cell string forming method comprises: forming a first conductive type conductor on a substrate And forming a plurality of stacked structures on the first conductive type conductor layer, wherein each of the stacked structures comprises: a second conductive type deposition layer disposed on the first conductive type conductor layer; and a resistive random storage The memory cell is disposed on the second conductive type deposition layer; and a first wire is disposed on the resistive random access memory cell. The method of manufacturing a resistive random access memory according to claim 8, wherein the method of forming the first conductive type conductor layer comprises performing the substrate An ion implantation process is formed or formed by a deposition method of on-site doping. The method for fabricating a resistive random access memory according to claim 8, wherein the method for forming the stacked structure comprises: depositing a second conductive type deposition material layer on the first conductive type conductor layer; Forming a resistive random access memory cell layer on the second conductive type deposition material layer; forming a first wire material layer on the resistive random access memory cell layer; and the first wire material layer, the The resistive random access memory cell layer and the second conductive type deposition material layer are subjected to a patterning process. The method for manufacturing a resistive random access memory according to claim 10, wherein the method for depositing the second conductive type deposition material layer comprises directly forming by a field doping deposition method or by the following method Forming: depositing an undoped semiconductor layer on the first conductive type conductor layer; depositing a second conductive type doped semiconductor layer on the undoped semiconductor layer; and doping the second conductive type doped semiconductor layer A plurality of second conductivity type dopants are diffused into the undoped semiconductor layer. The method for manufacturing a resistive random access memory according to claim 10, wherein the method for forming the resistive random access memory cell layer comprises: forming a first layer on the second conductive type deposition material layer a layer of electrode material; forming a layer of variable resistance material on the first electrode material layer; A second electrode material layer is formed on the variable resistance material layer. The method for manufacturing a resistive random access memory according to claim 8, further comprising forming a second conductivity type in the first conductive type conductor layer at both ends of the resistive random access memory cell string. Doped area. The method for manufacturing a resistive random access memory according to claim 8, further comprising forming a second wire electrically connected to the first conductive type conductor layer on the stacked structures, wherein the The two wires are disposed apart from the stacked structures. The method of manufacturing a resistive random access memory according to claim 14, wherein the second conductive line and the first conductive type conductor layer are not at the end of the resistive random access memory cell string. Connect between two adjacent stack structures.