CN109585450B

CN109585450B - Memory and forming method thereof

Info

Publication number: CN109585450B
Application number: CN201710897809.2A
Authority: CN
Inventors: 冯军宏
Original assignee: Semiconductor Manufacturing International Shanghai Corp; SMIC Advanced Technology R&D Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; SMIC Advanced Technology R&D Shanghai Corp
Priority date: 2017-09-28
Filing date: 2017-09-28
Publication date: 2020-11-03
Anticipated expiration: 2037-09-28
Also published as: CN109585450A

Abstract

A memory and a forming method thereof are provided, wherein the forming method comprises the following steps: a substrate comprising a storage region; the memory grid is positioned on the storage region substrate, and the thickness of the memory grid is larger than that of the selection grid; and the second source-drain doped region is positioned between the selection grid and the storage grid. The thickness of the storage grid electrode is larger, the area of the side wall of the storage grid electrode can be increased, so that the breakdown probability of a dielectric layer between the storage grid electrode and the second source drain plug is increased, the programming voltage of the formed memory is further reduced, and the power consumption of the memory is reduced; the thickness of the selective grid is small, the area of the side wall of the selective grid can be reduced, the breakdown probability of a dielectric layer between the selective grid and the first source drain plug is reduced, and the performance of formed storage is improved.

Description

Memory and forming method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a memory and a forming method thereof

OTP (One Time Programmable) memory belongs to a nonvolatile memory, and only allows One Time programming in use, thereby having high data reliability. At present, OTP memories are mainly used for initial information and data such as key saving. There are two basic types of OTP memory cells, fuse type and antifuse type. The antifuse OTP memory has important applications in the memory field due to its advantages of high radiation resistance, high security, high and low temperature resistance, etc.

The basic structure of an antifuse OTP memory cell is formed by sandwiching a dielectric layer with a high dielectric constant between two conductive electrodes. When not programmed, the anti-fuse OTP memory is equivalent to a capacitor, the impedance between the upper and lower electrode plates is very high, and the circuit is in an open circuit state. A programming high voltage is applied to the two polar plates, a dielectric layer between the two polar plates is broken down, and a path is formed between the two polar plates, so that the logic '0' and '1' states are stored before and after the programming of the antifuse.

However, the prior art OTP memories have poor performance.

Disclosure of Invention

The invention provides a memory and a forming method thereof, which can improve the performance of the memory.

To solve the above problems, the present invention provides a memory, including: a substrate comprising a storage region; the memory grid is positioned on the storage region substrate, and the thickness of the memory grid is larger than that of the selection grid; the first source-drain doped region and the second source-drain doped region are positioned in the storage region substrate on two sides of the selection grid, and the second source-drain doped region is positioned between the selection grid and the storage grid; the dielectric layer is positioned on the storage region substrate and covers the side wall of the storage grid and the side wall of the selection grid; the first source drain plug is positioned in the dielectric layer and electrically connected with the first source drain doped region; and the second source-drain plug is positioned in the dielectric layer, the dielectric layer is arranged between the second source-drain plug and the storage grid, and the second source-drain plug is electrically connected with the second source-drain doped region.

Optionally, the method further includes: the dummy gate is positioned on the substrate between the selection gate and the second source-drain doped region, and the width of the dummy gate is greater than or equal to that of the selection gate and less than that of the storage gate; and the third source-drain doped region is positioned in the substrate between the dummy gate and the selection gate.

Optionally, the method further includes: a third source drain plug located in the dielectric layer, the third source drain plug being connected to the third source drain doped region; and the connecting line is positioned on the dielectric layer and is connected with the third source-drain plug and the second source-drain plug.

Optionally, the thickness of the dummy gate is less than or equal to the thickness of the select gate.

Optionally, the width of the storage gate is greater than the width of the selection gate.

Optionally, the width of the storage gate is greater than 0.1 μm; the width of the selection gate is less than 0.05 μm.

Optionally, the method further includes: and the protective layer is positioned on the selection grid and the storage grid, the dielectric layer covers the side wall of the protective layer, and the protective layer is made of silicon nitride, silicon oxide or silicon oxynitride.

Optionally, the number of the storage regions is multiple, and the substrate further includes an isolation region located between adjacent storage regions; the memory includes: an isolation gate on the isolation region substrate.

The technical scheme of the invention also provides a forming method of the memory, which comprises the following steps: providing a substrate, wherein the substrate comprises a storage area; forming a dielectric layer, a discrete selection grid and a storage grid, a first source-drain doped region and a second source-drain doped region, wherein the dielectric layer is positioned on the substrate, the selection grid and the storage grid are positioned on the storage region substrate, the dielectric layer covers the storage grid and the side wall of the selection grid, the thickness of the storage grid is greater than that of the selection grid, the first source-drain doped region and the second source-drain doped region are respectively positioned in the storage region substrate at two sides of the selection grid, and the second source-drain doped region is positioned between the selection grid and the storage grid; forming a first source drain plug in the dielectric layer, wherein the first source drain plug is electrically connected with the first source drain doped region; and forming a second source drain plug in the dielectric layer, wherein the dielectric layer is arranged between the second source drain plug and the storage grid, and the second source drain plug is electrically connected with the second source drain doped region.

Optionally, the step of forming the storage gate and the selection gate includes: forming a discrete initial storage gate and an initial selection gate on the storage region substrate, wherein the width of the initial storage gate is greater than that of the initial selection gate; and performing gate etching on the initial storage gate and the initial selection gate, removing part of the initial storage gate to form a storage gate, removing part of the initial selection gate to form a selection gate, wherein the thickness of the removed initial storage gate is less than that of the removed initial selection gate.

Optionally, the step of forming the storage gate and the selection gate includes: forming a discrete initial storage grid and an initial selection grid on the storage region substrate, performing first etching on the initial storage grid, and removing the initial storage grid with partial thickness to form a storage grid; and carrying out second etching on the initial selection grid, and removing part of the initial selection grid to form the selection grid.

Optionally, the dielectric layer includes: the isolation structure covers the side wall of the selection grid and the side wall of the storage grid; the first dielectric layer is positioned on the selection grid, the storage grid and the isolation structure; the step of forming the dielectric layer comprises: before removing part of the initial selection grid and part of the initial selection grid, forming an isolation structure, wherein the isolation structure covers the initial selection grid and the initial storage grid side wall; after removing the initial selection grid with partial thickness and the initial selection grid with partial thickness, forming a first dielectric layer on the initial selection grid, the initial storage grid and the isolation structure; after removing part of the thickness of the initial storage grid electrode, forming a second groove in the isolation structure; after removing part of the thickness of the initial select gate, a first recess is formed in the isolation structure.

Optionally, before forming the first dielectric layer, the method further includes: and forming a protective layer in the second groove and the first groove.

Optionally, the step of forming the first source-drain plug and the second source-drain plug includes: etching the dielectric layer to form a storage contact hole and a selection contact hole which penetrate through the dielectric layer, wherein the bottom of the storage contact hole is exposed out of the second source-drain doped region, and the bottom of the selection contact hole is exposed out of the first source-drain doped region; forming a first source drain plug in the selective contact hole; and forming a second source drain plug in the storage contact hole.

Optionally, the step of forming the initial storage gate, the initial selection gate and the isolation structure includes: forming a first gate layer on the substrate; patterning the first gate layer to form a sacrificial storage gate and a sacrificial selection gate; forming an isolation structure covering the side wall of the sacrificial storage grid and the side wall of the sacrificial selection grid; removing the sacrificial selection grid and forming a first opening in the isolation structure; removing the sacrificial storage grid electrode and forming a second opening in the isolation structure; forming an initial selection gate in the first opening; and forming an initial storage gate in the second opening.

Optionally, the isolation structure includes: the side wall covers the side walls of the storage grid and the selection grid; the second dielectric layer is positioned on the substrate and covers the side wall of the side wall; the step of forming the isolation structure comprises: forming a side wall covering the side wall of the sacrificial storage grid and the side wall of the sacrificial selection grid; forming a second dielectric layer on the substrate, wherein the second dielectric layer covers the side wall of the side wall; and after the side wall is formed and before the second dielectric layer is formed, forming the first source drain doped region and the second source drain doped region.

Optionally, the step of forming the initial storage gate and the initial selection gate includes: forming a second gate layer on the substrate; patterning the second gate layer to form the initial storage gate and the initial selection gate; and after the initial storage grid and the initial selection grid are formed, forming the first source-drain doped region and the second source-drain doped region.

Optionally, the widths of the initial storage gate and the initial selection gate are the same; the thickness of the initial storage grid electrode removed by the first etching is a first thickness, the thickness of the initial selection grid electrode removed by the second etching is a second thickness, and the first thickness is larger than the second thickness.

Optionally, the method further includes: and forming a dummy gate and a third source drain doped region, wherein the dummy gate is positioned on the storage region substrate, the dummy gate is positioned between the second source drain doped region and the select gate, the width of the dummy gate is greater than that of the select gate and smaller than that of the storage gate, the third source drain doped region is positioned in the storage region substrate between the select gate and the dummy gate, and the third source drain doped region is electrically connected with the second source drain doped region.

Optionally, the dielectric layer further covers the sidewall of the dummy gate; the forming method further includes: forming a third source drain plug connected with the third source drain doping region in the dielectric layer; and forming a connecting line on the dielectric layer, wherein the connecting line is connected with the third source-drain plug and the second source-drain plug.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the memory provided by the technical scheme of the invention, the thickness of the storage grid is greater than that of the selection grid. The memory grid is large in thickness and capable of increasing the area of the side wall of the memory grid, when the dielectric layer in any area of the side wall of the memory grid is broken down, the capacitor formed by the memory grid, the first source drain plug and the dielectric layer becomes a low-resistance state, so that the memory can be programmed, namely the breakdown probability of the dielectric layer between the memory grid and the second source drain plug can be increased due to the fact that the thickness of the memory grid is large, the programming voltage of the formed memory is reduced, and the power consumption of the memory is reduced. The thickness of the selective grid is small, the area of the side wall of the selective grid can be reduced, the breakdown probability of a dielectric layer between the selective grid and the first source drain plug is reduced, and the performance of the formed memory is improved.

Further, a dummy gate is arranged on the storage region substrate, the thickness of the dummy gate is smaller than or equal to that of the select gate, the area of the side wall of the dummy gate is smaller, the probability that a dielectric layer between the dummy gate and the third source drain plug is broken down is smaller, and the probability that the dielectric layer between the dummy gate and the second source drain plug is broken down is smaller, so that the performance of the formed storage can be improved.

In the forming method of the memory provided by the technical scheme of the invention, the thickness of the storage grid electrode is larger than that of the selection grid electrode. The thickness of the storage grid electrode is larger, the area of the side wall of the storage grid electrode can be increased, so that the breakdown probability of a dielectric layer between the storage grid electrode and the second source drain plug is increased, the programming voltage of the formed memory is further reduced, and the power consumption of the memory is reduced; the thickness of the selective grid is small, the area of the side wall of the selective grid can be reduced, the breakdown probability of a dielectric layer between the selective grid and the first source drain plug is reduced, and the performance of the formed memory is improved.

Further, the width of the initial storage gate is greater than the width of the initial selection gate. In the process of etching the initial storage grid electrode and the initial selection grid electrode, polymerization is formed on the surface of the initial storage grid electrode, and the polymer is easy to reduce the etching rate of the initial storage grid electrode, so that the etching rate of the initial storage grid electrode is smaller than that of the initial selection grid electrode, and the thickness of the storage grid electrode is larger than that of the selection grid electrode. The width of the initial storage grid is larger than that of the initial selection grid, and the initial storage grid and the initial selection grid can be etched through the same process, so that the selection grid and the storage grid are formed. Therefore, the forming method can simplify the process flow.

Further, the forming method further includes: and forming a dummy gate on the substrate, wherein the dummy gate is positioned between the storage gate and the selection gate, and the width of the dummy gate is greater than or equal to that of the selection gate and is less than that of the storage gate. In the process of forming the dummy gate, the storage gate and the selection gate, the dummy gate can reduce the size distortion of the storage gate and the selection gate caused by the diffraction and refraction of light in the exposure process, and improve the performance of the formed memory.

Further, the initial storage grid and the initial selection grid are respectively etched through the first etching and the second etching, so that the thickness of the storage grid is larger than that of the selection grid. The widths of the initial storage grid and the initial selection grid are the same, so that the patterns in the photomask used in the process of forming the initial storage grid and the initial selection grid are the same, the distortion of an exposure pattern caused by the mutual influence of the patterns in the photomask in the photoetching process can be reduced, the widths of the initial storage grid and the initial selection grid can be accurately controlled, the widths of the storage grid and the selection grid are increased, and the performance of the formed memory is improved.

Drawings

FIG. 1 is a schematic diagram of a memory structure;

FIGS. 2 to 12 are schematic structural diagrams illustrating steps of a memory forming method according to an embodiment of the invention;

fig. 13 to 16 are schematic structural diagrams of steps of another embodiment of a memory forming method according to the present invention.

Detailed Description

The prior art semiconductor structures have a number of problems, such as: the performance of the memory is poor.

The reason for the poor performance of the prior art memory is now analyzed in connection with a memory:

fig. 1 is a schematic structural diagram of a memory.

Referring to fig. 1, the memory includes: the substrate 100 comprises an isolation region A and storage regions B positioned on two sides of the isolation region A; an isolation gate 121 on the isolation region a substrate 100; a select gate 110 and a storage gate 120 respectively located on the storage region B substrate 100; a first source-drain doped region 113 and a second source-drain doped region 123 respectively located in the substrate 100 at two sides of the select gate 110; a dielectric layer 130 covering the select gate 110, the storage gate 120, the isolation gate 121, the first source-drain doped region 113 and the second source-drain doped region 123; a first source-drain plug 112 and a second source-drain plug 122 located in the dielectric layer 130, wherein the first source-drain plug 112 is connected to the first source-drain doped region 113, and the second source-drain plug 122 is connected to the second source-drain doped region 123; and the isolation plugs are positioned in the dielectric layers at two sides of the isolation gate 121.

The storage gate 120, the second source-drain plug 122, and the dielectric layer 130 between the storage gate 120 and the second source-drain plug 122 constitute a capacitor. In the process of programming the memory, a larger programming voltage is connected between the storage gate 120 and the second source-drain plug 122, so that the dielectric layer 130 between the storage gate 120 and the second source-drain plug 122 can be broken down, the capacitor is in a low-resistance state, and the storage gate 120 and the second source-drain plug 122 are conducted, thereby programming the memory.

In order to reduce the influence of diffraction and interference of light on exposure during the formation of the storage gate 120, the selection gate 110 and the isolation gate 121, so that the widths of the storage gate 120, the selection gate 110 and the isolation gate 121 are easily controlled, the widths of the storage gate 120, the selection gate 110 and the isolation gate 121 are equal.

The steps of forming the select gate 110, the storage gate 120 and the isolation gate 121 include: forming a gate layer on the substrate 100; forming a patterned photoresist on the gate layer; and etching the gate layer by taking the photoresist as a mask to form a selection gate 110, a storage gate 120 and an isolation gate 121. In the exposure process of forming the photoresist, the interference and scattering effect of the patterns in the photomask on light is reduced, so that the distortion of the patterns in the photoresist is reduced, the widths of the formed selection gate 110, the storage gate 120 and the isolation gate 121 are easy to control, and the patterns in the photomask used for forming the photoresist are the same, so that the patterns in the photoresist are the same. Because the patterns in the photoresist are the same, when the gate layer is etched, the patterns in the photoresist have the same blocking effect on etching reactants, so that the etching rates of the gate layer are the same, and the widths and thicknesses of the formed selection gate 110, the storage gate 120 and the isolation gate 121 are the same.

If the thicknesses of the select gate 110, the storage gate 120 and the isolation gate 121 are too small, the area of the side wall of the storage gate 120 is small, so that the breakdown probability of the dielectric layer 130 between the storage gate 120 and the second source-drain plug 122 is small, the breakdown voltage is high, the programming voltage of the memory is high, and the energy consumption of the memory is large; if the thicknesses of the select gate 110, the storage gate 120 and the isolation gate 121 are too large, the area of the sidewall of the select gate is large, which results in a large probability of breakdown of the dielectric layer 130 between the select gate 110 and the first source-drain plug 112, and a large probability of breakdown of the dielectric layer 130 between the select gate 110 and the second source-drain plug 122, thereby resulting in poor stability of the memory.

To solve the technical problem, the present invention provides a semiconductor structure, comprising: a substrate comprising a storage region; the memory grid is positioned on the storage region substrate, and the thickness of the memory grid is larger than that of the selection grid; and the second source-drain doped region is positioned between the selection grid and the storage grid. The thickness of the storage grid electrode is larger, the area of the side wall of the storage grid electrode can be increased, so that the breakdown probability of a dielectric layer between the storage grid electrode and the second source drain plug is increased, the programming voltage of the formed memory is further reduced, and the power consumption of the memory is reduced; the thickness of the selective grid is small, the area of the side wall of the selective grid can be reduced, the breakdown probability of a dielectric layer between the selective grid and the first source drain plug is reduced, and the performance of formed storage is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 2 to 10 are schematic structural diagrams of steps of a memory forming method according to an embodiment of the invention.

In this embodiment, an OTP (One Time Programmable) memory is formed as the memory.

Referring to fig. 2, a substrate 200 is provided, the substrate 200 including a memory region I.

The memory area I is used to form a memory cell of the memory.

In this embodiment, the substrate 200 further has a fin portion (not shown). In other embodiments, the fin portion may not be provided on the substrate.

In this embodiment, the substrate 200 includes a plurality of memory regions I, and an isolation region II is provided between adjacent memory regions I.

The isolation region II is used for realizing isolation between adjacent storage regions I.

The forming method further includes: memory well regions are formed in the memory region I substrate 200 and isolation well regions are formed in the isolation regions II.

The device well region has first ions therein and the isolation well region has second ions therein.

In this embodiment, the memory cells formed by the adjacent storage regions I are electrically connected to each other, and the first ions and the second ions have the same conductivity type. In other embodiments, memory cells formed by adjacent storage regions are not connected to each other, and the first ions are of opposite conductivity type to the second ions.

And forming a dielectric layer, a discrete selection grid and a storage grid, a first source-drain doped region and a second source-drain doped region subsequently, wherein the dielectric layer is positioned on the substrate 200, the selection grid and the storage grid are positioned on the storage region I substrate 200, the dielectric layer covers the storage grid and the side wall of the selection grid, the thickness of the storage grid is greater than that of the selection grid, the first source-drain doped region and the second source-drain doped region are respectively positioned in the storage region I substrate 200 at two sides of the selection grid, and the second source-drain doped region is positioned between the selection grid and the storage grid.

The first source drain plug is used for realizing the electric connection between the first source drain doped region and an external circuit; the second source-drain plug, the storage grid and the dielectric layer between the second source-drain plug and the storage grid form an anti-fuse device, and the second source-drain plug and the storage grid respectively form two electrodes of the anti-fuse device.

The thickness of the select gate is the dimension of the select gate in the direction perpendicular to the surface of the substrate 200, and the thickness of the memory gate is the dimension of the memory gate in the direction perpendicular to the surface of the substrate 200.

In this embodiment, the process of forming the select gate and the storage gate is a gate last process. The dielectric layer includes: the isolation structure covers the sidewalls of the storage gate and the selection gate; and the first dielectric layer is positioned on the storage grid electrode, the selection grid electrode and the isolation structure.

In this embodiment, the memory further includes: an isolation gate on the isolation region II substrate 200; the dummy gate is positioned on the substrate 200 of the storage region I, the dummy gate is positioned between the selection gate and the storage gate, the width of the dummy gate is greater than or equal to that of the selection gate and is smaller than that of the storage gate, and the second source-drain doped region is positioned between the dummy gate and the storage gate; and a third source-drain doped region in the substrate 200 between the dummy gate and the select gate, the third source-drain doped region being electrically connected to the second source-drain doped region. In other embodiments, the memory may also not include one or both of the isolation gate and dummy gate. The memory may further not include the third source drain doped region.

The thickness of the dummy gate is the dimension of the dummy gate along the direction vertical to the surface of the substrate.

In this embodiment, the steps of forming the isolation structure, the select gate, the storage gate, the isolation gate, the dummy gate, and the dielectric layer are as shown in fig. 3 to 6.

And subsequently forming a discrete initial storage gate and an initial selection gate on the storage region I substrate 200, wherein the width of the initial storage gate is greater than that of the initial selection gate.

The width of the initial storage grid electrode is the size of the initial storage grid electrode in the direction vertical to the side wall of the initial storage grid electrode; the width of the initial select gate is the dimension of the select gate in a direction perpendicular to the initial select gate sidewalls.

In this embodiment, the steps of forming the initial storage gate, the initial selection gate and the isolation structure are as shown in fig. 3 to 5.

Referring to fig. 3, a first gate layer is formed on the substrate 200; the first gate layer is patterned to form a sacrificial memory gate 230 and a sacrificial select gate 210.

The first gate layer is used to form a sacrificial memory gate 230 and a sacrificial select gate 210; the sacrificial storage gate 230 is used to provide a space for the subsequent formation of an initial storage gate 231; the sacrificial select gates 210 are used to provide space for the subsequent formation of initial select gates 211.

In this embodiment, after the first gate layer is patterned, a sacrificial dummy gate 220 is further formed on the substrate 200. In other embodiments, the dummy gate is not formed, and the sacrificial dummy gate may not be formed after patterning.

The sacrificial dummy gate 220 is used to reduce the influence of the stored mask pattern on the size of the select gate 212 during the subsequent exposure process.

In this embodiment, the step of patterning includes: providing a photomask, wherein the photomask comprises a storage photomask graph, a selection photomask graph and a pseudo photomask graph, the storage photomask graph corresponds to the sacrifice storage grid 230, the selection photomask graph corresponds to the sacrifice selection grid 210, and the pseudo photomask graph corresponds to the sacrifice pseudo grid 220; forming an initial photoresist on the first gate layer; exposing the initial photoresist through the photomask to form photoresist; and etching the first gate layer by taking the photoresist as a mask.

In this embodiment, the width of the victim memory gate 230 is greater than the width of the victim select gate 210. The width of the sacrificial dummy gate 220 is equal to the width of the sacrificial select gate 210. In other embodiments, the width of the sacrificial dummy gate may be greater than the width of the sacrificial select gate and less than the width of the sacrificial storage gate.

The width of the sacrificial storage gate 230 is the dimension of the sacrificial storage gate 230 in the direction perpendicular to the sidewalls of the sacrificial storage gate 230; the width of the sacrificial select gate 210 is the dimension of the select gate 210 in a direction perpendicular to the sidewalls of the sacrificial select gate 210; the width of the sacrificial dummy gate 220 is the dimension of the sacrificial dummy gate 220 in the direction perpendicular to the sidewalls of the sacrificial dummy gate 220.

If the width of the sacrificial storage gate 230 is too small, it is not favorable for reducing the etching rate of the sacrificial storage gate 230 in the subsequent gate etching process, and thus it is not favorable for increasing the thickness of the post-storage gate 232, and further it is not favorable for reducing the programming voltage of the memory. In this embodiment, the width of the storage gate 232 is greater than 0.1 μm.

If the width of the sacrificial select gate 210 is too large, it is not favorable to increase the etching rate of the sacrificial select gate 210 in the subsequent gate etching process, and it is not favorable to decrease the thickness of the select gate 212, so that the dielectric layer between the subsequent select gate 212 and the first source-drain plug or the third source-drain plug is easily broken down, thereby affecting the stability of the memory. Specifically, in this embodiment, the width of the sacrificial select gate 210 is less than 0.05 μm.

Note that, if the width of the sacrificial dummy gate 220 is equal to the width of the sacrificial select gate 210, the width of the memory mask pattern is equal to the width of the select mask pattern. During the exposure process, the dummy reticle pattern can reduce the influence of the storage reticle pattern on the size of the sacrificial select gate 210. The width of the dummy sacrificial gate 220 is equal to the width of the sacrificial select gate 210, so that the distortion of the pattern in the photoresist corresponding to the select mask pattern can be reduced, and the width of the select gate 212 can be precisely controlled.

In addition, the width of the sacrificed memory gate 230 is greater than the width of the sacrificed select gate 210, and the width of the memory mask pattern is greater than the width of the select mask pattern. The width of the storage mask pattern is large, and the derivation and interference of the storage mask pattern to light is small in the exposure process, so that the pattern distortion in the photoresist corresponding to the storage mask pattern is not easily caused, and the width precision of the formed sacrificial memory gate 230 can be improved.

Subsequently forming an isolation structure covering the sidewalls of the sacrificial storage gate 230 and the sidewalls of the sacrificial selection gate 210; and forming a first source-drain doped region and a second source-drain doped region in the storage region I substrate 200, wherein the second source-drain doped region is positioned between the sacrificial selection gate and the sacrificial storage gate.

In this embodiment, the isolation structure includes: a sidewall covering sidewalls of the sacrificial storage gate 210 and the sacrificial select gate 230; and a second dielectric layer located on the substrate 200, wherein the second dielectric layer 252 covers the sidewall.

Specifically, in this embodiment, the steps of forming the isolation structure, the first source-drain doped region and the second source-drain doped region are as shown in fig. 3 and 4.

With continued reference to fig. 3, sidewalls 251 are formed overlying the sacrificial memory gates 230 and the sacrificial select gates 210.

The side walls 251 are used for protecting the storage gate 232 and the sacrificial gate when the dielectric layer is etched subsequently.

The step of forming the side wall 251 includes: forming sidewall layers on sidewalls and tops of the sacrificial memory gate 230, the sacrificial select gate 210, the sacrificial dummy gate 220 and the sacrificial isolation gate 240, and the substrate 200; and removing the top of the sacrificial storage gate 230, the sacrificial select gate 210, the sacrificial dummy gate 220 and the sacrificial isolation gate 240 and the sidewall layer on the substrate 200 to form a sidewall 251.

The side wall 251 is made of a material different from that of the second dielectric layer to be formed later, and is made of a material different from that of the first dielectric layer to be formed later.

In this embodiment, the sidewall 251 is made of silicon nitride. In other embodiments, the material of the sidewall may also be silicon oxynitride or silicon oxide.

Referring to fig. 4, after the side walls 251 are formed, a first source-drain doped region 281 and a second source-drain doped region 283 are respectively formed in the storage region I substrate 200 at two sides of the select gate 212, where the second source-drain doped region 283 is located between the select gate 212 and the storage gate 232.

In this embodiment, the substrate 200 of the storage region I further has a sacrificial dummy gate 220 thereon. The forming method further includes: a third source drain doped region 282 is formed in the storage region I substrate 200 between the sacrificial memory gate 230 and the sacrificial dummy gate 220.

In this embodiment, the steps of forming the third source/drain doped region 282, the second source/drain doped region 283 and the first source/drain doped region 281 include: forming a photoresist covering the isolation region II substrate 200 and the sacrificial isolation gate 240; and performing ion implantation on the substrate 200 by using the photoresist, the sacrificial select gate 210, the sacrificial storage gate 230 and the sacrificial dummy gate 220 as masks, and implanting source and drain ions into the substrate 200 to form the first source and drain doped region 281, the second source and drain doped region 283 and the third source and drain doped region 282.

In other embodiments, the step of forming the third source-drain doped region, the second source-drain doped region, and the first source-drain doped region includes: forming photoresist covering the isolation region substrate and the sacrificial isolation gate; etching the substrate by taking the photoresist, the sacrificial selection grid, the sacrificial storage grid and the sacrificial dummy grid as masks, respectively forming a first groove and a third groove in the substrate at two sides of the selection grid, wherein the third groove is positioned between the dummy grid and the selection grid, and a second groove is formed in the substrate between the dummy grid and the storage grid; a first source drain doped region is formed in the first groove; forming a second source drain doped region in the second groove; and forming a third source-drain doped region in the third groove.

The source and drain ions are P-type ions or N-type ions. The P-type ions include boron ions or BF₂ ⁺One or a combination of both. The N-type ions include: one or more of phosphorus ion, arsenic ion or antimony ion.

Referring to fig. 5, a second dielectric layer 252 is formed on the substrate 200, wherein the second dielectric layer 252 covers sidewalls of the sacrificial memory gates 230 and the sacrificial select gates 210 and exposes tops of the sacrificial memory gates 230 and the sacrificial select gates 210.

The second dielectric layer 252 is used for electrical isolation between the subsequently formed storage gate 232 and the sacrificial gate.

In this embodiment, the second dielectric layer 252 also covers sidewalls of the sacrificial dummy gate 220 and the sacrificial isolation gate 240.

In this embodiment, the second dielectric layer 252 is made of silicon oxide, silicon oxynitride, or a low-k dielectric material. The dielectric constant of the low-k dielectric material is less than 3.9.

The step of forming the second dielectric layer 252 includes: forming an initial second dielectric layer on the substrate 200, the sacrificial storage gate 230, the sacrificial select gate 210, the sacrificial isolation gate 240 and the sacrificial dummy gate 220; and performing first planarization treatment on the initial second dielectric layer, and removing the initial second dielectric layer on the sacrificial storage gate 230, the sacrificial selection gate 210, the sacrificial isolation gate 240 and the sacrificial dummy gate 220 to form a second dielectric layer 252.

In this embodiment, the process of forming the initial second dielectric layer includes a fluid chemical vapor deposition process. The gap filling performance of the initial second dielectric layer formed by the fluid chemical vapor deposition process is good, thereby increasing the isolation performance of the second dielectric layer 252. In other embodiments, the process of forming the initial second dielectric layer comprises a high aspect ratio deposition process.

The first planarization treatment process comprises chemical mechanical polishing.

The isolation structure includes the second dielectric layer 252 and the sidewall spacers 251.

Referring to fig. 6, the sacrificial select gate 210 is removed, and a first opening is formed in the isolation structure; removing the sacrificial storage gate 230, and forming a second opening in the isolation structure; forming an initial storage gate 231 in the second opening; an initial select gate 211 is formed in the first opening.

The second opening is used to receive the initial storage gate 231, and the first opening is used to receive the initial selection gate 211. The initial storage gate 231 is used for the subsequent formation of the storage gate 232, and the initial selection gate 211 is used for the subsequent formation of the selection gate 212.

The forming method further includes: removing the sacrificial dummy gate 220, and forming a third opening in the isolation structure; removing the sacrificial isolation gate 240, and forming a fourth opening in the isolation structure; forming an initial dummy gate 221 in the third opening; an initial isolation gate 241 is formed in the fourth opening.

The steps of forming the initial select gate 211, the initial storage gate 231, the initial isolation gate 241 and the initial dummy gate 221 include: forming metal layers in the first opening, the second opening, the third opening and the fourth opening and on the isolation structure; and carrying out second planarization treatment on the metal layer, and removing the metal layer on the isolation structure.

The metal layer is made of Al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.

The second planarization process includes chemical mechanical polishing.

Note that the second planarization process planarizes the metal layer surface, so that the thicknesses of the storage gate 232, the select gate 212, the dummy gate 222, and the isolation gate 242 are the same.

The thickness of the storage gate 232 is the dimension of the storage gate 232 in the direction perpendicular to the surface of the substrate 200; the thickness of the select gate 212 is the dimension of the select gate 212 in the direction perpendicular to the surface of the substrate 200; the thickness of the dummy gate 222 is the dimension of the dummy gate 222 along the direction vertical to the surface of the substrate 200; the thickness of the isolation gate 242 is the dimension of the isolation gate 242 in the direction perpendicular to the surface of the substrate 200.

Referring to fig. 7, gate etching is performed on the initial storage gate 231 and the initial selection gate 211 to remove a portion of the thickness of the initial storage gate 231 and form a storage gate 232, and remove a portion of the thickness of the initial selection gate 211 and form a selection gate 212, where the thickness of the removed initial storage gate 231 is smaller than the thickness of the removed initial selection gate 211.

The gate etch is used to make the thickness of the storage gate 232 greater than the thickness of the select gate 212. The larger thickness of the storage gate 232 can increase the area of the side wall of the storage gate 232, so that the breakdown probability of a dielectric layer between the storage gate 232 and a subsequently formed second source-drain plug is increased, the programming voltage of the formed memory is further reduced, and the power consumption of the memory is reduced; the thickness of the select gate 212 is small, and the area of the side wall of the select gate 212 can be reduced, so that the breakdown probability of a dielectric layer between the select gate 212 and a first source-drain plug formed later is reduced, the breakdown probability of a dielectric layer between the select gate 212 and a second source-drain plug is reduced, and the performance of the formed memory is improved.

In this embodiment, the width of the initial storage gate 231 is greater than the width of the initial selection gate 211. In the process of performing gate etching on the initial storage gate 231 and the initial selection gate 211, the surface of the initial storage gate 231 is more polymerized, and the polymer is easy to reduce the etching rate of the initial storage gate 231, so that the etching rate of the initial storage gate 231 is less than that of the initial selection gate 211. Therefore, the formation method can make the thickness of the storage gate 232 larger than the width of the selection gate 212. The width of the initial storage gate 231 is greater than that of the initial selection gate 211, and the initial storage gate 231 and the initial selection gate 211 can be etched through the same process, so as to form the selection gate 212 and the storage gate 232. Therefore, the forming method can simplify the process flow.

In this embodiment, after the isolation structure is formed, gate etching is performed on the initial storage gate 231 and the initial selection gate 211. After removing a part of the thickness of the initial storage gate 231, forming a second groove 293 in the isolation structure; after removing a partial thickness of the initial select gate 211, a first recess 291 is formed in the isolation structure.

In this embodiment, in the gate etching process, gate etching is further performed on the initial isolation gate 241 and the initial dummy gate 221, the dummy gate 222 with a partial thickness is removed to form a third groove 292, and the initial isolation gate 241 with a partial thickness is removed to form a fourth groove 294 in the isolation structure.

In this embodiment, the gate etching process includes: and (5) dry etching process. The dry etching process has good line width control, and can easily control the thickness of the storage gate 232. In other embodiments, the gate etching process may also be a wet etching process or a combination of a dry etching process and a wet etching process.

If the thicknesses of the initial storage gate 231 and the initial selection gate 211 are too large to be removed, the thicknesses of the storage gate 232 and the selection gate 212 are too small, and the thickness of the storage gate 232 is too small, which is not beneficial to increasing the area of the side wall of the storage gate 232 and further is not beneficial to reducing the programming voltage of the memory; if the thicknesses of the initial storage gate 231 and the initial selection gate 211 which are removed are too small, the thickness of the storage gate 232 is easily too large, so that the dielectric layer between the storage gate 232 and the storage plug or the third source drain plug 262 is easily broken down, and the performance of the memory is reduced. Specifically, in the embodiment, the thickness of the removed initial storage gate 231 is 15nm to 18 nm; the thickness of the removed initial selection gate 211 is 25nm to 31 nm.

Referring to fig. 8, a protective layer 253 is formed in the first groove 291 (shown in fig. 7) and the second groove 293 (shown in fig. 7).

The protective layer 253 is used for protecting the storage gate 232 and the selection gate 212 in the subsequent process of etching the dielectric layer, so that the loss of the storage gate 232 and the selection gate 212 is reduced.

The material of the protection layer 253 is different from that of the dielectric layer.

In this embodiment, the isolation structure is made of silicon oxide. The material of the protection layer 253 is silicon nitride or silicon oxynitride. In other embodiments, the isolation structure is a low-k dielectric material, and the material of the protective layer may be silicon oxide.

In this embodiment, the fourth groove 294 and the third groove 292 also have the protection layer 253 therein.

The step of forming the protective layer 253 includes: forming an initial protective layer in the first, second, fourth, and

third grooves

291, 293, 294, and 292, and on the isolation structure; and performing third planarization treatment on the initial protection layer, and removing the initial protection layer on the isolation structure to form a protection layer 253.

The process for forming the initial protection layer comprises a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

The third planarization process includes chemical mechanical polishing.

It should be noted that, in other embodiments, the protective layer may not be formed.

Referring to fig. 9, a first dielectric layer 260 is formed on the memory gate 232, the select gate 212 and the isolation structure.

The first dielectric layer 260 is used for realizing electrical isolation among the subsequently formed second source-drain plug, the second gate plug, the first source-drain plug and the first gate plug.

In this embodiment, the first dielectric layer 260 is located on the protective layer 253.

In this embodiment, the first dielectric layer 260 is made of silicon oxide. In other embodiments, the material of the first dielectric layer may also be a low-k dielectric material or an organic dielectric material.

In this embodiment, the process of forming the first dielectric layer 260 includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In other embodiments, the material of the first dielectric layer is an organic dielectric material, and the process for forming the first dielectric layer includes a spin-on process.

Referring to fig. 10 to 12, fig. 10 is a schematic diagram of subsequent steps based on fig. 9, fig. 12 (the dielectric layer and the protective layer are not shown in fig. 12) is a top view of fig. 10, fig. 10 is a cross-sectional view of fig. 12 along a cutting line 1-2, fig. 11 is a cross-sectional view of fig. 12 along a cutting line 3-4, a first source drain plug 261 and a second source drain plug 263 are formed in the dielectric layer, the first source drain plug 261 is electrically connected with the first source drain doped region 281, and the second source drain plug 263 is electrically connected with the second source drain doped region 283.

The first source/drain plug 261 is used to electrically connect the first source/drain doped region 281 with an external circuit. The second source-drain plug 263, the storage gate 232, and the dielectric layer between the second source-drain plug 263 and the storage gate 232 form a capacitor. When the memory is programmed, a large voltage difference exists between the second source-drain plug 263 and the storage gate 232, so that the dielectric layer between the second source-drain plug 263 and the storage gate 232 is broken down, the resistance of the dielectric layer between the second source-drain plug 263 and the storage gate 232 is reduced, and further programming is realized.

In this embodiment, the forming method further includes: forming a third source drain plug 262 in the dielectric layer, wherein the third source drain plug 262 is electrically connected with the third source drain doped region 282; an isolation plug 264 is formed in the dielectric layer, and the isolation plug 264 connects the substrate 200 between the isolation gate 242 and the storage gate 232.

The third source/drain plug 262 is used for electrically connecting the second source/drain doped region 283 and the third source/drain doped region 282 with a subsequently formed connection line.

The steps of forming the first source-drain plug 261, the second source-drain plug 263, the third source-drain plug 262 and the isolation plug 264 include: etching the dielectric layer, and respectively forming a selection contact hole, a storage contact hole, a pseudo contact hole and an isolation contact hole in the dielectric layer; forming plug metal layers in the selection contact hole, the storage contact hole, the dummy contact hole and the isolation contact hole and on the dielectric layer; and removing the plug metal layer on the dielectric layer.

The isolation plugs 264 are used for improving the uniformity of the process for etching the dielectric layer, so that the precision of the sizes of the selection contact hole, the storage contact hole and the dummy contact hole is ensured, and the precision of the sizes of the first source drain plug 261, the second source drain plug 263 and the third source drain plug 262 is further improved.

It should be noted that, in this embodiment, the select contact hole, the storage contact hole, the dummy contact hole, and the isolation contact hole are formed by a self-aligned etching process. In the process of etching the dielectric layer, the protective layer 253 can protect the storage gate 232, the selection gate 212, the isolation gate 242 and the dummy gate 222, so that the loss of the storage gate 232, the selection gate 212, the isolation gate 242 and the dummy gate 222 is reduced.

In this embodiment, the material of the first source-drain plug 261, the second source-drain plug 263, the isolation plug 264, and the third source-drain plug 262 is copper, aluminum, or tungsten.

The forming method further includes: forming a first gate plug 271 connected to the select gate 212; a second gate plug 272 connecting the storage gate 232 is formed.

The first gate plug 271 is used to electrically connect the select gate 212 to an external circuit. The second gate plug 272 is used to electrically connect the memory gate 232 to an external circuit.

In this embodiment, the material of the second gate plug 272 and the first gate plug 271 is copper, aluminum, or tungsten.

With continued reference to fig. 10 to 12, a connection line 270 is formed on the dielectric layer, and the connection line 270 connects the third source-drain plug 262 and the second source-drain plug 263.

The connecting line 270 is used to electrically connect the third source-drain plug 262 and the second source-drain plug 263, so as to electrically connect the second source-drain doped region 283 and the third source-drain doped region 282.

In this embodiment, the connecting line 270 is made of aluminum. In other embodiments, the material of the connecting line may also be copper.

The same points of the memory forming method in this embodiment as those in fig. 2 to 12 are not repeated herein, but the differences are as shown in fig. 13 to 16.

Referring to fig. 13, fig. 13 is a schematic diagram of a subsequent step based on fig. 2, in which a sacrificial memory gate 330 and a sacrificial select gate 210 are separately formed on the memory I substrate 200.

The sacrificial storage gates 330 are the same width as the sacrificial select gates 210 and the storage region I substrate 200 does not have sacrificial dummy gates 220 thereon.

The steps of forming the sacrificial memory gates 330 and the sacrificial select gates 210 include: forming a first gate layer on the substrate 200; the first gate layer is patterned to form the sacrificial memory gate 330 and the sacrificial select gate 210.

The step of patterning comprises: forming a photoresist on the first gate layer; providing a photomask, wherein the photomask is provided with a selection pattern and a storage pattern, the selection pattern corresponds to the selection grid 212, and the storage pattern corresponds to the storage grid 232; and exposing the photoresist through the photomask to form a storage exposure pattern and a selection exposure pattern in the photoresist, wherein the storage exposure pattern corresponds to the storage pattern, and the selection exposure pattern corresponds to the selection pattern.

The sacrificial memory gates 330 and the sacrificial select gates 210 have the same width, and the select pattern and the memory pattern have the same size. In the exposure process, the distortion of the storage exposure pattern and the selection exposure pattern caused by the mutual influence between the selection pattern and the storage pattern can be reduced, so that the widths of the formed sacrificial storage gate 330 and the sacrificial selection gate 210 can be accurately controlled, and further the widths of the storage gate and the selection gate which are formed subsequently can be accurately controlled.

In addition, since the widths of the sacrificial memory gate 330 and the sacrificial select gate 210 are the same, a sacrificial dummy gate does not need to be formed. Therefore, the memory has no dummy gate, so that the volume of the formed memory can be reduced, and the integration level of the memory can be improved.

Referring to fig. 14, an isolation structure is formed on the substrate 200; removing the sacrificial select gate 210, and forming a first opening in the isolation structure; removing the sacrificial storage gate 220, and forming a second opening in the isolation structure; forming an initial select gate 211 in the first opening; an initial storage gate 331 is formed in the second opening.

Referring to fig. 15, a first etching is performed on the initial storage gate 331 to remove a portion of the thickness of the initial storage gate 331 and form a storage gate 332, where the removed thickness of the initial storage gate 331 is a first thickness.

In this embodiment, the first etching is used to reduce the thickness of the initial storage gate 331, and a second groove 293 is formed in the dielectric layer.

The step of performing the first etching on the initial storage gate 331 includes: forming a first photolithography step 311 on the initial select gate 211; and performing first etching by using the first photoresist 311 as a mask.

In this embodiment, the first photoresist 311 further covers the isolation gate 241.

In this embodiment, the first etching process includes a dry etching process. The dry etching process has good line width control, and can easily control the thickness of the storage gate 332. In other embodiments, the first etching process may also be a wet etching process.

Referring to fig. 16, a second etching is performed on the initial select gate 211, and the initial select gate 211 with a partial thickness is removed to form a select gate 212, where the removed thickness of the initial select gate 211 is a second thickness, and the second thickness is smaller than the first thickness.

In this embodiment, the second etching is used to reduce the thickness of the initial select gate 211, a first groove 291 is formed in the dielectric layer, and the first groove 291 is used to subsequently accommodate a protection layer.

The step of performing a first etch on the initial select gate 211 includes: forming a second photolithography step 312 on the storage gate 332; and performing second etching by using the second photoresist 312 as a mask.

In this embodiment, the second photoresist 312 further covers the isolation gate 241.

In this embodiment, the second etching process includes a dry etching process. The dry etching process has good line width control, and can easily control the thickness of the select gate 212. In other embodiments, the second etching process may also be a wet etching process.

It should be noted that, the above embodiments are all described by taking a gate process as an example, and in other embodiments, the material of the memory gate and the select gate is polysilicon, poly germanium, or poly silicon germanium. The memory may also be formed by a gate-front process in yet another embodiment.

The same parts of this embodiment as those of the embodiment shown in fig. 2 to 12 are not repeated herein, but the differences are:

the step of forming the initial storage grid and the initial selection grid comprises the following steps: forming a second gate layer on the substrate; patterning the second gate layer to form the initial storage gate and the initial selection gate; and after the initial storage grid and the initial selection grid are formed, forming the second source-drain doped region and the first source-drain doped region.

In this embodiment, after the second dielectric layer is formed, gate etching is performed on the initial storage gate and the initial selection gate to form a storage gate and a selection gate.

In other embodiments, the initial storage gate may be subjected to a first etching process to remove a portion of the initial storage gate to form a storage gate; and carrying out second etching on the initial selection grid, and removing part of the initial selection grid to form the selection grid.

In this embodiment, after the second dielectric layer is formed, the initial select gate and the initial storage gate are removed by a portion of the thickness. In an embodiment thereof, the step of forming the select gate and the storage gate includes: and removing parts of the initial selection gate and the initial storage gate before forming the second dielectric layer. And forming a pattern layer on the substrate exposed by the selection gate and the storage gate before removing part of the initial selection gate and the initial storage gate. The pattern layer is used for protecting the substrate in the process of removing part of the initial selection gate and the initial storage gate.

With continuing reference to fig. 10 to 12, an embodiment of the present invention further provides a memory, including: a substrate 200, said substrate 200 comprising a storage area I; discrete select gates 212 and memory gates 232 on the storage I substrate 200, the thickness of the memory gates 232 being greater than the thickness of the select gates 212; a first source-drain doped region 281 and a second source-drain doped region 283 which are positioned in the storage region I substrate 200 at two sides of the select gate 212, wherein the second source-drain doped region 283 is positioned between the select gate 212 and the storage gate 232, and the second source-drain doped region 283 is electrically connected with the substrate 200 below the select gate 212; a dielectric layer located on the storage region I substrate 200, wherein the dielectric layer covers the sidewalls of the storage gate 232 and the sidewalls of the select gate 212; and the first source-drain plug 261 and the second source-drain plug 263 are positioned in the dielectric layer, the first source-drain plug 261 is connected with the first source-drain doped region 281, and the second source-drain plug 263 is connected with the second source-drain doped region 283.

In this embodiment, the memory further includes: a dummy gate 222 located on the storage region I substrate 200, the dummy gate 222 being located between the select gate 212 and the storage gate 232, the dummy gate 222 having a width greater than or equal to the width of the select gate 212 and less than the width of the storage gate 232; the second source-drain doped region 283 is located in the substrate 200 between the dummy gate 222 and the memory gate 232; a third source/drain doped region 282 in the substrate 200 between the dummy gate 222 and the select gate 212, wherein the third source/drain doped region 282 is electrically connected to the second source/drain doped region 283. In other embodiments, the memory may also not include the dummy gate (as shown in fig. 15).

The width of the dummy gate 222 is the dimension of the dummy gate 222 in the direction perpendicular to the sidewall of the dummy gate 222; the width of the select gate 212 is the dimension of the select gate 212 along the channel length direction under the select gate 212; the width of the storage gate 232 is the dimension of the storage gate 232 along the length of the channel under the storage gate 232.

In this embodiment, the memory further includes: a third source drain plug 262 in the dielectric layer, the third source drain plug 262 being connected to the third source drain doped region 282; and a connection line 270 on the dielectric layer, wherein the connection line 270 connects the third source-drain plug 262 and the second source-drain plug 263.

In this embodiment, the thickness of the dummy gate 222 is less than or equal to the thickness of the select gate 212.

In this embodiment, the width of the storage gate 232 is greater than the width of the select gate 212. In other embodiments, the width of the storage gate 232 is equal to the width of the select gate 212 (as shown in FIG. 15).

In this embodiment, the width of the storage gate 232 is greater than 0.1 μm; the width of the select gate 212 is less than 0.05 μm.

In this embodiment, the memory further includes: and the protective layer 253 is positioned on the selection gate 212 and the storage gate 232, and the material of the protective layer 253 is silicon nitride, silicon oxide or silicon oxynitride. In other embodiments, the memory may not include the protective layer.

The number of the storage regions I is multiple, and the substrate 200 further includes an isolation region II located between adjacent storage regions I; the memory includes: an isolation gate 242 on the isolation region II substrate 200.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. An antifuse OTP memory, comprising:

a substrate comprising a storage region;

the memory grid is positioned on the storage region substrate, and the thickness of the memory grid is larger than that of the selection grid;

the first source-drain doped region and the second source-drain doped region are positioned in the storage region substrate on two sides of the selection grid, and the second source-drain doped region is positioned between the selection grid and the storage grid;

the dielectric layer is positioned on the storage region substrate and covers the side wall of the storage grid and the side wall of the selection grid;

the first source drain plug is positioned in the dielectric layer and electrically connected with the first source drain doped region;

and the second source-drain plug is positioned in the dielectric layer, the dielectric layer is arranged between the second source-drain plug and the storage grid, and the second source-drain plug is electrically connected with the second source-drain doped region.

2. The antifuse OTP memory of claim 1, further comprising: the dummy gate is positioned on the substrate between the selection gate and the second source-drain doped region, and the width of the dummy gate is greater than or equal to that of the selection gate and less than that of the storage gate; and the third source-drain doped region is positioned in the substrate between the dummy gate and the selection gate.

3. The antifuse OTP memory of claim 2, further comprising: a third source drain plug located in the dielectric layer, the third source drain plug being connected to the third source drain doped region; and the connecting line is positioned on the dielectric layer and is connected with the third source-drain plug and the second source-drain plug.

4. The antifuse OTP memory of claim 2, wherein the dummy gate has a thickness less than the memory gate thickness.

5. The antifuse OTP memory of claim 1, wherein a width of the storage gate is greater than a width of the select gate.

6. The antifuse OTP memory of claim 5, wherein the width of the storage gate is greater than 0.1 μ ι η; the width of the selection gate is less than 0.05 μm.

7. The antifuse OTP memory of claim 1, further comprising: and the protective layer is positioned on the selection grid and the storage grid, the dielectric layer covers the side wall of the protective layer, and the protective layer is made of silicon nitride, silicon oxide or silicon oxynitride.

8. The antifuse OTP memory of claim 1, wherein the number of the memory regions is plural, the substrate further comprising an isolation region between adjacent memory regions; the memory includes: an isolation gate on the isolation region substrate.

9. A method for forming an antifuse (one-time programmable) memory, comprising:

providing a substrate, wherein the substrate comprises a storage area;

forming a dielectric layer, a discrete selection grid and a storage grid, a first source-drain doped region and a second source-drain doped region, wherein the dielectric layer is positioned on the substrate, the selection grid and the storage grid are positioned on the storage region substrate, the dielectric layer covers the storage grid and the side wall of the selection grid, the thickness of the storage grid is greater than that of the selection grid, the first source-drain doped region and the second source-drain doped region are respectively positioned in the storage region substrate at two sides of the selection grid, and the second source-drain doped region is positioned between the selection grid and the storage grid;

forming a first source drain plug in the dielectric layer, wherein the first source drain plug is electrically connected with the first source drain doped region;

and forming a second source drain plug in the dielectric layer, wherein the dielectric layer is arranged between the second source drain plug and the storage grid, and the second source drain plug is electrically connected with the second source drain doped region.

10. The method of forming an antifuse OTP memory of claim 9 wherein the steps of forming a memory gate and a select gate include: forming a discrete initial storage gate and an initial selection gate on the storage region substrate, wherein the width of the initial storage gate is greater than that of the initial selection gate; and performing gate etching on the initial storage gate and the initial selection gate, removing part of the initial storage gate to form a storage gate, removing part of the initial selection gate to form a selection gate, wherein the thickness of the removed initial storage gate is less than that of the removed initial selection gate.

11. The method of forming an antifuse OTP memory of claim 9, wherein the steps of forming the memory gate and the select gate include: forming a discrete initial storage grid and an initial selection grid on the storage region substrate, performing first etching on the initial storage grid, and removing the initial storage grid with partial thickness to form a storage grid; and carrying out second etching on the initial selection grid, and removing part of the initial selection grid to form the selection grid.

12. The method of forming an antifuse OTP memory of claim 10 or claim 11 wherein the dielectric layer comprises: the isolation structure covers the side wall of the selection grid and the side wall of the storage grid; the first dielectric layer is positioned on the selection grid, the storage grid and the isolation structure;

the step of forming the dielectric layer comprises: before removing the initial storage grid electrode with partial thickness and the initial selection grid electrode with partial thickness, forming an isolation structure, wherein the isolation structure covers the initial selection grid electrode and the initial storage grid electrode side wall; after removing the initial storage grid with partial thickness and the initial selection grid with partial thickness, forming a first dielectric layer on the initial selection grid, the initial storage grid and the isolation structure; after removing part of the thickness of the initial storage grid electrode, forming a second groove in the isolation structure; after removing part of the thickness of the initial select gate, a first recess is formed in the isolation structure.

13. The method of forming an antifuse OTP memory of claim 12, wherein prior to forming the first dielectric layer, further comprising: and forming a protective layer in the second groove and the first groove.

14. The method of forming an antifuse OTP memory of claim 12 wherein the steps of forming the first and second source drain plugs comprise: etching the dielectric layer to form a storage contact hole and a selection contact hole which penetrate through the dielectric layer, wherein the bottom of the storage contact hole is exposed out of the second source-drain doped region, and the bottom of the selection contact hole is exposed out of the first source-drain doped region; forming a first source drain plug in the selective contact hole; and forming a second source drain plug in the storage contact hole.

15. The method of forming an antifuse OTP memory of claim 12 wherein the steps of forming the initial memory gate, initial select gate, and isolation structure include: forming a first gate layer on the substrate; patterning the first gate layer to form a sacrificial storage gate and a sacrificial selection gate; forming an isolation structure covering the side wall of the sacrificial storage grid and the side wall of the sacrificial selection grid; removing the sacrificial selection grid and forming a first opening in the isolation structure; removing the sacrificial storage grid electrode and forming a second opening in the isolation structure; forming an initial selection gate in the first opening; and forming an initial storage gate in the second opening.

16. The method of forming an antifuse OTP memory of claim 15, wherein the isolation structure comprises: the side wall covers the side walls of the storage grid and the selection grid; the second dielectric layer is positioned on the substrate and covers the side wall of the side wall;

the step of forming the isolation structure comprises: forming a side wall covering the side wall of the sacrificial storage grid and the side wall of the sacrificial selection grid; forming a second dielectric layer on the substrate, wherein the second dielectric layer covers the side wall of the side wall;

and after the side wall is formed and before the second dielectric layer is formed, forming the first source drain doped region and the second source drain doped region.

17. The method of forming an antifuse OTP memory of claim 10 or claim 11 wherein the steps of forming the initial memory gate and initial select gate include: forming a second gate layer on the substrate; patterning the second gate layer to form the initial storage gate and the initial selection gate;

and after the initial storage grid and the initial selection grid are formed, forming the first source-drain doped region and the second source-drain doped region.

18. The method of forming an antifuse OTP memory of claim 11 wherein the widths of the initial memory gate and the initial select gate are the same; the thickness of the initial storage grid electrode removed by the first etching is a first thickness, the thickness of the initial selection grid electrode removed by the second etching is a second thickness, and the first thickness is larger than the second thickness.

19. The method of forming an antifuse OTP memory of claim 9, further comprising: and forming a dummy gate and a third source drain doped region, wherein the dummy gate is positioned on the storage region substrate, the dummy gate is positioned between the second source drain doped region and the select gate, the width of the dummy gate is greater than that of the select gate and smaller than that of the storage gate, the third source drain doped region is positioned in the storage region substrate between the select gate and the dummy gate, and the third source drain doped region is electrically connected with the second source drain doped region.

20. The method of forming an antifuse OTP memory of claim 19 wherein the dielectric layer also covers the dummy gate sidewalls; the forming method further includes: forming a third source drain plug connected with the third source drain doping region in the dielectric layer; and forming a connecting line on the dielectric layer, wherein the connecting line is connected with the third source-drain plug and the second source-drain plug.