TW201603225A - Semiconductor structure and manufacturing method for the same - Google Patents

Abstract

A semiconductor structure and a manufacturing method of the same are disclosed. The semiconductor structure includes a conductive layer, a conductive strip, a dielectric layer, and a conductive element. The conductive layer has a first conductive material. The conductive strip is in the same level as the conductive layer and has a second conductive material. The second conductive material is adjoined with the first conductive material having a conductivity characteristic different from a conductivity characteristic of the second conductive material. The conductive element crisscrosses the conductive strip and separated from the conductive strip by the dielectric layer.

Description

Semiconductor structure and method of manufacturing same 【0001】

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a memory and a method of fabricating the same.

【0002】

In recent years, the structure of semiconductor elements has been constantly changing, and the memory storage capacity of the elements has also been increasing. Memory devices are used in many products, such as MP3 players, digital cameras, computer files, and the like. As applications increase, so does the demand for memory devices toward smaller sizes and larger memory capacities. In response to this demand, it is required to manufacture a memory device having a high component density and a small size.

[0003]

Therefore, designers are all committed to developing a three-dimensional memory device that not only has many stacked planes but also achieves higher memory storage capacity, has a smaller size, and has good characteristics and stability.

[0004]

In accordance with an embodiment, a semiconductor structure is disclosed that includes a conductive layer, a conductive strip, a dielectric layer, and a conductive element. The conductive layer has a first conductive material. The conductive strips are at the same level as the conductive layer and have a second conductive material. The second conductive material is adjacent to the first conductive material having different conductive properties. The conductive elements are staggered with the conductive stripes and separated from the conductive stripes by a dielectric layer.

[0005]

In accordance with another embodiment, a method of fabricating a semiconductor structure is disclosed that includes the following steps. A first via hole is formed in a stacked structure to expose a conductive film having a first conductive material in the stacked structure. A dielectric layer is formed in the first via. The first through hole is filled with a conductive plug. A second via hole exposing the dielectric layer and the conductive film is formed in the stacked structure. A portion of the conductive film exposed by the second via hole is removed to form an aperture extending outward from the second via hole. The pores are filled with a second electrically conductive material. The second through hole is filled with a dielectric plug.

[0030]

102‧‧‧Stack structure
104‧‧‧Electrical film
106‧‧‧ dielectric film
108‧‧‧Memory array area
110‧‧‧ first through hole
112‧‧‧ dielectric layer
114‧‧‧conductive plug
116‧‧‧Upper surface
118‧‧‧ side wall
120‧‧‧ bottom surface
122‧‧‧mask layer
124‧‧‧ openings
126‧‧‧second through hole
128‧‧‧ side wall
130‧‧‧ side wall
132‧‧‧conductive stripe outline
134‧‧‧ pores
136‧‧‧Pushing area
138‧‧‧ Conductive layer
140‧‧‧ Conductive stripes
142‧‧‧ dielectric plug
144‧‧‧Electrically connected
146‧‧‧ conductive elements
148‧‧‧ side wall
150‧‧‧ side wall
152‧‧‧ openings

[0006]

FIGS. 1A through 9 illustrate a method of fabricating a semiconductor structure in accordance with an embodiment.

【0007】

FIGS. 1A through 9 illustrate a method of fabricating a semiconductor structure in accordance with an embodiment.

[0008]

Referring to the top and cross-sectional views of FIGS. 1A and 1B, the stacked structure 102 includes a conductive film 104 and a dielectric film 106 that are alternately stacked on a substrate (not shown). For the sake of brevity, the illustration labeled "A" in the present disclosure only shows the structure in one of the layers of the conductive film 104. The substrate may comprise a germanium wafer, an epitaxial layer or doped layer formed on the germanium material, and a suitable semiconductor material overlying the insulating layer. The conductive film 104 is formed of a first conductive material. The dielectric film 106 is formed of an oxide.

【0009】

Referring to FIGS. 2A and 2B, the etch step may be performed by lithography to form a first via 110 in the stacked structure 102 of the memory array region 108 (the illustration labeled "B" is first Structure near the through hole 110). The first via hole 110 can be controlled to stop on the lowermost dielectric film 106 according to the etching time.

[0010]

Referring to FIGS. 3A and 3B , the dielectric layer 112 is formed on the conductive film 104 and the dielectric film 106 exposed by the first via hole 110 . The first via hole 110 is filled with a conductive material to form a conductive plug 114. In some embodiments, a conductive material (not shown) formed on the upper surface 116 of the stacked structure 102 can be removed using chemical mechanical polishing (CMP). As shown in FIG. 3B, dielectric layer 112 is on sidewall 118 and bottom surface 120 of conductive plug 114. The dielectric layer 112 may be an ONO structure, an ONONO structure, an ONONONO structure, or a multilayer structure composed of a tunneling material/trapping material/blocking material, applied to a reverse gate (NAND) ) storage materials. Wherein, the first layer oxide and nitride from the inside to the outside, and the oxide (O1N1O2) of the second layer are tunneling materials, the second layer nitride (N2) is a trapping material, and the third layer oxide ( O3), or a third layer of oxide/nitride or a fourth layer of oxide (O3/N3/O4) is a barrier material.

[0011]

Referring to FIGS. 4A-4C, a patterned mask layer 122 (not shown in FIG. 4A for simplicity) is formed on the stacked structure 102, and the mask layer 122 is placed in the pattern of the memory array region 108. The opening 124 is transferred downward into the stacked structure 102 to form a second through hole 126 (the structure indicated as "C" is a structure in the vicinity of the second through hole 126). Mask layer 122 may comprise a photoresist or other suitable material, such as tantalum nitride, which may be patterned using an etch step using lithography techniques.

[0012]

Referring to FIG. 4A, the formed second via hole 126 is adjacent between the first via holes 110 in the Z direction, and at least exposes the dielectric layer 112 in the first via hole 110. In some embodiments, the second via 126 may expose the conductive plug 114 in the first via 110 more. Up to this step, the first via hole 110 and the second via hole 126 define a conductive stripe profile 132 extending in the Z direction between the groups of sidewalls 128, 130 connected in the Z direction.

[0013]

Referring to FIGS. 5A-5C, the portion of the conductive film 104 exposed by the second via 126 in the memory array region 108 is removed to form a sidewall 130 from the second via 126 (ie, the dielectric film 106). The sidewalls 130) are outwardly extending and interposed between the dielectric films 106; leaving a conductive film 104 in the pad regions 136 that do not overlap the memory array regions 108 to form the conductive layer 138. In an embodiment, the conductive film 104 is removed by an etching step, and the etching step is higher for the conductive film 104 (or the first conductive material) than for the dielectric layer 112, the conductive plug 114, and the dielectric film 106. And/or the etch rate of the mask layer 122, or substantially no removal of the dielectric layer 112, the conductive plugs 114, the dielectric film 106, and/or the mask layer 122. The etching step may be an isotropic etching process, including wet etching or dry etching. For example, in the case where the first conductive material is polycrystalline germanium, the removal method may include dry etching of a CF ₄ /O ₂ /N ₂ mixed gas, or use of tetramethylammonium hydroxide (TMAH) or heat. Wet etching of hot ammonia. The outer edge contour of the aperture 134 is not limited to the rectangular shape as shown, but may become other contours depending on the etching condition, such as a ring shape or an irregular shape or the like.

[0014]

In some embodiments, although the pores 134 are formed over a large area, since the dielectric layer 112 and the conductive plugs 114 in the first via holes 110 can support the dielectric films 106 on the upper and lower sides of the apertures 134 are separated from each other, and the stacked structure Other regions where voids 134 are not formed (e.g., pad region 136) also provide support so that different layers of dielectric film 106 in memory array region 108 can maintain a desired separation location, i.e., apertures 134 can have desired Space Form.

[0015]

Referring to FIGS. 6A-6C, the apertures 134 are filled with a second conductive material to form conductive strips 140 that extend toward the Z-axis and are separated from one another. In an embodiment, different levels of conductive stripes 140 are formed simultaneously using the same deposition process and thus have substantially uniform material properties. In some embodiments, an annealing process, such as a laser annealing process, may also be performed to enhance the properties of the second conductive material.

[0016]

As shown in FIG. 6A, the second conductive material filled in the voids 134 is adjacent to the portion (or the conductive layer 138) left by the conductive film 104, so that the conductive stripes 140 in the memory array region 108 are electrically connected to each other. Conductive layer 138 in pad region 136. Each conductive layer includes a conductive layer 138 and conductive stripes 140. In some embodiments, the mask layer 122 is also used to perform an isotropic etching process to remove the second conductive material exposed by the mask layer 122 in the second via hole 126 or the sidewall 130 of the dielectric film 106 ( Not shown) to prevent the second conductive materials filled in the different levels of pores 134 from shorting each other.

[0017]

Referring to FIGS. 7A-7C, the second via 126 is filled with a dielectric material to form a dielectric plug 142. As shown in FIG. 7A, conductive stripes 140 are defined by adjacent dielectric layers 112 and dielectric plugs 142. In one embodiment, the dielectric plug 142 is an oxide.

[0018]

Referring to FIGS. 8A-8C, chemical mechanical polishing can be performed to remove the dielectric material (not shown) over the upper surface 116 of the stacked structure 102 from the mask layer 122 (Figs. 7B and 7C). . In other embodiments, the mask layer 122 may also be retained or removed in other suitable steps.

[0019]

Referring to FIGS. 8A and 8B, conductive connections 144 extending in the X direction and separated from each other are formed on the conductive plugs 114 and across the conductive strips 140 between the conductive plugs 114. Adjacent conductive connections 144 and conductive plugs 114 form conductive elements 146 that are staggered with conductive strips 140 and separated from conductive strips 140 by dielectric layer 112. The conductive connection 144 and the conductive plug 114 may be formed of a third conductive material. The method of forming the conductive connection 144 may include depositing a third conductive material on the stacked structure 102 and then performing an etching step using lithography to pattern the third conductive material.

[0020]

The semiconductor structure of the embodiment is a three-dimensional vertical gate NAND flash memory stack. In the memory array region 108, the conductive strips 140 extending in the Z direction are used as bit lines, and the conductive elements 146 extending in the X direction are used. Make a word line.

[0021]

In some comparative examples, the formation of the bit lines is defined by patterning the stacked structure of the conductive film and the dielectric film, and forming a strip-like opening at a time. In other words, the entire side wall is exposed to the opening during the formation of the bit line. However, a stripe stack comprising a high aspect ratio of the bit line, which is open on both sides and not supported by other components, is susceptible to other stresses (eg, in the immersion cleaning step, filled in the opening) The bending of the liquid, or the stress caused by the immersion and pulling action, causes the structure to be damaged or even an undesired short circuit, which reduces the product yield.

[0022]

In the embodiment of the present disclosure, the outline of each layer of the conductive strips 140 is defined by using through holes formed in different steps (including the first through holes 110 and the second through holes 126), and the conductive stripes 140 are formed in the process. The two conductive materials are supported. For example, in the steps of FIGS. 6A-6C, the second conductive material filled in the voids 134 is received by the dielectric film 106 and the dielectric layer 112 and the conductive plug in the first via hole 110. The plug 114 is supported. Therefore, compared with the comparative example, the embodiment has a relatively stable structural feature, is less prone to deformation, and has high product reliability.

[0023]

In order to meet the electrical requirements of the device, the first conductive material for the conductive layer 138 (or the portion left by the conductive film 104), the second conductive material of the conductive strip 140, and the third conductive material with the conductive member 146 may have Different conductive properties. In some designs, the conductive layer 138, which is a bit-up region, should have a resistance that is less than the resistance of a normally off bit line, so the resistance of the first conductive material needs to be less than Two conductive materials. In one embodiment, the first conductive material is a doped germanium-containing material, such as a heavily doped N-type polysilicon (N+ poly). The second conductive material is an undoped germanium-containing material or an intrinsic silicon such as an undoped polysilicon. The third conductive material is heavily doped P-type germanium (P+ SiGe).

[0024]

Conductive elements 146 (character lines) are located on the opposite sidewalls 148, 150 of the conductive strips 140, which are formed by self-alignment filling the first vias 110 (see, for example, the contents of FIGS. 3A and 3B). Said), therefore, can have an accurate expected structure to improve product yield.

[0025]

As described with reference to FIGS. 6A-6C, the second conductive materials of different levels are simultaneously formed by the same deposition process, and thus the formed conductive stripes 140 have substantially uniform material properties, so that the memories in the array are made. The bit line channels of the cells can have substantially the same electrical properties, thereby increasing the performance of the device.

[0026]

Referring to FIG. 9, in other embodiments, openings 152 of different depths are formed in the stacked structure 102 in the pad region 136 to expose different levels of the conductive layer 138, respectively.

[0027]

Other processes not shown may also be performed thereafter. The opening 152 is filled, for example, with a dielectric (not shown) and a contact plug electrically connected to the conductive layer 138 is formed in the dielectric. Other conductive members electrically connected to the contact plugs or word lines, such as conductive contacts or metal layers such as Ml, M2, etc., are formed over the stacked structure 102. In some embodiments, the steps of forming other elements may be interspersed between the above steps, or the order of the steps may be appropriately changed.

[0028]

The disclosure is not limited to the embodiments described above, and may be appropriately modified according to actual needs or other designs. In another embodiment, for example, the first conductive material of the conductive layer 138 uses heavily doped N-type germanium (N+ SiGe), and the second conductive material of the conductive strip 140 uses an essentially or undoped germanium. Oh, and the third conductive material of the conductive element 146 uses a heavily doped P-type polysilicon. Wherein the step of removing the first conductive material of germanium (SiGe) in the memory array region 108, for example, chemical plasma etching using pure CF ₄ gas as an etching gas; etching using HCl; or using HF/HNO ₃ / Wet etching of CH ₃ COOH etchant. The electrically conductive material may also comprise a metal such as TiN, Ti, TaN, Ta, Au, W, etc., or a suitable metal halide. Dielectrics for dielectric films, dielectric layers, dielectric plugs, or other insulating elements may include oxides, nitrides, oxynitrides, such as hafnium oxide, tantalum nitride, hafnium oxynitride, or others, respectively. Suitable dielectric materials can have a single layer structure or a multilayer structure. The dielectric material or conductive material may be formed in a suitable manner, including physical vapor deposition, chemical vapor deposition, and the like. The etching or removing step may include wet etching or dry etching or the like.

[0029]

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

104‧‧‧Electrical film

108‧‧‧Memory array area

110‧‧‧ first through hole

112‧‧‧ dielectric layer

114‧‧‧conductive plug

126‧‧‧second through hole

134‧‧‧ pores

136‧‧‧Pushing area

138‧‧‧ Conductive layer

140‧‧‧ Conductive stripes

144‧‧‧Electrically connected

146‧‧‧ conductive elements

148‧‧‧ side wall

150‧‧‧ side wall

Claims (10)

[Item 1] A semiconductor structure comprising:
a conductive layer having a first conductive material;
a conductive strip, located at the same level as the conductive layer, and having a second conductive material, wherein the second conductive material is adjacent to the first conductive material having different conductive properties;
a dielectric layer; and a conductive element interleaved with the conductive strip and separated from the conductive strip by the dielectric layer. [Item 2] The semiconductor structure of claim 1, comprising a stack of multiple conductive layers, wherein the conductive layers each comprise the conductive layer and the conductive strips, and the conductive layers of different layers are exposed through openings of different depths respectively. . [Item 3] The semiconductor structure of claim 1, comprising a memory array region and a pad region that do not overlap each other, wherein the conductive strip is located in the memory array region, and the conductive layer is located in the pad region. . [Item 4] The semiconductor structure of claim 1, wherein the conductive element comprises a conductive plug, the dielectric layer being located on a sidewall and a bottom surface of the conductive plug. [Item 5] The semiconductor structure of claim 1, wherein the conductive element has a third conductive material different from the first conductive material and the second conductive material. [Item 6] The semiconductor structure of claim 1, wherein the conductive element comprises an adjacent conductive plug and a conductive connection, the conductive plug is located on opposite sidewalls of the conductive strip, the conductive connection is located The conductive stripes are above the upper surface. [Item 7] The semiconductor structure of claim 1, further comprising a dielectric plug, wherein the conductive strip is defined by the adjacent dielectric layer and the dielectric plug. [Item 8] A method of fabricating a semiconductor structure, comprising:
Forming a first via hole in a stacked structure to expose a conductive film having a first conductive material in the stacked structure;
Forming a dielectric layer in the first via hole;
Filling the first through hole with a conductive plug;
Forming a second via hole exposing the dielectric layer and the conductive film in the stacked structure;
Removing a portion of the conductive film exposed by the second via hole to form an aperture extending outward from the second via hole;
Filling the aperture with a second conductive material; and filling the second via with a dielectric plug. [Item 9] The method of manufacturing the semiconductor structure of claim 8, wherein the second via exposes the conductive layer and the dielectric layer in the first via and the conductive via, the second via The exposed portion of the conductive film is removed by an etching step, the etching rate of the conductive film being higher than the etching rate for the dielectric layer and the conductive plug. [Item 10] The method of fabricating a semiconductor structure according to claim 8 , further comprising forming a conductive connection on the conductive plug, wherein the second conductive material filled in the aperture forms a conductive strip, the conductive stripe The contour is defined by the first through hole and the sidewall of the second through hole.