KR101441280B1 - 혼합된 유형의 메모리 장치를 동작시키는 시스템 및 방법 - Google Patents

혼합된 유형의 메모리 장치를 동작시키는 시스템 및 방법 Download PDF

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Publication number
KR101441280B1
KR101441280B1 KR1020147001536A KR20147001536A KR101441280B1 KR 101441280 B1 KR101441280 B1 KR 101441280B1 KR 1020147001536 A KR1020147001536 A KR 1020147001536A KR 20147001536 A KR20147001536 A KR 20147001536A KR 101441280 B1 KR101441280 B1 KR 101441280B1
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KR
South Korea
Prior art keywords
memory
type
address
devices
serial
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KR1020147001536A
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English (en)
Korean (ko)
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KR20140019478A (ko
Inventor
학준 오
홍 범 편
진기 김
Original Assignee
컨버전트 인텔렉츄얼 프로퍼티 매니지먼트 인코포레이티드
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Publication date
Priority claimed from US11/622,828 external-priority patent/US8271758B2/en
Priority claimed from US11/771,241 external-priority patent/US7925854B2/en
Application filed by 컨버전트 인텔렉츄얼 프로퍼티 매니지먼트 인코포레이티드 filed Critical 컨버전트 인텔렉츄얼 프로퍼티 매니지먼트 인코포레이티드
Publication of KR20140019478A publication Critical patent/KR20140019478A/ko
Application granted granted Critical
Publication of KR101441280B1 publication Critical patent/KR101441280B1/ko

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
  • Information Transfer Systems (AREA)
KR1020147001536A 2006-12-06 2007-12-04 혼합된 유형의 메모리 장치를 동작시키는 시스템 및 방법 KR101441280B1 (ko)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US86877306P 2006-12-06 2006-12-06
US60/868,773 2006-12-06
US87089206P 2006-12-20 2006-12-20
US60/870,892 2006-12-20
US11/622,828 2007-01-12
US11/622,828 US8271758B2 (en) 2006-12-06 2007-01-12 Apparatus and method for producing IDS for interconnected devices of mixed type
US11/771,241 2007-06-29
US11/771,241 US7925854B2 (en) 2006-12-06 2007-06-29 System and method of operating memory devices of mixed type
PCT/CA2007/002182 WO2008067658A1 (en) 2006-12-06 2007-12-04 System and method of operating memory devices of mixed type

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR1020127027959A Division KR101441225B1 (ko) 2006-12-06 2007-12-04 혼합된 유형의 메모리 장치를 동작시키는 시스템 및 방법

Publications (2)

Publication Number Publication Date
KR20140019478A KR20140019478A (ko) 2014-02-14
KR101441280B1 true KR101441280B1 (ko) 2014-09-17

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Family Applications (3)

Application Number Title Priority Date Filing Date
KR1020097014049A KR101441154B1 (ko) 2006-12-06 2007-12-04 혼합된 유형의 메모리 장치를 동작시키는 시스템 및 방법
KR1020147001536A KR101441280B1 (ko) 2006-12-06 2007-12-04 혼합된 유형의 메모리 장치를 동작시키는 시스템 및 방법
KR1020127027959A KR101441225B1 (ko) 2006-12-06 2007-12-04 혼합된 유형의 메모리 장치를 동작시키는 시스템 및 방법

Family Applications Before (1)

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KR1020097014049A KR101441154B1 (ko) 2006-12-06 2007-12-04 혼합된 유형의 메모리 장치를 동작시키는 시스템 및 방법

Family Applications After (1)

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KR1020127027959A KR101441225B1 (ko) 2006-12-06 2007-12-04 혼합된 유형의 메모리 장치를 동작시키는 시스템 및 방법

Country Status (5)

Country Link
EP (1) EP2118903A4 (ja)
JP (3) JP5683813B2 (ja)
KR (3) KR101441154B1 (ja)
TW (1) TWI470645B (ja)
WO (1) WO2008067658A1 (ja)

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US9697872B2 (en) * 2011-12-07 2017-07-04 Cypress Semiconductor Corporation High speed serial peripheral interface memory subsystem
US8614920B2 (en) 2012-04-02 2013-12-24 Winbond Electronics Corporation Method and apparatus for logic read in flash memory
JP5467134B1 (ja) * 2012-09-27 2014-04-09 華邦電子股▲ふん▼有限公司 フラッシュメモリ装置およびメモリ装置の操作方法
US10067903B2 (en) 2015-07-30 2018-09-04 SK Hynix Inc. Semiconductor device
US11755255B2 (en) 2014-10-28 2023-09-12 SK Hynix Inc. Memory device comprising a plurality of memories sharing a resistance for impedance matching
KR102366767B1 (ko) * 2015-07-30 2022-02-23 에스케이하이닉스 주식회사 반도체 장치
KR102358177B1 (ko) 2015-12-24 2022-02-07 에스케이하이닉스 주식회사 제어회로 및 제어회로를 포함하는 메모리 장치
US10146608B2 (en) * 2015-04-06 2018-12-04 Rambus Inc. Memory module register access
FR3041806B1 (fr) * 2015-09-25 2017-10-20 Stmicroelectronics Rousset Dispositif de memoire non volatile, par exemple du type eeprom, ayant une capacite memoire importante, par exemple 16mbits
GB2568725B (en) * 2017-11-24 2021-08-18 Ge Aviat Systems Ltd Method and apparatus for initializing a controller module
GB2568724B (en) * 2017-11-24 2021-08-18 Ge Aviat Systems Ltd Method and apparatus for initializing a controller module
CN110413197B (zh) * 2018-04-28 2023-06-27 伊姆西Ip控股有限责任公司 管理存储系统的方法、设备和计算机程序产品
TWI696113B (zh) * 2019-01-02 2020-06-11 慧榮科技股份有限公司 用來進行組態管理之方法以及資料儲存裝置及其控制器
US20210081318A1 (en) * 2019-09-17 2021-03-18 Micron Technology, Inc. Flexible provisioning of multi-tier memory
TWI749598B (zh) * 2020-06-18 2021-12-11 華邦電子股份有限公司 一種記憶體裝置及其連續讀寫方法
US11120851B1 (en) 2020-07-12 2021-09-14 Winbond Electronics Corp. Memory apparatus and burst read and burst write method thereof
CN113641595B (zh) * 2021-07-30 2023-08-11 珠海一微半导体股份有限公司 独立块保护模式的spi flash在brom阶段的类型识别方法及系统

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US20060031593A1 (en) * 2004-08-09 2006-02-09 Sinclair Alan W Ring bus structure and its use in flash memory systems

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US20060031593A1 (en) * 2004-08-09 2006-02-09 Sinclair Alan W Ring bus structure and its use in flash memory systems

Also Published As

Publication number Publication date
KR20140019478A (ko) 2014-02-14
TWI470645B (zh) 2015-01-21
KR101441154B1 (ko) 2014-09-17
JP5351130B2 (ja) 2013-11-27
JP2010511943A (ja) 2010-04-15
KR20120135334A (ko) 2012-12-12
WO2008067658A1 (en) 2008-06-12
JP2014063523A (ja) 2014-04-10
EP2118903A4 (en) 2010-01-06
KR101441225B1 (ko) 2014-09-17
KR20090102787A (ko) 2009-09-30
EP2118903A1 (en) 2009-11-18
JP5695724B2 (ja) 2015-04-08
TW200845037A (en) 2008-11-16
JP2011054204A (ja) 2011-03-17
JP5683813B2 (ja) 2015-03-11

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