WO2008067658A1 - System and method of operating memory devices of mixed type - Google Patents

System and method of operating memory devices of mixed type Download PDF

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Publication number
WO2008067658A1
WO2008067658A1 PCT/CA2007/002182 CA2007002182W WO2008067658A1 WO 2008067658 A1 WO2008067658 A1 WO 2008067658A1 CA 2007002182 W CA2007002182 W CA 2007002182W WO 2008067658 A1 WO2008067658 A1 WO 2008067658A1
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WO
WIPO (PCT)
Prior art keywords
address
memory
type
serial
devices
Prior art date
Application number
PCT/CA2007/002182
Other languages
English (en)
French (fr)
Inventor
Hakjune Oh
Hong Beom Pyeon
Jin-Ki Kim
Original Assignee
Mosaid Technologies Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/622,828 external-priority patent/US8271758B2/en
Priority claimed from US11/771,241 external-priority patent/US7925854B2/en
Application filed by Mosaid Technologies Incorporated filed Critical Mosaid Technologies Incorporated
Priority to KR1020147001536A priority Critical patent/KR101441280B1/ko
Priority to EP07855464A priority patent/EP2118903A4/en
Priority to KR1020127027959A priority patent/KR101441225B1/ko
Priority to KR1020097014049A priority patent/KR101441154B1/ko
Priority to JP2009539576A priority patent/JP5683813B2/ja
Publication of WO2008067658A1 publication Critical patent/WO2008067658A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Definitions

  • the present invention relates generally to semiconductor device systems More particularly, the present invention relates to an apparatus and a method for controlling semiconductor devices, such as, for example, memory systems with memory devices of varying or mixed type
  • Computer-based systems contain semiconductor devices, such as, for example, memory devices and processing devices Memory is where information is stored while waiting to be operated on by the Central Processing Unit (CPU) of the computer Memory is controlled by a memory controller, which can form part of the CPU or be separate from the CPU
  • the memory controller has an interface with the memory for communicating information
  • Known interfaces include parallel interfaces and serial interfaces
  • Parallel interfaces use a large number of pins to read and write data
  • Unfortunately as the number of input pins and wires increases, so do a number of undesired effects
  • These undesired effects include inter-symbol interference, signal skew and cross talk Therefore, there is a need in the art for memory modules that have increased memory capacities and/or operating speeds while minimizing the number input pins and wires for accessing the memory modules
  • Serial interfaces use fewer pins to read and write data Serial flash memory is now available, but this tends to be very slow
  • many conventional memories are using serial bus interface schemes that operate in the range of 1 MHz - 20MHz with the SPI (Serial Peripheral Interface) or I 2 C (Inter- Integrated Circuit) compatible interface
  • SPI Serial Peripheral Interface
  • I 2 C Inter- Integrated Circuit
  • FIG. 1A shown are block diagrams of four primary flash memory architectures
  • the four primary flash-memory architectures include a traditional XIP model as shown in Figure 1A, a shadow model as shown in Figure 1 B, a store-and- download model with NAND as shown in Figure 1 C, and a newer store-and-download model with hybridized NAND flash memory as shown in Figure 1 D.
  • the traditional XIP model has a NOR flash memory 102 and volatile memory 103, which is likely SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory), connected to an application processor 101.
  • the NOR flash memory 102 executes code, while the volatile memory 103 accounts for constantly changing system elements, such as variables, stack, and heat.
  • the NOR flash memory 102 can also provide data and code storage as well.
  • the advantage of the XIP model is simplicity, but the disadvantage is its slow write speed.
  • the shadow model has a NOR flash memory 105, NAND flash memory 106, and volatile memory 107, which is likely SRAM or DRAM, connected to an application processor 104. Users boot a system with the NOR flash memory 105 and use the NAND flash memory 106 for storage. The volatile memory 107 handles all of the execution.
  • the shadow model is an expensive model in that it is using the NOR flash memory 105, which is relatively pricey, only to boot up the system.
  • the architecture is also a bit more complex, which means that it consumes more design time and cost.
  • the shadow model also tends to be power-hungry because the volatile memory is constantly active.
  • the store-and-download architecture has a NAND flash memory 110 and volatile memory 1 11 , which is likely SRAM or DRAM, connected to an application processor 108.
  • the store-and-download architecture has no NOR flash memory, but there is an OTP (one-time-programmable) storage 109 or ROM (Read Only Memory) core designed into the application processor 108.
  • the application processor 108 loads information into the volatile memory 1 11 , which accesses the NAND flash memory 110 for data storage.
  • the architecture is a bit more complex and requires more initial engineering costs, but ultimately, the unit cost of the system is less expensive.
  • the main difficulty of the model is that users must employ extensive error-correction and error- detection coding because NAND flash memory is typically less reliable. Storing and downloading designs tend to require more power, as the RAM takes a more active role.
  • the hybrid store and download model has a hybrid NAND flash memory 113 and volatile memory 114, which is likely SRAM or DRAM, connected to an application processor 112.
  • the hybrid NAND flash memory 113 mixes SRAM, control logic and
  • Hybrid NAND flash memory to create a memory device that is supposed to look like a NOR flash device
  • This hybrid model reads much faster than a standard NAND flash device and at the same speed as a NOR flash device It also offers better write performance than NOR flash devices
  • Hybrid NAND flash memories are now available Hybrid model requires less error- correction and error-detection coding than store-and-download models with standard NAND flash memories
  • the unit cost for hybridized NAND flash memories is, for example, 30 to 40% less than NOR flash memories at the same density
  • the cost of stand-alone NAND flash memories is slightly less than that of hybridized NAND flash memories
  • a system or apparatus comprising memory devices of varying or mixed type, the memory devices being serially interconnected, so that input data is serially transferred from device to device
  • a semiconductor device for use in a serial interconnection configuration of a plurality of devices of mixed type wherein the plurality of devices are serially interconnected
  • a first device of the serial interconnection configuration receives a serial input
  • the serial input is propagated through the serial interconnection configuration
  • the serial input contains a device type identification, a command and a device address identification
  • the device executes the command based on the device type identification and the device address identification
  • the semiconductor device may include a device controller for controlling operation of the device in response to the received serial input
  • the semiconductor device may further include a device type holder for holding a device type identification, the held type identification being provided for indicating the type of the device, and an address holder for holding a device address assigned in response to the serial input provided, the assigned address being provided for indication of the address of the device
  • a system comprising a plurality of devices of mixed type, the devices being configured in a serial interconnection configuration wherein the devices are serially interconnected Each of the devices has serial input and output connections
  • the system further comprises a serial output/input controller having a serial output connection for providing a serial input to the serial input connection of a first device of the serial interconnection configuration
  • the serial input is propagated through the serial interconnection configuration
  • the serial output/input controller has a serial input connection for receiving a serial output from a last device of the serial interconnection configuration
  • the serial input contains a device type identification, a command and a device address identification
  • the plurality of devices is configured in one serial interconnection configuration, the type of the devices being mixed
  • Each of the devices may include a device controller for controlling operation of the device in response to received serial input
  • each of the devices may further comprise a device address indicator for indicating a device address to be assigned to the device, and a device type indicator for indicating a device type identification of that device
  • a method for operating a plurality of devices of mixed type the devices being configured in at least one serial interconnection configuration wherein the devices are serially interconnected, the method comprising providing a serial input to a first device of the serial interconnection configuration, the serial input being propagated through the serial interconnection configuration, the serial input containing a device type identification, a command and a device address identification
  • the method may further comprise holding a device type identification of the device, and holding a device address assigned in response to the serial input provided
  • the method may further comprise determining whether the received device type identification matches the held device type identification
  • the received device type identification matches the held device type identification, a device type match result is provided, and the received device type identification does not match the held device type identification, a non-device type match result
  • the method may further comprise determining whether the received device address identification matches the held device address
  • determining whether the received device address identification matches the held device address e.g., where the received device address identification matches the held device address, a device address match result is provided, and where the received device address identification does not match the held device address, a non-device address match result is provided
  • the method may execute the received command of the serial input in response to the device type match result and the device address match result
  • an apparatus for operating a plurality of devices of mixed type the devices being configured in at least one serial interconnection configuration wherein the devices are serially interconnected
  • the apparatus comprising a controller for providing a serial input to a first device of the serial interconnection configuration, the serial input being propagated through the serial interconnection configuration, the serial input containing a device type identification, a command and a device address identification.
  • each of the devices has serial input and output connections and the controller has a serial output connections connected to the serial input connection of the first device and a serial input connection connected to the serial output connection of a last device of the serial interconnection configuration.
  • a method comprising: assigning device addresses to a plurality of devices of mixed type, the devices being configured in at least one serial interconnection configuration wherein the devices are serially interconnected; and accessing the devices of the serial interconnection configuration based on a device type and a device address.
  • the method may further comprise establishing addresses in each of the devices of one type.
  • the step of establishing comprises: providing a serial input containing a device type identification, a device address identification and an address number to a first device of the serial interconnection configuration.
  • the step of accessing may comprise: enabling at least one device of a first type in the serial interconnection configuration to be processed; and enabling at least one device of a second type in the serial interconnection configuration to be processed, during the process of the device of the first type, process time of the device of the first type being greater than that of the device of the second type.
  • a memory system architecture in which a memory controller controls memory devices that are interconnected with serial links.
  • the memory controller has an output interface for sending memory commands, and an input interface for receiving memory responses for those memory commands requisitioning such responses.
  • Each memory device may be of any memory type, such as NAND flash or NOR flash for example.
  • Each memory command is specific to the memory type of the intended memory device.
  • a data path for the memory commands and the memory responses is provided through the links and interconnected devices.
  • a given memory command may traverse many memory devices in order to reach its intended memory device. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to the memory controller.
  • the memory commands sent by the memory controller are propagated through the serially interconnected memory devices in response to clocks.
  • the command execution of one memory device is not overlapped with that of another memory device (e.g., a next device) in clock timings.
  • the command execution of memory devices can be overlapped with each other In an address assignment operation, an address number changing by one device is completed before another device performs an address number changing
  • a memory devices which have memory types of, for example, NAND Flash EEPROM, NOR Flash EEPROM, AND Flash EEPROM, DiNOR Flash EEPROM, Serial Flash EEPROM, DRAM, SRAM, ROM, EPROM, FRAM, MRAM, and PCRAM
  • NAND Flash EEPROM NAND Flash EEPROM
  • NOR Flash EEPROM AND Flash EEPROM
  • DiNOR Flash EEPROM Serial Flash EEPROM
  • DRAM DRAM
  • SRAM SRAM
  • ROM ROM
  • EPROM EPROM
  • FRAM FRAM
  • MRAM Magnetoresistive RAM
  • PCRAM PCRAM
  • Figures 1 A, 1 B, 1 C and 1 D are block diagrams of four flash memory architectures
  • Figure 2A is a block diagram of a memory system according to an embodiment of the present invention
  • Figure 2B is a block diagram of a memory system according to an embodiment of the present invention.
  • FIG. 2C is a flowchart illustrating operations of the memory system shown in Figure 2B
  • Figures 3A, 3B, 3C, 3D and 3E are schematics of specific example memory systems according to embodiments of the present invention
  • Figure 3F is a schematic of another example memory system according to an embodiment of the present invention
  • Figure 3G is a timing diagram of example single data rate operation of memory devices
  • Figure 3H is a timing diagram of example double data rate operation of memory devices
  • Figure 4A is a schematic of an example memory device used as the memory devices shown in Figures 3A, 3B, 3C, 3D and 3E,
  • Figure 4B is a schematic of an example memory device used as the memory devices shown in Figure 3F
  • Figure 5A is a schematic of an example register block used to identify a memory type of a memory device
  • Figure 5B is a table of an example encoding scheme for each memory device type
  • Figure 6A is a flowchart of a method of assigning device addresses with type-dependent addressing
  • Figure 6B is a flowchart of details of a device address assignment step of the method shown in Figure 6A,
  • Figures 7A, 7B, 7C and 7D are timing diagrams of assigning device addresses with type- dependent addressing
  • Figure 8 is a timing diagram of an example input with type-dependent addressing
  • Figure 9 is a timing diagram of example signaling through two adjacent memory devices
  • Figure 10 is a table of example predetermined formats for memory operations with type-dependent addressing
  • Figure 11 is a table of an example encoding scheme for type-dependent addressing
  • Figure 12 is a table of an example encoding scheme for NAND flash commands with type-dependent addressing
  • Figure 13 is a table of an example encoding scheme for NOR flash commands with type-dependent addressing
  • Figure 14 is a flowchart of a method of processing memory operations with type-dependent addressing
  • Figures 15A and 15B are timing diagrams of processing memory operations with type-dependent addressing
  • Figure 16A is a schematic of another example memory device block used as the memory devices shown in Figures 3A, 3B, 3C, 3D and 3E
  • Figure 16B is a flowchart of a device address assignment operation by the device shown in Figure 16A
  • Figure 16C is a flowchart of another device address assignment operation by the device shown in Figure 16A,
  • FIG 17 is a schematic of another example memory device block used as the memory devices shown in Figures 3F,
  • Figure 18 shows a memory system of two channels according to another embodiment of the present invention.
  • Figures 19A and 19B are schematics of specific example memory devices used in the memory system shown in Figure 18,
  • Figures 2OA and 2OB are schematics of other specific example memory devices used in the memory system shown in Figure 18,
  • Figure 21 is a timing diagram of another example of initializing the memory system
  • Figure 22 is a schematic of another example memory system according to an embodiment of the present invention.
  • Figure 23 is a block diagram of a memory system according to another embodiment of the present invention.
  • Figure 24 is a schematic of specific example memory devices used in the memory system shown in Figure 23
  • Figure 25 is a block diagram of a memory system according to another embodiment of the present invention.
  • Figure 26 is a schematic of specific example memory devices used in the memory system shown in Figure 25
  • the present invention provides apparatus and method for controlling semiconductor devices, such as, for example, memory systems with memory devices of mixed type
  • a memory system includes a memory controller and a serial interconnection configuration of memory devices
  • Some memory subsystems employ multiple memory devices, such as, for example, flash memory devices, with interfaces
  • the command string may be fed to all of the devices even though the command may only be performed on one of the devices
  • the command string may contain a device identifier (ID) or a device address that identifies the memory device to which the command is directed
  • ID device identifier
  • Each device receiving the command string compares the ID contained in the command string to an ID associated with the device If the two match, the device will assume that the command is directed to the device to execute the command
  • ID device identifier
  • MCP Multi Chip Package
  • FIG 2A shows a memory system according to an embodiment of the present invention
  • a memory system includes a controller 100 and a plurality of devices 300-0, 300-1 , , and 300-N in a serial interconnection configuration N is an integer greater than one In this particular example, the number of the serially interconnected memory devices is (N+1 )
  • the controller 100 and the devices 300-0, 300-1 , , and 300-N are interconnected using any appropriate connections, such as, for example, links In the illustrated example, the links are serial links
  • the controller 100 and the devices 300-0, 300-1 , , and 300-N are interconnected through serial links LO, L1 , L2, , LN and L(N+1 )
  • the controller 100 has controller operation circuitry 130
  • Each of the devices 300-0, 300-1 , , and 300-N has device operation circuitry 230 that performs memory operation control and memory initialization functions
  • the devices 300-0, 300-1 , , and 300-N have respective memory-type specific components such as respective memories 320-0, 320-1 , , and 320-N
  • Each of the devices 300-0, 300-1 , , and 300-N has a memory type from a plurality of supported memory types
  • the plurality of supported memory types is defined on an implementation-specific basis Information on or identification of the memory type of each device is stored in a register 250 thereof However, the types of the devices are unknown to the controller 100
  • Each of the controller operation circuitry and the device operation circuitry includes input and output circuitry, e g , interface circuitry
  • Figure 2B shows an example memory system according to one embodiment of the present invention
  • the memory system 40 includes a memory controller 10 and a plurality of memory devices 30-0, 30-1 , , and 30-N in a serial interconnection configuration N is an integer greater than one In this particular example, the number of the serially interconnected memory devices is (N+1 )
  • the memory controller 10 and the memory devices 30-0, 30-1 , , and 30-N are interconnected using, such as, for example, serial links LO, L1.
  • the memory controller 10 has an output interface 11 , an input interface 12 and controller operation circuitry 13 In some implementations, as shown in the illustrated example, the memory controller 10 also has another interface 14 for connection with another electronic circuit (not shown)
  • the memory controller 10 may have other components, but they are not shown for sake of simplicity
  • Some components of the memory devices 30-0, 30-1 , , and 30-N are identically numbered
  • each of the memory devices 30-0, 30-1 , , and 30-N has an input interface 21 , an output interface 22 and memory device operation circuitry 23 that performs memory operation control and memory initialization functions
  • the memory devices 30-0, 30-1 , , and 30-N have respective memory-type specific components such as respective memory cores 32-0, 32-1 , , and 32-N
  • Each of the memory devices 30-0, 30-1 , , and 30-N has a device type from a plurality of supported memory types The plurality of supported memory types is defined on an implementation-specific basis This can be fixed, or in some embodiment
  • the plurality of supported memory types might for example include any two or more of NAND Flash EEPROM, NOR Flash EEPROM, AND Flash EEPROM, DiNOR Flash EEPROM, Serial Flash EEPROM, DRAM, SRAM, ROM, EPROM, FRAM, MRAM (Magnetoresistive Random Access Memory), and PCRAM Other combinations of supported memory types are also possible
  • Each of the memory devices 30-0, 30-1 , , and 30-N is aware of its memory type This might for example be stored in a register as indicated by 25, however, more generally, each of the memory devices 30-0, 30-1 , , and 30-N may be provided with any appropriate circuitry for maintaining an identification of its memory device type Other mechanisms by which each of the memory devices 30-0, 30-1 , , and 30-N is aware of its device type are also possible.
  • Each of the memory devices 30-0, 30-1 , , and 30-N may have other components, but they are not shown for sake of simplicity
  • the controller operation circuitry 13 of the memory controller 10 performs memory operation control and memory initialization functions
  • the controller operation circuitry 13 sends memory commands over the output interface 11
  • a data path for each memory command is provided by the combination of the memory devices 30-0, 30-1 , , and 30-N and the serial links LO, L1 , L2, , LN and L(N+1 )
  • the memory command traverses the first memory device 30-0 over the serial links LO and L1
  • the memory command requisitions a response from the second memory device 30-1 , the response will traverse the third memory device, and the N-th (last) device 30-N over the serial links L2, , LN and L(N+1 ) back to the memory controller 10
  • each of the memory devices 30-0, 30-1 , , and 30-N may be any one of the plurality of supported device types
  • the controller operation circuitry 13 of the memory controller 10 is operable to send over the output interface 11 , memory commands specific to the device type and receive over the input interface 12 memory responses for those memory commands requisitioning such responses For example, if the controller operation circuitry 13 issues a command intended for the second memory device 30-1 , then the command that is issued is specific to the device type of the second memory device 30-1 , which may be different from the device type of other memory devices
  • Each of the memory devices 30-0, 30-1 , , and 30-N executes those memory commands that are addressed to the memory device, and forwards over the output interface 22 those memory commands that are addressed to another memory device
  • the memory system 40 can be expanded as appropriate in terms of different device types or mixed memory device type as well as memory density expansion without sacrificing system's overall performance
  • the memory system 40 performs operations of two phases an initialization phase as indicated by 35 and a normal operation phase as indicated by 36, as shown in Figure 2C
  • the initialization phase 35 the memory devices 30-0, 30-1 , , and 30-N are assigned with device addresses The assigned device addresses are held in the memory devices Thereafter, in the normal operation phase 36, a target or addressed memory device performs data access operations
  • the controller operation circuitry 13 of the memory controller 10 sends memory commands over the output interface 11 for controlling the memory devices 30-0, 30-1 , , and 30-N
  • the controller operation circuitry 13 sends memory commands Each of the commands has a first portion and a second portion that in combination uniquely identify a selected memory device of the plurality of memory devices
  • the first portion identifies a device type of the selected memory device while the second portion identifies a device address of the selected memory device
  • Each memory command also has a command portion
  • the memory device operation circuitry 23 determines whether the memory command is addressed to the memory device (e g , the first memory device 30-0) in response to the first portion and the second portion of the memory command in combination For example, the memory device operation circuitry 23 first interprets the first portion indicating the device type If the device type indicated by the first portion is different from the device type of the first memory device 30-0 provided by the device type register 25, the memory device operation circuitry 23 of that device will not need to look at any further portions of the received memory command It is, thus, determined that the received command is addressed to one of the other memory devices 30-1 , , and 30-N Accordingly, the memory device operation circuitry 23 forwards the memory command over the output interface 22 However, if the device type indicated by the first portion is identical to the device type of the first memory device 30-0, then the memory device operation circuitry 23 determines whether the device address indicated by the second portion matches the device address of the first memory device 3
  • the controller operation circuitry 13 of the memory controller 10 controls the plurality of memory devices by sending memory commands
  • Each of the memory commands includes a first portion that uniquely identifies a selected memory device of the plurality of memory devices The first portion identifies the device address of the selected memory device.
  • Each memory command also has a command portion identifying a selected command to be executed by the selected memory device. As before, each memory command may also include other portions as appropriate.
  • the memory device operation circuitry 23 determines whether the memory command is addressed to that device (i.e., the first memory device 30-0) in response to the first portion of the memory command.
  • the memory device operation circuitry 23 determines whether the device address indicated by the first portion matches the device address of the first memory device 30-0. If there is a match between the two device addresses, then the memory device operation circuitry 23 executes the selected command indicated by the command portion. Otherwise, the memory device operation circuitry 23 forwards the memory command over the output interface 22.
  • the controller operation circuitry 13 of the memory controller 10 is operable to send memory commands over the output interface 11 in response to requests received over the interface 14, and is further operable to respond to the requests using memory responses received over the input interface 12.
  • the interface 14 may be any appropriate interface to another device or system (not shown) that uses the memory system 40.
  • memory commands There are many possibilities for the memory commands. These might include one or more of read operations, write operations, erase operations, read status operations, read ID operations, write configuration register operations, write address operations, and reset operations. There may be other memory commands.
  • the way in which the memory controller 10 sends memory commands may depend on the manner in which the device addresses are assigned. Example implementations for assigning the device addresses are provided below.
  • the device addresses are predetermined or hard-wired.
  • the controller operation circuitry 13 assigns the device addresses during an initialization stage. For example purposes, first and second implementations are described below; however, other implementations are possible.
  • the controller operation circuitry 13 is operable to, for each device type of the plurality of supported device types, send over the output interface 11 a respective initialization message for assigning the device address to each memory device of that device type.
  • Each of the memory devices 30-0, 30-1 and 30-N receives and processes the initialization messages For example, the first memory device 30-0 receives the initialization messages over the first input interface 21 For each initialization message received, if the initialization message is indicated to be for another device type than that of the first memory device 30-0, then the memory device operation circuitry 23 forwards the initialization message over the output interface 22 However, if the initialization message is indicated to be for the device type of the first memory 30-0, then the memory device operation circuitry 23 determines the device address from the initialization message This involves reading a device address from the initialization message In some implementations, the device address as it is read from the initialization message becomes the device address of the first memory device 30-0 The memory device operation circuitry 23 forwards the initialization message over the output interface 22 with a new device address Each of
  • the new device address that is forwarded to the next device is an increment of the device address Therefore, if the first memory device of a given device type is assigned an address of 0, then the last memory device of the given device type will be assigned an address of m-1 , where m is the number of memory devices of the given device type
  • the new device address that is forwarded to the next device is an increment of the device address Therefore, if the first memory device 30-0 is assigned an address of 0, then the last memory device 30-N will be assigned an address of N, where the number of memory devices is (N+1 ) By receiving the initialization response over the input interface 12 indicating an incremented device address of the last memory device 30-N, the controller operation circuitry 13 can determine the device address of each memory device
  • the controller operation circuitry 13 determines the device type of each memory device For each device address, the controller operation circuitry 13 sends over the output interface 11 an additional initialization message for determining the device type of the memory device of the device address.
  • the controller operation circuitry 13 sends over the output interface 11 an additional initialization message for determining the device type of the memory device of the device address.
  • Each of the memory devices 30-0, 30-1 , , and 30-N receives and processes the additional initialization messages
  • the first memory device 30-0 determines based on the device address indicated in the additional initialization message whether the additional initialization message is intended for the first memory device 30-0 If it is, then the first memory device 30-0 responds to the additional initialization message over the output interface 22 with an identification of its device type If the additional initialization message is intended for one of the other memory device 30-1 , , and 30-N, then the first memory device 30-0 forwards the additional initialization message over the output interface 22.
  • Each of the other memory devices 30-1 , ..., and 30-N performs similar processing of the additional initialization messages.
  • the controller operation circuitry 13 of the memory controller 10 receives over the input interface 12 for each memory device an initialization response indicating the device type of the memory device.
  • the first and second implementations described above for the controller operation circuitry 13 are very specific for example purposes only. Variations and modifications are possible.
  • the first implementation is described above to involve a plurality of initialization messages for assigning the device address to each memory device; however, alternatively, there may be one or more initialization messages for this purpose.
  • the second implementation is described above to involve a plurality of additional initialization messages for determining the device type of each memory device; however, alternatively, the there may be one or more additional initialization messages for this purpose.
  • the address of the received initialization message is established as the device address and a new address is generated and sent to the next device.
  • each memory device receives an address and increments it before establishing this as the device address.
  • a detailed example of this implementation is described in commonly assigned co-pending U.S. Patent Application No. 11/529,293 "Packet Based ID Generation for Serially Interconnected Devices" filed September 29, 2006, which is hereby incorporated by reference in its entirety.
  • the memory controller 10 has a reset output (not shown) for connection with each of the memory devices 30-0, 30-1 and 30-N. Examples of this are provided in the examples that are described below. More generally, the memory system 40 may be reset using any appropriate resetting implementation.
  • the memory controller 10 has a serial clock output (not shown) for connection with each of the memory devices 30-0, 30-1 , ..., and 30-N. Examples of this are provided in the examples that are described below. More generally, the memory system 40 may be provided with a serial clock using any appropriate clock implementation.
  • the memory controller 10 has a chip select (not shown) for connection with each of the memory devices 30-0, 30-1 , ..., and 30-N. Examples of this are provided in the examples that are described below. More generally, the memory devices 30-0,
  • 30-1 and 30-N can be enabled using any appropriate device enabling implementation.
  • FIG. 2C shows operations of the memory system shown in Figure 2B.
  • the controller operation circuitry 13 of the controller 10 sends memory commands over the output interface 11 for controlling the devices 30-0, 30-1 and 30-N.
  • the controller operation circuitry 13 controls the devices 30-0, 30-1 , ..., and 30-N, by sending memory commands. There are many ways that this can be accomplished. For example purposes, some example implementations are described below; however, other implementations are possible.
  • the memory system 40 performs operations of two phases: an initialization phase as indicated by 35; and a normal operation phase as indicated by 36.
  • the initialization phase 35 (or an initialization mode)
  • the devices 30-0, 30-1 , ..., and 30-N are assigned with device addresses.
  • the assigned device addresses are held in the devices 30-0, 30-1 , ..., and 30-N.
  • the normal operation phase 36 or a normal operation mode
  • a target or addressed memory device performs data access operations.
  • the controller operation circuitry 13 sends memory commands.
  • the commands have portions of a device address assignment to assign unique addresses to the devices and of a device address related number.
  • the device address related number of the command from the controller operation circuitry 13 is an initial value or number and the initial number is incremented by each of the devices. Each of the incremented number is held in a respective device as its device address.
  • the controller operation circuitry 13 of the controller 10 sends memory commands.
  • the memory commands include a first portion that uniquely identifies a selected memory device of the plurality of memory devices, with the device address. No device type is included in the memory commands.
  • Each memory command also has a command portion identifying a selected command to be executed by the selected memory device.
  • Each memory command may also include other portions as appropriate.
  • the first device 30-0 receives a memory command and then, the device operation circuitry 23 thereof determines whether the memory command is addressed to that device (i.e., the first device 30-0) in response to the first portion of the memory command.
  • the device operation circuitry 23 determines whether the device address indicated by the first portion matches the device address of the first device 30-0. If there is a match between the two device addresses, the device operation circuitry 23 of the device 30-0 will execute the selected command indicated by the command portion. Otherwise, the device operation circuitry 23 forwards the memory command over the output interface 22 to a next device (e.g., the second device 30-1 ).
  • the controller operation circuitry 13 of the controller 10 is operable to send memory commands over the output interface 11 in response to requests received over the interface 14, and is further operable to respond to the requests using memory responses received over the input interface 12.
  • the interface 14 may be any appropriate interface to another device or system (not shown) that uses the memory system 40.
  • memory commands There are many possibilities for the memory commands. These might include one or more of read operations, write operations, erase operations, read status operations, read DA operations, write configuration register operations, write address operations and reset operations. There may be other memory commands.
  • the way in which the controller 10 sends memory commands may depend on the manner in which the device addresses are assigned. Example implementations for assigning the device addresses are provided below.
  • SCLK represents a clock signal and a clock input connection of a memory device
  • SIP represents a serial input port signal and a serial input port connection
  • SOP represents a serial output port signal and a serial output port connection
  • IPE represents an input port enable signal and an input port enable connection
  • OPE represents an output port enable signal and an output port enable connection
  • CS# represents a chip select signal and a chip select input connection or port
  • RST# represents a reset signal and a reset input connection or port.
  • Figures 3A, 3B, 3C, 3D, 3E and 3F show specific example memory systems according to embodiments of the present invention. It is to be understood that these Figures are very specific and are provided for example purposes only.
  • FIG 3A shows a general configuration of an example memory system.
  • a memory system 41 includes a memory controller 50 and a plurality (n+1 ) of memory devices, n being an integer.
  • the memory controller 50 and the memory devices are connected with serial links.
  • the serial interconnection configuration includes first device 80
  • the memory controller 50 has a reset port 51 , a chip select port 52, and a serial clock port 53 connected to each of the memory devices 80, 81 , 82, , and 83 Accordingly, each of the memory devices 80, 81 , 82, , and 83 has a reset port 61 , a chip select port 62, and a serial clock port 63
  • the memory controller 50 has an output interface including a serial output 54, an input enable 55, and output enable 56 connected to the first memory device 80 Accordingly, the first memory device 80 has an input interface including a serial input 64, an input enable 65, and an output enable 66
  • the first memory device 80 also has an output interface including a serial output 67, an input enable echo 68 and an output enable echo 69
  • Each of the other memory devices 81 , 82 and 83 has corresponding input interfaces 64, 65, 66 and output interfaces 67, 68, 69 so that the memory devices 80, 81 , 82
  • the memory controller 50 has components (not shown) similar to those of the memory controller shown in Figure 2B, but they are not shown for sake of simplicity
  • the memory devices 80, 81 , 82, , and 83 have memory-type specific components such as memories 8OA, 81 A, 82A, , and 83A, respectively In the illustrated example, however, their device types are not specified
  • Each of the memory devices 80, 81 , 82, , and 83 has interface circuitry (not shown) between its interfaces and its memory
  • Each of the memory devices 80, 81 , 82, , and 83 also has a register 60 for maintaining an identification of its device type
  • each of the memory devices 80, 81 , 82, , and 83 has alternative circuitry for maintaining the identification of its device type
  • Each of the memory devices 80, 81 , 82, , and 83 may have other components, but they are not shown for sake of simplicity In operation, the memory system 41 operates in a similar manner as the memory system
  • Figure 3B shows a first specific example memory system 42
  • the memory system 42 is similar to the memory system 41 shown in Figure 3B
  • the memory system 42 includes (n+1 ) memory devices 84, 85, 86, , and 87 having the memory cores 84A, 85A, 86A, 87A that are the same as the Figure 3B example
  • the first memory device 84 has a NOR flash memory core 84A and the second, third, , and (n+1 )-th memory devices 85, 86, , and 87 have NAND flash memory cores 85A, 86A, , and 87A, respectively
  • the Figure 3C example differs from the Figure 3B example in that the type-wise addressing scheme is employed, namely the first addressing scheme introduced previously
  • the types plus addresses are indicated as 'NOR-O', 'NAND-O', 'NAND-T, , and 'NAND-(n-i )', assuming there is one NOR device and 'n' NAND devices
  • Figure 3C shows a second specific example memory system 43
  • the memory system 43 is identical to the memory system 42 shown in Figure 3C, except the memory system 43 has different memory devices
  • the memory system 43 includes a plurality (n+1 ) of memory devices 88, 89, 90, , and 91 having mixed memory cores 88A, 89A, 9OA, , and 91 A, respectively
  • the first memory device 88 has an SRAM memory core 88A and the second memory device 89 has a NOR flash memory core 89A
  • the third, and (n+1 )-th memory device 91 have NAND flash memory cores 9OA, , and 91 A, respectively
  • the memory devices are addressed using the type-wise addressing scheme
  • the types plus addresses are indicated as 'SRAM-O', 'NOR-O', 'NAND-O', , and 'NAND-(n-2) ⁇ assuming there is one SRAM device, one NOR device and '(n-1 )' NAND devices
  • Figure 3D shows a third specific example memory system 44 including a plurality (n+1 ) of memory devices
  • the memory system 44 is identical to the memory system 42 shown in Figure 3C, except the memory system 44 has different memory devices 92, 93, , 94 and 95
  • the memory cores 92A, 93A, 94A, and 95A of the memory devices 92, 93, , 94 and 95 are mixed
  • the first, second, third, , and n-th memory devices 92, 93, , and 94 have NAND flash memory cores 92A, 93A, , and 94A, respectively
  • the last ((n+1 )-th) memory device 95 has a NOR flash memory core 95A
  • the memory devices are addressed using the type-wise addressing scheme The types plus addresses are indicated as 'NAND-O', 'NAND-1 ', , 'NAND-(n-i )', and 'NOR-O',
  • Figures 3B - 3E can be implemented with an identical circuit layout, identical memory controller 50, and 'lots' or 'sockets' for the memory devices, assuming that the memory controller 50 is capable of interacting with at least NOR flash devices, NAND flash devices and SRAM devices. Then, an arbitrary arrangement of the supported device types can be installed in the 'lots' or 'sockets', Figures 3B, 3C, 3D and 3E being respective examples of this
  • serial clock is connected in point-to-point ring type scheme with the addition of output echo clock signal, 'SCLK_O'
  • the SCLK is a system clock to synchronize a memory controller 5OA and memory devices 180, 181 , 182, , and 183
  • the echo clock signal output from each memory device is fed to the clock input SCLK of the next memory device
  • the memory controller 5OA and the memory devices 180, 181 , 182, , and 183 operate as a master device and slave devices, respectively
  • the assigned addresses are indicated as 'Dev ⁇ ce-0', 'Device- 1 ', 'Dev ⁇ ce-2', , and 'Device-n', assuming there are (n+1 ) memory devices
  • clocking is based on SDR (Single Data Rate), however, it is to be understood that other appropriate clocking schemes may be contemplated
  • Other appropriate clocking schemes may, for example, include DDR (Double Data Rate), QDR (Quad Data Rate), rising edge SDR or falling edge SDR
  • DDR Double Data Rate
  • QDR Quad Data Rate
  • rising edge SDR rising edge SDR
  • falling edge SDR There may be other appropriate clocking schemes that may be contemplated
  • Figure 3G shows a relative timing sequence for an example SDR operation of memory devices
  • Figure 3G shows operation in one port
  • the operation is that information transferred to the devices 80, 81 , 82, , and 83 can be captured at different times of the clock signal SCLK fed to the serial clock ports 63 the devices
  • information fed to one of the devices at its serial input 64 can be captured at the rising edge of the clock signal SCLK
  • the chip select signal is commonly connected to enable all devices at the same time, so that input data of the first device is transferable through the serial interconnection configuration
  • information fed to the device at the SIP connection may be captured at the falling edge of the clock signal SCLK
  • Figure 3H shows a relative timing sequence for an example DDR operation of memory devices
  • Figure 3H shows operation in one port In the DDR operation, both of the rising and falling edges of the clock signal SCLK can be used to capture information fed to the serial input 64
  • Figure 4A shows an example memory device block used as memory devices shown in Figures 3A - 3E
  • a memory device 140A represents any one of the memory devices and includes a device controller/processor 142A, a device type match determiner 143, a memory 144, a device type register 146, an address match determiner 147, a device address register 148 and an address increment operator 149
  • the device controller/processor 142A controls the operations of the memory device 140A
  • the memory 144 includes any type of memories, such as, for example, NAND flash memory, NOR flash memory, SRAM, DRAM
  • the device type register 146 includes the register 60 for maintaining an identification of its device type as shown in Figures 3A - 3E
  • the device address register 148 holds an assigned device address (DA) by the device controller/processor 142A of that memory device 140A Details of the device type register 146 are shown in Figure 5A
  • the device type match determiner 143 and the address match determiner 147 perform relevant match determination functions under control by the
  • the device 140A has a reset port "RST#”, a chip select port “CS#” and a serial clock port “SCLK” connected to the memory controller (e g , the memory controller 50 as shown in Figure 3A)
  • the device controller/processor 142A is connected to a serial input “SIP”, an input enable “IPE” and an output enable “OPE” of that memory device connected to the previous memory device or the memory controller
  • the device controller/processor 142A is connected to a serial output "SOP”, an input enable echo "IPEQ” and an output enable echo "OPEQ” of that memory device connected to the next memory device
  • the memory 144 corresponds to the flash memory core
  • the device type register 146 corresponds to the type register 60 for maintaining an identification of its device type An example format of a memory command issued by the memory controller is
  • TYPE is a device type for identification of a specific memory device type
  • TDA is a target device address for identification of an address of a specific memory device
  • CMD is an operation command to be executed by the target memory device DATA contains information (a number or value) on process or control for the memory device Examples of various operation commands CMD are shown in Table 1
  • the device controller/processor 142A determines whether the memory command is addressed to that memory device 140A in response to the device type and the device address contained in the serial input (Sl) For example, the device type match determiner 143, under control by the device controller/processor 142A, determines whether the device type ('DTs') in the Sl, matches the device type ('DTr') held in the device type register 146 In a case of a match between them, the device type match determiner 143 provides a type match indication 143M to the device controller/processor 142A Then, the address match determiner 147, under control by the device controller/processor 142A, determines whether the device address ('DAs') contained in the SI matches the device address ('DAr') held in the device address register 148 In a case of a match between them, the address match determiner 147 provides an address match indication 147M to the device controller/processor 142A
  • the device controller/processor 142A in response to the type match indication 143M and the address match indication 147M, the device controller/processor 142A provides the device address (DA) contained in the SI to the address increment operation 149 that perform a calculation of "+1" Thus, a calculated or incremented address (DA+1 ) is outputted to the device controller/processor 142A The incremented device address is fed to the next device through the SOP In a case where neither the type match indication 143M nor the address match indication 147M is provided, the device controller/processor 142A forwards the command over the SOP to the next device
  • the device controller/processor 142A executes the received command contained in the SI In a case where neither the type match indication 143M nor the address match indication 147M is provided, the device controller/processor 142A forwards the command over the SOP to the next device
  • FIG. 4B shows an example memory device used as the memory devices shown in Figure 3F
  • a memory device 140B shown in Figure 4B represents any one of the memory devices shown in Figure 3F
  • the memory device 140B is similar to the memory device 140A shown in Figure 4A
  • a device controller/processor 142B of the memory device 140B includes a clock synchronizer 191 for outputting an output clock synchronized with an input clock that is fed thereto
  • the clock synchronizer 191 may include a phase-locked loop (PLL) or a delay-locked loop (DLL) that provides the output echo clock signal SCLK_O of the clock signal SCLK input from the previous memory device
  • PLL phase-locked loop
  • DLL delay-locked loop
  • Other operations of the device 140B are the same as those of the device 140A shown in Figure 4A
  • each of the memory devices has a register (e g , the device type register 146)
  • Flash memories e g , NAND flash, NOR flash memories) contain factory programmed registers inside the device
  • the eFuse array 121 is shown with an eight-bit configuration of bits 7, 6, 5,
  • first four bits 7 - 4 are OOOO' and second four bits 3 - 0 are '0111 '
  • This represents O7h' ( 00000111 ), for example
  • this configuration indicates a PCRAM memory type
  • Different configurations may indicate different device types
  • 'closed' and 'open' fuses indicate '0' and '1 , respectively
  • Such O' and '1 ' logics are detected by the eFuse level detection logic unit 122 and detected bit status (bits 7 - 0) are provided to the device controller/processor 142A shown in Figure 4A
  • the register block 120 may have conventional poly or metal Fuse, OTP (One Time Programmable memory), or any non-volatile programmable components
  • Figure 5B shows a table of an example encoding scheme for each device type
  • 'RFU' means 'Reserved for Future Usage'
  • the table defines the encoding scheme for each of 10 memory types NAND Flash, NOR Flash, DRAM, SRAM, PSRAM, DiNOR Flash, FeRAM, PCRAM, Serial EEPROM, and MRAM
  • the SRAM memory type has an encoding scheme of '03h'
  • the NAND flash type is assigned as '0Oh'
  • NOR flash type is assigned as '01 h'
  • the bit structure is the MSB (most significant bit) to the LSB (least significant bit) In other implementations, it can be reversed in order, which starts from the LSB first instead of MSB
  • Some register configurations are reserved for future use (RFU)
  • each memory device has a memory type A process for assigning the device addresses with type-dependent addressing is described below with reference to Figure 6A
  • Figure 6A shows a method of assigning device addresses with type-dependent addressing It is to be understood that this process is very specific for example purposes only The method is applicable to any memory system wherein a plurality of memory devices is serially interconnected (e g , the memory system shown in Figure 3B)
  • the memory controller 50 performs a write device address operation for memory devices of device type 'm' (step 6-2)
  • the write device address operation has a target device address (TDA) of '0Oh' because all memory devices have a device address initially set to OOh' during power-up
  • TDA target device address
  • the write device address operation traverses each of the memory devices
  • Each memory device of the device type 'm' is assigned its device address based on the device address indicated by the write device address operation
  • Each memory device that is assigned its device address increments the device address indicated by the write device address operation before forwarding it along to the next memory device Eventually, the write device address operation makes its way back to the memory controller 50 If the write device address operation arrives back at the memory controller 50 as indicated by signals input enable echo (IPEQ) and serial input (SIP) (YES at step 6-3)
  • step 6B the device received the write device address operation determines whether the received device type 'm" matches the device type thereof registered in the device type register 146 (step 6-8) This is performed by the device controller/processor 142A and the device type match determiner 143 If there is a device type match (YES at step 6-8), the device will further determine whether the target device address (TDA) matches the device address registered in the device address register 148 (step 6-9) This is performed by the device controller/processor 142A and the address match determiner 147 If there is a device address match (YES at step 6-9), the received device address will be registered in the device address register 148 (step 6- 10) and the received device address will be incremented (DA+1 ) (step 6-11 ) Such a device address increment is performed by the device controller/processor 142A and the address increment operator 149 If there is no device type match (NO at step 6-8), neither
  • FIGS 7A 1 7B, 7C and 7D show timing sequences for the signals for assigning device addresses with type-dependent addressing
  • the timing diagram shows example signals that may result from a memory system having one NOR-type flash device and 'n' NAND-type flash devices interconnected This sort of memory system is similar to the memory system 42 of Figure 3D
  • memory commands issued by the memory controller are formatted For example, in the memory system only NAND flash devices are assigned with device addresses from "0", the memory command issued by the memory controller is Memory Command (2)
  • TDA identifies devices holding device address "0" when the initialization operations are performed It is presumed that all memory devices of the serial interconnection configuration have been reset to "0"
  • CMD (39h) identifies the operation to be executed is the "write device address" (see Table 1 )
  • the timing diagram includes signals for the input enable (IPE) and the serial input (SIP) for dev ⁇ ce_0 as indicated by 7-2 and 7-3, respectively.
  • the timing diagram includes signals for the input enable (IPE_1 ) and the serial input (SIP_1 ) for dev ⁇ ce_1 as indicated by 7-4 and 7-5, respectively
  • the timing diagram includes signals for the input enable (IPE_2) and the serial input (SIP_2) for dev ⁇ ce_2 as indicated by 7-6 and 7-7, respectively
  • the timing diagram includes signals for the input enable (IPE_n-1 ) and the serial input (SIP_n-1 ) for dev ⁇ ce_(n-1 ) as indicated by 7-8 and 7-9, respectively
  • the timing diagram includes signals for the input enable (IPE_n) and the serial input (SIP_n) for devicejn as indicated by 7-10 and 7- 11 , respectively
  • the timing diagram includes signals for the input enable echo (IPEQ) and the serial output (SOP) for dev ⁇ ce_n,
  • devices _0, _1 , , _(n-1 ) and _n will correspond to the memory devices 92, 93, , 94 and 95, respectively
  • a first write device address operation 7-14 is issued by the memory controller 50
  • the first write device address operation 7-14 indicates a device type of NAND flash
  • the first write device address operation 7-14 traverses each memory device
  • Each NAND flash memory device is assigned its device address based on the device address indicated by the write device address operation
  • Each memory device that is assigned its device address increments the device address indicated by the first write device address operation before forwarding it along to the next memory device
  • There is no increment by the last memory device because this memory device is not a NAND flash device, rather it is a NOR flash device
  • the first write device address operation 7-14 makes it way back to the memory controller
  • the memory controller determines the number of NAND flash devices to be equal to 'n' as indicated by the first write device address operation
  • the memory controller 50 issues an additional write device address operation for each additional device type A second write device address operation 7-15 indicating a device type of NOR flash is issued
  • the memory command for device address assignments of the NOR flash devices is
  • the second write device address operation 7-15 traverses each memory device None of the NAND flash devices increment the device address indicated by the second write device address operation.
  • the last memory device which is a NOR device, is assigned its device address (TDA) as OOh'
  • TDA device address
  • the last memory device also increments the device address indicated by the second write device address operation before forwarding it to the memory controller
  • the memory controller determines that there is one NOR device based on the device address indicated by the second write device address operation
  • TYPE of the memory command issued by the memory controller will be "03h" (see Figure 5B)
  • the memory controller 50 issues a first write device address operation for a device type of NAND flash
  • TYPE NAND flash
  • TDA (0Oh)
  • CMD 39h
  • DATA (0Oh) contained in the SIP
  • the CMD causes the device controller/processor 142A of the device 92 to perform the "write device address" operation
  • Both of the TYPE of the SIP (DTs) and the device type (DTr) held in the device type register 146 are NAND flash and thus, the device type match determiner 143 provides a device type match result ( ⁇ e , the type match indication 143M)
  • the TDA is '0Oh' (DAs) matches the device address (DAr) held in the device address register 148 and thus, the address match determiner
  • the device 94 performs the same operations and is set as "NAND-(n-1 )"
  • the whole instruction (of the SIP_(n-1 )) except the DATA is bypassed
  • These operations are performed during a time period TP1-(n-1 ) between the IPE_(n-1 ) transition to high and the IPE_n transition to high
  • the device 95 does not, however, perform the same operations
  • the device 95 determines no device type match ( ⁇ e , mismatch) and ignores the instruction Therefore, the DATA (nh) remains same for the next device with DATA no-increment
  • the instruction output from the device 95 (the last device) is transferred to the memory controller 50 as a feedback during a time period TP1-SO
  • the memory controller 50 recognizes the total number of the NAND-type devices being "n" from the
  • the memory controller 50 issues a second write device address operation for a device type of NOR flash
  • TYPE NOR flash
  • TDA (0Oh)
  • CMD 39h
  • DATA (0Oh) contained in the SIP
  • the CMD (39h) causes the device controller/processor 142A of the device 92 to perform the device type match determination
  • the TYPE of the SIP (DTs) is NOR flash and the device type (DTr) held in the device type register 146 is NAND flash
  • the device type match determiner 143 provides a no-device type match result (or a mismatch) and the device 92 ignores the received (or input) write device address instruction
  • the DATA remains same with no increment
  • the device 92 (the device controller/processor 142A) forwards the TYPE (NOR flash), TDA (0Oh), CMD (39h) and DATA (0Oh) to the next device 93
  • the device 93 performs the same operations Due to a mismatch of the device type, the device 93 (the device controller/processor 142A) ignores the received instruction (a write device address) and the DATA byte remains same with no increment
  • the device 93 forwards the TYPE (NOR flash), TDA (0Oh), CMD (39h) and DATA (0Oh) contained in the SIP_2 to the next device 94 ( ⁇ e , dev ⁇ ce_2) These operations are performed during a time period TP2-1 between the IPE transition to high and the IPE_2 transition to high
  • the device 94 performs the same functions Due to a mismatch of the device type, the device 94 ignores the write device address and the DATA byte remains same with no increment
  • Both of the TYPE of the SIP (DTs) and the device type (DTr) held in the device type register 146 are NOR flash and thus, the device type match determiner 143 provides a device type match result (i.e., the type match indication 143M). Also, the TDA is '0Oh' (DAs) matches the device address (DAr) held in the device address register 148 and thus, the address match determiner 147 provides a device address match result (i.e., the address match indication 147M).
  • the address increment operator 149 performs an addition of DATA and one to achieve an address increment ("DA+1").
  • the device controller/processor 142A of the device 95 causes the device address register 148 to replace the previously held address with the received address (the value or number of DATA of the SIP), so that the device 95 is set as "NOR-O".
  • the number of DATA of the SIP is replaced by the incremented address number.
  • the whole instruction (of the SIP) except the DATA is bypassed. Therefore, the TYPE (NAND flash), TDA (0Oh), CMD (39h) and incremented DATA (01 h) contained in the SOP is output.
  • the output SOP is transmitted to the memory controller 50. These operations are performed during a time period TP2-n between the IPE_n transition to high and the IPEQ transition to high.
  • the instruction output from the device 95 is transferred to the memory controller 50 as a feedback during a time period TP2-SO.
  • the memory controller 50 recognizes the total number of the NO-type devices being "1 " from the number or value of the DATA.
  • the memory controller 50 issues another write device address operation for another device type. If there is no more device type to be initialized, then the system 44 is ready for the normal operation (e.g., the phase Il as shown in Figure 2C).
  • Example details will now be provided in the context of the examples presented above with reference to Figures 3A - 3F. These details relate to implementations having type- dependent addressing. In these implementations, each memory device has a device type and a device address, both of which are used for addressing purposes. Alternative implementations use type-independent addressing, details of which are provided below under a different section header. It is to be understood that details provided in this section are very specific for example purposes only.
  • FIG. 8 shows a timing sequence for the signals of an example input with type- dependent addressing.
  • This timing diagram is applicable to every memory device of the example memory systems described above with reference to Figures 3A - 3F.
  • signals are plotted for the chip select (CS#) as indicated by 8-1 and the serial clock (SCLK) as indicated by 8-2
  • the timing diagram includes signals for the input interface, namely the input enable (IPE) as indicated by 8-3, the serial input (SIP) as indicated by 8-4, and the output enable (OPE) as indicated by 8-5
  • the timing diagram includes a signal from the output interface, namely the serial output (SOP) as indicated by 8-6
  • the chip select CS# 8-1 is active low' and therefore should be logic 'low' in order to enable all of the memory devices connected in the memory system
  • the SCLK 8-2 is a free running serial clock signal
  • the IPE 8-3 has a transition point from logic low' to logic 'high' indicating the beginning of an input stream in serialized byte mode
  • the memory device receiving IPE 8-3 in the logic 'high' state should be ready to process data streaming through the SIP port in byte mode definition
  • the first byte of SIP 8-4 carries the information of 'Device Type'
  • the first byte includes eight cycles of SCLK 8-2 referenced to the rising edges, MSB (Most Significant Bit) first, LSB (Least Significant Bit) last Following the first byte, the second byte of the SIP 8-4 continues carrying the 'Device Address' information (e g , a target device address (TDA)
  • TDA target device address
  • the third byte follows the second byte carrying the 'Command' information,
  • alignment of a 'serial byte' of the SIP 8-4 along with IPE 8-3 is defined as a series of eight clock cycles using the rising edge of the SCLK 8-2
  • falling edges of the SCLK 8-2 can be used too If both rising edges and falling edges of the SCLK 8-2 are used, then only 4 clock cycles will be necessary for forming one 'serial byte' because of 'double-edges' of clocking
  • One byte includes eight bits, and one bit represents either a state of logic 'high' or logic 'low'
  • the SOP 8-6 is indicated as a logic 'don't care', as the memory device is not enabling data output to the next memory device. However, if the memory device were to be enabling data output to the next memory device, then the memory device would have the output enable (OPE) driven to a logic 'high' state and the SOP 8-6 would not be a logic
  • the byte of the SIP 8-4 carrying the information may the LSB go first and the MSB goes to last position
  • Figure 9 shows a timing sequence of example signaling through two adjacent memory devices This timing diagram is applicable to each pair of adjacent memory devices of the example memory systems described above with reference to Figures 3C, 3D, 3E and 3E
  • the first device named Device 0, and the second device, named Device 1
  • the suffix '_D0' and '_DV in every signal name represent two devices, Device 0 and Device 1 , respectively, for the purpose of description
  • a signal is plotted for the serial clock (SCLK) as indicated by 9-1
  • the timing diagram includes signals for the input interface of Device 0, namely the input enable (IPE_D0), the serial input (SIP_D0) and the output enable (OPE_D0) as indicated by 9- 2, 9-3 and 9-4, respectively
  • the timing diagram includes signals from the output interface of Device 1 , namely the serial output (SOP_D0), the input enable echo (IPEQ_D0) and the output enable echo (OPEQ_D0) as
  • IPE_D0 9-2 transitions to a logic 'high' state on the rising edge of the SCLK 9-1 , which means the beginning of serial data stream-in through SIP_D0 9-3
  • Device 0 starts to receive SIP_D0 9-3 and processes appropriate operation according to the serial stream-in information
  • Device 0 echoes the logic 'high' state of IPE_D0 9-4 to IPEQ_D0 9-6, which is connected to the IPE port of Device 1
  • stream-in data of SIP_D0 9-3 is echoed to SOP_D0 9-5, which is connected to the SOP port of Device 1
  • IPE_D1 9-8 shows the same signal waveforms logically with IPEQ_D0 9-7 signal in Device 0 level because IP
  • any appropriate clock cycle latency may be implemented For example, clock cycle latencies of a half clock cycle, two clock cycles, or more than two clock cycles may be implemented.
  • the clock cycle latency through each memory device determines the total clock latency of the memory system Assuming a one clock cycle latency and four devices in the system, then the last device's SOP_D3, IPEQ_D3 will have four clock cycles of latencies from the original SIP_D0 9-3, IPE_D0 9-2 signals From T13 to T17 in Device 0 level, OPE_D0 9-4 signal is active, causing the serial output operation from Device 0 through the signal SOP_D0 9-5 At time T13, OPE_D0's 9-4 logic 'high' state is detected on the rising edge of SCLK 9-1 , then Device 0 starts to output serial data stream through SOP_D0 9-5 port according to the device's previous condition In this example, Device 0 is selected to output serial data, and Device 1 is not selected, therefore, Device 1 just echoes
  • the output enable echo (OPEQ) 69 from the last device 83, 87 91 , 95 or 99 is connected to the respective memory controller 50 In this manner, the memory controller 50 does not need to count the number of clock latencies, which is determined by the number of interconnected devices The memory controller can detect the rising point of the OPEQ signal from the last device and can decide the starting point of serial data output streaming from the devices in the interconnection. In alternative implementations where the output enable echo (OPEQ) 69 from the last device 83, 87 91 , 95 or 99 is not connected to the memory controller 10, the memory controller 50 may predict based on prior knowledge of clock latencies as to when serial data will be received over the serial input (SIP) 59
  • Figure 10 shows a table of example predetermined formats for memory operations with type-dependent addressing It is to be understood that this table is very specific for example purposes only In the table, TYPE Target Device Type TDA Target Device Address CMD Command Code CA Column Address RA Row Address
  • the table shows varying formats for different memory operations
  • the first byte defines the device type (TYPE) This information can be compared with on-chip pre-programmed device type register values in order to decide whether a serial input stream of data through the SIP port should be processed or not
  • the second column designates the target device addresses (TDA), which is used to distinguish between memory devices of the same device type
  • TDA target device addresses
  • the third byte defines a command definition (CMD) If appropriate (e g , read operations), the 4th, 5th and/or more bytes define row address (RA) and/or column address (CA) information If appropriate (e g , write operations), additional bytes define the data (DATA) transmitted by the operation
  • CMD command definition
  • RA row address
  • CA column address
  • additional bytes define the data (DATA) transmitted by the operation
  • the device type, the device address, and the command are encoded
  • TDA the row address
  • CA column address
  • this device address definition can be expanded using another serial byte(s) as appropriate
  • row address and column address bytes are shown in a similar way as device address format
  • the table definition can alternatively be in reverse order to have the LSB first
  • Figure 12 shows a table of an example encoding scheme for NAND flash commands with type-dependent addressing In the table,
  • each command includes the device type (Device TYPE) which according to the table of Figure 5B is OOh' for the NAND flash memory
  • each command includes the device address (Target DA), which is indicated as 'valid'
  • the device address can identify any device address to select a specific device in the serial interconnection
  • the device address column can be expanded to more bytes if appropriate
  • each command includes a command definition
  • the command definition shown is similar to the conventional NAND flash memory command definition
  • the 4th column and 5th column in the table represents row address and column address, respectively, for selection of a specific row and column location in memory cell array block of NAND flash device As shown in the table some commands do not include row and/or column address
  • the number of bytes for each row and column address range can be changed according to the memory array size for the specific density Row address and column address can be switched in either way Therefore, column address bytes can alternatively be first and row address bytes can follow the column address It depends on a specific memory chip design preference
  • the last column shows an input data column definition for 'write' operation commands, like 'Serial Data Input (8Oh)', 'Random Data Input (85h)' and 'Write Configuration Register (AOh)', for example
  • This input data byte can be as small as one byte or as large as N- bytes according to device specification 'Read Status (7Oh)' command is necessary in order to check the status of each device using the same serial link port SOP, otherwise each device needs separate extra hard pin for the purpose of status indication
  • It also can be changed to different hex-number definition 'Write Device Address (39h)' command is used if the interconnected devices use the soft generated device number instead of hard pin configuration 'Reset (FFh)
  • Figure 13 shows a table of an example encoding scheme for NOR flash command with type-dependent addressing.
  • Table 13 shows a table of an example encoding scheme for NOR flash command with type-dependent addressing.
  • the table of Figure 13 follows a similar format as the table of Figure 12 However, the table of Figure 13 can be seen to have a different set of 12 commands Read, Write To Buffer, Program Buffer to Flash (confirm), Chip Erase, Sector Erase, Program/Erase Suspend,
  • Each command includes the device type (Device TYPE), which according to the table of Figure 5B is '01 h' for the NOR flash memory 'Write DN Entry (39h)' command is used if the interconnected devices use the soft generated device number instead of hard pin configuration
  • the 'Reset (FFh)' command may perform a soft reset function to each selected device This soft reset distinguishes from 'hard reset' using
  • Figure 14 shows a method of processing memory operations with type-dependent addressing. This process shows a general concept A specific command or operation flow chart may be different from this example An operation that does not involve reading or writing data, for example, does not involve transferring data Also, if a command does not involve row or column address, then the memory device does not transfer row/column address bytes When serial signal stream bytes are bypassed through IPE, SIP, OPE or SOP of each device in the interconnection, there is one clock cycle latency delay if bypass circuit is designed with one clock latency
  • the memory device compares the device type indicated by the memory command with its own device type as indicated by its type register (step 14-1 )
  • the memory command is specific to the device type indicated by the memory command If the memory device determines whether the device type of the memory command matches the device type of its register (step 14-2) In a case where there is a type match between the two device types (YES at step 14-2), the memory device further compares the device address indicated by the memory command with its own device address as indicated by its device address register (step 14-3) If the memory device determines whether the device address of the memory command matches the device address of its register (step 14-4) In a case where there is an address match (YES at step 14- 4), the memory device executes the command (step 14-5) Depending on the command, this may involve the memory device processing the row and column address indicated by the memory command, and may also involve processing data received as part of the memory command However, if there is no match in the device type (NO at step 14-2), or
  • FIGS 15A and 15B show timing sequences for the signals for processing memory operations with type-dependent addressing
  • the timing diagram shows example signals that may result from the memory system of Figure 3B, which has one NOR-type flash device 84 and three NAND-type flash devices 85, 86, , and 87 interconnected
  • the memory command for page read of NAND flash devices issued by the memory controller is
  • TYPE (0Oh) identifies "NAND flash” devices (see Figure 5B)
  • TDA (01 h) identifies devices holding device address "1 "
  • CMD (0Oh) identifies the operation to be executed is the "page read” Raw/Column Addresses, instead of DATA, identify the raw and column addresses of the memory
  • the NOR-type flash device 84 is the first device in the interconnection ( ⁇ e , closest to the memory controller 50) It has unique type plus device number (or type plus device identification, or type plus device address) as 'NOR-O'
  • the NAND- type flash devices 85, 86, ,and 87 are connected in series next to the NOR-O device 84, having unique device numbers as 'NAND-O', 'NAND-1 ' and 'NAND-(n-i )'
  • SCLK serial clock
  • the timing diagram includes signals for the serial input (SIP) for each memory device 84, 85, 86, and 87 as indicated by 15-2, 15-3, 15-4, 15-5, respectively
  • the timing diagram includes signals for the output enable (OPE) for each memory device 84, 85, 86, , and 87 as indicated by 15-6, 15-7, 15-8, 15-9,
  • This serial stream of input signals is passed through the devices in sequence, and only the selected device (in this case, NAND-1 ) processes the given 'page read' command inside the device
  • NAND-type flash memory takes much longer time (typically 20 ⁇ s) for internal 'page read operation' which transfers data from the NAND flash cells to data registers block Therefore, the memory controller should wait for that time of 20 ⁇ s
  • the memory controller can access NOR-type flash device, NOR-O, while waiting for NAND-1 's long page read time So, as indicated by 15-16, a 'page read command set for NOR- 0' is issued right after the 'page read command set for NAND-1 ' NOR-type flash memory has very fast read access time, such as 100ns for example, therefore, the memory controller can perform many
  • the operating system copies a page into physical memory only if an attempt is made to access it ( ⁇ e , if a page fault occurs) It follows that a process begins execution with none of its pages in physical memory, and many page faults will occur until most of a process's working set of pages is located in physical memory
  • the final read data output from NOR-O appears on SOP port at NAND-2, which directly connects to the SOP port of the controller after 4 clock cycle latency because the total number of connected memory devices is four
  • the memory controller can access NAND-1
  • the memory controller issues 'page read command set for NAND-1 ' without row/column address bytes, and raises OPE 15-6 signal from logic 'low' to logic 'high' state, which enables output circuitry in NAND-1 device, then read data output from NAND-1 starts to be streamed out through SIP/SOP ports connected in series as indicated by 15-19
  • OPE 15-6 OPE 15-6 signal from logic 'low' to logic 'high' state
  • the device that received the write device address operation determines whether the received device type ('DTs") matches the device type thereof registered in the device type register 146 (step 16-8) If there is a device type match (YES at step 16-8) or a device type match result, then the address match determiner 147 determines whether the target device address (TDA) ( ⁇ e , 'DAs') matches the device address (DAr) registered in the device address register 148 (step 16-9) If there is a device address match (YES at step 16-9) or a device address match result, the device address match determiner 147 outputs the address match indication 147M Then, the received device address ('DA') is incremented by the address increment operator 149 (step 16-10) The incremented address ('DA+1 ') is registered in the device address register 148 (step 16-11 ) and the incremented device address is transmitted to the next device If there is no device type match (NO at step 16-8)
  • Figure 16C shows another device address assignment operation performed by the device of Figure 6A Steps 16-8 and 16-9 of Figure 16C are identical to those of Figure 16B If there is a device type match (YES at step 16-8) and a device address match (YES at step 16-9), the received device address ( 1 DA') is incremented by the address increment operator 149 (step 16-12) The incremented address ('DA+1 ') is registered in the device address register 148 (step 16-13) and the incremented device address is transmitted to the next device (step 16-14)
  • Figure 17 shows another example memory device block used as the memory devices shown in Figure 3F
  • a memory device 140B shown in Figure 17 is similar to the memory device 140A shown in Figure 4A Referring to Figure 17, an address increment operator 149 performs operation in response to a request in the initial phase from the device controller/processor 142B The device 140B performs similar operations to those of Figure 16B The incremented device address provided by the address increment operator 149 is registered in the device address register 148 and transmitted to
  • Figure 18 shows a memory system of two channels according to another embodiment of the present invention
  • a first channel of the memory controller 150 is connected to a first serial interconnection configuration of memory devices 151 that are connected via serial links
  • a second channel of the memory controller 150 is connected to a second serial interconnection configuration of memory devices 152 that are connected via serial links
  • the serial output (SOP), the input enable echo (IPEQ) and the output enable echo (OPEQ) from the last device of each of the serial interconnection configuration 131 are feed backed to the memory controller 150 Details of the first serial interconnection configuration of memory devices 151 are shown in Figure 19A Details of the second serial interconnection configuration of memory devices 152 are shown in Figure 19B
  • the first serial interconnection configuration of memory devices 151 includes (n+1 ) NOR flash memory devices 160, 161 , 162, , and 163 that are serially interconnected
  • the devices 160, 161 , 162, , and 163 have NOR flash memory cores 160A, 161A, 162A, , and 163A, respectively
  • Each of the devices 160, 161 , 162, , and 163 has a register 60 for holding its memory type (NOR flash)
  • the devices 160, 161, 162, , and 163 are assigned device addresses "NOR-O", “NOR-1 ", "NOR-2", , and "NOR-n", respectively
  • the assigned device addresses are held in the registers (not shown) of the devices
  • the second serial interconnection configuration of memory devices 152 includes (n+1 ) NAND flash memory devices 170, 171 , 172, , and 173 that are serially interconnected
  • the devices 170, 171 , 172, , and 173 have NAND flash memory cores 170A, 171A, 172A, , and 173A, respectively
  • Each of the devices 170, 171 , 172, and 173 has a register 60 for holding its memory type (NAND flash)
  • the devices 170, 171 , 172, , and 173 are assigned device addresses "NAND-O", "NAND-1 ", "NAND-2", , and "NAND-n", respectively
  • the assigned device addresses are held in the registers (not shown) of the devices
  • the first serial interconnection configuration of memory devices 151 may include devices of mixed type
  • the second serial interconnection configuration of memory devices 152 may include devices of mixed type
  • FIGs 2OA and 2OB show schematics of other specific example memory devices used in the memory system shown in Figure 16 Referring to Figure 2OA, the first serial interconnection configuration of memory devices
  • the first memory device 210 has a NOR flash memory core 210A and the second, third, , and (n+1 )-th memory devices 211 , 212, , and 213 have NAND flash memory cores 211 A, 212A, , and 213A, respectively
  • the Figure 3C example differs from the Figure 3B example in that the type-wise addressing scheme is employed, namely the first addressing scheme introduced previously The types plus addresses are indicated as 'NOR-O', 'NAND-O', 'NAND-1 ', , and 'NAND-(n-i )', assuming there is one NOR device and 'n' NAND devices
  • the second serial interconnection configuration of memory devices 152 includes a plurality (
  • one memory command e g , the "write device address” command of the SIP is not overlapped with another memory command (e g , the "write device address” command of SIP_1 )
  • the memory commands in the serial inputs to the devices may be overlapped as shown in Figure 21 It requires, however, that the device address (DATA) increment by one device should be completed before the other device performs the address (DATA) increment
  • the transmission of data, information or signals is performed by a single bit or a plurality of bits
  • the data transmission over the serial input SIP and the serial output SOP is performed by a single bit or by a plurality of bits (M bits) as shown in Figure 22, M being an integer greater than one
  • the interface may include a single I/O pin or a plurality of I/O pins
  • Figure 23 shows a memory system according to another embodiment of the present invention
  • the memory system shown in Figure 23 includes a serial interconnection configuration of a plurality of memory devices 351 and a memory controller 350 for controlling operations of the devices Details of memory devices in the configuration are shown in Figure 24
  • the configuration includes (n+1 ) memory devices Dev ⁇ ce-0, Dev ⁇ ce-1 , Dev ⁇ ce-2, — and Device-n
  • Each of the memory devices has a plurality of ports
  • each device is a two port device
  • the memory controller 350 provides a reset signal "RST#", a chip select signal "CS#” and a serial clock signal "SCLK' to the respective ports of each of the memory devices
  • a first memory device (Dev ⁇ ce-0) has a plurality of data input ports (SIP1 , SIP2), a plurality of data output ports (SOP1 , SOP2), a plurality of control input ports (IPE10, IPE2), and a plurality of
  • the devices shown in Figures 4B and 17 can be used in the serial interconnection configuration of memory devices.
  • the clock signal SCLK is required to be transmitted as shown in Figure 3F and each device has a clock synchronization circuit for providing the output echo clock signal, 'SCLK_O' for the next device.
  • the device elements and circuits are connected to each other as shown in the figures, for the sake of simplicity.
  • elements, circuits, etc. may be connected directly to each other.
  • elements, circuits etc. may be connected indirectly to each other through other elements, circuits, etc., necessary for operation of the devices or apparatus.
  • the elements and circuits are directly or indirectly coupled with or connected to each other.

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PCT/CA2007/002182 2006-12-06 2007-12-04 System and method of operating memory devices of mixed type WO2008067658A1 (en)

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KR1020147001536A KR101441280B1 (ko) 2006-12-06 2007-12-04 혼합된 유형의 메모리 장치를 동작시키는 시스템 및 방법
EP07855464A EP2118903A4 (en) 2006-12-06 2007-12-04 SYSTEM AND METHOD FOR OPERATING MIXED TYPE MEMORY ARRANGEMENTS
KR1020127027959A KR101441225B1 (ko) 2006-12-06 2007-12-04 혼합된 유형의 메모리 장치를 동작시키는 시스템 및 방법
KR1020097014049A KR101441154B1 (ko) 2006-12-06 2007-12-04 혼합된 유형의 메모리 장치를 동작시키는 시스템 및 방법
JP2009539576A JP5683813B2 (ja) 2006-12-06 2007-12-04 混合されたタイプのメモリデバイスを動作させるシステムおよび方法

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US86877306P 2006-12-06 2006-12-06
US60/868,773 2006-12-06
US87089206P 2006-12-20 2006-12-20
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US11/622,828 2007-01-12
US11/622,828 US8271758B2 (en) 2006-12-06 2007-01-12 Apparatus and method for producing IDS for interconnected devices of mixed type
US11/771,241 2007-06-29
US11/771,241 US7925854B2 (en) 2006-12-06 2007-06-29 System and method of operating memory devices of mixed type

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JP5351130B2 (ja) 2013-11-27
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JP2014063523A (ja) 2014-04-10
EP2118903A4 (en) 2010-01-06
KR101441225B1 (ko) 2014-09-17
KR20090102787A (ko) 2009-09-30
EP2118903A1 (en) 2009-11-18
JP5695724B2 (ja) 2015-04-08
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