KR101429913B1 - Driving apparatus for liquid crystal display device and method for driving the same - Google Patents

Abstract

The present invention relates to a driving apparatus for a liquid crystal display device and a driving method thereof, which can reduce manufacturing cost by reducing the area of a liquid crystal display device and simplifying the structure thereof by reducing signal transmission pins and signal transmission lines of each driving device A liquid crystal display device comprising a liquid crystal panel formed with a plurality of pixel regions, a gate driver for driving gate lines of the liquid crystal panel, and a timing controller for controlling the gate driver by generating a gate control signal, And the gate driver includes a GOE generator for receiving a gate start pulse and a gate shift clock in the gate control signal to generate a gate output enable signal.

Gate start pulse, gate shift clock, gate output enable signal,

Description

[0001] The present invention relates to a driving apparatus for a liquid crystal display device and a method of driving the same,

The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a liquid crystal display device capable of reducing a signal transmission pin and a signal transmission line of each driving device to reduce an area of a liquid crystal display device, The present invention relates to a driving apparatus of a device and a driving method thereof.

Description of the Related Art [0002] In recent years, lightweight thin flat panel displays have been mainly used as image display devices used in monitors for personal computers, portable terminals, and various information devices. As such flat panel display devices, a liquid crystal display, a light emitting display, a plasma display panel, a field emission display, and the like are emerging.

Among them, the liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel having a plurality of pixel cells and displaying an image, and a driving circuit for driving the liquid crystal panel.

A plurality of gate lines and a plurality of data lines are arranged in an intersecting manner in the liquid crystal panel, and pixel cells are positioned in an area where gate lines and data lines intersect with each other. Pixel electrodes and a common electrode for applying an electric field to each pixel cell are formed. Each of the pixel electrodes is connected to a thin film transistor (TFT) as a switching element. The TFT is turned on by the scan pulse of the gate line so that the data signal of the data line is charged to the pixel electrode.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a timing controller for supplying a control signal for controlling the gate driver and the data driver.

Here, the gate driver has a shift register for sequentially outputting the scan pulses. The shift register is responsive to a gate control signal from the timing controller, for example, a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE) Sequentially generates scan pulses, and sequentially supplies the scan pulses to the gate lines.

Accordingly, in the conventional liquid crystal display device, each of the timing controller and the gate driver is provided with a plurality of pins for supplying or supplying GSP, GSC, and SOE signals. Further, transmission lines for transmitting the GSP, GSC, and SOE signals are provided between the timing controller and the gate driver, which causes a problem that the configuration becomes complicated. Specifically, signal transmission pins (Pin) and signal transmission lines formed in each of the timing controller and the gate driver have complicated configurations to increase the area of the liquid crystal display device and increase the manufacturing cost thereof.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to reduce the area of the liquid crystal display device by simplifying the signal transmission pin and the signal transmission line of each driving device, And it is an object of the present invention to provide a driving apparatus for a liquid crystal display device and a driving method thereof.

According to an aspect of the present invention, there is provided an apparatus for driving a liquid crystal display, including a liquid crystal panel having a plurality of pixel regions, a gate driver for driving gate lines of the liquid crystal panel, And a timing controller for controlling the gate driver, wherein the gate driver includes a GOE generator for receiving a gate start pulse and a gate shift clock of the gate control signal to generate a gate output enable signal .

The gate driver may include a shift register having a plurality of stages connected to one another to output the scan pulse sequentially by shifting the gate start pulse according to the gate shift clock, An output controller for controlling a width of a scan pulse sequentially input according to the gate output enable signal to sequentially output a gate-on voltage, a gate control unit for controlling a level of the gate- On voltage is shifted to a predetermined level in order to prevent the level shifted gate-on voltage from being distorted according to the RC time constant of each gate line, and an output Buffered .

The GOE generator includes an edge detector for detecting a rising edge of the gate shift clock and outputting an edge detection signal when the gate start pulse is input, A counter for counting clock pulses input from the clock oscillator in response to the edge detection signal and outputting a count signal; a counter for counting clock pulses inputted from the clock oscillator in response to the edge detection signal to output a source gate output enable signal And a reverser for inverting the source gate output enable signal and outputting it as the gate output enable signal.

And the count signal is sequentially output to at least 3-bit digital signals. The GOE generator is formed outside the gate driver.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device including a liquid crystal panel having a plurality of pixel regions, a gate driver for driving gate lines of the liquid crystal panel, And a timing controller for controlling the gate driver, wherein the gate driver receives a gate start pulse and a gate shift clock in the gate control signal to generate a gate output enable signal The method comprising the steps of:

Wherein the step of generating the gate output enable signal comprises the steps of detecting a rising edge of the gate shift clock and outputting an edge detection signal when the gate start pulse is input, Counting the clock pulses in accordance with the edge detection signal to output a count signal, and outputting a source gate output enable signal for a preset valid period according to the sequentially input count signal, And outputting the gate output enable signal by inverting the source gate output enable signal.

And the count signal is sequentially output to at least 3-bit digital signals.

The driving device and the driving method of the liquid crystal display device according to the present invention having the above-described features reduce the area of the liquid crystal display device by reducing signal transmission pins and signal transmission lines of each driving device, The manufacturing cost can be reduced.

Hereinafter, a driving apparatus and a driving method of a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram illustrating a liquid crystal display device according to an embodiment of the present invention.

1 includes a liquid crystal panel 2 formed with a plurality of pixel regions, a data driver 4 for driving data lines DL1 to DLm of the liquid crystal panel 2, a liquid crystal panel 2 A gate driver 6 for driving the gate lines GL1 to GLn of the liquid crystal panel 2 and image data RGB input from the outside to the data driver 4 in accordance with driving of the liquid crystal panel 2, And a timing controller 8 for generating the gate control signals GCS and DCS and controlling the data and gate drivers 4 and 6.

Here, the gate driver 6 receives a gate start pulse (GSP) and a gate shift clock (GSC) in the gate control signal from the timing controller 8 and outputs a gate output enable signal GOE Gate Output Enable) signal.

The liquid crystal panel 2 includes a thin film transistor (TFT) formed in each pixel region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, a liquid crystal capacitor (Clc). The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT and a common electrode facing the pixel electrode and the liquid crystal. The TFT supplies data signals from the data lines DL1 to DLm to the pixel electrodes in response to the scan pulses from the gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the data signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage. The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied. The storage capacitor Cst is formed by overlapping the pixel electrode with the previous gate line and the insulating film interposed therebetween. Alternatively, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line and the insulating film interposed therebetween.

The data driver 4 receives a data control signal DCS from the timing controller 8, for example, a source start pulse SSP, a source shift clock SSC, a source output enable SOE (Source Output Enable) signal from the timing controller 8 to an analog voltage, that is, a video signal. Specifically, the data driver 4 latches the image data (Data) input according to the SSC, and then, in response to the SOE signal, applies a scan pulse to each of the gate lines GL1 to GLn, To each of the data lines DL1 to DLm. At this time, the data driver 4 selects a positive or negative gamma voltage having a predetermined level according to the gray level of the image data Data, and supplies the selected gamma voltage to each of the data lines DL1 to DLm as a video signal do.

The gate driver 6 sequentially generates scan pulses in response to a gate control signal GCS from the timing controller 8, for example, GSP and GSC, and generates a scan pulse according to the GOE signal from the GOE generator, . Then, the scan pulses whose pulse widths are controlled are again supplied with the gate-on voltages sequentially to the gate lines GL1 to GLn. Specifically, the gate driver 6 shifts the GSP from the timing controller 8 according to the GSC to sequentially generate scan pulses. On the basis of the GOE signal input from the GOE generation unit, the pulse width of the scan pulses is controlled to sequentially supply the gate-on voltages whose pulse widths are controlled to the gate lines GL1 to GLn. Then, the gate-off voltage is supplied during the period when the gate-on voltage is not supplied to the gate lines GL1 to GLn.

The timing controller 8 arranges image data (RGB) from the outside so as to be suitable for driving the liquid crystal panel 2 and supplies it to the data driver 4. [ A gate control signal GCS and a data control signal DCS are generated using external synchronization signals DCLK, DE, Hsync and Vsync to control the data driver 4 and the gate driver 6 . At this time, the timing controller 8 supplies GSP and GSC to the gate driver 6 with the gate control signal GCS.

2 is a block diagram showing the gate driver of FIG. 1 according to the embodiment of the present invention.

The gate driver 6 shown in FIG. 2 includes a shift register 12 for sequentially generating a scan pulse in response to a gate control signal GCS from the timing controller 8, that is, GSP and GSC, a timing controller 8, A GOE generator 14 for generating a GOE signal using GSP and GSC from the GOE generator 14 and a GOE signal from the GOE generator 14 to control the width of a scan pulse sequentially input to the gate- And Vout1 to Voutn.

The gate driver 6 includes a level shifter for shifting the levels of the gate-on voltages Vdot1 to Voutn to a constant level in order to stabilize the levels of the gate-on voltages Vdot1 to Voutn sequentially output from the output controller 16, The output buffers for amplifying and outputting the gate-on voltages Vdot1 to Voutn to prevent the gate-on voltages Vdot1 to Voutn from the level shifter from being distorted according to the RC time constants of the gate lines GL1 to GLn . The level shifter and the output buffer are provided so as to correspond to the respective gate lines GL1 to GLn.

The shift register 12 has a plurality of stages ST1 to STn which are connected to each other and sequentially shift the GSP inputted from the timing controller 8 according to the GSC to sequentially output scan pulses. Each of the plurality of stages ST1 to STn may be constituted by at least one flip flop F / F and may be constituted by a switching circuit composed of at least one node and an NMOS or PMOS transistor. In addition, the shift register 12 may be constituted by a circuit in which at least one logic operation gate (AND_Gate, OR_Gate, XOR_Gate, NOR_Gate) is combined.

The GOE generating unit 14 detects a rising edge of the GSC when the GSP is input from the timing controller 8. [ The SOE signal is generated by counting self generated clock pulses from the time when the leaking edge is detected. The GOE generating unit 14 will be described in more detail with reference to the accompanying drawings.

The output control unit 16 is provided at the output terminal of each of the plurality of stages ST1 to STn and supplies the width of the scan pulse sequentially input from the plurality of stages ST1 to STn in accordance with the GOE signal from the GOE generating unit 14 And a plurality of AND gates (AND_G) for controlling them. Each of the plurality of AND gates AND_G outputs the respective scan pulses at the gate-on voltages Vdot1 to Voutn during a period in which the GOE signal is input to the high level. The plurality of gate-on voltages Vdot1 to Voutn are supplied to the gate lines GL1 to GLm through the level shifter and the output buffer.

3 is a block diagram showing the GOE generator shown in FIG. 4 is an input / output waveform diagram of the GOE generator shown in FIG.

The GOE generator 14 shown in FIG. 3 includes an edge detector 22 for detecting a rising edge of a GSC when a GSP is inputted from the timing controller 8 and outputting an edge detection signal ED, A clock oscillator 24 for generating a clock pulse CP so as to maintain a constant pulse width by using an input gate driving voltage and a clock oscillator 24 for inputting a clock from the clock oscillator 24 in accordance with an edge detection signal ED from the edge detector 22, A counter 26 for counting the clock pulses CP to output a count signal CS and a count signal CS input from the counter 26 to output a source GOE signal GOE ' A comparator 28 and an inverter 30 for inverting the source GOE signal GOE 'from the comparator 28 and outputting it as a GOE signal.

The edge detecting unit 22 detects a missing edge of the GSC when the GSP is inputted from the timing controller 8, and outputs an edge detecting signal ED. At this time, the edge detection signal ED is output every losing time of the GSC, and the edge detection signal ED is also used as a reset signal of the counter 26.

The clock oscillator 24 continuously generates a clock pulse CP to maintain a constant interval, that is, a constant pulse width, using a gate driving voltage input from the outside, for example, a gate high voltage or a DC driving voltage. At this time, the clock pulse CP may be repeatedly generated such that one period is synchronized with the high period of the edge detection signal ED.

The counter 26 is reset when the edge detection signal ED from the edge detector 22 is input and counts the clock pulses CP input from the clock oscillator 24. Then, the count signal CS is sequentially supplied to the comparator 28. [ Since the count signal CS is output as a digital signal, it may be transmitted with at least three bits of data between the counter 26 and the comparator 28.

The comparator 28 outputs the source GOE signal GOE 'for a predetermined validity period by the user in accordance with the count signal CS sequentially input from the counter 26. [ For example, when the count signal CS is input with 3 bits and the set valid period is set to 3 to 7, in this case, the comparator 28 means 7 from the period in which "011 " It is possible to output the source GOE signal GOE 'at a high or a low level during the period in which "111" is inputted. Hereinafter, only the case where the source GOE signal GOE 'is output at the low level during the above validity period will be described.

The inverter 30 inverts the source GOE signal GOE 'from the comparator 28 and outputs it as a GOE signal, where the inverter 30 uses the source GOE signal GOE' as the GOE signal .

Referring to FIG. 4, a method of generating a GOE signal will be described in more detail as follows.

First, the T1 period is a period during which the edge detection signal ED is generated. In other words, the edge detecting section 22 is reset when the GSP is input from the timing controller 8, and detects the leaking edge of the inputted GSC. Then, an edge detection signal ED having a predetermined pulse width is generated every time the GSC is leased. Here, the pulse width of the edge detection signal ED can be set in advance according to the pulse width of the GSC. This edge detection signal ED is supplied to the counter 26. [

On the other hand, the clock oscillator 24 continuously generates a clock pulse CP using a gate high voltage or a DC driving voltage inputted from the outside to have a constant pulse width. As described above, the clock pulse CP can be repeatedly generated so that one period is synchronized with the high period of the edge detection signal ED. This clock pulse CP is supplied to the counter 26. [

The T2 period is a period in which the counter 26 supplied with the edge detection signal ED counts the clock pulses CP and supplies the count signal CS to the comparator 28 in sequence. That is, the counter 26 is reset when the edge detection signal ED is input, and then sequentially counts the clock pulses CP input from the clock oscillator 24. Then, the counted count signal CS is sequentially supplied to the comparator 28. As described above, the count signal CS is output as a digital signal.

T3 to T4 are periods during which the source GOE signal GOE 'and the GOE signal are output. Specifically, the comparator 28 outputs the source GOE signal GOE 'at a high or a low level for a predetermined validity period (T3 to T4) in accordance with the count signal CS sequentially input from the counter 26. [ FIG. 4 shows a case where the source GOE signal GOE 'is output at a low level during the valid period (T3 to T4). That is, when the effective period is set to 3 to 7, the comparator 28 sets the source GOE signal GOE 'to the low level during a period T4 during which "111" is input from the period T3 during which "011" Output.

On the other hand, the inverter 30 inverts the source GOE signal GOE 'from the comparator 28 and outputs it as a GOE signal. If the source GOE signal GOE 'is output as a high level and the source GOE signal GOE' is used as the GOE signal during the above T3 to T4, the inverter 30 need not be provided.

The GOE generation unit 14 may be configured to generate the GOE generator 14 based on the ratio of the ratio of the ratio of the ratio of the ratio And may be mounted on a display portion or a PCB substrate. When the gate driver 6 is formed of a plurality of gate driving integrated circuits (Gata-IC) and mounted on a circuit film or the like, the GOE generating portion 14 can be embedded in each gate driving integrated circuit (Gata-IC) have.

As described above, the gate driver 4 according to the embodiment of the present invention generates a GOE signal by itself using the GSP and the GSC input as the gate control signal GCS. Then, the gate-on voltage is sequentially output to the gate lines GL1 to GLn using the GOE signal. Accordingly, the liquid crystal display device of the present invention reduces the area of the liquid crystal display device and simplifies the structure of the liquid crystal display device by reducing the signal transmission pins (Pin) and signal transmission lines of the timing controller 8 and the gate driver 4, Can be reduced.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

1 is a configuration diagram illustrating a liquid crystal display device according to an embodiment of the present invention;

2 is a configuration diagram illustrating the gate driver of FIG. 1 according to an embodiment of the present invention;

3 is a block diagram showing the GOE generator shown in FIG. 2. FIG.

4 is an input / output waveform diagram of the GOE generator shown in FIG.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

2: liquid crystal panel 4: data driver

6: Gate driver 8: Timing controller

12: Shift register 14: GOE generator

16: output control section 22: edge detection section

24: clock oscillator 26: counter

28: Comparator 30:

ST1 to STn: First to n < th > stages

Claims (8)

A liquid crystal display comprising a liquid crystal panel formed with a plurality of pixel regions, a gate driver for driving gate lines of the liquid crystal panel, and a timing controller for controlling the gate driver by generating a gate start pulse and a gate shift clock, Wherein the gate driver generates a gate output enable signal by itself using the gate shift clock when the gate start pulse is inputted so that only the gate start pulse and the gate shift clock are supplied from the timing controller, And the driving unit sequentially drives the liquid crystal display device. The method according to claim 1, The gate driver A shift register having a plurality of stages connected to each other to sequentially shift the gate start pulse according to the gate shift clock to sequentially output a scan pulse, A GOE generator for generating a gate output enable signal using the gate start pulse and the gate shift clock, An output controller for controlling a width of a scan pulse sequentially input according to the gate output enable signal to sequentially output a gate-on voltage, A level shifter for shifting the level of the gate-on voltage to a predetermined level in order to stabilize the level of the gate-on voltage, and And an output buffer for amplifying and outputting a gate-on voltage to prevent the level-shifted gate-on voltage from being distorted according to the RC time constant of each gate line. 3. The method of claim 2, The GOE generator An edge detector for detecting a rising edge of the gate shift clock and outputting an edge detection signal when the gate start pulse is input, A clock oscillator for generating a clock pulse so as to maintain a constant pulse width using a gate driving voltage input from the outside, A counter for counting clock pulses input from the clock oscillator according to the edge detection signal and outputting a count signal, A comparator for outputting a source gate output enable signal for a predetermined valid period in accordance with the count signal, And a reverser for inverting the source gate output enable signal and outputting the inverted signal as the gate output enable signal. The method of claim 3, The count signal Wherein the digital signal is sequentially output with at least 3-bit digital signals. 5. The method of claim 4, The GOE generator Wherein the gate driver is formed outside the gate driver. A liquid crystal panel formed with a plurality of pixel regions, a gate driver for driving gate lines of the liquid crystal panel, and a timing controller for controlling the gate driver by generating gate start pulses and gate shift clocks In this case, And the gate driver receiving the gate start pulse and the gate shift clock to generate a gate output enable signal, Wherein the gate driver receives only the gate start pulse and the gate shift clock from the timing controller, and sequentially drives the gate lines. The method according to claim 6, The step of generating the gate output enable signal Detecting a rising edge of the gate shift clock and outputting an edge detection signal when the gate start pulse is input, Generating a clock pulse to maintain a constant pulse width using a gate driving voltage input from the outside, Counting the clock pulses according to the edge detection signal and outputting a count signal, Outputting a source gate output enable signal for a predetermined validity period in accordance with the count signal, and Inverting the source gate output enable signal and outputting the gate output enable signal. 8. The method of claim 7, The count signal And sequentially outputting the digital signals with at least 3-bit digital signals.

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