KR101392609B1 - Apparatus and method for establishing device identifiers for serially interconnected devices - Google Patents

Abstract

The method and apparatus operate multiple devices in a serial interconnect configuration to establish a device identifier (ID) for each device. The input signal is transmitted over the serial interconnection to the first device using an input also used by the first device to input other information (e.g., data, command, control signal). The generating circuit generates the device ID in response to the input signal. The transfer circuit then transmits the output signal associated with the device ID to the second device via the serial output of the first device. The serial output is also used by the first device to output other information (e.g., signals, data) to other devices in the serial interconnect configuration.

Description

[0001] APPARATUS AND METHOD FOR ESTABLISHING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES [0002]

The present invention relates generally to semiconductor device systems. More particularly, the present invention relates to an apparatus and method for establishing a device identifier in synchronization with a clock signal for a serial interconnect configuration of the device.

Nowadays, computer-based systems can be found everywhere and have been extended to many everyday devices such as cell phones, handheld computers, automobiles, medical devices, personal computers and so on. In general, societies rely heavily on computer-based systems to handle everyday tasks, from simple tasks such as checkbook closing to relatively complex tasks such as forecasting weather. As technology advances, more work moves to computer-based systems. This, in turn, makes society more dependent on these systems

A typical computer based system optionally includes one or more peripheral devices such as a system board and a display unit and a disk unit. The system board often includes one or more processors, a memory subsystem, and other circuitry such as a serial device interface, a network device controller, and a hard disk controller.

The type of processor used on a particular system board typically depends on the type of task performed by the system. For example, a system that performs a limited set of tasks, such as monitoring the emissions generated by an automotive engine, and adjusting the air / fuel mixture to ensure that the engine is completely burning the fuel, A simple dedicated processor can be used. On the other hand, a system that performs many different tasks, such as managing a large number of users and running many different applications, is a general-purpose function in nature. It performs high-speed operations and manipulates data to minimize the response time Lt; RTI ID = 0.0 > and / or < / RTI >

A memory subsystem is a storage medium that holds information (e.g., instructions, data values) used by a processor. The memory subsystem typically includes a controller circuit and one or more memory devices. The controller circuit is generally configured to interface the processor with the memory device and enable the processor to store and retrieve the memory device and information. The memory device holds the actual information.

As with a processor, the type of device used in the memory subsystem is often driven by the type of task being performed by the computer system. For example, a computer system may have tasks that need to be booted without the aid of a disk drive, and may execute a set of software routines that do not change often. Here, the memory subsystem may use non-volatile devices, such as flash memory devices, to store software routines. Other computer systems can perform very complex tasks requiring large amounts of high-speed data storage to hold a large portion of the information. Here, the memory subsystem can use a high-speed, high-density DRAM (Dynamic Random Access Memory) device to store information.

Since flash memory devices are suitable for various embedded applications requiring non-volatile storage media, the demand for these devices continues to increase significantly. For example, flash is widely used to store data used by these devices in various consumer devices such as digital cameras, cell phones, USB flash devices, and portable music players. The market demand for flash memory has brought tremendous improvements to flash memory technology in terms of speed and density over the past few years. Because of these improvements, it is expected that applications that continue to use disk drives for mass storage will someday be able to replace hard disk drives with flash memory-based devices.

Some flash devices use a serial interface, such as multiple flash devices, which are used to perform operations such as read, write, and erase operations in a memory included in the device. These operations are generally selected in an apparatus using a command string supplied in series with the apparatus. The command string generally includes commands that indicate the selected operation as well as other parameters. For example, a write operation may be selected by serially supplying an information string to a device that includes a write command, data to be written, and the address of the memory to which the data is to be written.

The command can only be executed on one of the devices, but the command string can be supplied to all devices. To select the device on which the command is to be executed, the command string may include a device identifier (ID) identifying the flash device to which the command points. Each device receiving the command string compares the device ID contained in the command string with the ID associated with the device. If the two match, the device assumes that the command is pointing to the device and executes the command.

The problem with the above described configuration relates to establishing a device ID for each device. A technique that can be used to establish a device ID for a device is to hardwire the device's unique internal device ID with the device. A disadvantage of this approach, however, is that once a large volume of devices is produced, the size of the device ID must be fairly large to ensure that each device contains a unique device ID. Managing a large device ID adds significant complexity to the device, resulting in an increase in the production cost of the device. Also, reclaiming the device ID associated with a device that is no longer in use may add additional complexity to this approach.

Another study of assigning device IDs to devices involves externally hardwiring device IDs for each device. Here, the device ID can be designated by wiring the various pins of the device to a specific state to establish the device ID for the device. The device reads the wired state of the pin and establishes its identity from the read state. However, the disadvantage of this study is that external wiring is required to assign a device ID for each device. This can add, for example, the complexity of a printed circuit board (PCB) holding a memory device. Another disadvantage of this study is that it may require a dedicated pin to allocate the device ID. This can consume valuable resources that can be used better in other ways. Also, a dedicated pin for allocation of the device ID may require a larger footprint for the device than if the pin was not used to allocate the device ID.

One of the proposed solutions for explaining the above-mentioned limitations of the prior art is to provide a device identifier (e.g., a serial number) for the device in a manner that does not require special internal or external hard wiring of the device ID, ID) is automatically established. This technique is disclosed in related U.S. Patent Application No. 11 / 521,734, filed on September 15, 2006, the disclosure of which is incorporated herein by reference in its entirety. In summary, this technique enables the role of the Input Port Enable (IPE) signal to vary based on the device configuration of a single chip, multidrop or serial interconnect. The serial input (SI) and serial output (SO) functions can transmit and receive all data types without time limitation during the associated operation. It also does not require additional pin or pin function changes from the main pin definition. This ID generation and allocation technique depends on the number of available pins and is determined by the number of link ports. Thus, for example, in a multi-independent serial link (MISL), for a single port, the maximum number of supported devices is eight devices. In the case of a dual port, the maximum number of devices is 64 (i.e., 3 pins for one port).

A device and method for establishing a device identifier for a serial interconnect configuration of a device is disclosed. The device may be a memory device such as, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), and a flash memory. Such a serial interconnection may be implemented in a multi-independent serial link (MISL).

The configuration of this technique makes it possible for an identifier to be assigned to a device without requiring an additional hard pin to the device for this purpose. Using the function and timing definitions, the identifier of each device can be automatically generated by an apparatus that includes associated combination logic, such as an adder.

In a first configuration, the present invention provides a device for establishing a device identifier (ID) for a device configured in a serial interconnection configuration having a plurality of devices. The apparatus includes an ID generator for generating a device ID in response to an input signal received at a serial input of the device and outputting the output signal associated with the generated device ID via a serial output of the device in synchronization with the clock.

In one example, the input signal received at the device includes a value associated with the device ID of the device, and the generated device ID associated with the output signal includes a value associated with the device ID of another device in the serial interconnect configuration.

In another example, the input signal received at the device includes a value associated with the device ID of the previous device in a serial interconnection configuration, and the generated device ID associated with the output signal includes a value associated with the device ID of the device in the serial interconnection configuration .

In yet another embodiment, the ID generator comprises an ID calculator (where N is an integer greater than or equal to one) that produces an N-bit ID, generates a calculated value based on the N-bit ID, and a predetermined number, And an ID feeder.

For example, the ID calculator performs calculation for adding 1 to the N-bit ID, and the addition result is supplied as the N-bit ID. Alternatively, the calculation may be performed by subtracting 1 from the N-bit ID, and the subtraction result is supplied as the N-bit ID.

The technique also provides an apparatus for generating a device identifier (ID) for a device coupled to one of a plurality of devices in a serial interconnect configuration. The apparatus may include at least one cell for storing data, a serial input connection for receiving serial input data, and a serial output connection for supplying serial output data. This apparatus comprises: an input register circuit for registering serial N-bit ID data included in serial input data and supplying the registered N-bit ID data as parallel N-bit ID data (N is an integer of 1 or more); A calculation circuit for performing calculations based on the parallel N-bit ID data and the given number data to supply N-bit calculation data; Registering N-bit computed data as parallel N-bit computed data, supplying the registered parallel N-bit computed data as serial N-bit data, wherein the serial N-bit data is stored in an input register Circuit, which is transmitted to the circuit.

For example, the device may be a memory device comprising a calculation circuit having a circuit for adding a given number data to parallel N-bit ID data or subtracting a given number of data from parallel N-bit ID data to generate a new ID Do.

For example, the adding circuit or the subtracting circuit may include an N-bit adder or a subtracter, and performs parallel addition or subtraction. The parallel added or subtracted data is fed to an N-bit parallel-to-serial register, which in turn feeds the serial ID data that is transmitted to the other memory device.

The apparatus may include a selector for selecting serial N-bit data to be supplied to another generator coupled to another memory device, in accordance with the ID generation enable signal. The ID generation enabling signal may be generated in accordance with the command included in the serial input data. The selector may select data derived from the cell to store the data in the memory device and deliver the data to the other memory device, depending on the status of the ID generation enable signal.

In another configuration, the present invention provides an apparatus configured with a serial interconnection arrangement of a plurality of apparatuses, the apparatus comprising a device identifier (ID) establisher for establishing a device ID for the apparatus. The device ID establisher includes an ID generator for generating a device ID in response to a received input signal at a serial input of the device and outputting an output signal associated with the generated device ID via a serial output of the device in synchronization with the clock.

In another configuration, the present invention provides a serial interconnect configuration of a plurality of devices. Each device comprising: a serial input and a serial output, each receiving an input signal and transmitting an output signal; A clock input for receiving a clock signal; (ID) establisher for establishing a device ID for a device, the device ID establisher having an ID generator for generating a device ID in response to an input signal received at a serial input of the device, And is associated with the generated device ID, via the serial output of the device.

In another configuration, the present invention provides a method for establishing a device identifier (ID) for a device configured with a serial interconnect configuration having a plurality of devices. The method includes generating a device ID in response to a serial input signal and outputting a signal associated with the device ID via a serial output of the device. Generation and transmission are synchronous with the clock.

Other configurations and features of the present invention will become apparent to those skilled in the art upon examination of the following description of specific embodiments of the invention in conjunction with the accompanying drawings.

Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings.
FIG. 1A is a block diagram of an apparatus configuration including a plurality of single port devices configured in a serial interconnection configuration in which embodiments of the present invention may be implemented.
Figure 1B is a block diagram illustrating one of the devices shown in Figure 1A.
2A is a block diagram illustrating communications between devices configured in a serial interconnect configuration.
2B is a timing diagram illustrating communications between devices configured in the serial interconnect configuration shown in FIG. 2A.
Figures 3a and 3b are a block diagram of an apparatus using an example of ID generation logic for a single link and a timing diagram of signals for a memory device, respectively.
Figures 4A and 4B are block diagrams and timing diagrams of signals for the device using the example ID generation logic for dual link, respectively.
5A is a high level block diagram that may be used to generate an ID for a device in accordance with an embodiment of the present invention.
5B is a detailed block diagram of the logic shown in FIG. 5A.
Figure 5C is a block diagram of the ID generator shown in Figures 5A and 5B.
6 is a timing chart of the number of devices (DN) registers and clock generation for the command register.
7 is a timing chart of ID generation.
8 is a timing diagram of delay in a normal operation mode.
9A is a timing chart of ID generation controlled by the output port enable signal.
9B is a diagram of ID bit length control by the output port enable signal.
10 is a timing chart of the ID output enable signal, the shift clock signal, and other signals.
11 is a timing diagram of ID generation and related signals.
12A is a block diagram showing an ID temporary register configuration.
12B is a timing chart of the signal for the ID temporary register.
13A is a high-verb block diagram of logic that may be used to generate an ID for a device in accordance with a second embodiment of the present invention.
13B is a detailed block diagram of the logic shown in FIG. 13A.
13C is a block diagram of the ID generator shown in Figs. 13A and 13B.
Fig. 14 is a diagram of ID bit length control by the output port enable signal for the embodiment shown in Fig. 13A.
15A is a high-level block diagram of logic that may be used to generate an ID for a device in accordance with a third embodiment of the present invention.
15B is a detailed block diagram of the logic shown in FIG. 15A.
15C is a block diagram of the ID generator shown in Figs. 15A and 15B.
Fig. 16 is a timing chart of signals for the ID generation logic shown in Fig. 15A.
FIG. 17 is a diagram of ID bit length control by the output port enable signal for the embodiment shown in FIG. 15A.

Generally, the present invention provides a system comprising a plurality of devices in a serial interconnection configuration. An apparatus and method for establishing a device identifier for a serial interconnect configuration of a device is disclosed. Such a serial interconnection may be implemented as a multi-independent serial link (MISL).

The method and apparatus according to the techniques described herein can be applied to a memory system having a plurality of devices of serial interconnection. These devices may be memory devices such as, for example, dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory.

In conventional memory devices, the ID assignment is (0000), (0001), ... , (1111), and so on. Assigning an ID in this manner generally means that pin assignment is necessary to make the connection.

Serialization commands and data applied to the memory device enable fewer pins to be used to perform various functions associated with the device. Assigning an ID to a particular memory device may be done using a serial input enable and output enable signal port associated with the device. Here, the number associated with the device ' s ID may be increased by being sent to each device serially one by one. No complicated timing need be generated. An entry timing and an exit timing may be used for the ID write operation of the device.

In general, the arrangement of the present invention provides a method and apparatus controller for establishing a device identifier (ID) for a device configured in a serial interconnect configuration having a plurality of devices, the device controller comprising: Likewise, in response to the input signal received at the serial input of the first device, a device ID associated with the first device is generated, and in serial interconnection via the serial output of the first device in synchronism with the clock signal, Lt; RTI ID = 0.0 > ID < / RTI >

Embodiments of the present invention will be described with reference to the drawings. In the following description, the same reference numerals are used for signals and input / output connections. For example, reference character CLK denotes a clock signal and a clock input connection, IPE denotes an input port enable signal and an input port enable input connection of the device, and OPE denotes an output port enable signal and an output port enable Where CS # represents the chip select signal and the chip select input connection, IPEQ represents the input port enable input connection of the device and the input port enable output signal, OPEQ represents the output port enable output connection of the device, Output enable output signal.

1A shows an example device configuration including a plurality of single port devices configured in a serial interconnect configuration with various signal inputs and outputs. In this particular embodiment, the device configuration includes four devices 0, 1, 2, 3 (110-1, 110-2, 110-3, 110-4). Each of the interconnected devices 110-1 to 110-4 has the same structure. The memory controller (not shown) is connected to the chip select (CS #), serial input (SI), input port enable (IPE), output port enable (OPE), clock (CLK) (Not shown). The memory system may include a serial interconnect configuration of the device and a memory controller that controls the operation of the serially interconnected devices.

FIG. 1B shows one device 110-i representing any one of the devices 110-1 through 110-4 shown in FIG. 1A. The device 110-i includes a device controller 130 and a memory 120 including, for example, random access memory or flash memory. For example, the random access memory may be a dynamic random access memory (DRAM), a static random access memory (SRAM), or a magnetoresistive random access memory (MRAM), and the flash memory may be a NAND type, a NOR type, an AND type, Flash memory is possible. The device controller 130 has a device identifier (ID) generator 140. The device 110-i has a serial input port (SIP) connection, a serial output port (SOP) connection, a chip select input (CS #), and a clock input (CLK). SIP is used to send information (e.g., command, address, and data information) to the device 110-i. The SOP is used to transfer information from the device 110-i. The CLK input receives the clock signal. The CS # input receives the chip select signal CS # and enables all devices to operate simultaneously. The device controller 130 accesses the memory 120 in accordance with input signals (e.g., SI, IPE, OPE, CLK) to perform various control and processing functions and then accesses the next device 110- (i + And supplies serial output data.

1A and 1B, a SIP and an SOP are configured to allow a SOP of a previous device 110- (i-1) in a serial interconnection to be coupled to a SIP of a device 110-i in a serial interconnection, And is connected between the devices in the configuration. For example, the SOP of device 1 110-1 is coupled to the SIP of device 2 110-2. Each CLK input of the four devices 110-1 to 110-4 is supplied with a clock signal CLK from a memory controller (not shown). The clock signal (CLK) is distributed to all devices over a common link. As will be described in more detail below, the clock signal CLK in particular is used to latch the information input to the device 110-i in the various registers contained therein. The CS # input is a conventional chip select input for selecting a device. The CS # input is coupled to a common link to enable a chip select signal CS # to be simultaneously applied to all devices 110-1 to 110-4, thus selecting all devices.

The device 110-i also has an input port enable (IPE) input, an output port enable (OPE) input, an input port enable output (IPEQ), and an output port enable output (OPEQ). IPE is used to input the input port enable signal IPEi to the device 110-i. Given the IPE, the signal IPEi is used by the device to enable SIP so that the information is input serially to the device 110-i via SIP. Likewise, the OPE is used to input the output port enable signal OPEi to the device 110-i. Given an OPE, an OPEi signal is used by the device to enable the SOP so that information is serially input to the device 110-i via the SOP. IPEQ and OPEQ are output ports for outputting the IPEQi and OPEQi signals from the device 110-i, respectively. The CS # and CLK inputs are coupled to individual links that distribute the chip select signal CS # and the clock signal CLK to the four devices 110-1 to 110-4, respectively, as described above.

SIP and SOP are combined from the previous device 110- (i-1) to the next device 110- (i + 1) in a serial interconnection configuration as described above. In addition, the IPEQ and OPEQ outputs of the previous device 110- (i-1) are coupled to the IPEQ and OPEQ inputs of the previous device 110- (i-1) in a serial interconnect configuration. This arrangement allows IPE and OPE signals to be transmitted from one device to the next in a serial interconnect configuration (e.g., from device 0 (110-1) to device 1 (110-2)).

Information transmitted to the devices 110-1 through 110-4 may be latched at different times of the clock signal CLK supplied to the CLK input. For example, in a single data rate (SDR) implementation, the information input from the SIP to the device 110-i may be latched on the rising or falling edge of the clock signal CLK. Alternatively, in a double data rate (DDR) implementation, the rising and falling edges of the clock signal CLK may be used to latch the information input in the SIP.

The configuration of the devices 110-1 through 110-4 in FIG. 1A is similar to that of the serial interconnects (e.g., inputs SI and outputs SO) and conventional multi-drop connections (e.g., CLK and CS # . Thus, this configuration can be referred to as a hybrid of serial interconnection and multi-drop configurations, and each advantage can be realized.

ID generator 140 generates an ID to establish the device ID for the device in the serial interconnect configuration.

Figures 2a and 2b show three devices 210-1 through 210-3 configured with serial interconnection, with an attached timing diagram indicating the signals transmitted between the devices. The chip select signal CS # (not shown) is given first to select the device. Information is transmitted from the serial interconnection to the first device 210-1 by zooming IPE and clock data to the device 210-1 at successive rising edges of the clock signal CLK. The input port enable signal IPE goes from the first device 210-1 to the second device 210-2 less than one period, as shown by the signal IPE_0. This progress is such that information is clocked in one cycle from the SOP of the first device 210-1 to the SIP input of the second device 210-2 after the information is clocked to the first device 210-1 . This process is repeated for successive devices of the serial interconnection. For example, information is input from the latch point of the data at the first device 210-1 to the third device 210-3 of the serial interconnection at the third rising edge of the clock signal (CLK). Control signals IPE_0, IPE_1, IPE_2 are synchronized with the rising edge of signal CLK to ensure proper setup time for these signals in the next device in the serial interconnection configuration.

Figures 3a and 4a illustrate an example of an operation for generating a device identifier (ID) for a memory device in a serial interconnection configuration for a single and a dual link, respectively. FIG. 3A shows devices 310-1, 310-3, 310-n connected in a single link arrangement, and FIG. 3B shows signal timing for the device shown in FIG. 3A. Similarly, FIG. 4A shows devices 410-1, -, 410-m, 410-n connected in a dual link arrangement, and FIG. 4B shows signal timing for the device shown in FIG. 4A. Here, n is an integer larger than 1, and m is (n-1). In the specific example shown in Figures 3a and 4a, each device comprises a device controller having an ID generator similar to Figure 1b.

The operational example may be applied to generate a device ID using two inputs of the serial interconnection, SIP and SOP inputs, and for use with the other port in the serial interconnection, the first input receiving the serial input and the second The port receives the control signal. ID generation techniques are not limited to MISL applications, and any serial connection configuration (e.g., a daisy-cascade connection) having a plurality of existing input pins, if the serial connection (e.g., daisy chain) Lt; / RTI >

In this example, the IPE has the capability to obtain a serial input stream based on one byte unit, so that the OPE is selected to latch the serial ID input stream after the chip select signal CS # is low again. By the 'write ID start' command, the OPE obtains an input stream configured with a period equal to the total number of ID bits. The ID bit is established by the size of the internal ID register. For example, if the device has a 12-bit ID register, the OPE remains high for 12 periods. A 12-bit device ID allows up to 4096 addresses in a serial interconnect. Thus, this embodiment can mount a large number of devices in a serial interconnection configuration, and the number is not limited by the number of pins of each device. In addition, each device does not require the added complexity of the internal hardwired device ID.

In Figures 3B and 4B, the ID generation mode setup period, referred to as "IDGMS ", is defined by the ID bit length + 8 cycles (command bit length) + predefined clock cycles corresponding to the assumed number of devices interconnected in series It is an equal time interval.

For signal transmission between OPE input and OPEQ output, op1 and op2, non-overlapping time intervals greater than two cycles must occur to avoid motion conflicts caused by ID increase and data transmission to adjacent adjacent devices. After the OPE is given in each of the devices 310-1, 310-n, the latched ID input data is stored in the device's ID register (which is referred to as "516 " in FIG. 5A) An increment operation with this input is performed. The function of the OPE signal is to determine the number of ID bits from the 1 bit to the maximum number of finite bits of the ID register to each memory device. If the number of ID bits is equal to the number of defined bits in the ID register ("fixed ID bit"), the order of the ID bits is irrelevant. However, in all other cases, the signals corresponding to the device ID must be transmitted in order starting with the least significant bit (LSB) and ending with the most significant bit (MSB), which will be explained later.

Figures 5A and 5B illustrate logic examples associated with generation of an ID of a device controller 500 within a device 110-i configured with serial interconnection. The clock generator 501 receives the clock signal supplied to the CLK input of the apparatus, and supplies an internal clock signal including "Clk_cmd" and "Clk_dn ". The command clock 'clk_cmd' is given a number of times equal to the bit length of the command serial bits. As shown in FIG. 6, for example, if the memory system has a command on a byte basis, clk_cmd needs 8 clock cycles to latch the serial command bit, and latches the latched data until the next command is received . The device number (DN) clock 'clk_dn' clocks the ID input, which is stored in the input DN register 504 and the ID temporary register 518. The sequence for receiving and storing the signal received at the SIP input corresponds to a predetermined sequence. For example, the device may be configured to first receive a signal corresponding to a device ID, and then receive a command bit. As a result of this sequence, the number of cycles of clk_dn is generated, and clk_cmd is established by the clock generator 501.

To decode the command bits, the serial input command stream is shifted to the command register 502 in accordance with the command clock 'clk_cmd', and the command register 502 then registers the registered M bit command data to the command interpreter 503 in parallel . The command interpreter 503 is a command decoder and delivers an internal command signal to start additional control. These two command signals (cmd_wr_id_entry, cmd_wr_id_exit) are shown to start and stop the ID generation mode.

Prior to the ID write generator establishing the command 'write ID start', the memory controller (not shown) sends a reset signal to reset the input of the device in the serial interconnection configuration. The reset input is connected in common. All devices in the serial interconnect configuration are reset by a reset signal. Upon reset, all devices are enabled to accept the 'write ID start' command by default, and all devices have a default ID of '0'. As a result, all devices in the serial interconnect can be selected at the same time, and command 'write ID start' commands all devices by having a command 'ID number' of '0'.

The input DN register 504 stores the input ID data from the previous device. During normal operation (rather than in the ID generation mode), the input DN register 504 temporarily stores the contents of the input ID stream from the SIP to be compared with the device ID number in the N-bit ID register 56 (e.g., a 10-bit register) . During device ID generation, input DN register 504 does not receive serial input data. Instead, the ID temporary register 518 obtains the serial data and sends it to the ID generator or establisher illustrated in the ID generation enable block 506. [ The number of bits N is an integer equal to the number of bits in the ID number and may be equal to any number suitable for identifying all devices in the serial interconnection.

ID comparator 505 serves to identify data and commands addressed to the device during normal device operation. The comparator 505 compares the ID number of each incoming data in the input DN register 504 with the device ID stored in the N bit ID register 516 and provides an 'ID_match' signal. If the ID numbers are the same or match, the signal 'ID_match' is equal to '1'. Otherwise, this signal is equal to '0'. As a result, each device in the serial interconnection matches the incoming ID number with the device ID stored in each device to determine if the signal is addressed.

Figure 5C shows the ID generator 600 of the device controller 500 of Figures 5A and 5B. ID generation enable unit 506 outputs the N bit input of ID temporary register 518 to N bit adder 508 (e.g., an " id_gen_en " For example, a 10-bit adder), and an N-bit ID register 516. An example of signal timing for the ID generation enable signal is shown in Fig. This simultaneous transmission prevents unnecessary signal changes of the N-bit adder 508 and the N-bit ID register 516. [ The device ID is stored in the ID register 516 according to the sequence of the device ID and the word length. For example, if the N bit ID register 516 is 10 bits long and the OPE signal has 5 cycles high, the N bit ID register 516 stores the 5 bit device ID, The signal is sent to the next device. The remaining bits in the ID register 516 are ignored, and thus remain at a value of '0' or 'do not care'.

During the ID generation process, in the example described above, the N-bit serial input is first stored in the ID temporary register 518 before being transferred to the N-bit adder 508 and the N-bit ID register 516. [ Simultaneous transmission from the temporary register overcomes the limit of the serial-parallel (STP) register. For example, consider the case where the number of ID bits (e.g., 5 bits) is smaller than the number of bits of the ID register and the adder (e.g., 10 bits). During ID generation and assignment processing, 5 bits (bits 0 (LSB) to 4 (MSB)) are loaded into the first 5 bits of the STP register and supplied in parallel to the 10-bit adder. As will be readily apparent to those skilled in the art, the LSB is loaded into bit 4 of the register and does not correspond to the LSB of the adder. Although the order of the bits is reserved from the MSB (bit 0) to the LSB (bit 4), the position of the MSB in the STP register does not correspond to the MSB position of the 10 bit adder. Therefore, regardless of which bits are assigned as the first bit, the conventional STP register results in generating a faulty device ID. This limitation of the STP register ensures that the bits corresponding to the device ID are transmitted to the next device in the order starting from the LSB and ending with the MSB, as will be discussed in detail later with reference to Figures 12A and 12B, (In the LSB of the ID temporary register 518 to bit 0) in the order received in the register.

The ID generation controller 507 receives the input signals CS # (CS_en), cmd_wr_id_entry, and cmd_wr_id_exit, and transmits an 'id_gen_en' signal to start the ID generation mode. For example, if the signal CS # is toggled low to high and low (see FIG. 7), the signal 'id_gen_en' is given and the signal cmd_wr_id_entry is given. As will be apparent to those skilled in the art, any other modification of the signal CS # may be given an 'id_gen_en'.

8 shows the delay of the normal operation. Basically, MISL has one cycle delay between two adjacent devices. However, the 'write ID entry' command changes the path from one cycle delay to 'ID bit (ID register bit size) + two cycles', as shown in FIG. 9A described later.

9A and 9B show the logic and signal timing of ID generation control by an output port enable (OPE) signal. In these operations, the ID bit length is determined by the length of the OPE signal high, and can be applied to a serial interconnection configuration that includes different numbers of devices. The function of the OPE signal is described below with reference to Figs. 5A, 5B and 5C. Alternatively, the OPE signal is not required to determine the ID bit length, but instead may be determined by a predetermined value, the bit size of the ID register 516, or a value associated with another signal.

9B, the ID feeder illustrated as a 10-bit ID temporary register 518, a 10-bit ID register 516, a 10-bit adder 508, a 10-bit parallel-to-serial register 510, Respectively. The functions of these registers are described below with reference to Figures 5A, 5B and 5C. The maximum device ID number is determined by the bit size of the internal adder 508 and the parallel-to-serial register 510. In addition, the device ID number reflects the maximum number of devices that can be connected in a serial interconnection configuration. For example, a 10 bit device ID allows up to 1024 devices to be connected to the serial bus in a single serial interconnection scheme.

Alternatively, the OPE input may be configured to obtain an input data stream of the ID number of the previous device rather than IPE. This additional function of the OPE input provides a simple timing for the ID generation mode. 3a and 4a, a write ID entry is given and the chip select signal CS # is toggled from low to high again to low as shown in Figures 3b and 4b , The OPE is given a high state for the same amount of time as the bit length of the ID register incorporated in each memory device.

5A through 5C and 9B, the ID write generator 517 generates the 'wr_id_en' signal and latches the output of the ID generation enable block 506 to the N bit ID register 516 in the ID generation mode . This signal is set by the falling edge of the OPE signal.

The N-bit adder 508, which is a static adder, performs the add operation of the input of the ID generator 506 and the fixed constant (for example, "+1") as shown in FIG. 5A. For example, if N is 8, the adder may calculate the sum of the number of 8 bits from the ID temporary register 518 and the integer 10000000 (the order of LSB to MSB). As a result, adder 508 generates the next number in the sequence of device ID numbers. The adder 508 may be replaced by another logic circuit that performs the same '+1' operation. In addition, the logic 500 may be configured to perform other operations on N-bit numbers, such as subtraction (described later) or addition of other integers, to produce a continuous device ID.

The resulting ID data is written to the parallel-to-serial register 510 and transmitted as a serial signal to the next device via the SOP output. The serial ID number may be used by the next device as its device ID, or it may be operated by the next device to generate the device ID. Alternatively, the logic may include additional operations to change the serial ID number, and the result is given as being associated with the device ID stored in the N-bit ID register 516. [

In the parallel-to-serial register 510, the inputs are transmitted in parallel and the outputs are transmitted in series. Serial data write generator 509 supplies a 'wr_data_pts' signal to activate the parallel input path of the parallel-to-serial register 510, in accordance with the 'id_gen_en' signal from the ID generation controller 507. The path is disabled after the rising edge of the first clock cycle of shift_clock with some delay to serially transmit the ID data through the SOP. The LSB bit is the first bit to be transmitted, and the MSB is the last bit to be transmitted.

A selector (e.g., a multiplexer) 511S selects one of the two paths according to the id_gen_en signal. 0 ", that is, Sdata (serial read data from the memory cell) of the selector 511S is supplied as the SOP to the output buffer 515S if id_gen_en is 0, that is, in the normal operation mode, As a SIP. Otherwise, the bottom input path '1' is selected, that is, the Sdata_id (serial id data) is supplied as an SOP to the output buffer 515S, and as shown in FIG. 5b, And functions as an SIP.

It must be clocked to the clock signal to send the ID number to the next device in series. The data shift clock generator 512 synchronizes the signal 'Sdata_id' (serial ID data) with the clock by transmitting the clock signal 'shift_clock' to the parallel-to-serial register 510.

The shift register unit 513 supplies an ID output enable signal ('id_out_en') generated to notify the number of shift clock cycles. The shift register unit 513 shifts the OPE signal by the number of bits obtained by adding two periods to the bit length of the ID register so as to provide sufficient time margin for serial data latching and addition operations. The shift register unit 513 includes a one-period shift register and an (N + 2) -speed shift register for shifting the signal 'opei' and supplying the shifted 'opei' to a selector (for example, a multiplexer) Lt; / RTI > In addition, the shift register unit 513 includes a (N + 1) period shift register having an additional one-period shift register and supplies the shifted signal 'opei' to the OR gate. The resultant signal 'id_out_en' is supplied to the data shift clock generator 512.

The signal 'id_out_en' enables the signal 'shift_clock' in the data shift clock generator 512 so that the shift clock is generated one cycle earlier than the OPEQ signal is generated. 10, this function assures the proper timing of the signal because the next device latches the data in the first clock signal (i.e., the OPEQ signal in the previous device) superimposed by the OPE signal . A shift clock is generated for a period of the total period plus one period of the number of ID bits so that previous data is not reliably maintained and a continuous device receives an incorrect ID number from the SOP of the current device. Fig. 11 shows the timing of various signals associated with the ID generation processing described here with reference to the examples shown in Figs. 5A, 5B and 5C.

The device controller 500 for ID generation also includes a plurality of input buffers. One input buffer 514-1 receives the chip select signal CS #, and the buffered output signal is inverted by the inverter. The inverted CS # signal is supplied to the ID generation controller 507 as 'CS_en'. The other input buffer 514-2 receives the SI from the SIP input and provides it to the command register 502, the input DN register 504 and the ID temporary register 518. The other input buffer 514-3 receives the clock signal 'Clock', and the buffered output signal 'Clocki' is supplied to the clock generator 501. The other input buffers 514-4 and 514-5 receive IPE and OPE, respectively, and the buffered output signal is supplied to the selector 511E, and the selected output signal is supplied to the clock generator 501. [

In addition, the device controller 500 includes an output buffer 515Q that provides an OPEQ signal to the OPE input of the next device (not shown). The OPEQ signal is a selected output signal from a selector (e.g., multiplexer) 511Q that selects one of the output signals from the 1-cycle shift register and (N + 2) -th shift register of the shift register unit 513. The selected output signal (i.e., the OPEQ signal) is transmitted to the OPE input of the next device.

For example, referring to Figures 3A (and 4A), 3B (and 4B) and 5A-5C, SI) is stored in the N-bit ID register 516. [ The N-bit adder 508 of the device 310-1 (410-1) adds +1 to the original ID number and outputs the '10000' output data of the N-bit adder 508 to the parallel-to-serial register 510 Latch. The selector 511Q supplies '10000' to the output buffer 515S as the SOP '10000', and is supplied to the SIP of the next device 310-2 (410-2). The received ID number '10000' (of SI) is stored in N bit ID register 516 of device 310-2 (410-2), and a '+1' addition is performed in N bit adder 508 . The '01000' output data of the N-bit adder 508 is latched into the parallel-to-serial register 510 of the device 310-2 (410-2). The selector 511Q supplies '01000' to the output buffer 515S as SOP '01000', and is supplied to the SIP of the next device 310-3 (410-3). The received ID number '01000' is stored in the N-bit ID register 516 of the device 310-3 (410-3). This process continues until the last device 310-n (410-n) is reached. All bit sequences follow the LSB first and MSB final rules for the ID generation mode. Thus, the device ID assigned to each device is the same as the received ID. The generated ID ('+ 1' added ID or calculated ID) is supplied to the SIP of the next device in the serial interconnection configuration.

Table 1 shows the device according to the above-described embodiment and the assigned ID (LSB? MSB).

Table 1

Device number Assigned ID

First device 00000

Second device 10000

Third device 01000

The fourth device 00100

Fifth device 00000

  ... ...

31st device 01111

32nd Apparatus 11111

The N bit ID register 516 is filled with the ID number in the ID generation mode. This content is reset to the initial value setting, for example, by a hard reset pin. The contents of the N bit ID register 516 are compared to the input ID stream of the input DN register 504 at the beginning of any normal operation.

In the ID generation mode (as opposed to normal operation), the device ID value and bit size can be interchanged and are determined according to the length of time that the OPE signal is given. The ID temporary register 518 has this function by storing each serial bit at a specified bit position without serial data transmission.

Figure 12A shows the ID temporary register 518 shown in Figures 5A-5C. 12B shows signal timing for the ID temporary register 518. FIG. Referring to Figures 5A-5C and 12A and 12B, the ID temporary register 518 has (n + 1) bit storage corresponding to the (n + 1) clock control. According to the DN clock 'clk_dn', the (n + 1) clock control unit supplies 'clk0' to 'clk (n)' supplied to the (n + 1) bit storage units, respectively. The serial input SI is supplied in parallel to the (n + 1) bit storage storing the SI data according to clocks clk0 to clk (n). The stored data is supplied as bit data 'bit0' to 'bit (n)'.

Note that the N-bit adder 508 provides one way to increase the received ID number. When executed in multiple devices in a serial interconnect configuration, the ID generation logic has a cumulative effect of supplying a unique device ID for each device, and the device ID is incremented by '1' in each device. Alternatively, various logic may be substituted for the n-bit adder 508 to generate a unique device ID in each device.

In another example, the ID generation logic associated with generating an ID of a device controller establishes a device ID as a result of the N-bit operation. This other example requires that the output of the N-bit adder 508 is transferred to the N-bit ID register 516 and the N-bit ID register 516 stores a value other than the received ID number, The device ID is established for the device, as shown in FIG. The ID generator 710 of the device controller 700 of Figures 13A and 13B is shown in Figure 13C. 14, an ID provider, illustrated as a 10 bit ID temporary register 518, a 10 bit ID register 516, a 10 bit adder 508, and a 10 bit parallel-to-serial register 510, Lt; / RTI > 9B, the 10-bit ID temporary register 518 sends the ID bit to the 10-bit adder 508. [ The ID added or calculated by the 10-bit adder 508 is supplied to the 10-bit ID register 516 and the 10-bit parallel-to-serial register 510. All other operations of the device controller 700 shown in Figures 13A and 13B are similar to the device controller 500 previously described.

To further illustrate the embodiment, for example, referring to Figures 3A (and 4A), Figures 13A-13C, and 14, apparatus 310-1 (410-1) . The N-bit adder 508 adds +1 to the SIP input and latches the '10000' output data of the N-bit adder 508 into the N-bit ID register 516. The selector 511Q supplies '10000' to the output buffer 515S as the SOP '10000', and is supplied to the SIP of the next device 310-2 (410-2). The sum of '10000' (of SI) and '+1' received from the device 310-2 (410-2) is added. The '01000' output data of the N-bit adder is latched in the N-bit ID register 516 and the parallel-to-serial register 510. The selector 511Q supplies '01000' to the output buffer 515S as SOP '01000', and is supplied to the SIP of the next device 310-3 (410-3). This process continues until the final device 310-n (410-n) is reached. All bit sequences follow the LSB first and MSB final rules for the ID generation mode. Thus, the device ID assigned to each device is not the same as the received ID. The generated ID ('+ 1' added ID or calculated ID) is assigned to the current device and is supplied to the SIP of the next device in the serial interconnection configuration.

Table 2 shows the devices and assigned IDs (LSB? MSB) according to Figs. 13A and 13B.

Table 2

Device number ID received ID assigned ID

First device 00000 00000

Second device 10000 01000

Third device 01000 11000

The fourth device 11000 00100

Fifth device 00100 10100

  ... ... ...

31st device 01111 11111

In another embodiment, the ID generation logic associated with generating an ID of a device controller establishes a device ID as a result of an N-bit subtraction operation. For example, as shown in FIGS. 15A and 15B, an 'N-bit subtractor' subtracts '1' from the received ID number. The ID generator 810 of the device controller 800 of Figures 15A and 15B is shown in Figure 15C. The device controller 800 has an N-bit subtractor 708 instead of the N-bit adder 508 shown in Figures 15B and 13B.

Referring to FIGS. 3A to 3B, 4A to 4B and 15A to 15C, the input ID number or value '11111' of the SIP received by the device 310-1 (410-1) is stored in the N-bit ID register 516 do. The N-bit subtractor 708 subtracts 1 from the SIP input and latches the '11110' output data of the N-bit subtractor 708 into the parallel-to-serial register 510. The selector 511Q supplies '11110' to the output buffer 515Q as SOP '11110' and is supplied to the SIP of the next device 310-2 (410-2). '11110' (of SI) is stored in N bit ID register 516 of device 310-2 (410-2), and a '-1' subtraction is performed in N bit subtractor 708. The '11101' output data of the N-bit subtractor 708 is latched into the parallel-to-serial register 510. The selector 511Q supplies '11101' to the output buffer 515S as SOP '11101', and is supplied to the SIP of the next device 310-3 (410-3). This process continues until the final device 310-n (410-n) is reached. All bit sequences follow the LSB first and MSB final rules for the ID generation mode. Thus, the device ID assigned to each device is the same as the received ID. The generated ID ('-1' subtracted ID or calculated ID) is supplied to the SIP of the next device in the serial interconnection configuration.

Table 3 shows the device according to the above-described embodiment and the assigned ID (LSB? MSB).

Table 3

Device number Assigned ID

The first device 11111

The second device 01111

Third device 10111

The fourth device 00111

The fifth device 11011

  ... ...

31st apparatus 10000

32nd device 00000

Due to the "count-down" ID generation of this embodiment, the timing of the signal is different from that shown in Fig. Fig. 16 shows the timing of various signals associated with the ID generation processing described herein with reference to the embodiment shown in Figs. 15A, 15B, and 15C. FIG. 17 shows ID bit length control by the OPE signal in the embodiment shown in FIG. 15A.

15A-15C, 16, and 17, the 10-bit ID temporary register 518 sends the ID bit to a 10-bit register 516 and a 10-bit subtractor 708. The ID, which is subtracted or calculated by the subtractor 708, is supplied to a 10-bit parallel-to-serial register 510. All other operations of the device controller 800 are similar to the embodiments of Figs. 15a-b and 13a-b previously described.

It will be apparent to those skilled in the art to implement the embodiment shown in Figures 13a, 13b, 13c with the N-bit subtractor 708 shown in Figures 15a, 15b, 15c. Table 4 shows the device according to the above-described embodiment and the assigned ID (LSB? MSB).

Table 4

Device number ID received ID assigned ID

First device 11111 01111

Second device 01111 10111

Third device 10111 00111

The fourth device 00111 11011

The fifth device 11011 11010

  ... ... ...

31st apparatus 10000 00000

Similarly, it is clear that an integer other than '1' is added to or subtracted from the received ID number to implement a system that provides a discontinuous sequence of device ID numbers for a set of devices.

The above-described ID generation logic and method may be incorporated into a memory device, such as a flash memory device, which requires a device identifier without an external hard pin assignment, for example. In addition, embodiments of the ID generation logic may be implemented as a single or separate device to support the generation of an ID of any memory device. For a single device implementation, the pin assignment is changed according to the internal signal request of the selected memory device.

The above embodiments of device ID generation may be varied for implementation in many different systems without departing from the principles described herein. For example, referring to Figures 5A and 5B, a command based on 'write ID start' may be introduced with 'write ID end' by CS # change from low to high and back to low. Also, one designated pin can be assigned to receive the 'start mode enable', replacing the role of command 'write ID start'.

Another way to terminate ID generation is to use a shutdown command or an internal shutdown logic execution on the device instead of a CS # change.

Independent of the flash memory including the Multi-Independent Serial Link (MISL), the techniques described herein may be applied to any device in a serial interconnection configuration that requires an ID number to select one of the connected devices Can be applied.

There are many variations in the example. The active "high" or "low" logic signal can each be changed to an active "low" The "high" and "low" states of the signal can be represented by the low and high supply voltages Vss and Vdd, respectively.

In the example described above, device elements and circuits are connected to each other for simplicity, as shown in the figure. In practically applying this technology to a memory system, devices, elements, circuits, and the like can be directly connected or coupled to each other. In addition, elements, circuits, and the like may be indirectly connected or coupled to each other through other devices, elements, circuits, and the like as necessary for the operation of the memory system.

In the foregoing description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. It will be apparent, however, to one skilled in the art, that these specific details are not required to practice the present invention. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the present invention. For example, no specific details are provided as to whether the embodiments of the invention described herein are implemented as software routines, hardware circuits, firmware, or combinations thereof.

The above-described embodiments of the present invention are for illustrative purposes only. Modifications, modifications, and variations may be effected to the specific embodiments by those skilled in the art without departing from the scope of the invention, which is defined only by the appended claims.

Claims (7)

A method for establishing a device identifier (ID) for a device configured as a serially coupled configuration having a plurality of devices including at least first and second semiconductor memory devices,
In the first semiconductor memory device,
Receiving an input signal comprising a first ID value,
Generating a device ID based on the first ID value,
Supplying an output signal comprising a second ID value corresponding to the generated device ID, and
Storing the first ID value as an assigned ID for the first semiconductor memory device in response to a first ID store signal; Also,
In the second semiconductor memory device,
Receiving an input signal derived from the output signal including the second ID value supplied from the first semiconductor memory device,
Generating a device ID based on the second ID value,
Supplying an output signal comprising a third ID value corresponding to the generated device ID, and
Storing the second ID value as an assigned ID for the second semiconductor memory device in response to a second ID store signal
And establishing a device identifier. The method according to claim 1, wherein the second semiconductor memory device latches the second ID value based on both rising and falling edges of a clock signal received in the second semiconductor memory device. A method for establishing a device identifier (ID) for a device configured as a serially coupled configuration having a plurality of devices including at least a first and a second device,
In the first device,
Receiving an input signal comprising a first ID value,
Generating a device ID based on the first ID value,
Supplying an output signal including a second ID value corresponding to the generated device ID,
Storing the second ID value as an assigned ID for the first device; Also,
In the second device,
Receiving an input signal derived from the output signal including the second ID value supplied from the first device,
Generating a device ID based on the second ID value,
Supplying an output signal comprising a third ID value corresponding to the generated device ID, and
Storing the third ID value as an assigned ID for the second device
And establishing a device identifier. 4. The method of claim 3, wherein the second device latches the third ID value based on both rising and falling edges of a clock signal received at the second device. The method of any one of claims 1 to 4, wherein the plurality of devices in the configuration coupled in series are coupled with a serial connection link. The method of claim 5, wherein the first ID value is represented by an M-bit signal, the second ID value is represented by an N-bit signal, and M and N are integers. 7. The method of claim 6, wherein generating the device ID comprises calculating a predetermined value and the M bit value.

Images