JP2012208948A - Device and method for establishing device identifier for serially interconnected device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method or device for establishing a device identifier (ID) for each device by operating many devices in a serial interconnection configuration.SOLUTION: An input signal is transmitted to a first device through a serial interconnection by using an input, and the input is used by the first device to input other information (for example, data, a command, and a control signal) thereto. A generation circuit generates a device ID in response to the input signal. Then, a transfer circuit transfers an output signal associated with the device ID to a second device through a serial output of the first device. The serial output is also used by the first device to output other information (for example, a signal and data) to another device in a serial interconnection configuration.

Description

  The present invention generally relates to semiconductor device systems. More particularly, the present invention relates to an apparatus and method for establishing a device identifier in synchronization with a clock signal for a serial interconnect configuration of devices.

  Today, computer-based systems can be found everywhere and have entered many everyday devices, such as mobile phones, handheld computers, automobiles, medical devices, personal computers, and the like. Overall, society relies heavily on computer-based systems to handle everyday tasks, from simple tasks such as balancing checkbooks to relatively complex tasks such as weather forecasts. As technology advances, operations are increasingly moved to computer-based systems. This makes society increasingly dependent on these systems.

  A typical computer-based system comprises a system board and optionally peripheral devices such as one or more display units, disk units. System boards often include one or more processors, a memory subsystem, and other circuits such as serial device interfaces, network device controllers, hard disk controllers, and the like.

  The type of processor used on a particular system board typically depends on the type of task performed by this system. For example, a task that monitors the exhaust generated by an automobile engine and adjusts the air / fuel mixture to ensure that the engine is completely fueled uses a simple dedicated processor to perform this task. be able to. On the other hand, systems that perform many different tasks, such as managing many users and running many different applications, perform high-speed operations, process data, and provide services to user requests One or more complex processors that are configured to minimize the response time to may be used.

  A memory subsystem is a storage device that holds information (eg, instructions, data values) used by a processor. A memory subsystem typically includes a controller circuit and one or more devices. The controller circuit is typically configured to interface the processor and the memory device, allowing the processor to store information into and retrieve information from the memory device. The memory device holds actual information.

  Like a processor, the type of device used for a memory subsystem is often driven by a type of task performed by a computer system. For example, a computer system may have a task that must boot without disk drive assistance and execute a set of software routines that do not change often. Here, the memory subsystem can use a non-volatile device, such as a flash memory device, to store software routines. Other computer systems may perform very complex tasks that require large high-speed data storage to hold most of the information. Here, the memory subsystem can use a high-speed high-density dynamic random access memory (DRAM) device to store information.

  The demand for flash memory devices continues to grow significantly as these devices are well adapted to various embedded applications that require non-volatile storage. For example, flash memory is widely used in various consumer devices such as digital cameras, cell phones, USB flash drives, portable music players, etc. to store data used by these devices. Market demand for flash memory has led to significant improvements over the past few years in flash memory technology, both in terms of speed and density. These improvements have led to the prediction that flash memory-based devices will someday replace hard disk drives in applications that have continued to use disk drives for mass storage.

  Some flash devices use a serial interface, such as multiple flash devices, which are used to perform operations such as read, write, and erase operations on the memory contained in the device. . These operations are selected on certain devices, usually using command strings, and these command strings are sent serially to multiple devices. The command string includes a command representing the action to be normally selected as well as other parameters. For example, a write operation can be selected by serially sending an information string that includes a write command to the device, the data to be written, and the address of the memory into which the data is to be written.

  The command string may be sent to all devices, even if this command can only be executed on one device. In order to select a device on which to execute the command, the command string may include a device identifier (ID) that identifies the flash device for which the command is intended. Each device receiving the command string compares the ID associated with that device with the device ID contained in the command string. If the two match, the device assumes that the command is for that device and executes the command.

  The problem with the above configuration involves establishing a device ID for each device. One technique that can be used to establish a device ID for a device is to hardwire an internal unique device ID in the device. However, the drawback with this approach is that when large numbers of devices are produced, the size of the device ID may need to be significantly increased to ensure that each device contains a unique device ID. . Handling large device IDs can significantly increase device complexity, which can increase the cost of producing the device. Furthermore, reusing device IDs associated with devices that are no longer used may further increase the complexity of this scheme.

  Another technique for assigning device IDs to multiple devices is related to hard-wiring the device ID externally to each device. Here, in order to establish a device ID for a device, the device ID is defined by wiring various pins in a certain state on the device. The device reads the state of the wired pin and establishes its ID from the read state. However, one drawback with this approach is that external wiring is required to assign a device ID to each device. This can increase the complexity of, for example, a printed circuit board (PCB) that holds the memory device. Another drawback with this approach is that it may require a dedicated pin for device ID assignment. This creates the risk of consuming valuable resources that could otherwise be used better. Further, dedicated pins for device ID assignment may require a larger footprint for the device than if no pins are used for device ID assignment.

  One solution aimed at addressing the limitations of the prior art is a device identifier for a device (e.g., in a serial interconnect configuration, in a way that does not require special internal or external hard wires of the device ID). ID) is automatically established. Such techniques are taught in related US patent application Ser. No. 11/521734, filed Sep. 15, 2006, the teachings of which are hereby incorporated by reference in their entirety. In short, this technique allows the role of input port enable (IPE) signals to change based on single-chip, multi-drop, or serial interconnect device configurations. The serial input (SI) and serial output (SO) functions can transmit and receive all data types without timing limitations throughout the operation. There is no need to change the pin function from an additional pin or main pin layout. This ID generation and assignment technique depends on the number of pins available and the number of pins is determined by the number of link ports. Thus, for example, in a multi-independent serial link (MISL), the maximum number of devices supported for a single port is eight devices. For dual ports, the maximum number of devices is 64 (that is, 3 pins per port).

  An apparatus and method for establishing a device identifier for a device in a serial interconnect configuration is disclosed. The device may be a memory device such as dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, and the like. Such serial interconnects may be implemented in a multi-independent serial link (MISL).

  In aspects of the present technique, this allows an identifier to be assigned to a device without requiring additional hard pins on the device. With function and timing definitions, an identifier for each device is automatically generated by the device that includes the associated combinatorial logic, such as an adder.

  In a first aspect, the present invention provides an apparatus for establishing a device identifier (ID) for a device configured in a serial interconnect configuration having a plurality of devices. The device generates a device ID in response to the input signal received at the device's serial input, and outputs an output signal related to the generated device ID in synchronization with the clock via the device's serial output Equipped with a producer.

  In one embodiment, the input signal received at the device includes a value associated with the device ID of this device, and the generated device ID associated with the output signal is associated with the device ID of other devices in the serial interconnect configuration. Value to be included.

  In another embodiment, the input signal received at the device includes a value associated with the device ID of the previous device in the serial interconnect configuration, and the generated device ID associated with the output signal is in the serial interconnect configuration. Contains a value associated with the device ID of this device.

  In a further embodiment, the ID generator creates an N-bit ID where N is 1 or more and generates a calculated value based on the N-bit ID and a predetermined number, and a device ID that matches the calculated value And an ID supplier for providing

  For example, the ID calculator performs a calculation of adding 1 to an N-bit ID, and the addition result is provided as an N-bit ID. Alternatively, the calculation may be performed by subtracting 1 from the N-bit ID, and the subtraction result is provided as the N-bit ID.

  The technique also provides an apparatus for generating a device identifier (ID) for a device coupled to one of a plurality of devices in a serial interconnect configuration. The device may have at least one cell for storing data, a serial input connection for receiving serial input data, and a serial output connection for providing serial output data. The apparatus records the serial N-bit ID data included in the serial input data, and provides an N-bit ID data recorded as parallel N (N is an integer of 1 or more) bit ID data, and an input recording circuit for providing To provide N-bit calculation data, a calculation circuit that performs calculations based on parallel N-bit ID data and a given number of data, and records, calculates and records N-bit calculation data as calculated parallel N-bit data Parallel N-bit data provided as serial N-bit data in the serial N-bit data, and the serial N-bit data is input to an input recording circuit included in another generator coupled to another device. Transferred.

  For example, a device may generate a new ID by using a circuit for adding a given number of data to parallel N-bit ID data, or for subtracting a given number of data from parallel N-bit ID data. It may be a memory device including a computing circuit having a circuit.

  For example, the adder circuit or subtractor circuit may include an N-bit adder or subtractor that performs parallel addition or subtraction. The added or subtracted parallel data is sent to an N-bit parallel serial register to provide a serial ID that is then transferred to another memory device.

  The apparatus can include a selector that selects serial N-bit data to be transferred to another generator coupled to another memory device in response to the ID generation enable signal. The ID generation enable signal may be generated in accordance with a command included in the serial input data. The selector can select data obtained from the storage data cell in the memory device, and can transfer the data to another memory device in accordance with the status of the ID generation enable signal.

  In a further aspect, the present invention provides a device configured with a serial interconnect configuration of a plurality of devices, the device comprising a device identifier (ID) establisher for establishing a device ID for the device. The device ID establisher generates a device ID in response to an input signal received at the device's serial input, and synchronizes with the clock via the device's serial output and an output signal associated with the generated device ID. Including an ID generator.

  In another aspect, the present invention provides a multiple device serial interconnect configuration. Each device receives an input signal and transfers an output signal, a serial input and a serial output, a clock input that receives a clock signal, and a device identifier (ID) establisher that establishes a device ID for the device, The device ID establisher has an ID generator that generates a device ID in response to an input signal received at the serial input of the device, and the output signal is synchronized with the clock via the serial output of the device Associated with the generated device ID.

  In yet another aspect, the present invention provides a method for establishing a device identifier (ID) for a device configured in a serial interconnect configuration having a plurality of devices. The method includes generating a device ID in response to a serial input signal and outputting a signal associated with the device ID via a serial output of the device. Generation and transfer are synchronized to the clock.

  Other aspects and features of the present invention will become apparent to those skilled in the art from the following summary of specific embodiments of the invention taken in conjunction with the accompanying drawings.

  Embodiments of the present invention will now be described by way of example only with reference to the accompanying drawings.

1 is a block diagram of a device configuration comprising a plurality of single port devices configured in a serial interconnect configuration, in which embodiments of the present invention may be implemented. FIG. 1B is a block diagram showing one of the devices shown in FIG. 1A. FIG. 4 is a block diagram illustrating communication between devices configured in a serial interconnect configuration. FIG. 2B is a timing diagram showing communication between devices configured in the serial interconnection configuration shown in FIG. 2A. It is a block diagram of a device taking ID generation logic by a single link as an example. FIG. 6 is a timing diagram of signals for a memory device. It is a block diagram of a device taking ID generation logic by dual link as an example. FIG. 6 is a timing diagram of signals for a device. FIG. 5 is a high level block diagram of logic that can be used to generate an ID for a device according to an embodiment of the invention. FIG. 5B is a detailed block diagram of the logic shown in FIG. 5A. FIG. 5B is a block diagram of the ID generator shown in FIGS. 5A and 5B. FIG. 10 is a timing diagram of clock generation for a device number (DN) register and a command register. It is a timing diagram of ID generation. It is a timing diagram of the waiting time in the normal operation mode. It is a timing diagram of ID generation controlled by an output port enable signal. It is a figure which shows control of ID bit length by an output port enable signal. FIG. 6 is a timing diagram of an ID output enable signal, a shift clock signal, and other signals. FIG. 6 is a timing diagram of ID generation and related signals. It is a block diagram which shows the structure of ID temporary register. It is a timing diagram of a signal for the ID temporary register. FIG. 6 is an advanced block diagram of logic that can be used to generate an ID for a device according to a second embodiment of the present invention. FIG. 13B is a detailed block diagram of the logic shown in FIG. 13A. 14 is a block diagram of the ID generator shown in FIGS. 13A and 13B. FIG. FIG. 13B is a diagram showing ID bit length control by an output port enable signal for the embodiment shown in FIG. 13A. FIG. 6 is an advanced block diagram of logic that can be used to generate an ID for a device according to a third embodiment of the present invention. FIG. 15B is a detailed block diagram of the logic shown in FIG. 15A. FIG. 16 is a block diagram of the ID generator shown in FIGS. 15A and 15B. FIG. 15B is a timing diagram of signals for the ID generation logic shown in FIG. 15A. FIG. 15B is a diagram showing ID bit length control by an output port enable signal for the embodiment shown in FIG. 15A.

  In general, the present invention provides a system that includes a plurality of devices in a serial interconnect configuration. An apparatus and method for establishing a device identifier for a device in a serial interconnect configuration is disclosed. Such serial interconnects may be implemented in a multi-independent serial link (MISL).

  The methods and apparatus according to the techniques described herein are applicable to memory systems having multiple devices in a serial interconnect. The device may be a memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a flash memory.

  In conventional memory devices, ID assignment is usually performed using additional pins to create logical combinations such as (0000), (0001),..., (1111). Thus, usually assigning an ID means that pin assignment must be required to cover the connection.

  Command and data serialization applied to a memory device allows the execution of various functions associated with the device using fewer pins. ID assignment to a particular memory device can be performed using the serial input enable and output enable signal ports associated with the device. Here, the number associated with the device ID may be transferred and serially incremented by 1 for each device. There is no need to generate complicated timing. For the entry timing and exit timing, the device ID write operation can be used.

  In general, aspects of the present invention provide a method and device controller for establishing a device identifier (ID) for a device configured in a serial interconnect configuration having a plurality of devices, as described below, and the device The controller generates a device ID associated with the first device in response to an input signal received at the serial input of the first device, and outputs an output signal associated with the device ID via the serial output of the first device, An ID generator is provided for transferring to a second device in a serial interconnect configuration in synchronization with the clock signal.

  Embodiments of the present invention will be described with reference to the drawings. In the following description, the same reference numerals are used for signal, input and output connections. For example, reference sign CLK represents clock signal and clock input connection, IPE represents input port enable signal and device input port enable input connection, OPE represents output enable signal and device output port enable connection, CS # represents chip Represents a select signal and a chip select input connection, IPEQ represents a device input port enable output connection and input port enable output signal, and OPEQ represents a device output port enable output connection and output enable output signal.

  FIG. 1A shows an exemplary device configuration that includes multiple single port devices configured in a serial interconnect configuration with inputs and outputs for various signals. In this particular example, the device configuration includes four devices 0, 1, 2, and 3 (110-1, 110-2, 110-3, and 110-4). Each of the interconnected devices 110-1 to 110-4 has the same structure. The memory controller (not shown) includes chip select CS #, serial input (SI), input port enable (IPE), output port enable (OPE), clock CLK and other control and data information provided to the device ( A collection of signals including (not shown). The memory system may include a serial interconnect configuration of such devices and a memory controller that controls the operation of the serially interconnected devices.

  FIG. 1B shows one device 110-i that represents any one of the devices 110-1 to 110-4 shown in FIG. 1A. The device 110-i includes a device controller 130 and a memory 120 including a random access memory (RAM), a flash memory, and the like. For example, the random access memory may be dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), and flash memory is NAND type, NOR type, AND type and other types of flash It can be memory. The device controller 130 has a device identifier (ID) generator 140. Device 110-i has a serial input port (SIP) connection, a serial output port (SOP) connection, a chip select input (CS #) and a clock input (CLK). SIP is used to transfer information (eg, command, address and data information) to device 110-i. The SOP is used to transfer information from the device 110-i. The CLK input receives a clock signal. The CS # input receives the chip select signal CS #, which can operate simultaneously on all devices. The device controller 130 performs process functions with access to the memory 120 in response to various control and input signals (e.g. SI, IPE, OPE, CLK) and serializes to the next device 110- (i + 1) Provide output data.

  Referring to FIGS. 1A and 1B, the SIP and SOP are connected between devices in a serial interconnect configuration, so that the SOP of device 110- (i-1) before the serial interconnect is a serial interconnect device Combined with 110-i SIP. For example, the SOP of device 1, 110-1 is coupled to the SIP of device 2, 110-2. Each of the four devices 110-1 to 110-4 receives a clock signal CLK from a memory controller (not shown). The clock signal CLK is distributed to all devices via a common link. As described further below, the clock signal CLK is used to, among other things, latch information inputs to the device 110-i at various registers contained therein. The CS # input is a conventional chip selection input for selecting a device. The CS # input is coupled to a common link, from which the chip select signal CS # can be asserted simultaneously to all of the devices 110-1 through 110-4, so that all of the devices are selected.

  Device 110-i further has an input port enable (IPE) input, an output port enable (OPE) input, an input port enable output (IPEQ), and an output port enable output (OPEQ). IPE is used to input an input port enable signal IPEi to device 110-i. Signal IPEi is used by the device to enable SIP, so that when IPE is asserted, information is serially input to device 110-i via SIP. Similarly, OPE is used to input an output port enable signal OPEi to device 110-i. The OPEi signal is used by the device to enable the SOP so that when OPE is asserted, information is serially output from the device 110-i via the SOP. IPEQ and OPEQ are outputs that output IPEQi and OPEQi signals from the device 110-i, respectively. The CS # and CLK inputs are coupled to separate links that distribute the chip select signal CS # and clock signal CLK to the four devices 110-1 to 110-4, respectively, as described above.

  The SIP and SOP are coupled from the previous device 110- (i-l) to the next device 110- (i + 1) in the serial interconnect configuration as described above. Further, the IPEQ and OPEQ outputs of the previous device 110- (i-1) are coupled to the IPE and OPE inputs of the current device 110-i in the serial interconnect configuration, respectively. This arrangement allows IPE and OPE signals to be transferred from one device in the serial interconnect configuration to the next (eg, device 0, 110-1 to device 1, 110-2).

  Information transmitted to devices 110-1 through 110-4 can be latched with different time clock signals CLK fed into the CLK input. For example, in a single data rate (SDR) implementation, information input to the device 110-i in SIP can be latched at one of the rising and falling edges of the clock signal CLK. Alternatively, in a double data rate (DDR) implementation, both rising and falling edges of the clock signal CLK can be used to latch information inputs in SIP.

  The configuration of devices 110-1 through 110-4 in FIG. 1A includes both serial interconnects (eg, input SI and output SO) and conventional multidrop connections (eg, CLK and CS #). Therefore, this configuration can be referred to as a hybrid of serial interconnect and multi-drop configurations, and the advantages of each can be realized.

  The ID generator 140 generates an ID and establishes a device ID for the devices in the serial interconnect configuration.

  FIGS. 2A and 2B show three devices 210-1 through 210-3 configured with serial interconnects, and the signals transferred between the devices in the accompanying timing diagrams. A chip select signal CS # (not shown) is first asserted to select the device. Information is sent to this first device 210-1 in the serial interconnect by asserting IPE and clocking data to device 210-1 (on the next rising edge of clock signal CLK). The input port enable signal IPE is propagated to the second device 210-2 via the first device 210-1 within less than one cycle as indicated by the signal IPE_0. This propagation allows the information to be clocked from the SOP of the first device 210-1 to the SIP input of the second device 210-2 one cycle after the information is clocked into the first device 210-1. This process is repeated for subsequent devices on the serial interconnect. For example, information is input from the latch point of data in the first device 210-1 to the third device 210-3 in the serial interconnect at the third rising edge of the clock signal CLK. The control signals IPE_0, IPE_1, IPE_2 are synchronized with the rising edge of the signal CLK, which ensures that the proper setup time for these signals is ensured at the next device in the serial interconnect configuration.

  3A and 4A illustrate exemplary operations for generating device identifiers (IDs) for memory devices in a serial interconnect configuration for single and dual links, respectively. FIG. 3A shows devices 310-1 through 310-m and 310-n connected in a single link configuration, and FIG. 3B shows signal timing for the device shown in FIG. 3A. Similarly, FIG. 4A shows devices 410-1 through 410-m and 410-n connected in a dual link configuration, and FIG. 4B shows signal timing for the device shown in FIG. 4A. Here, n is an integer of 2 or more, and m is n-1. In the particular embodiment shown in FIGS. 3A and 4A, each device includes a device controller having an ID generator that is similar to that of FIG. 1B.

  This exemplary operation is to generate a device ID using two inputs of the serial interconnect, the SIP and SOP inputs, where the first input receives the serial input and the second port receives the control signal. It can be adapted for use with other ports in an interconnect. This ID generation technique is not limited to MISL applications, but in any serial interconnect configuration (e.g. daisy cascade) with multiple existing input pins if the serial connection (e.g. daisy chain) system has a clock. Applicable.

  In this embodiment, the IPE has a function of catching the serial input stream based on a unit of 1 byte. As a result, the OPE is selected after the chip selection signal CS # becomes low again to latch the serial ID input stream. . With the “write ID entry” command, OPE catches an input stream consisting of the same cycle as the total number of ID bits. The ID bit is established by the size of the internal ID register. For example, if the device has a 12-bit ID register, OPE will hold the “high” state for 12 cycles. The 12-bit device ID allows for up to 4,096 addresses on the serial interconnect. Thus, this embodiment is applicable to a large number of devices in a serial interconnect configuration, and the number is not limited by the number of pins at each device. Furthermore, each device does not require the additional complexity of an internal hardwired device ID.

  3B and 4B, the ID generation mode setting period referred to in `` IDGMS '' is a predetermined clock cycle corresponding to the ID bit length + 8 cycles (command bit length) + the expected number of serially interconnect devices. It is an equal time interval.

  For signal transfer between OPE input and OPEQ output or op1 and op2, more than two cycles of non-overlapping time segment to avoid operation conflict caused by ID increment and data transfer to adjacent next device Should exist. After the OPE is asserted on each device 310-1 to 310-n, the ID input data to be latched is stored in the device's ID register (referred to as eg `` 516 '' in FIG. An increment operation is performed, after which the OPEQ output is asserted. The function of the OPE signal is to determine the number of ID bits from one bit of the defined bits of the ID register in each memory device to the maximum number of bits. If the number of ID bits and the number of defined bits in the ID register are equal (“fixed ID bits”), the order of the ID bits is irrelevant. However, in all other cases, the signal corresponding to the device ID is transferred to the next device in the order starting with the least significant bit (LSB) and ending with the most significant bit (MSB). The reason for this will be explained later.

  FIGS. 5A and 5B illustrate exemplary logic associated with ID generation for a device controller 500 in a device 110-i configured with a serial interconnect. Clock generator 501 receives the clock signal sent to the CLK input of the device and provides an internal clock signal including “Clk_cmd” and “Clk_dn”. The command clock “Clk_cmd” is asserted many times equal to the bit length of the command serial bit. As shown in Figure 6, for example, if the memory system has a 1-byte command, clk_cmd needs 8 clock cycles to latch the serial command bit length and then latches until the next command received Hold the data. The device number (DN) clock “clk_dn” clocks the ID input and is stored in the input DN register 504 and the ID temporary register 518. The sequence of received and stored signals received at the SIP input matches the predefined sequence. For example, the device may be configured to first receive a signal that matches the device ID, and subsequently receive command bits. As a result of this order, a number of Clk_dn cycles are generated, and then Clk_cmd is issued by the clock generator 501.

  In order to decode the command bits, the serial input command stream is shifted into the command register 502 in response to the command clock “clk_cmd”, and the command register 502 transmits the next recorded M-bit command data to the interpreter 503 in parallel. . A command interpreter 503 is a command decoder, and passes an internal command signal for starting additional control. Two such command signals (cmd_wr_id_entry, cmd_wr_id_exit) are shown and serve to start and stop the ID generation mode.

  Before the ID write generator issues the command “write ID entry”, the memory controller (not shown) sends a reset signal to the reset input of the serial interconnect configuration device. The reset inputs are connected in common. All devices in the serial interconnect configuration are reset by a reset signal. Upon reset, all devices can receive a “write ID entry” command by default, and all devices have a default ID of “zero”. As a result, all devices on the serial interconnect can be selected simultaneously and by having a command “ID numbers” of “zero”, the command “write ID entry” gives an instruction to all devices.

  Input DN register 504 stores input ID data from the previous device. During normal operation (not in ID generation mode), the input DN register 504 temporarily stores the contents of the input ID stream from the SIP to be compared with the device ID number in the N-bit ID register 516 (e.g., a 10-bit register). Remember me. During the generation of the device ID, the input DN register 504 does not receive serial input data. Instead, ID temporary register 518 catches the serial data and sends it to the ID generator or establisher illustrated as ID generation enable block 506. The number of bits N is an integer equal to the number of bits in the ID number and can be equal to any number suitable for identifying all devices in the serial interconnect.

  The ID comparator 505 serves to identify data and command signals addressed to the device during normal device operation. Comparator 505 compares the device ID stored in N-bit ID register 516 at the input DN register 504 with the ID number of each incoming data and provides an “ID_match” signal. If the ID numbers are the same or equivalent, the ID_match signal is equal to “1”. Otherwise, it is “0”. As a result, each device in the serial interconnect will determine whether the signal is addressed to that device by the incoming ID number being equivalent to the device ID stored in that device. decide.

  FIG. 5C shows the ID generator 600 of the device controller 500 of FIGS. 5A and 5B. In response to the “id_gen_en” (ID generation enable) signal from the ID generation controller 507, the ID generation enable block 506 illustrates the N-bit input of the ID temporary register 518 as an N-bit adder 508 (for example, a 10-bit adder). And transfer to the N-bit ID register 516. Exemplary signal timing for the ID generation enable signal is shown in FIG. This simultaneous transfer prevents unnecessary signal transitions of the N-bit adder 508 and the N-bit ID register 516. The device ID is stored in the ID register 516 by the device ID sequence and word length. For example, if the N-bit ID register 516 is 10 bits long and the OPE signal has a “high” state of 5 cycles, the N-bit ID register 516 stores the 5-bit device ID and corresponds to the 5-bit device ID The signal is transferred to the next device. The remaining bits of the ID register 516 are ignored and therefore remain at the value “0” or “do n’t care”.

  During the ID generation process, in the embodiment described above, the N-bit serial input is first stored in the ID temporary register 518 and then transferred to the N-bit adder 508 and the N-bit ID register 516. Simultaneous transfers from temporary registers overcome the limitations of serial-parallel (STP) registers. As an example, consider a case where the number of ID bits (for example, 5 bits) is less than the number of bits of an ID register and an adder (for example, 10 bits). During the ID generation and ID assignment process, 5 bits (bit 0 (LSB) to bit 4 (MSB)) are loaded into the first 5 bits of the STP register and then provided in parallel to the 10-bit adder. As will be readily appreciated by those skilled in the art, the LSB will be placed on bit 4 of the register, which does not match the LSB of the adder. Even if the bit order is reversed from MSB (bit 0) to LSB (bit 4), the MSB position in the STP register will not match the MSB position of the 10-bit adder. Therefore, regardless of which bit is assigned as the first bit, a conventional STP register will result in an incorrect device ID. This STP register limitation ensures that the bits that match the device ID are transferred to the next device in the order that they begin with the LSB and end with the MSB, and are explained in more detail later with reference to FIGS. 12A and 12B. And by storing them in the order received in the ID temporary register (from LSB of ID temporary register 518 to bit 0).

  The ID generation controller 507 receives the input signals CS # (CS_en), cmd_wr_id_entry, and cmd_wr_id_exit, and transmits an “id_gen_en” signal for starting the ID generation mode. The “id_gen_en” signal is asserted, for example, when the signal CS # switches from low to high and then low again (see FIG. 7), while the signal cmd_wr_id_entry is simultaneously asserted. Note that “id_gen_en” can be asserted simultaneously with the transition of any other signal CS #, as will be apparent to those skilled in the art.

  FIG. 8 shows the waiting time in normal operation. Basically, MISL has a one cycle latency between two neighboring devices. However, the “write ID entry” command changes the path from the 1-cycle waiting time to “ID bit (ID register bit size) +2 cycles” as shown in FIG. 9A described below.

  9A and 9B show the logic and signal timing of ID generation control by the output port enable (OPE) signal. Under this operation, the ID bit length can be determined by the length of the OPE signal high and can be adapted to a serial interconnect configuration that includes a different number of devices. The function of the OPE signal is described below with reference to FIGS. 5A, 5B and 5C. Alternatively, the OPE signal is not required to determine the ID bit length, but instead may be determined by a predetermined value, the bit size of the ID register 516, or a value related to other signals.

  In FIG. 9B, an ID provider illustrated as a 10-bit ID temporary register 518, a 10-bit ID register 516, a 10-bit adder 508, and a 10-bit parallel-serial register 510 is shown while generating a 5-bit device ID. ing. The function of these registers is described below with reference to FIGS. 5A, 5B and 5C. The maximum device ID number is determined by the bit size of the internal adder 508 and the parallel-serial register 510. In addition, the device ID number affects the maximum number of devices that can be connected in a serial interconnect configuration. For example, a 10-bit device ID can connect up to 1024 devices on a serial bus by a single serial interconnection method.

  Alternatively, the OPE input may be configured to capture an input data stream of the ID number of the previous device rather than the IPE. This additional functionality of the OPE input brings simple timing to the ID generation mode. In one implementation for FIGS. 3A and 4A, “write ID entry” is asserted as shown in FIGS. 3B and 4B, and the chip select signal CS # switches from “low” to “high” and then “low”. OPE is asserted high for a time equal to the bit length of the ID register embedded in each memory device.

  Referring to FIGS. 5A-5C and 9B, the ID write generator 517 generates a “wr_id_en” signal that latches the output of the / ID generation enable block 506 in the N-bit ID register 516 in the ID generation mode. This signal is set by the falling edge of the OPE signal.

  The N-bit adder 508, which is a static adder, performs an addition operation of the input of the ID generation block 506 and a fixed integer, for example, “+1” as shown in FIG. 5A. For example, when N is equal to 8, the adder can calculate the sum of the 8-bit number from the ID temporary register 518 and the integer “10000000” (in order of LSB to MSB). As a result, adder 508 generates the next number in the sequence of device ID numbers. The adder 508 can be replaced with another logic circuit that performs a similar “+1” operation. Further, the logic 500 may be configured to perform other operations such as subtraction or addition of other integers (as described below) to N-bit numbers to generate subsequent device IDs. it can.

  The resulting ID data is written to the parallel-serial register 510 and then transferred to the next device as a serial signal via the SOP output of the device. The serial ID number may be used as the device ID by the next device and may be processed by the next device to generate the device ID. Alternatively, this logic may include additional operations to change the serial ID number if the resulting value relates to the device ID stored in the N-bit ID register 516.

  In the parallel-serial register 510, the input is transmitted in a parallel format, and the output is transmitted in a serial format. In response to the “id_gen_en” signal from the ID generation controller 507, the parallel-serial data write generator 509 provides a “wr_data_pts” signal that drives the parallel input path of the parallel-serial register 510. The path is disabled by sending ID data serially over the SOP with a slight delay after the rising edge of the first clock cycle of shift_clock. The LSB bit is the first bit transmitted and the MSB is the last bit transmitted.

  The selector (eg, multiplexer) 511S selects one of the two paths according to the id_gen_en signal. If id_gen_en is zero, that is, in normal operating mode, the top input “0” of selector 511S or Sdata (serial read data from memory cell) is provided as SOP to output buffer 515S, which is for the next device Work as SIP. In other cases (ID generation mode), bottom input path `` 1 '' is selected, i.e., Sdata_id (serial id data) is provided as SOP to output buffer 515S, which is the next device as shown in Figure 5B Work as a SIP against.

  In order to send the ID number serially to the next device, it must be clocked according to the clock signal. The data shift clock generator 512 provides the clock signal “shift_clock” to the parallel-serial register 510, thereby synchronizing the clock and the signal “Sdata_id” (serial ID data).

  The shift register block 513 provides an ID output enable signal (“id_out_en”) that is generated to notify the number of shift clock cycles. The shift register block 513 shifts the OPE signal by the number of bits equal to the ID register bit length + 2 cycles to provide a timing margin sufficient to perform serial data latch and addition operations. The shift register block 513 includes a 1 cycle shift register and an (N + 2) cycle shift register to shift the signal “opei” and provide the shifted “opei” to the selector (eg, multiplexer) 511Q. The shift register block 513 also includes an (N + 1) cycle shift register along with an additional one cycle shift register to provide the signal “opei” shifted together to the OR gate. The resulting signal “id_out_en” is provided to the data shift clock generator 512.

  The signal “shift_clock” is enabled by the data shift clock generator 512, and a signal “id_out_en” is generated that issues a shift clock one cycle earlier than the OPEQ signal. This feature ensures proper timing of the signal because the next device latches the data with the first clock signal superimposed by the OPE signal (i.e. the OPEQ signal from the previous device), as shown in Figure 10 . A shift clock is generated for a cycle duration that totals the number of ID bits plus one cycle, and the previous data (subsequent devices will receive an incorrect ID number from the current device's SOP) Guarantee that it will not be retained. FIG. 11 shows the timing of various signals in connection with the ID generation process described herein with reference to the embodiments shown in FIGS. 5A, 5B and 5C.

  The device controller 500 for generating ID also includes a plurality of input buffers. The one input buffer 514-1 receives the chip selection signal CS #, and the buffered output signal is inverted by the inverter. The inverted CS # signal is provided to the ID generation controller 507 as “CS_en”. Another input buffer 514-2 receives the SI from the SIP input and provides it to the command register 502, the input DN register 504, and the ID temporary register 518. Another input buffer 514-3 receives the clock signal “Clock” and its buffered output signal “Clocki” is provided to the clock generator 501. The other input buffers 514-4 and 514-5 receive IPE and OPE, respectively, and their buffered output signals are provided to the selector 511E, and the selected output signal is fed to the clock generator 501.

  In addition, the device controller 500 includes an output buffer 515Q that provides an OPEQ signal to the OPE input of the next device (not shown). The OPEQ signal is a selected output signal from a selector (eg, multiplexer) 511Q that selects one of the output signals from the 1 cycle shift register and the (N + 2) cycle shift register of the shift register block 513. The selected output signal (that is, the OPEQ signal) is transmitted to the next device OPE input.

  For example, referring to FIG.3A (and FIG.4A), FIG.3B (and FIG.4B) and FIGS.5A-5C, device 310-1 (410-1) has the first ID number or value `` 00000 '' (for SI) Is stored in the N-bit ID register 516. The N-bit adder 508 of the device 310-1 (410-1) adds +1 to the first ID number, and latches the “10000” output data of the N-bit adder 508 in the parallel-serial register 510. The selector 511Q provides “10000” as the SOP “10000” to the output buffer 515S, which is provided to the SIP of the next device 310-2 (410-2). The received ID number “10000” (SI) is stored in the N-bit ID register 516 of the device 310-2 (410-2), and “+1” addition is performed by the N-bit adder 508. The “01000” output data of the N-bit adder 508 is latched in the parallel-serial register 510 of the device 310-2 (410-2). The selector 511Q provides “01000” as the SOP “01000” to the output buffer 515S, which is provided to the SIP of the next device 310-3 (410-3). The received ID number “01000” is stored in the N-bit ID register 516 of the device 310-3 (410-3). This process continues until the last device 310-n (410-n) is reached. The order of all bits follows the rule that the LSB is first and the MSB last for the ID generation mode. Therefore, the device ID assigned by each device is the same as the received ID. The generated ID (the ID plus “+1” or the calculated ID) is provided to the SIP of the next device in the serial interconnect configuration.

  Table 1 shows the devices and assigned IDs (LSB → MSB) according to the embodiment described above.

  N-bit ID register 516 is filled with an ID number in the ID generation mode. This content is reset to the initial value setting by, for example, a hard reset pin. The contents of the N-bit ID register 516 are compared with the input ID stream of the input DN register 504 when any normal operation is started.

  In ID generation mode (and in contrast to normal operation), the device ID value and bit size are subject to change and are therefore determined according to the length of time that the OPE signal is asserted. The ID temporary register 518 accommodates this function by storing each serial bit at a designated bit position without serial data transfer.

  FIG. 12A illustrates the ID temporary register 518 shown in FIGS. 5A-5C. FIG. 12B shows signal timing for the ID temporary register 518. Referring to FIGS. 5A-5C, 12A and 12B, the ID temporary register 518 has (n + 1) bit storage corresponding to (n + 1) clock control blocks. In response to the DN clock “clk_dn”, the (n + 1) clock control block provides clocks “clk0” to “clk (n)”, respectively, which are fed into the (n + 1) bit store. Serial input SI is sent in parallel to (n + 1) bit storage, which stores SI data in response to clocks “clk0”-“clk (n)”. The stored data is provided as bit data “bit0” to “bit (n)”.

  Note that N-bit adder 508 provides one way to increment the received ID number. When implemented with multiple devices in a serial interconnect configuration, this ID generation logic has a cumulative effect of providing a unique device ID for each device, and the device ID number is incremented by “1” for each device. Alternatively, various logic can be substituted into the n-bit adder 508 to generate a unique device ID for each device.

  In another embodiment, ID generation logic associated with device controller ID generation establishes a device ID as a result of an N-bit operation. This alternative is that the output of the N-bit adder 508 is transferred to the N-bit ID register 516, which stores this value, not the received ID number, as shown in FIGS. 13A and 13B. As such, it requires establishing a device ID for the device. The ID generator 710 of the device controller 700 of FIGS. 13A and 13B is shown in FIG. 13C. In FIG. 14, an ID provider illustrated as a 10-bit ID temporary register 518, a 10-bit ID register 516, a 10-bit adder 508, and a 10-bit parallel-serial register 510 is shown while generating a 5-bit device ID. . Unlike the embodiment shown in FIG. 9B, the 10-bit ID temporary register 518 transfers the ID bits to the 10-bit adder 508. The ID added or calculated by the 10-bit adder 508 is then provided to the 10-bit ID register 516 and the 10-bit parallel-serial register 510. All operations of the device controller 700 shown in FIGS. 13A and 13B are the same as those of the device controller 500 described above.

  To further describe the embodiments, for example, referring to FIGS. 3A (and 4A), FIGS. 13A-13C and FIG. 14, device 310-1 (410-1) receives “00000” (SI). The N-bit adder 508 adds +1 to the SIP input, and latches “10000” output data of the N-bit adder 508 in the N-bit ID register 516 and the parallel-serial register 510. The selector 511Q provides “10000” as the SOP “10000” to the output buffer 515S, which is provided to the SIP of the next device 310-2 (410-2). The addition of “10000” (SI) and “+1” received by the device 310-2 (410-2) is executed by the N-bit adder 508. The “01000” output data of the N-bit adder is latched in the N-bit ID register 516 and the parallel-serial register 510. The selector 511Q provides “01000” as the SOP “01000” to the output buffer 515S, which is provided to the SIP of the next device 310-3 (410-3). This process continues until the last device 310-n (410-n) is reached. The order of all bits follows the rule that the LSB is first and the MSB last for the ID generation mode. Therefore, the device ID assigned by each device is not the same as the received ID. The generated ID (the ID plus “+1” or the calculated ID) is assigned to the current device and is also provided to the SIP of the next device in the serial interconnect configuration.

  Table 2 shows the devices and assigned IDs (LSB → MSB) according to the embodiment shown in FIGS. 13A and 13B.

  In yet another embodiment, the ID generation logic associated with device controller ID generation establishes the device ID as a result of an N-bit subtraction operation. For example, as shown in FIGS. 15A and 15B, “1” can be subtracted from the ID number received by the “N-bit subtractor”. The ID generator 810 of the device controller 800 of FIGS. 15A and 15B is shown in FIG. 15C. The device controller 800 has an N-bit subtracter 708 instead of the N-bit adder 508 shown in FIGS. 5B and 13B.

  Referring to FIGS. 3A-3B, 4A-4B and 15A-15C, the SIP input ID number or value “11111” received by device 310-1 (410-1) is stored in N-bit ID register 516. The N-bit subtracter 708 subtracts 1 from the SIP input, and latches the “11110” output data of the N-bit subtractor 708 in the parallel-serial register 510. The selector 511Q provides “11110” as the SOP “11110” to the output buffer 515Q, which is provided to the SIP of the next device 310-2 (410-2). “11110” (SI) is stored in the N-bit ID register 516 of this device 310-2 (410-2), and “−1” subtraction is performed by the N-bit subtractor 708. The “11101” output data of the N-bit subtracter 708 is latched in the parallel-serial register 510. The selector 511Q provides “11101” as the SOP “11101” to the output buffer 515S, which is provided to the SIP of the next device 310-3 (410-3). This process continues until the last device 310-n (410-n) is reached. The order of all bits follows the rule that the LSB is first and the MSB last for the ID generation mode. Therefore, the device ID assigned by each device is the same as the received ID. The generated ID (the ID minus "-1" or the calculated ID) is provided to the SIP of the next device on the serial interconnect.

  Table 3 shows the devices and assigned IDs (LSB → MSB) according to the embodiment described above.

  Due to the occurrence of the “countdown” ID in this embodiment, the signal timing differs from that shown in FIG. FIG. 16 illustrates various timings associated with the ID generation process described herein with reference to the embodiment illustrated in FIGS. 15A, 15B, and 15C. FIG. 17 illustrates control of the ID bit length by the OPE signal with respect to the embodiment illustrated in FIG. 15A.

  Referring to FIGS. 15A-15C, 16 and 17, the 10-bit ID temporary register 518 transfers the ID bits to the 10-bit ID register 516 and the 10-bit subtractor 708. The ID subtracted or calculated by the subtractor 708 is then provided to the 10-bit parallel-serial register 510. All other operations of this device controller 800 are similar to the previously described embodiments of FIGS. 5A-5B and 13A-13B.

  It will be apparent to those skilled in the art to implement the N-bit subtractor 708 shown in FIGS. 15A, 15B and 15C together in the embodiment shown in FIGS. 13A, 13B and 13C. Table 4 shows the devices and assigned IDs (LSB → MSB) according to the embodiment described above.

  Similarly, it will also be apparent that an integer other than “1” can be added or subtracted to the received ID number to implement a system, giving a series of devices a non-cumulative sequence of device numbers. .

  The ID generation logic and method described above can be incorporated into a memory device such as, for example, a flash memory device that requires a device identifier without assigning external hard pins. Embodiments of ID generation logic can also be implemented as single or individual devices to support ID generation for any memory device. For a single device implementation, the pin allocation is changed according to the internal signal conditions of the selected memory device.

  The above embodiments of device ID generation can be modified for implementation in many different systems without departing from the principles described herein. For example, referring to FIGS. 5A and 5B, a command based on “write ID entry” can introduce a “write ID exit” together by CS # transition low to high and low. In addition, one dedicated pin may be assigned and can receive the “entry mode enable” and act as a “write ID entry” command instead.

  An alternative method of exiting ID generation is to use an exit command or an implementation of exit logic in the device instead of CS # transition.

  Apart from flash memory including MISL (Multi Independent Serial Link), this technique described here is in a serial interconnect configuration that requires an ID number to select one of the connected devices. It can be applied to any device without limitation.

  There are many modifications to the embodiment. An active “high” or “low” logic signal can be changed to an active “low” or “high” logic signal, respectively. Logic “high” and “low” state signals can be represented by low and high supply voltages Vss and Vdd, respectively.

  In the above embodiment, the device elements and circuits are connected to each other as shown for simplicity. In practical application of technology to memory systems, devices, elements, circuits, etc., they may be directly connected or coupled to each other. In addition, devices, elements, circuits, etc. may be indirectly connected and coupled to each other via other devices, elements, circuits, etc. as needed for operation of the memory system.

  In the above description, numerous details are set forth for purposes of explanation in order to provide a consistent understanding of embodiments of the present invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the invention. In other instances, well-known electrical structures and circuits are shown in block diagram form in order to avoid obscuring the present invention. For example, specific details are not provided as to whether the embodiments of the invention described herein are implemented as software routines, hardware circuits, firmware, or combinations thereof.

The above-described embodiments of the present invention are intended to be examples only. Changes, modifications and variations may be made to one of ordinary skill in the art to a particular embodiment without departing from the scope of the invention, which is defined only by the claims appended hereto.
An apparatus and method for establishing a device identifier for a device in a serial interconnect configuration is disclosed. The device may be a memory device such as dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, and the like. Such serial interconnects may be implemented in a multi-independent serial link (MISL).
In aspects of the present technique, this allows an identifier to be assigned to a device without requiring additional hard pins on the device. With function and timing definitions, an identifier for each device is automatically generated by the device that includes the associated combinatorial logic, such as an adder.
In a first aspect, the present invention provides an apparatus for establishing a device identifier (ID) for a device configured in a serial interconnect configuration having a plurality of devices. The device generates a device ID in response to the input signal received at the device's serial input, and outputs an output signal related to the generated device ID in synchronization with the clock via the device's serial output Equipped with a producer. The device may receive a command or data signal with a serial input and transmit the command or data signal with a serial output.
In one embodiment, the input signal received at the device includes a value associated with the device ID of this device, and the generated device ID associated with the output signal is associated with the device ID of other devices in the serial interconnect configuration. Value to be included.
In another embodiment, the input signal received at the device includes a value associated with the device ID of the previous device in the serial interconnect configuration, and the generated device ID associated with the output signal is in the serial interconnect configuration. Contains a value associated with the device ID of this device.
In a further embodiment, the ID generator creates an N-bit ID where N is 1 or more and generates a calculated value based on the N-bit ID and a predetermined number, and a device ID that matches the calculated value And an ID supplier for providing
For example, the ID calculator performs a calculation of adding 1 to an N-bit ID, and the addition result is provided as an N-bit ID. Alternatively, the calculation may be performed by subtracting 1 from the N-bit ID, and the subtraction result is provided as the N-bit ID.
The ID provider may include a shift circuit for shifting out the N-bit ID in synchronization with a clock. The N-bit ID may be related to the input signal. In a further embodiment, the apparatus may further include an ID generation controller that controls generation of the N-bit ID in response to a command in the input signal.
In a further aspect, the present invention provides a device configured with a serial interconnect configuration of a plurality of devices, the device comprising a device identifier (ID) establisher for establishing a device ID for the device. The device ID establisher generates a device ID in response to an input signal received at the device's serial input, and synchronizes with the clock via the device's serial output and an output signal associated with the generated device ID. Including an ID generator. The plurality of devices may be connected to a serial link. The device may receive a command or data signal with a serial input and transmit the command or data signal with a serial output.
Each of the plurality of devices may include a memory device such as a random access memory or a flash memory. The input signal received at the device may include a value associated with the device ID of this device, and the generated device ID associated with the output signal is associated with the device ID of other devices in the serial interconnect configuration. A value may be included. Alternatively, the input signal received at the device may include a value associated with the device ID of the previous device in the serial interconnect configuration, and the generated device ID associated with the output signal is in the serial interconnect configuration. A value related to the device ID of a certain device may be included.
In one embodiment, the ID generator includes an ID generator that generates an N-bit ID, where N is an integer equal to or greater than 1, and a calculator that generates a calculated value based on the N-bit ID and a predetermined number. And an ID provider that provides the device ID that matches the calculated value. The N-bit ID may be related to the input signal. The calculated value may be an integer calculation result with the N-bit ID.
In one embodiment, the ID provider may include a shift circuit for shifting out the N-bit ID in synchronization with a clock.
In one embodiment, the device may further include an ID generation controller that controls generation of the N-bit ID in response to a command in the input signal.
In another aspect, the present invention provides a multiple device serial interconnect configuration. Each device receives an input signal and transfers an output signal, a serial input and a serial output, a clock input that receives a clock signal, and a device identifier (ID) establisher that establishes a device ID for the device, The device ID establisher has an ID generator that generates a device ID in response to an input signal received at the serial input of the device, and the output signal is synchronized with the clock via the serial output of the device Associated with the generated device ID.
In yet another aspect, the invention provides a device identifier (ID) for a device configured in a serial interconnect configuration having a plurality of devices, such as a memory device or other device connected to a serial link. Provide a method for establishing. The memory device can be, for example, a random access memory or a flash memory. The method includes generating a device ID in response to a serial input signal and outputting a signal associated with the device ID via a serial output of the device. The generation and transfer are synchronized with the clock. The device may receive a command or data signal with a serial input and transmit the command or data signal with a serial output.
In one embodiment, the input signal received at the device may include a value associated with the device ID of the device, and the generated device ID associated with the output signal may be the other device in the serial interconnect configuration. A value related to the device ID may be included. In a further embodiment, the input signal received at the device may include a value associated with the device ID of the previous device in the serial interconnect configuration, and the generated device ID associated with the output signal is the serial interconnect A value related to the device ID of this device in the configuration may be included.
The ID generator is an ID generator that generates an N-bit ID, where N is an integer equal to or greater than 1, a calculator that generates a calculated value based on the N-bit ID and a predetermined number, and the calculated value An ID provider that provides the matching device ID may be provided. The calculated value may be an integer calculation result with the N-bit ID. The N-bit ID may be related to the input signal. The serial interconnection configuration may further include an ID generation controller that controls generation of the N-bit ID in response to a command in the input signal.
In one embodiment, the ID provider may include a shift circuit for shifting out the N-bit ID in synchronization with a clock.
In a further aspect, the present invention provides a method for establishing a device identifier (ID) for a device configured in a serial interconnect configuration having a plurality of devices. The method includes generating a device ID in response to a serial input signal, and a signal generated and transferred in synchronization with a clock, wherein the signal associated with the device ID is transmitted via a serial output of the device. Outputting.
The method may further include a step of resetting the device ID of the device to a predetermined value prior to the ID generation step. For example, the step of resetting the device ID is executed in a parallel manner for all devices.
In the ID generation step, the ID included in the serial input signal may be in response to a generation command.
The device ID generation step includes generating an N-bit ID, wherein N is an integer equal to or greater than 1, calculating a value based on an N-bit word and a predetermined number, and the device that matches the calculated value Providing an ID may be included. The calculated value may be, for example, a calculation result of the N-bit ID and an integer. The N-bit ID may be related to the input signal. Providing the device ID may include shifting out the N-bit ID in synchronization with a clock. The calculating step may include adding or subtracting an integer value and the N-bit ID value.
The method may further include controlling the generation of the N-bit ID in response to a command in the input signal.

110-1 Device 0
110-2 Device 1
110-3 Device 2
110-4 Device 3
110-i device i
110- (i-1) device
120 memory
130 Device controller
140 ID generator
210-1 devices
210-2 devices
210-3 Device
310_1 devices
310_m device
310_n devices
410_1 devices
410_m device
410_n devices
500 device controller
501 clock generator
502 Command register
503 interpreter
504 Input DN register
505 ID comparator
506 ID generation enable block
507 ID generator controller
508 N-bit adder
510 10-bit parallel-serial register
516 N-bit ID register
518 ID temporary register
600 ID generator
515S output buffer
512 data shift clock generator
500 device controller logic
510 parallel-serial register
511E selector
515Q output buffer
511Q selector
513 Shift register block
514-1 Input buffer
514-2 Input buffer
514-3 Input buffer
514-4 Input buffer
514-5 Input buffer
310-1 devices
410-1 devices
310-2 devices
410-2 devices
515-S output buffer
508 N-bit adder
310-3 devices
410-3 devices
310-n device
410-n devices
700 device controller
708 N-bit subtractor
710 ID generator
800 device controller

Claims (32)

An apparatus for use in a serial interconnect configuration having a plurality of devices,
The apparatus is an apparatus for establishing a device identifier (ID) for at least one device of the serial interconnect configuration;
The device is
An ID generator configured to generate a device ID in response to an input signal including the received ID value and to output an output signal including an ID value corresponding to the generated device ID;
And an ID storage means configured to store the ID value as an ID assigned for the at least one device corresponding to an ID storage signal. The ID value is included in the input signal including ID data,
The apparatus according to claim 1, wherein the ID value is included in the output signal including ID data corresponding to the generated device ID.   3. The apparatus of claim 2, wherein each of the ID values corresponds to the generated device ID that is included in the input signal and includes N-bit ID data, wherein the N is an integer greater than or equal to one. .   The apparatus according to claim 3, wherein the ID storage means is configured to store N-bit ID data included in the input signal as the assigned ID for the at least one device.   The apparatus according to claim 3, wherein the ID storage means is configured to store N-bit ID data corresponding to the generated device ID as the assigned ID for the at least one device.   The apparatus according to claim 2, wherein the generated device ID is a calculation result of the ID value included in the input signal and a predetermined number.   8. The apparatus according to any one of claims 1 to 7, wherein the apparatus is configured to output the output signal from the at least one device to a subsequent device in the serial interconnect configuration in synchronization with a clock. The device described.   The apparatus according to claim 4 or 5, further comprising a data shifter for shifting the N-bit ID data in synchronization with a clock.   The apparatus of claim 1, further comprising an ID generation controller configured to output an ID generation enable signal in response to an ID generation control signal.   The apparatus of claim 9, wherein the ID generation controller is configured to output the ID generation enable signal in response to an ID generation start signal.   The apparatus of claim 10, wherein the ID generation controller is further configured to output the ID generation enable signal in response to an ID generation stop signal.   The apparatus of claim 11, further comprising a decoder that decodes an ID generation command to output an ID generation start signal and an ID generation stop signal.   The apparatus of claim 12, wherein the decoder is configured to perform decoding corresponding to a first control signal.   The apparatus of any one of claims 9 to 13, wherein the apparatus further comprises an enabler for enabling an ID generator to generate the ID in response to the ID generation enable signal. The apparatus further comprises an ID storage signal generator that outputs an ID storage signal in response to a second control signal,
The apparatus according to claim 1, wherein the storage means is configured to perform storage of the ID value in response to the ID storage signal.   6. The N-bit ID data of the output signal is transferred from the at least one device to the subsequent device in order, starting from the least significant bit to the most significant bit. The device described in 1. A device configured in a serial interconnect configuration of multiple devices,
The device includes a device ID establisher for establishing a device identifier (ID) for the device;
The device ID establisher
An ID generator configured to generate a device ID in response to an input signal including an ID value and to output an output signal including an ID value corresponding to the generated device ID;
An ID storage means configured to store the ID value as an ID assigned for the device corresponding to an ID storage signal. The ID value is included in the input signal including ID data,
The device according to claim 17, wherein the ID value is included in the output signal including ID data corresponding to the generated device ID. Each of the ID values is included in the input signal, the generated device ID includes N-bit ID data, and the N is an integer of 1 or more,
The ID storage means stores N-bit ID data included in the input signal as the assigned ID for the device, or the generated device ID as the assigned ID for the device. The device of claim 18, wherein the device is configured to store a plurality of N-bit ID data.   The ID generator includes a calculator for performing calculation based on the N-bit ID data and an integer included in the input signal to output the N-bit ID data of the generated device ID. 20. The device of claim 19, comprising. The device ID establisher further includes an ID storage signal generator that outputs an ID storage signal in response to a second control signal;
The device of claim 17, wherein the storage means is configured to perform storage of the ID value in response to the ID storage signal.   The device according to any one of claims 17 to 21, wherein the device is configured to transfer the output signal to a subsequent device in the serial interconnect configuration in synchronization with a clock. A system having a plurality of serially connected devices including at least a first and a second device,
The first device is:
A first ID generator configured to generate a device ID in response to an input signal including an ID value and to output an output signal including an ID value corresponding to the generated device ID;
First ID storage means configured to store the ID value as an ID assigned for the device corresponding to a first ID storage signal;
The system, wherein the second device is configured to receive the output signal output from the first device. The plurality of devices are connected to a serial connection link;
24. The system of claim 23, wherein the output signal is transferred from the first device to the second device via the serial connection link. The ID value is included in the input signal including ID data,
The system according to claim 24, wherein the ID value is included in the output signal including ID data corresponding to the generated device ID. Each of the ID values is included in the input signal, the generated device ID includes N-bit ID data, and the N is an integer of 1 or more,
The ID storage means stores N-bit ID data included in the input signal as the assigned ID for the first device, or as the assigned ID for the first device. 26. The system of claim 25, configured to store N-bit ID data of the generated device ID. The second device is:
A second ID generator configured to generate a device ID in response to the output signal including the ID value received from the first device;
Assigned to store the ID value included in the output signal from the first device or for the second device corresponding to a second ID storage signal of the second device 27. A second ID storage means configured to store the ID value of the device ID generated by the second ID generator as an ID. The system described in.   27. A system according to any one of claims 23 to 26, wherein the first device is configured to output the output signal to the second device in synchronization with a clock. The first device comprises a signal input and a signal output; the second device comprises a signal input;
The first ID generator is configured to receive the input signal via the signal input of the first device;
The output signal is output via the signal output of the first device;
29. The system of claim 28, wherein the output signal from the first device is received via the signal input of the second device and provided to the second ID generator. The system
A controller for communicating with the plurality of serially connected devices;
27. The system according to any one of claims 23 to 26, wherein the input signal including the ID value received at the first device is output from the controller. A method for establishing a device identifier (ID) for a device configured in a serial interconnect configuration having a plurality of devices, the method comprising:
At least one of the plurality of devices is
Receiving an input signal including a first ID value;
Generating a device ID based on the first ID value;
Outputting an output signal including a second ID value corresponding to the generated device ID to subsequent devices in the serial interconnect configuration;
Storing the ID value as an ID assigned for the device corresponding to an ID storage signal. A method for establishing a device identifier (ID) for a device configured in a serial interconnect configuration having a plurality of devices comprising at least a first and a second device, the method comprising:
The first device is
Receiving an input signal including a first ID value;
Generating a device ID based on the first ID value;
Outputting an output signal including a second ID value corresponding to the generated device ID;
Storing the ID value as an ID assigned for the first device corresponding to a first ID storage signal;
The second device is
Receiving the output signal including a second ID value as an input signal;
Generating a device ID based on the second ID value;
Outputting an output signal including a third ID value corresponding to the generated device ID;
Storing the ID value as an ID assigned for the second device corresponding to a second ID storage signal;
Including methods.