JP3892655B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a data / signal transmission system, and more particularly to a method of handling data or signals exchanged between semiconductor integrated circuit devices with a current amount, for example, transmission in which a semiconductor memory and its controller are connected. It is used for the system.
[0002]
[Prior art]
A conventional transmission system for connecting a plurality of LSIs handles a voltage potential as data. For example, a conventional transmission system to which a semiconductor memory and its controller are connected is configured as shown in FIG. 56 or FIG. Yes.
[0003]
The conventional transmission system shown in FIG. 56 has a plurality of synchronous dynamic memories (SDRAMs) 421 arranged two-dimensionally and a clock / clock for supplying a clock signal Clock and an address signal Address from the common memory controller 420 to each SDRAM 421. An address bus 422 is connected, and a data bus 423 for transmitting data DATA is connected between the memory controller 420 and the SDRAM 421 in each row, and the memory controller 420 corresponds to the SDRAM 421 in each column. Control signal bus 424 for supplying control signals (RAS # 1, CAS # 1, WE # 1, CS # 1) to (RAS # 4, CAS # 4, WE # 4, CS # 4). ing.
[0004]
The configuration of the memory module in which the plurality of SDRAMs 421 are two-dimensionally arranged on a printed circuit board can increase the data bus width, and can transmit a large amount of data through a relatively low-speed bus.
[0005]
However, the transmission system shown in FIG. 56 has a problem that there are many bus wirings and a problem that reflection noise easily occurs because the bus is not terminated, and data reading cannot be performed at high speed. Furthermore, since the loads of the control signal bus, the address bus, and the data bus are not uniform, the setup / hold time between signals in each SDRAM varies depending on the distance from the memory controller to each SDRAM.
[0006]
As a result, the timing margin in each SDRAM cannot be shortened, and the operation of each SDRAM cannot be accelerated. Therefore, if an attempt is made to increase the data transfer rate, the bus width must be increased, the layout of the memory module becomes difficult, and furthermore, it is difficult to align the load between the signals.
[0007]
On the other hand, in the conventional transmission system shown in FIG. 57, a plurality of Rambus type DRAMs (RDRAM) 331 are connected via a one-dimensional data transmission path Rambus channel (proposed by Rambus), and this Rambus channel is connected to an external bus. The memory controller 330 is connected between them, and the reference potential Vref and the synchronous clock CTM from the clock signal source 332 are supplied to each RDRAM 331 via the Rambus channel. The Rambus channel is terminated by a terminal resistance 333 so that reflection noise does not occur, and the load of each bus is uniformed in order to suppress skew between transmission data signals of the bus.
[0008]
The configuration of a memory module in which a plurality of RDRAMs 331 as described above are arranged one-dimensionally on a printed circuit board can simplify the bus configuration, and can transmit and receive large amounts of data by increasing the synchronization clock speed. it can.
[0009]
[Problems to be solved by the invention]
However, since the transmission system shown in FIG. 57 speeds up data transmission / reception instead of increasing the bus width, the specification of the skew between the buses in the entire memory module is strict and the jitter of the clock driver is also limited. In order to cope with this, the resistance and inductance of the wiring on the printed circuit board of the memory module and the mutual conductance between the wirings must be precisely controlled, leading to high costs.
[0010]
In addition, due to miniaturization of LSI elements, the power supply voltage for output (see FIG. 56) and the bus termination voltage VTERM (see FIG. 57) are reduced in consideration of the breakdown voltage of the LSI transistors in the memory module. I have to do it. As a result, the voltage amplitude of the data also decreases, and erroneous reading of data is likely to occur.
[0011]
As described above, the conventional transmission system that handles a large amount of data on a relatively low-speed bus has a situation that the number of bus wirings is increased and the data reading speed cannot be increased.
[0012]
In addition, the conventional transmission system that simplifies the bus configuration and speeds up the synchronous clock to transmit and receive large amounts of data has strict specifications for the skew between the buses in the entire system, and limits the jitter of the clock driver. Therefore, there is a situation that leads to high cost in order to cope with it.
[0013]
Furthermore, as a common situation for both, with miniaturization, the breakdown voltage of the LSI transistor in the memory module is taken into consideration, the power supply voltage for output (see FIG. 56) and the termination voltage (see FIG. 57) are lowered, and the data If the amplitude is reduced, erroneous reading of data is likely to occur.
[0014]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described circumstances, and a data / signal transmission system and a semiconductor integrated circuit that can avoid the situation when a voltage potential is handled as transmission data by handling an amount of current as transmission data. An object is to provide an apparatus.
[0015]
In addition, the present invention makes it possible to perform multi-value data transmission without increasing the transmission data width by performing multi-value current data, with a wide voltage noise margin and fine LSI elements. A semiconductor integrated circuit device that can easily withstand a drop in power supply voltage and the amplitude voltage of an external signal line, and can transmit and receive a large amount of data even when transmitting a low-speed synchronous clock, and a semiconductor integrated circuit device using the same An object is to provide a data / signal transmission system.
[0016]
[Means for Solving the Problems]
  A semiconductor integrated circuit device according to a first aspect of the present invention includes a data input circuit including an AD converter that converts multi-valued current data input from the outside into a data set of binary voltage levels; An internal circuit to which binary voltage level data is supplied from a data input circuit, and a DA converter that multi-values an aggregate of binary voltage level data supplied from the internal circuit are multi-valued. A data output circuit that outputs current data to the outside, and further includes a current transfer circuit that transfers the multi-valued current data input from the outside as a current output to a subsequent stage.The current transfer circuit includes a first transistor connected in a current mirror to a current input transistor that receives multi-valued current data input from the outside at one end and a gate of a current path, and the first transistor A second transistor in which one end of the current path and the gate are connected to one end of the current path of the transistor, a current mirror connection to the second transistor, and multi-valued current data input from the outside is output as current And a third transistor that transfers to the subsequent stage.
  According to a second aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a data input circuit having an AD converter that converts multi-valued current data input from the outside into a set of binary voltage level data; An internal circuit to which binary voltage level data is supplied from the data input circuit, and a DA converter that multi-values a collection of binary voltage level data supplied from the internal circuit, A data output circuit for outputting the current data to the outside, and the AD converter and the DA converter use a clock signal current as a current source.
[0017]
  Also,According to a third aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a data input circuit having an AD converter that converts multi-valued current data input from outside into a data set of binary voltage levels; An internal circuit to which binary voltage level data is supplied from a data input circuit, and a DA converter that multi-values an aggregate of binary voltage level data supplied from the internal circuit are multi-valued. A data output circuit for outputting current data to the outside, an operation mode for outputting the multi-valued current data input from the outside to the outside via the AD converter and the DA converter, and the external A current transfer mode in which multi-valued current data input from is output to the outside without passing through the AD converter and DA converter.
[0018]
  Also,According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a data input circuit having an AD converter that converts multi-valued current data input from the outside into a data set of binary voltage levels; An internal circuit to which binary voltage level data is supplied from a data input circuit, and a DA converter that multi-values an aggregate of binary voltage level data supplied from the internal circuit are multi-valued. A data output circuit for outputting current data to the outside, and a clock signal input from the outside or output to the outside is a current-controlled clock signal current, and the clock signal current is output to the outside A circuit comprising: a reference current source connected between a power supply node and a ground node; a first transistor to which a clock control signal is applied to a gate; A second transistor connected to each other, a first current mirror circuit for outputting a clock signal current obtained by folding the current of the second transistor to an external clock signal line, and the clock signal current from the outside As a circuit to be input, a drain and a gate are connected to each other, a transistor in which a clock signal current input from an external clock signal line is input to the drain, and a second current mirror that folds the current of the transistor and extracts a clock signal current Circuit.
[0019]
  Also,According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit device including a data input circuit having an AD converter that converts multi-valued current data input from the outside into a data set of binary voltage levels; An internal circuit to which binary voltage level data is supplied from a data input circuit, and a DA converter that multi-values an aggregate of binary voltage level data supplied from the internal circuit are multi-valued. A data output circuit for outputting current data to the outside, and the data output circuit simultaneously outputs a clock signal component when the DA voltage converter multi-values the data set of the two voltage levels. Current data on which the clock signal current is superimposed is output to the outside, and the data input circuit receives the current data input on which the clock signal current is superimposed on the AD converter. By and can be converted to the collection of data of the voltage levels of the two values, at the same time take out the clock signal current component.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
First, the outline of the present invention will be described.
[0021]
The data transmission system according to the present invention and the LSI compatible therewith are characterized in that data or signals are transmitted by current data or signals that are multi-valued between semiconductor integrated circuit devices. When performing current transmission of data, it is basically desirable that there is a one-to-one transmission side and reception side. Therefore, when simply transferring a large amount of data / signal, the number of data lines / number of signal lines Will increase.
[0022]
In order to avoid this, the data (current) is multivalued by paying attention to the fact that the current is additive. This multi-value current has a wider noise margin than multi-value voltage. In addition, since data (current) is multi-valued, a large amount of data can be transmitted and received even when a low-speed synchronous clock transmission unit is used.
[0023]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0024]
<First Embodiment>
FIG. 1 is a block diagram showing a part of the LSI according to the first embodiment. Here, the system configuration when the data output circuit section of the first LSI (CHIP-A) 11 is current output and the data input circuit section of the second LSI (CHIP-B) 12 is current input is simplified. Show.
[0025]
That is, the data output circuit section of the first LSI 11 has a digital-to-analog converter (DAC) 14 that multi-values binary voltage data output from the internal circuit 13 and a multi-value output DACout of the DAC 14. Output buffer PMOS transistor 15 that outputs to the external data line 1 as a current value of.
[0026]
The data input circuit portion of the second LSI 12 to which multi-value current is input from the external data line 1 includes an NMOS transistor 16 for input buffer that receives the input current from the external data line 1, and a current mirror connected to the transistor 16. It has a connected NMOS transistor 17 and an analog-to-digital converter (ADC) 19 that converts the current ADCin flowing through the transistor 17 into binary voltage data and supplies it to the internal circuit 18.
[0027]
According to the above configuration, the first LSI 11 outputs current data obtained by multi-valued binary voltage data to the external data line 1, and the second LSI 12 receives multi-value current data input from the external data line 1. Can be converted into binary voltage data and extracted. Therefore, it is possible to realize a transmission system capable of transmitting multi-value current data between a plurality of LSIs via the external data line 1.
[0028]
Second Embodiment
FIG. 2 is a block diagram showing a part of the LSI according to the second embodiment. Here, the system configuration when the data output circuit section of the first LSI (CHIP-A) 21 is a current input and the data input circuit section of the second LSI (CHIP-B) 22 is a current output is simplified. Show.
[0029]
That is, the data output circuit section of the first LSI 21 includes a DAC 23 that multi-values binary voltage data output from the internal circuit 13, a PMOS transistor 24 that converts the output of the DAC 23 into a multi-value current, An NMOS transistor 25 that receives a multi-value current from the transistor 24, and an NMOS transistor 26 for output buffer that is current mirror connected to the transistor 25 and sucks multi-value current data from the external data line 1.
[0030]
The data input circuit section of the second LSI 22 is connected to the external data line 1 and discharges multi-value current data, converts it into binary voltage data in accordance with the multi-value current data, and sends it to the internal circuit 18. It has ADC27 to supply.
[0031]
According to the above configuration, as in the first embodiment described above, the first LSI 21 outputs current data obtained by multi-valued binary voltage data to the external data line 1, and the second LSI 22 outputs the external data line. Multi-value current data input from 1 can be converted into binary voltage data and extracted. Therefore, it is possible to realize a transmission system capable of transmitting multi-value current data between a plurality of LSIs via the external data line 1.
[0032]
<Third Embodiment>
FIG. 3 is a block diagram showing a part of an LSI according to the third embodiment. Here, each of the first LSI (CHIP-A) 31 and the second LSI (CHIP-B) 32 has a dual configuration of a data input circuit unit and a data output circuit unit, and the data transmission direction is one each. The system configuration in the case where the two external data lines 1a and 1b are connected in the direction is shown.
[0033]
In each of the LSIs 31 and 32, the node where the data input circuit is connected to the external data line and the node where the data output circuit is connected to the external data line are separated separately.
[0034]
That is, the data output circuit section of the first LSI 31 is similar to the data output circuit section of the first LSI 11 in FIG. 1, and the DAC 14 multi-values the binary voltage data output from the internal circuit 13; An output buffer transistor 15 for converting the output of the DAC 14 into a multi-value current and outputting the current to the external data line 1a is provided.
[0035]
Further, the data input circuit portion of the first LSI 31 is connected to the external data line 1b, and an input through which a current flows in response to a multi-value current input is the same as the data input circuit portion of the second LSI 12 in FIG. Buffer transistors 16 and 17 and an ADC 19 for converting a multi-value current into binary voltage data and supplying it to the internal circuit 13 are provided.
[0036]
On the other hand, the data input circuit section of the second LSI 32 is connected to the external data line 1a, and is used for an input buffer in which a current flows in response to a multi-value current input, like the data input circuit section of the second LSI 31 Transistors 16 and 17 and an ADC 19 that converts a multi-value current into binary voltage data and supplies it to the internal circuit 18 are provided.
[0037]
Similarly to the data output circuit section of the first LSI 31, the data output circuit section of the second LSI 32 has a DAC 14 that multi-values the binary voltage data output from the internal circuit 18, and the DAC 14 An output buffer transistor 15 that converts the output into a multi-value current and outputs the current to the external data line 1b is provided.
[0038]
According to the above configuration, it is possible to realize a transmission system capable of bidirectionally transmitting multi-valued current data by using two external data lines 1a and 1b separately between a plurality of LSIs.
[0039]
<Fourth embodiment>
FIG. 4 is a block diagram showing a part of an LSI according to the fourth embodiment. Here, each of the first LSI (CHIP-A) 41 and the second LSI (CHIP-B) 42 has a dual configuration of a data input circuit section and a data output circuit section, and the data transmission direction is bidirectional. 2 shows a system configuration when connected by an external data line 1.
[0040]
Here, the data input circuit portion and the data output circuit portion of the first LSI 41 are correspondingly controlled in the active / inactive state by the input enable signal WEA and the inverted signal / OEA of the output enable signal. The data input circuit portion and the data output circuit portion are correspondingly controlled to be activated / inactivated by the input enable signal WEB and the inverted signal / OEB of the output enable signal.
[0041]
Each LSI 41, 42 has a data input circuit and a data output circuit connected in common to the external data line connection node N via the input switch transistors 44, 47 and the output switch transistors 43, 46, respectively. ing.
[0042]
That is, the data output circuit section of the first LSI 41 has the same configuration as the data output circuit section of the first LSI 31 in FIG. 3, and the active / inactive state is controlled by the inverted signal / OEA of the output enable signal. Connected to the external data line 1 through the output switch PMOS transistor 43.
[0043]
Further, the data input circuit section of the first LSI 41 has the same configuration as the data input circuit section of the first LSI 31 in FIG. 3, and an input switch whose active / inactive state is controlled by the input enable signal WEA. This is connected to the external data line 1 through the NMOS transistor 44 for use. A switching NMOS transistor 45 whose active / inactive state is controlled by an input enable signal WEA is also inserted between the transistor 17 and the ADC 19.
[0044]
The data output circuit section of the second LSI 42 has the same configuration as the data output circuit section of the first LSI 41, but the output switch PMOS transistor 46 connected to the external data line 1 has an output enable. The active / inactive state is controlled by the inverted signal / OEB of the signal.
[0045]
The data input circuit section of the second LSI 42 has the same configuration as the data input circuit section of the first LSI 41, but the input switch NMOS transistor 47 connected to the external data line 1 has an input enable. The active / inactive state is controlled by the signal WEB. The input switch NMOS transistor 48 inserted between the transistor 17 and the ADC 19 is also controlled to be activated / deactivated by the input enable signal WEB.
[0046]
Each of the LSIs 41 and 42 receives a control signal and an address signal supplied from an LSI (not shown) on the controller side by a circuit as shown in FIG. 1, decodes it, and outputs the control signal (WEA, / OEA), (WEB, / OEB).
[0047]
According to the above configuration, it is possible to realize a transmission system capable of bidirectionally transmitting multi-valued current data using a single external data line 1 in common between a plurality of LSIs.
[0048]
<Fifth Embodiment>
FIG. 5 is a block diagram showing a transmission system according to the fifth embodiment.
[0049]
Here, a system configuration in which a plurality of DRAMs 52 are daisy chain connected to one memory controller 51 and the memory controller 51 is connected to an external bus 50 is shown.
[0050]
The daisy chain connection employs the Source Synchronous Strobe method. That is, as the clock signal, the basic clock signal CLK and the strobe signal STROBE used for data transmission / reception (output from the transmission side to the reception side in accordance with data transmission) are used. In this example, a basic clock signal CLK is supplied from a clock signal source (clock source) 53 to the controller 51 and the DRAM 52.
[0051]
In this example, two data lines (input data line 54 or output data line 55) having a unidirectional data transmission direction are used, and one strobe signal line 56 having a bidirectional transmission direction is used. A case where data is transmitted bidirectionally between the controller 51 and the DRAM 52 is shown. Further, a part of the DRAM 52, for example, an input / output circuit part thereof has the same configuration as the circuit shown in any of FIGS.
[0052]
FIG. 6 is a waveform diagram showing an example of the operation of the transmission system of FIG.
[0053]
Multi-valued input current data Input (A) from input data line 54 is input and multi-valued by controlling transmission / reception with strobe signal voltage STROBE (V) synchronized with clock signal voltage CLK (V). The current output to the output data line 55 of the output current data Output (A) is performed.
[0054]
<Sixth Embodiment>
FIG. 7 is a block diagram showing a transmission system according to the sixth embodiment.
[0055]
This transmission system is different from the transmission system according to the fifth embodiment shown in FIG. 5 in that two strobe signal lines 61 and 62 having a unidirectional transmission direction are used as strobe signal lines. The same.
[0056]
<Seventh embodiment>
FIG. 8 is a block diagram showing a transmission system according to the seventh embodiment.
[0057]
This transmission system is different from the transmission system according to the sixth embodiment shown in FIG. 7 in that one bidirectional data line 71 is used as a data line. Further, a part of the DRAM 52, for example, an input / output circuit part thereof has the same configuration as the circuit shown in FIG. Others are the same as in the sixth embodiment.
[0058]
FIG. 9 is a waveform diagram showing an example of the operation of the transmission system of FIG.
[0059]
By the input control strobe signal voltage I-STROBE (V) synchronized with the clock signal voltage CLK (V), current input of the multi-valued input data Input (A) from the bidirectional data line 71 is performed, Current output to the bidirectional data line 71 of the multi-valued output current data Output (A) is performed by the output control strobe signal voltage O-STROBE (V).
[0060]
<Eighth Embodiment>
FIG. 10 is a block diagram showing a transmission system according to the eighth embodiment.
[0061]
Here, a configuration of a transmission system in the case where a plurality of DRAMs 102 are star connected to one memory controller 101 and the memory controller 101 is connected to an external bus 100 is shown.
[0062]
The source connection uses the Source Synchronous Strobe method. That is, the bus between the master (memory controller) 101 and the plurality of DRAMs 102 is one-to-one, and the basic clock signal and the strobe signal STROBE used for data transmission / reception are used as the clock signal. In this example, a clock signal voltage is supplied from the clock signal source 103 to the memory controller 101 and the DRAM 102. In addition, the bus connection between the memory controller 101 and the DRAM 102 shows a case where two unidirectional data lines 104 and 105 and one bidirectional strobe signal line 106 are used. Further, a part of the DRAM 102, for example, an input / output circuit part thereof has the same configuration as the circuit shown in any of FIGS.
[0063]
In the transmission systems of the fifth to eighth embodiments described above, the clock signal and the strobe signal are both driven by voltage. However, the clock signal and the strobe signal may be changed to be current-driven. .
[0064]
<Ninth Embodiment>
The ninth embodiment relates to a DAC provided in a data output circuit unit of an LSI suitable for the transmission system according to the present invention.
[0065]
FIG. 11 is a circuit diagram illustrating an example of a DAC according to the ninth embodiment. FIG. 11 shows an example of a DAC that converts, for example, 8-bit binary voltage data DO7 to DO0 into decimal current data DACout.
[0066]
As shown in FIG. 11, eight weight current source NMOS transistors N1 to N8 are current-mirror connected to a reference current source NMOS transistor N0. The weighting current source NMOS transistors N1 to N8 have current values that are 1 times, 2 times, 4 times, 64 times, and 128 times that of the current value of the NMOS transistor N0 for the reference current source. So the size (Wi, ..., Wi x 128) is set.
[0067]
One ends of switching NMOS transistors S1 to S8 are connected to the NMOS transistors N1 to N8, and the other ends of the NMOS transistors S1 to S8 are collectively connected via a load PMOS transistor PL. Connected to the power node. The NMOS transistors S1 to S8 are sized (Wo,..., Wo ×) so as to have current values of 1 ×, 2 ×, 4 ×,..., 64 ×, and 128 times based on the current value of the NMOS transistor N0. 128) is set.
[0068]
The gates of the NMOS transistors S1 to S8 are inputted with the least significant bit DO0 to the most significant bit DO7 of 8-bit binary voltage data, respectively. As a result, the DAC shown in FIG. 11 operates so as to suck in the DA conversion output current DACout flowing to the collective connection node of the NMOS transistors S1 to S8.
[0069]
In other words, the DAC shown in FIG. 11 is connected to the reference current source transistor (N0) and the reference current source transistor (N0) in a current mirror connection, and is 2 in comparison with the current value of the reference current source transistor (N0).^n-1First to nth weighted current source transistors (N1 to N8) sized to have double weighted current values, and one ends corresponding to the first to nth weighted current source transistors. Are connected together and connected to the output node at the other end.^n-1The first to nth switches that are set to have a current value that is weighted twice, and that are input from the least significant bit DO0 to the most significant bit DOn of n-bit binary voltage data corresponding to each gate. Transistor (S1 to S8).
[0070]
In general, it is necessary to match the reference current values on the input side and output side of the transmission system, but there is no problem if the conversion amount is known even if the reference current values do not match. However, in this example, it is assumed that the reference current is the same on the input side and the output side.
[0071]
<Tenth Embodiment>
The ninth embodiment relates to an ADC provided in an LSI data input circuit unit suitable for the transmission system according to the present invention.
[0072]
12, FIG. 13, and FIG. 14 are circuit diagrams showing examples of the ADC according to the tenth embodiment. FIGS. 12, 13 and 14 show an example of an ADC (successive comparison ADC) that converts decimal current data ADCin into 8-bit binary voltage data DI7 to DI0. ing. 12 shows a circuit for converting the most significant bits DI7 to DI4 of the binary voltage data DI7 to DI0 in one ADC, and FIG. 13 shows a circuit for converting bits DI3 and DI2. 14 shows circuits for converting the bits DI1 and DI0, respectively.
[0073]
As shown in FIGS. 12, 13, and 14, the PMOS transistor P0 has a source connected to the power supply node, a gate and a drain connected, and an input current ADCin applied to the drain. The PMOS transistors P8 to P1 have the same size (W1) as the PMOS transistor P0, respectively, and are current mirror connected to the PMOS transistor P0. As a result, the PMOS transistors P8 to P1 pass a current equal to the input current ADCin.
[0074]
On the other hand, a plurality of weighted current source NMOS transistors N8 to N1 are current mirror-connected to the reference current source NMOS transistor N0. The plurality of weighted current source NMOS transistors N8 to N1 are 128 times, 64 times, 32 times, 16 times, 8 times, 4 times, 2 times the current value of the NMOS transistor N0 for the reference current source. The size (Wi × 128,..., Wi) is set so as to have a current value of 1 or 2 times.
[0075]
The NMOS transistor S8 to which the most significant bit DI7 of the binary voltage data DI7 to DI0 is applied to the gate is sized (Wo × 128) so as to have a current value 128 times the reference current. Similarly, the size (Wo × 64) of the NMOS transistor S7 to which the bit DI6 is applied to the gate is set to have a current value 64 times the reference current. Similarly, the size (Wo × 32) of the NMOS transistor S6 to which the bit DI5 is applied to the gate is set to have a current value 32 times the reference current. Similarly, the size (Wo × 16) of the NMOS transistor S5 to which the bit DI4 is applied to the gate is set to have a current value 16 times the reference current. Similarly, the NMOS transistor S4 to which the bit DI3 is applied to the gate is set in size (Wo × 8) so as to have a current value that is eight times the reference current. Similarly, the size (Wo × 4) of the NMOS transistor S3 to which the bit DI2 is applied to the gate is set to have a current value that is four times the reference current. Similarly, the size (Wo × 2) of the NMOS transistor S2 to which the bit DI1 is applied to the gate is set to have a current value that is twice the reference current.
[0076]
The NMOS transistors C8 to C1 to which the comparison enable signal en is applied to the gate have a current value of 128 times, 64 times, 32 times, 16 times, 8 times, 4 times, 2 times, or 1 time of the reference current. The size (Wo × 128, ..., Wo) is set to hold.
[0077]
A first comparison circuit COMP1 shown in FIG. 12 is connected in series between a power supply node and a ground node, and includes a PMOS transistor P8 that passes an input current, an NMOS transistor C8 to which a signal en is applied to the gate, and a reference current. It comprises an NMOS transistor N8 that supplies 128 times the current and an amplifier circuit A8 that converts the drain potential of the PMOS transistor P8 to a binary level.
[0078]
As a result, the first comparison circuit COMP1 compares the input current with the magnitude of the current 128 times the reference current flowing in response to the signal en, and compares the logic level of the most significant bit DI7 among the binary data DI7 to DI0. To decide.
[0079]
The second comparison circuit COMP2 shown in FIG. 12 is different from the first comparison circuit COMP1 in that the PMOS transistor P8 is changed to P7, the NMOS transistor C8 is changed to S8, and the amplifier circuit A8 is changed to A7. The difference is that the NMOS transistor C7 whose signal en is applied to the gate and the NMOS transistor N7 that flows 64 times the reference current are connected in series between the drain of the transistor P7 and the ground node, and the others are the same It is.
[0080]
That is, the second comparison circuit COMP2 includes a PMOS transistor P7 that passes an input current between a power supply node and a ground node, an NMOS transistor S8 to which a bit DI7 is applied to the gate, and an NMOS that passes a current 128 times the reference current. Transistor N8 is connected in series. Further, between the drain of the PMOS transistor P7 and the ground node, an NMOS transistor C7 to which a signal en is applied to the gate and an NMOS transistor N7 for flowing a current 64 times the reference current are connected in series, and the PMOS transistor It comprises an amplifier circuit A8 that converts the drain potential of P7 to a binary level.
[0081]
As a result, when the bit DI7 is “HIGH”, the second comparison circuit COMP2 obtains a value obtained by subtracting 128 times the reference current from the input current and 64 times the reference current flowing in response to the signal en. In comparison, when bit DI7 is “LOW”, the input current is compared with the current 64 times the reference current flowing in response to signal en, and the logical level of bit DI6 of binary data DI7 to DI0 is compared. To decide.
[0082]
The third comparison circuit COMP3 shown in FIG. 12 is different from the second comparison circuit COMP2 in that the PMOS transistor P7 is changed to P6, the NMOS transistor C7 is changed to S7, and the amplification circuit A7 is changed to A6. Between the drain of the transistor P6 and the ground node, an NMOS transistor C6 to which the signal en is applied to the gate and an NMOS transistor N6 that passes a current 32 times the reference current are connected in series, and the others are the same. It is.
[0083]
As a result, when the bits DI7 and DI6 are “HIGH”, the third comparison circuit COMP3 receives the signal en and the reference current flowing by subtracting 128 times and 64 times the reference current from the input current. Compare the current 32 times, and if the bits DI7 and DI6 are “LOW” respectively, compare the input current with the current 32 times the reference current flowing in response to the signal en, and the binary data DI7 to DI0 Of these, the logic level of bit DI5 is determined.
[0084]
The fourth comparison circuit COMP4 shown in FIG. 12 is different from the third comparison circuit COMP3 in that the PMOS transistor P6 is changed to P5, the NMOS transistor C6 is changed to S6, and the amplification circuit A6 is changed to A5. Between the drain of the transistor P5 and the ground node, an NMOS transistor C5 to which the signal en is applied to the gate and an NMOS transistor N5 that passes a current 16 times the reference current are connected in series, and the others are the same. It is.
[0085]
Thereby, the fourth comparison circuit COMP4 receives the signal en and flows by subtracting 128 times, 64 times and 32 times the reference current from the input current when the bits DI7 to DI5 are “HIGH”, respectively. Compares the current 16 times the reference current, and if the bits DI7 to DI5 are “LOW”, compares the input current with the current 16 times the reference current flowing in response to the signal en, and the binary data Of the DI7 to DI0, the logic level of the bit DI4 is determined.
[0086]
The fifth comparison circuit COMP5 shown in FIG. 13 is different from the fourth comparison circuit COMP4 in that the PMOS transistor P5 is changed to P4, the NMOS transistor C5 is changed to S5, and the amplifier circuit A5 is changed to A4. Between the drain of the transistor P4 and the ground node, there is a difference in that an NMOS transistor C4 to which the signal en is applied to the gate and an NMOS transistor N4 that supplies a current eight times the reference current are connected in series. It is.
[0087]
As a result, the fifth comparison circuit COMP5, when the bits DI7 to DI4 are “HIGH”, obtains the signal en obtained by subtracting 128 times, 64 times, 32 times and 16 times the reference current from the input current. Compared with the current that is 8 times the reference current that flows, if the bits DI7 to DI4 are each LOW, compare the input current and the current that is 8 times the reference current that flows in response to the signal en, Of the binary data DI7 to DI0, the logic level of the bit DI3 is determined.
[0088]
The sixth comparison circuit COMP6 shown in FIG. 13 is different from the fifth comparison circuit COMP5 in that the PMOS transistor P4 is changed to P3, the NMOS transistor C4 is changed to S4, and the amplifier circuit A4 is changed to A3. Between the drain of the transistor P3 and the ground node, an NMOS transistor C3 to which the signal en is applied to the gate and an NMOS transistor N3 that supplies a current four times the reference current are connected in series, and the others are the same. It is.
[0089]
Accordingly, the sixth comparison circuit COMP6 is obtained by subtracting 128 times, 64 times, 32 times, 16 times and 8 times the reference current from the input current when the bits DI7 to DI3 are “HIGH”, respectively. Compared with the current that is 4 times the reference current that flows in response to the signal en. When the bits DI7 to DI3 are “LOW”, the input current and the current that is 4 times the reference current that flows in response to the signal en are In comparison, the logic level of the bit DI2 is determined among the binary data DI7 to DI0.
[0090]
The seventh comparison circuit COMP7 shown in FIG. 14 is different from the sixth comparison circuit COMP6 in that the PMOS transistor P3 is changed to P2, the NMOS transistor C3 is changed to S3, and the amplifier circuit A3 is changed to A2. Between the drain of the transistor P2 and the ground node, an NMOS transistor C2 to which the signal en is applied to the gate and an NMOS transistor N2 that supplies a current twice the reference current are connected in series, and the others are the same. It is.
[0091]
Thus, the seventh comparison circuit COMP7 subtracts 128 times, 64 times, 32 times, 16 times, 8 times and 4 times the reference current from the input current when DI7 to DI2 are “HIGH”, respectively. When the bit DI7 to DI2 is “LOW”, the current that is twice the reference current that flows in response to the input current and the signal en is compared. And the logical level of the bit DI1 among the binary data DI7 to DI0 is determined.
[0092]
The eighth comparison circuit COMP8 shown in FIG. 14 is different from the seventh comparison circuit COMP7 in that the PMOS transistor P2 is changed to P1, the NMOS transistor C2 is changed to S2, the amplifier circuit A2 is changed to A1, and the PMOS Between the drain of the transistor P1 and the ground node, there is a difference in that an NMOS transistor C1 whose signal en is applied to the gate and an NMOS transistor N1 that supplies a current that is one time the reference current are connected in series, and the others are the same It is.
[0093]
As a result, the eighth comparison circuit COMP8, when the bits DI7 to DI1 are “HIGH”, is 128 times, 64 times, 32 times, 16 times, 8 times, 4 times and 2 times the reference current from the input current. When the bit DI7 to DI1 are “LOW”, the reference current flowing in response to the input current and the signal en is compared. Compared with the current of 1 time, the logic level of the least significant bit DI0 of the binary data DI7 to DI0 is determined.
[0094]
That is, the ADC shown in FIGS. 12 to 14 receives 2 of the reference current that flows in response to the comparison enable signal en.^n-1A first comparison circuit COMP1 that compares the current value weighted twice and the input current to determine the logic level of the nth bit that is the most significant bit of the n-bit binary data; Depending on the logic level of the 1st bit, 2 from the input current to the reference current^n-12 times the input current minus the double current value or the reference current that flows in response to the comparison enable signal^n-2A combination of a second comparison circuit COMP2 that compares the magnitude of the current with the double current and determines the logic level of the (n-1) th bit in the binary data, and the logic level of the upper bits of the reference current from the input current 2 of the reference current that flows in response to the comparison enable signal and the input current minus a multiple of the current value corresponding to^n-3A third comparison circuit COMP3 to an nth comparison circuit for comparing the magnitudes of the currents with the currents of 1 to 1 times and determining the logic levels of the (n-2) th to least significant bits of the binary data. And COMPn.
[0095]
FIG. 15 is a circuit diagram showing an example of a reference current source (constant current source) BGR used in the DAC shown in FIG. 11 or the ADC shown in FIGS. 12, 13 and 14.
[0096]
A band gap reference circuit is known as a reference current source, and is described in, for example, analog integrated circuit design technology (below) (Baifukan) co-authored by P.R.Gray and R.G.Meyer.
[0097]
The reference current source shown in FIG. 15 is configured by simplifying the cascade connection and replacing the bipolar transistor with a diode based on P.310 and FIG. 12.29 of the above-mentioned literature. explain.
[0098]
Between the power supply node and the ground node, a PMOS transistor TP1, an NMOS transistor TN1 having a drain / gate connected to each other, and a diode D1 are connected in series. Similarly, a PMOS transistor TP2, an NMOS transistor TN2, a resistance element R1, and a diode D2 are connected in series between a power supply node and a ground node. Similarly, between the power supply node and the ground node, a PMOS transistor TP3, a resistance element R2, and a diode D3, which are connected to each other at their gates and drains, are connected in series.
[0099]
The three PMOS transistors TP1 to TP3 are connected to each other to form a current mirror circuit, and the two NOS transistors TN1 and TN2 are connected to each other to form a current mirror circuit. .
[0100]
On the other hand, a PMOS transistor TP4, an NMOS transistor TN3, and a resistance element R3 are connected in series between the power supply node and the ground node. The potential of the source of the NMOS transistor TN3 and the potential of the drain of the PMOS transistor TP3 are input corresponding to the (−) input terminal and the (+) input terminal of the voltage comparison circuit CP. The output terminal is connected to the gate of the PMOS transistor TN3. Further, a current output PMOS transistor TP5 is current mirror connected to the PMOS transistor TP4, and a reference current Iout is output from the drain thereof.
[0101]
In the above configuration, the currents flowing through the diodes D1, D2, and D3 are set to be the same. The diodes D2 and D3 have the same size and are set larger than the diode D1. The resistance elements R1, R2, and R3 have the same resistance value.
[0102]
Suppose that the currents flowing through the diodes D1, D2, and D3 are Id, the anode-cathode voltages of the diodes D1, D2, and D3 are Vbe1, Vbe2, and Vbe3, respectively, and the current that flows through the resistance element R3 is I. ,
Vbe1 = Id xR1 + Vbe2
Id x R2 + Vbe3 = I x R3
Since the diodes D2 and D3 have the same size and are set to have the same flowing current,
Vbe2 = Vbe3
Since the resistance value of the resistance element R1 and the resistance value of R2 are the same,
R2 = R3
here,
ΔVbe = Vbe1 −Vbe2
Vbe = Vbe2 = Vbe3
After all,
I = ΔVbe / R1 + Vbe / R2 (1)
It becomes.
[0103]
In the above equation (1), Vbe corresponds to a voltage at which a current starts to flow forward in the diodes D1, D2, and D3, and corresponds to a difference in Fermi level between the P side and the N side. At higher temperatures, the P-side level tends to be higher and the N-side level tends to be lower due to the Fermi-Dirac distribution, and the difference in Fermi level becomes smaller and Vbe becomes smaller.
[0104]
In the above equation (1), ΔVbe is generated from the difference between the current Id1 flowing through the diode D1 and the current Id2 flowing through the diode D2.
Id = α × exp (q × Vbe / KT) −1 (2)
It is. Here, α includes the size effect of the diodes D1 and D2. Assuming that the sizes of the diodes D1 and D2 are the same, −1 can be ignored for the exponential term in the above equation (2)
ΔVbe = (KT / q) × log {Id1 / Id2} (3)
And is proportional to temperature.
[0105]
Therefore, by using Vbe and ΔVbe whose temperature characteristics change in opposite directions and adjusting the ratio of currents Id1 / Id2 flowing through the diodes D1 and D2 and the resistance values of the resistors R1 and R2, temperature dependence from I is eliminated. Can do.
[0106]
<Eleventh embodiment>
In the case of adopting the Source Synchronous Strobe method as described above, it is possible to send a reference current instead of a voltage as the strobe signal STROBE, and an eleventh embodiment considering this point will be described below.
[0107]
FIG. 16 is a circuit diagram showing an example of a current drive circuit according to the eleventh embodiment. Note that the current drive circuit shown in FIG. 16 is provided in an LSI that drives the strobe signal STROBE in a daisy chain connection transmission system.
[0108]
As shown in FIG. 16, in the first LSI (CHIP-A) 16A for the controller, an NMOS transistor 161 having a reference current source BGR and a strobe enable signal en applied to the gate between the power supply node and the ground node. An NMOS transistor 162 to which the drain and gate are connected is connected in series. Similarly, a PMOS transistor 163 and an NMOS transistor 164, whose gates and drains are connected, are connected in series between the power supply node and the ground node. The two NMOS transistors 162 and 164 are connected to each other to form a current mirror circuit. A current output PMOS transistor 165 is connected in current mirror to the PMOS transistor 163.
[0109]
According to the first LSI 16A configured as described above, the current output from the drain of the current output PMOS transistor 165 can be output to the external strobe signal line 2 as the strobe signal STROBE.
[0110]
On the other hand, in the second LSI (CHIP-B) 16B, the strobe signal current is input from the external strobe signal line 2 to the NMOS transistor 166 having the drain and gate connected to each other. A PMOS transistor 167 and an NMOS transistor 168, whose gates and drains are connected, are connected in series between the power supply node and the ground node, and the NMOS transistor 168 is connected to the NMOS transistor 166 in a current mirror connection. Yes. A PMOS transistor 169 is connected to the PMOS transistor 167 as a current mirror.
[0111]
According to the second LSI 16B configured as described above, the strobe signal current output from the drain of the PMOS transistor 169 can be supplied to the internal circuit. This strobe signal current is supplied to the DAC current source or the ADC current source. Can be used as
[0112]
FIG. 17 is a waveform diagram showing an example of the operation when the strobe signal STROBE shown in FIG. 16 is current-driven. Here, CLK (V) is a clock signal voltage, STROBE (A) is a strobe signal current, Input (A) is a current data input, and Output (A) is a current data output.
[0113]
FIG. 18 is a circuit diagram schematically showing an example of a transmission path of a strobe signal current in the daisy chain-connected transmission system according to the eleventh embodiment. For example, the PMOS transistor 164 is a current source of the DAC 14a, and the PMOS transistor 169 is a current source of the ADC 19a.
[0114]
<Twelfth embodiment>
The above-mentioned Source Synchronous Strobe method is adopted, and it is possible to send the strobe signal STROBE as a reference current as shown in FIG. 16 and to send the strobe signal current superimposed on the data current. Twelve embodiments are described below. In addition, the same code | symbol is attached | subjected to the same part as FIG.
[0115]
FIG. 19A is a circuit diagram schematically illustrating a transmission path of a strobe signal current in a daisy chain-connected transmission system according to the twelfth embodiment.
[0116]
That is, in the twelfth embodiment, when the binary voltage data DO0 to DO7 is DA-converted by the DAC 14a in the next-stage LSI 18B, one unit of data representing the strobe signal STROBE is added. As a result, when the current data controlled by the output of the DAC 14a is output to the external data line 1 through the transistor 43 that is switch-controlled by the output enable signal / OE, the current meaning the strobe signal STROBE is equivalent to one unit. It becomes possible to add.
[0117]
The ADC 19a folds back the data current supplied through the external data line 1 (the strobe signal current is added by one unit) by the NMOS current mirror circuits 16 and 17 in the data input circuit section. The folded data current is input to the transistor 48 that is switch-controlled by the input enable signal WE, and this is AD converted. At this time, the ADC 19a is configured to recognize and convert that the current value of one unit is an extra data value, so that when a current of one unit or more flows, the strobe signal STROBE is output. It can be determined that it has been received.
[0118]
FIG. 20 is a circuit diagram showing an example of the DAC 14a shown in FIG. 19A. FIG. 20 shows a case where 8-bit binary voltage data (DO7 to DO0) and 1-bit strobe signal (clock signal) STRB are converted into decimal current data.
[0119]
The DAC shown in FIG. 20 is compared with the DAC shown in FIG.
(1) One NMOS transistor N1a for strobe signal current source is connected to the NMOS transistor N0 for reference current source in a current mirror connection. The NMOS transistor N1a is connected to the NMOS transistor N0 for reference current source. Must be sized to have the same current value as
[0120]
(2) The switch NMOS transistor SB to which the strobe signal STRB is applied to the gate is connected between the DA conversion output node and the drain of the NMOS transistor N1a for the strobe signal current source.
[0121]
The above two configurations are different, and the other configurations are the same as the DAC shown in FIG.
[0122]
Further, the operation of the DAC shown in FIG. 20 is basically the same as the operation of the DAC shown in FIG. 11 and is particularly different in that a DA conversion operation corresponding to the strobe signal STRB for 1 bit is added.
[0123]
21, FIG. 22, FIG. 23 and FIG. 24 are circuit diagrams showing an example of the ADC 19a shown in FIG. 19A. 21 to 24 show an example of an ADC that converts decimal current data ADCin into 8-bit binary voltage data DI7 to DI0 and 1-bit strobe signal STRB. ing. 21 shows a circuit for converting the most significant bits DI7 to DI4 of the binary voltage data DI7 to DI0 in one ADC, and FIG. 22 shows a circuit for converting the bits DI3 and DI2. 23 shows a circuit for converting the bits DI1 and DI0, and FIG. 24 shows a circuit for converting the strobe signal STRB for one bit.
[0124]
The circuits shown in FIGS. 21, 22, 23, and 24 differ from the ADC shown in FIGS. 12, 13, and 14 in the following configurations (1) to (9), and the others are the same. Since there are, the reference numerals are omitted.
[0125]
(1) In the first comparison circuit COMP1a, instead of the two NMOS transistors C8 and N8 connected in series in order to pass a weighting current that is 128 times the reference current, a weighting current that is 129 times the reference current is used. Two NMOS transistors C8a and N8a that are sized to flow are used.
[0126]
(2) In the second comparison circuit COMP2a, instead of the two NMOS transistors C7 and N7 connected in series to pass a weighting current 64 times the reference current, a weighting current 65 times the reference current is used. Two NMOS transistors C7a and N7a whose sizes are set to flow are used.
[0127]
(3) In the third comparison circuit COMP3a, instead of the two NMOS transistors C6 and N6 connected in series in order to pass a weighting current that is 32 times the reference current, a weighting current that is 33 times the reference current is used. Two NMOS transistors C6a and N6a that are sized to flow are used.
[0128]
(4) In the fourth comparison circuit COMP4a, instead of the two NMOS transistors C5 and N5 connected in series in order to pass a weighting current that is 16 times the reference current, a weighting current that is 17 times the reference current is used. Two NMOS transistors C5a and N5a, which are sized to flow, are used.
[0129]
(5) In the fifth comparison circuit COMP5a, instead of the two NMOS transistors C4 and N4 connected in series to pass a weighting current that is eight times the reference current, a weighting current that is nine times the reference current is used. Two NMOS transistors C4a and N4a whose sizes are set to flow are used.
[0130]
(6) In the sixth comparison circuit COMP6a, instead of the two NMOS transistors C3 and N3 connected in series to pass a weighting current four times the reference current, a weighting current five times the reference current is used. Two NMOS transistors C3a and N3a whose sizes are set to flow are used.
[0131]
(7) In the seventh comparison circuit COMP7a, instead of the two NMOS transistors C2 and N2 connected in series to pass a weighting current twice as large as the reference current, a weighting current that is three times as large as the reference current is used. Two NMOS transistors C2a and N2a whose sizes are set to flow are used.
[0132]
(8) In the eighth comparison circuit COMP8a, instead of the two NMOS transistors C1 and N1 connected in series in order to pass a weighting current that is one time the reference current, a weighting current that is twice the reference current is used. Two NMOS transistors C1a and N1a whose sizes are set to flow are used.
[0133]
(9) A comparison circuit COMP-S for strobe signals is added. This comparison circuit COMP-S replaces the two NMOS transistors C1a and N1a that are connected in series in order to pass a weighting current twice the reference current as compared with the eighth comparison circuit COMP8 shown in FIG. Thus, two NMOS transistors C1 ′ and N1 ′ each having a size set to pass a weighting current that is one times the reference current are used, and further, between the drain of the PMOS transistor P1 and the ground node. The difference is that the NMOS transistor C1 to which the minimum weight bit DI0 is applied to the gate and the NMOS transistor N1 that flows a current that is one time the reference current are connected in series, and the others are the same.
[0134]
As a result, when the bits DI7 to DI0 are “HIGH”, the comparison circuit COMP-S for strobe signals is 128 times, 64 times, 32 times, 16 times, 8 times, 4 times the reference current. Compares the subtracted times, 2 times and 1 times with the current that is 1 times the reference current that flows in response to the signal en. If the bits DI7 to DI0 are “LOW”, the input current and the signal en are The level of the strobe signal (clock signal) STRB is determined by comparing the received current with a current that is one time the reference current.
[0135]
That is, the ADC shown in FIGS. 21 to 24 receives 2 of the reference current that flows in response to the comparison enable signal en.^n-1A first comparison circuit COMP1a that compares the magnitude of the current value weighted by +1 and the input current and determines the logic level of the nth bit that is the most significant bit of the n-bit binary data; According to the logic level of the nth bit, the reference current is 2 from the input current.^n-12 times the input current and the reference current that flows in response to the comparison enable signal.^n-2A second comparison circuit COMP2a that compares the magnitude of the current with +1 times the current and determines the logic level of the (n-1) th bit of the binary data; and the logic level of the upper bit with respect to the reference current A value obtained by subtracting a current value corresponding to a multiple corresponding to the combination, or 2 of the reference current that flows in response to the input current and the comparison enable signal.^n-3+1 times to 2⁰The third comparison circuit COMP3a to the nth comparison circuit COMPna for comparing the magnitudes of the currents with the current of +1 times and determining the logic levels of the (n−2) th to the least significant bits of the binary data. And a value obtained by subtracting a current value corresponding to a multiple corresponding to a combination of the logic levels of the most significant bit to the least significant bit with respect to the reference current from the input current or the input current, and the comparison enable signal. And a clock signal comparison circuit COMP-S for comparing the magnitude of the current with a current that is one time the reference current flowing in the direction and determining the logic level of the strobe signal STRB.
[0136]
The operation of the ADC shown in FIGS. 21 to 24 is basically the same as the operation of the ADC shown in FIGS. 12 to 14, except that an AD conversion operation corresponding to the strobe signal STRB for 1 bit is added. . In this case, if one unit of current can be detected after converting bits DI7 to DI1, it corresponds to the strobe signal STRB. That is, since the strobe signal STRB can be detected after the AD conversion of the data current is completed, the strobe signal STRB can be used as a control signal for a circuit that latches the conversion output of the bits DI7 to DI1. That is, the bits DI7 to DI1 are latched in the data latch circuit 170 at the rising edge of the strobe signal STRB.
[0137]
According to the twelfth embodiment, the strobe signal STROBE can be sent as the reference current, and the strobe signal current can be sent superimposed on the data current.
[0138]
FIG. 25 is a waveform diagram showing an example of the operation when the strobe signal current is superimposed on the current data Input (A) and Output (A) in the daisy chain-connected transmission system shown in FIG. 19A. Here, the current data period T1 shows only the strobe signal current STRB, and the current data period T2 shows the case where the strobe signal current STRB is superimposed on the current data.
[0139]
<First and Second Modifications of DAC>
The DAC shown in FIG. 20 treats the 1-bit strobe signal (clock signal) STRB as having the same weight as the least significant bits of the 8-bit binary voltage data DO7 to DO0.
[0140]
However, the strobe signal (clock signal) STRB for 1 bit may be assigned to the upper bits or the lower bits than the 8-bit binary voltage data DO7 to DO0. FIG. 26 shows a first modification in which the strobe signal STRB is assigned to the upper bits, and FIG. 27 shows a second modification in which the strobe signal STRB is assigned to the lower bits.
[0141]
The DAC shown in FIG. 26 is different from the DAC shown in FIG. 20 in that a reference current source is replaced with a strobe signal current source NMOS transistor N1a and a switch NMOS transistor SB to which the strobe signal STRB is applied to the gate. The difference is that NMOS transistors N9 and S9 having a size in which a current flowing 256 times as large as that of the NMOS transistor is provided are the same.
[0142]
That is, the DAC shown in FIG. 26 is connected to the reference current source transistor N0 and the reference current source transistor in a current mirror connection, and is 2 in comparison with the current value of the reference current source transistor.ⁿCorresponding to the first to (n + 1) th weighted current source transistors N1 to N9 sized to have a current value weighted twice, and to the first to (n + 1) th weighted current source transistors Each one end is connected and each other end is connected to the output node in a lump.ⁿThe size is set so as to have a current value that is weighted twice, and the least significant bit DO0 to the most significant bit DO7 of the n-bit binary voltage data and the strobe signal STRB are input corresponding to each gate. To (n + 1) th switching transistors S1 to S9.
[0143]
The operation of the DAC shown in FIG. 26 is basically the same as the operation of the DAC shown in FIG. 20, and the strobe signal STRB is assigned to higher bits than the 8-bit binary voltage data DO7 to DO0 and is DA-converted. The point is different.
[0144]
Compared to the DAC shown in FIG. 20, the DAC shown in FIG. 27 replaces the NMOS transistor N1a for the strobe signal current source and the switching NMOS transistor SB to which the strobe signal STRB is applied to the gate, with a reference current source. The difference is that NMOS transistors N1 / 2 and S1 / 2 in which the size of a current that is ½ times that of the current NMOS transistor is set are provided, and the others are the same, so the reference numerals are omitted.
[0145]
That is, the DAC shown in FIG. 27 is connected to the reference current source transistor N0 and the reference current source transistor in a current mirror connection, and is 2 times larger than the current value of the reference current source transistor.^n-11st to (n + 1) th weighted current source transistors N1 to N8, N1 / 2 sized to have current values weighted by a factor of 1/2 and 1/2, and the first to (n + 1) th of the first to (n + 1) th One end is connected to each of the weighted current source transistors, and the other ends are collectively connected to the output node.^n-1The size is set so as to have a current value weighted twice or 1/2 times, and the least significant bit DO0 to the most significant bit DO7 of the n-bit binary voltage data and the strobe signal STRB corresponding to each gate. Are provided with first to (n + 1) th switching transistors S1 to S8, S1 / 2.
[0146]
The operation of the DAC shown in FIG. 27 is basically the same as the operation of the DAC shown in FIG. 20, and the strobe signal STRB is assigned to lower bits than the 8-bit binary voltage data DO7 to DO0 and DA-converted. The point is different.
[0147]
<First and Second Modifications of ADC>
The ADC shown in FIGS. 21 to 24 treats the 1-bit strobe signal (clock signal) STRB as having the same weight as the least significant bits of the 8-bit binary voltage data DO7 to DO0.
[0148]
However, the strobe signal (clock signal) STRB for 1 bit may be assigned to the upper bits or the lower bits than the 8-bit binary voltage data DO7 to DO0. A first modification example in which the strobe signal STRB is assigned to the upper bits is shown in FIGS. 28 to 30, and a second modification example in which the strobe signal STRB is assigned to the lower bits is shown in FIGS. 31 to 34.
[0149]
The ADC shown in FIGS. 28 to 30 uses a strobe signal (clock) STRB instead of the comparison enable signal en as compared with the ADC shown in FIGS. 21 to 24, and the strobe signal STRB is gated. The size of the NMOS transistors C8b to C1b applied to the NMOS transistor C8b, the size of the NMOS transistors N8b to N1b for weighted current sources connected in series to the NMOS transistors C8b to C1b, and the configuration of the comparison circuit COMP-SU for the strobe signal Different. Since the others are the same, the reference numerals are omitted.
[0150]
That is, the ADC shown in FIGS. 28 to 30 receives 2 of the reference current that flows in response to the comparison enable signal en.ⁿA comparison circuit COMP-SU for comparing the current value weighted twice and the input current and determining the logic level of the strobe signal STRB, and (2) of the reference current flowing in response to the strobe signal STRB.ⁿ+2^n-1) A first comparison circuit COMP1b that compares the magnitude of the current value weighted twice and the input current and determines the logic level of the nth bit that is the most significant bit of the n-bit binary data; According to the logic level of the nth bit, the reference current is 2 from the input current.^n-1(2) of the reference current flowing by receiving the input current and the strobe signal STRB.ⁿ+2^n-2) A second comparison circuit COMP2b for comparing the magnitude of the current with the double current and determining the logic level of the (n-1) th bit in the binary data, and the logic level of the upper bit with respect to the reference current A current value corresponding to a multiple corresponding to the combination is subtracted from the input current, or (2) of the reference current that flows in response to the input current and the strobe signal STRB.ⁿ+2^n-3) ~ (2ⁿ+2⁰) A third comparison circuit COMP3b to an nth comparison circuit COMPnb that compares the magnitudes of the currents with each other and compares them to determine the logic level of the (n−2) th to least significant bits of the binary data. It is characterized by comprising.
[0151]
The operation of the ADC shown in FIGS. 28 to 30 is basically the same as the operation of the ADC shown in FIGS. 21 to 24, and the strobe signal STRB is assigned to higher bits than the 8-bit binary voltage data DO7 to DO0. The difference is that AD conversion is performed.
[0152]
31 to 34 are compared with the ADCs shown in FIGS. 21 to 24, the sizes of NMOS transistors C8c to C1c to which the comparison enable signal en is applied to the gate, and are connected in series to these NMOS transistors C8c to C1c. The weighted current source NMOS transistors N8c to N1c are different in size and the configuration of the strobe signal comparison circuit COMP-SD. Since the others are the same, the reference numerals are omitted.
[0153]
That is, the ADC shown in FIGS. 31 to 34 receives 2 of the reference current that flows in response to the comparison enable signal en.^n-1The first comparison circuit COMP1c that compares the current value weighted by +1/2 and the input current and determines the logic level of the nth bit that is the most significant bit of the n-bit binary data And a reference current of 2 from the input current according to the logic level of the nth bit.^n-12 times the reference current that flows in response to the input current and the comparison enable signal en.^n-2A second comparison circuit COMP2c that compares the magnitude of the current with +1/2 times the current and determines the logic level of the (n-1) th bit of the binary data; A current value corresponding to a multiple corresponding to a combination of logic levels is subtracted from the input current or 2 of a reference current that flows in response to the input current and the comparison enable signal en.^n-3+1/2 times to 2⁰A third comparison circuit COMP3c to n-th circuit for comparing the magnitudes of the currents with +1/2 times the current and determining the logic level of the (n−2) th to least significant bits of the binary data. The comparison circuit COMPnc and the input current obtained by subtracting the current value corresponding to a multiple corresponding to the combination of the logic levels of the most significant bit to the least significant bit with respect to the reference current, or the comparison A comparison circuit COMP-SD for clock signal that compares the magnitude with a current that is half the reference current flowing in response to the enable signal en and determines the logic level of the strobe signal STRB is provided. It is.
[0154]
The operation of the ADC shown in FIGS. 31 to 34 is basically the same as the operation of the ADC shown in FIGS. 21 to 24, and the strobe signal STRB is set to a lower bit than the 8-bit binary voltage data DO7 to DO0. The difference is that it is assigned and AD converted.
[0155]
As described above, when the strobe signal STRB signal is the lowest, the determination of the strobe signal STRB is made last. Therefore, data is latched at the rising edge of the strobe signal STRB.
[0156]
When the strobe signal STRB is the highest, the strobe signal STRB is determined first. Therefore, as shown in FIG. 19B, the strobe signal STRB is delayed by the time required for AD conversion of the bits DO7 to DO0 by the delay circuit 171 and then the data is latched at the rising edge of the delayed strobe signal STRBd. Alternatively, as shown in FIG. 19C, after strobe signal STRB is inverted by inverter 172, data may be latched at the falling edge of the inverted strobe signal / STRB.
[0157]
<Relationship between DAC reference current and ADC reference current, first to third modifications of reference current source>
In order to accurately perform the circuit operation of the DAC and the circuit operation of the ADC, the reference current of the ADC may be set to be larger than 1/2 and smaller than twice the reference current of the DAC.
[0158]
In order to increase the operation margin of the amplifier circuit on the output side of the ADC, it is desirable to increase the potential amplitude of the input of the amplifier circuit. In this case, the reference current of the ADC is larger than one time the reference current of the DAC, It is better to set it smaller than 2 times.
[0159]
Based on the relationship between the reference currents, the value of the reference current may be determined according to specifications. In this case, as shown in FIG. 35, the current value of the BGR is used as it is as the reference current for DAC, and for example, 1.5 times the reference current for DAC is used as the reference current for ADC. 36 and 37, a reference current source is provided in the transmission system, the reference current for DAC uses the current value of the reference current source as it is, and the reference current for ADC is the current value of the reference current source. For example, it is possible to use 1.5 times.
[0160]
FIG. 35 shows a circuit example when the current value of the BGR in the LSI is used as a reference current for DAC, and a current value 1.5 times the current value of the BGR is used as a reference current for ADC.
[0161]
The circuit shown in FIG. 35 supplies the output current of the PMOS transistor TP5, which is current mirror connected to the PMOS transistor TP4 in the output stage of the BGR shown in FIG. 15, as a reference current for DAC. A PMOS transistor TP6 having a size of 1.5 × W is connected to the PMOS transistor TP4 as a current mirror, and an output current of the PMOS transistor TP6 is supplied as a reference current for ADC. In FIG. 35, the same parts as those in FIG. 15 are denoted by the same reference numerals.
[0162]
In FIG. 36, in the daisy chain connection transmission system, the reference current values of the DAC and ADC in the LSI are determined by an external reference current source, and the reference current for the DAC uses the current value of the reference current source. In the circuit example, the reference current for ADC is 1.5 times the current value of the reference current source.
[0163]
In FIG. 36, the first LSI chip 351 receives a reference current input from an external (eg, controller) reference current source 350 by a current mirror circuit including NMOS transistors 353 and 354, and receives this reference current as PMOS transistors 355 and 356. The current mirror circuit consisting of Further, PMOS transistors 357 and 358 are connected to the PMOS transistor 355 as a current mirror. In this case, assuming that the size of the PMOS transistors 356 and 357 is W, the size of the PMOS transistor 358 is set to 1.5 × W. The output current of the PMOS transistor 357 is supplied as a reference current for DAC, the output current of the PMOS transistor 358 is supplied as a reference current for ADC, and the output current of the PMOS transistor 356 is supplied to the second LSI chip in the next stage. 352 is transmitted as a reference current.
[0164]
The second LSI chip 352 has the same configuration as that of the first LSI chip 351, and receives a reference current input from the first LSI 351 in the previous stage by a current mirror circuit including NMOS transistors 353 and 354. The output current of the transistor 357 is supplied as a reference current for DAC, the output current of the PMOS transistor 358 is supplied as a reference current for ADC, and the output current of the PMOS transistor 356 is transmitted as a reference current to the LSI chip at the next stage.
[0165]
FIG. 37 shows that the reference current values of the DAC and ADC in the LSI are determined by an external (eg, controller) reference current source in the star-connected transmission system, and the reference current source uses the current value of the reference current source. In the circuit example, the reference current for ADC uses 1.5 times the current value of the reference current source.
[0166]
In FIG. 37, the first LSI chip 361 receives a reference current input from an external (eg, controller) reference current source 360 by a current mirror circuit including NMOS transistors 363 and 364, and receives this reference current as PMOS transistors 365 and 366. The current mirror circuit consisting of A PMOS transistor 367 is further connected to the PMOS transistor 365 as a current mirror. In this case, assuming that the size of the PMOS transistor 366 is W, the size of the PMOS transistor 367 is set to 1.5 × W. The output current of the PMOS transistor 366 is supplied as a reference current for DAC, and the output current of the PMOS transistor 367 is supplied as a reference current for ADC. The second LSI chip 362 has the same configuration as the first LSI chip 361 and operates in the same manner. However, a current output different from that of the first LSI chip 361 is received.
[0167]
<13th Embodiment>
In the above-described daisy chain connection transmission system, when the current from the preceding LSI is transferred to the succeeding LSI, it is inefficient to convert the current input to AD and then DA again to obtain the current output. A thirteenth embodiment in which this point is improved will be described below.
[0168]
FIG. 38 is a circuit diagram schematically showing a memory LSI compatible with a daisy chain-connected transmission system according to the thirteenth embodiment.
[0169]
38 includes a current input type data input circuit unit 241 connected to an external data line, a memory cell array 242 for storing voltage data output from the ADC 19 of the data input circuit unit, and the memory The current output type data output circuit unit 243 that converts the voltage data output from the cell array 242 by the DAC 14 and outputs the converted data to the external data line, and directly converts the input current from the external data line on the previous stage into a current output without AD conversion. A current transfer circuit 244 for transferring to the external data line on the rear stage side.
[0170]
The current transfer circuit 244 includes an NMOS transistor 245 that is current-mirror connected to the current input NMOS transistor 16 of the data input circuit unit 241, and a PMOS having a gate and a drain connected to a path through which the current of the NMOS transistor 245 flows. A transistor 246, a PMOS transistor 247 that is current-mirror connected to the PMOS transistor 246, and a current transfer that is connected between the PMOS transistor 247 and a current output node, and an inverted signal / PASS of the transfer enable signal is applied to the gate. PMOS transistor 248.
[0171]
In the current output type data output circuit unit 243, a PMOS transistor 249, to which a transfer enable signal PASS is applied, is inserted and connected between a current output PMOS transistor 15 and a current output node.
[0172]
Therefore, when the signal / PASS is inactive (“HIGH” level), the current transfer PMOS transistor 248 is turned off, and the current output PMOS transistor 249 is turned on to output from the memory cell array 242. Current data corresponding to the voltage data to be output is output.
[0173]
On the other hand, when the signal / PASS becomes active ("LOW" level), the current transfer PMOS transistor 248 is turned on and the current output PMOS transistor 249 is turned off. It is possible to transfer the current as it is to the subsequent LSI as a current output without AD conversion.
[0174]
According to the thirteenth embodiment, the power consumption can be reduced as compared with the case where the current input is AD-converted and then DA-converted again to output the current.
[0175]
<Fourteenth embodiment>
In the daisy chain connection transmission system described above, the current data to be transmitted is not limited to one type, and a plurality of types of data can be selected. A fourteenth embodiment in consideration of this point will be described below.
[0176]
FIG. 39 is a circuit diagram schematically showing a memory LSI compatible with a daisy chain-connected transmission system according to the fourteenth embodiment, and the same components as those in FIG. 38 are denoted by the same reference numerals.
[0177]
In the data input circuit portion of this memory LSI, the input current from the external data line on the previous stage side is input to the ADC 19 via the NMOS transistor 251 to which the signal / PASS is applied to the gate, and binary conversion output data by this ADC 19 is input. Are selectively stored in the memory cell array 242, the register (A) 253 and the register (B) 254 by the first multiplexer (MUX) 252. The output data from the memory cell array 242, the register (A) 253, and the register (B) 254 are selectively switched by the second MUX 255 and input to the DAC 14, and the current corresponding to the decimal conversion output by the DAC 14 The transfer enable signal PASS is output to the external data line on the rear stage side through the PMOS transistor 249 to which the gate is applied.
[0178]
Also, an input current from the external data line on the preceding stage is input to the current transfer circuit 244, a transfer NMOS transistor 256 to which the transfer enable signal PASS is applied to the gate, and a PMOS transistor 248 to which the signal / PASS is applied to the gate. To control the current transfer operation and output a current to the external data line on the rear stage side.
[0179]
<Modification of 14th Embodiment>
In the fourteenth embodiment, it is assumed that the current transmitted through the external data line is only data. However, the present invention is not limited to this, and the control signal can be included in the data as described above. A modified example in consideration of the above will be described below.
[0180]
FIG. 40 is a circuit diagram schematically showing a memory LSI according to a modification of the fourteenth embodiment.
[0181]
The LSI shown in FIG. 40 inputs a control signal included in the data obtained by converting the input current by the ADC 19 to the command decoder 261, as compared with the LSI described above with reference to FIG. The command decoder 261 controls the activation / inactivation of complementary signals PASS and / PASS which are decode outputs according to the result of interpreting the content of the control signal included in the data. That is, when the input current is transferred by the current transfer circuit 244, the signals PASS and / PASS are activated (the signal PASS is “HIGH” and the signal / PASS is “LOW”), and the data is converted by the DAC 14 again. When outputting own data, the signals PASS and / PASS are deactivated (the signal PASS is “LOW” and the signal / PASS is “HIGH”).
[0182]
When the signals PASS and / PASS are activated, the current transfer transistor 248 is turned on and the data output transistor 249 is turned off. When the signals PASS and / PASS are deactivated, the current transfer transistor 248 is turned on. Is turned off, and the data output transistor 249 is turned on.
[0183]
<Fifteenth embodiment>
FIG. 41 is a circuit diagram schematically showing a memory LSI that is compatible with a daisy chain-connected transmission system according to the fifteenth embodiment.
[0184]
This memory LSI separates a data (DQ) transmission path and a control signal / address signal (RQ) transmission path such as Read / Write.
[0185]
That is, the data (DQ) transmission path is almost the same as the configuration in which the two multiplexers 252 and 255, the two registers (A) 253, and the register (B) 254 in the memory LSI described above with reference to FIG. Similarly, the current data input DQIN is received from the data input line on the front stage side, and the current data output DQOUT is output to the data output line on the rear stage side.
[0186]
On the other hand, the transmission path of the control signal / address signal (RQ) is a current input type control signal / address signal input circuit section that receives the control signal / address signal input RQIN from the control signal / address signal input line on the preceding stage side. 271; a decoder 272 that decodes voltage data output from the ADC 19a of the input circuit unit and outputs a control signal such as a transfer enable signal PASS and Read / Write; and an address signal; and the control signal / address signal input circuit unit An NMOS transistor 274 that is current-mirror connected to the NMOS transistor 273 for current input 271, a PMOS transistor 275 that is connected to the gate and drain through which the current of the NMOS transistor 274 flows, and a current mirror-connected to the PMOS transistor 275 , The drain is connected to the control signal / address signal output node, And a PMOS transistor 276 for outputting a control signal / address signal line current output RQOUT the control signal / address signal lines.
[0187]
<Sixteenth Embodiment>
FIG. 42 is a circuit diagram schematically showing a memory LSI suitable for the star-connected transmission system according to the sixteenth embodiment.
[0188]
Since this memory LSI corresponds to star connection as compared with the memory LSI described above with reference to FIG. 41, a current transfer circuit and a control signal / address signal (RQ) transmission path in the data (DQ) transmission path. However, the current transfer circuit is omitted, and the input enable signal WE is used instead of the signal / PASS, and the output enable signal / OE is used instead of the signal PASS.
[0189]
Compared with the input / output operation with the memory LSI transmission system described above with reference to FIG. 41, the input / output operation with the memory LSI transmission system includes a star-connected transmission system and a daisy chain-connected transmission system. This is basically the same although it differs depending on the difference in the communication protocol.
[0190]
<First Modification of Fifteenth and Sixteenth Embodiments>
In the fifteenth and sixteenth embodiments, the control signal / address signal is handled on the same transmission path. However, the present invention is not limited to this, and the control signal / address signal can be separated.
[0191]
<Second Modification of Fifteenth and Sixteenth Embodiments>
In the fifteenth embodiment and the sixteenth embodiment, one set of data (DQ) transmission paths is provided. However, when the data to be transmitted is increased to two sets or further increased, the data ( DQ) transmission route should be added.
[0192]
<Seventeenth Embodiment>
In the above-described embodiment, the strobe signal current is superimposed on the data current. However, it is also possible to superimpose the clock signal current on the data current, and the seventeenth embodiment considering this point will be described below.
[0193]
FIG. 43 is a block diagram showing a daisy chain connection transmission system according to the seventeenth embodiment.
[0194]
Here, a system configuration is shown in which a plurality of DRAMs 292 are daisy chain connected to one memory controller 291 by two unidirectional data lines 1a and 1b, and the controller 291 is connected to an external bus 290. .
[0195]
The memory controller 291 of this transmission system receives a voltage mode clock signal input from the clock signal source 293, converts it into a current mode clock signal, outputs it constantly, and superimposes the data current on the clock current output during data output. Is configured to do.
[0196]
In the DRAM 292 of this transmission system, a current drive circuit may be configured as in the case of transmitting the strobe signal current superimposed on the data current as shown in FIG. 19A, for example.
[0197]
In this case, for example, a circuit as shown in FIG. 20 may be provided as the DAC 14a of the output unit of the current drive circuit shown in FIG. 19A, and the clock signal Clock may be used instead of the strobe signal STRB. Further, as the ADC 19a of the input part of the current drive circuit, for example, circuits as shown in FIGS. 21 to 23 may be provided, and the clock signal Clock may be used instead of the strobe signal STRB.
[0198]
FIG. 44 is a waveform diagram showing an example of the operation when the data current is superimposed on the clock signal current in the transmission system shown in FIG.
[0199]
<Modification of 17th Embodiment>
It is also possible to send a reference current as the clock signal and generate a clock signal voltage in response to the reference current. A modified example in consideration of this point will be described below.
[0200]
FIG. 45 is a circuit diagram showing an example of a current drive circuit that outputs a clock signal as a current and a circuit that converts the clock signal current into a clock signal voltage in a transmission system according to a modification of the seventeenth embodiment.
[0201]
In FIG. 45, in the first LSI 321 for the controller, the reference current source BGR, the NMOS transistor 323 to which the clock source signal en is applied to the gate, and the drain / gate are connected between the power supply node and the ground node. The NMOS transistors 324 are connected in series. Similarly, a PMOS transistor 325 and an NMOS transistor 326, whose gates and drains are connected, are connected in series between the power supply node and the ground node. The two NOS transistors 324 and 326 are connected to each other to form a current mirror circuit. A current output PMOS transistor 327 is current-mirror connected to the PMOS transistor 325.
[0202]
According to the first LSI 321 configured as described above, the current output from the drain of the PMOS transistor 327 for current output can be output to the external signal line (strobe signal line) as the clock signal Clock.
[0203]
On the other hand, in the second LSI 322, the strobe signal current is input from the external strobe signal line 2 to the NMOS transistor 328 having the drain and gate connected to each other. A PMOS transistor 329 and an NMOS transistor 330 having gates and drains connected to each other are connected in series between a power supply node and a ground node, and the NMOS transistor 330 is connected to the NMOS transistor 328 in a current mirror connection. Yes. A PMOS transistor 331 is connected to the PMOS transistor 329 in a current mirror connection.
[0204]
Further, an NMOS transistor 332 having a reference current source BGR and drain / gate connected to each other is connected in series between the power supply node and the ground node. An NMOS transistor 333 is connected to the NMOS transistor 332 in a current mirror, and the drain of the NMOS transistor 333 is connected to the drain of the PMOS transistor 331. An amplifier circuit 334 is connected to the drain interconnection node of the PMOS transistor 331 and the NMOS transistor 333.
[0205]
Here, the current of the reference current source BGR of the second LSI 322 is set equal to the current of the reference current source BGR of the first LSI 321, and half of the current of the PMOS transistor 331 is transferred to the NMOS transistor 333 in the second LSI 322. Set the size to flow.
[0206]
According to the second LSI 322 configured as described above, the amplifier circuit 334 normally receives a low potential input, but receives a high potential input when a current is output from the PMOS transistor 331 when a clock signal current is input. The clock signal current input can be converted into a clock signal voltage, output, and supplied to an internal circuit.
[0207]
<Eighteenth embodiment>
FIG. 46 is a block diagram showing a transmission system according to the eighteenth embodiment.
[0208]
This transmission system differs from the transmission system according to the fifth embodiment shown in FIG. 5 in that the strobe signal line is terminated as a bus line and the clock signal line is also terminated, and the others are the same.
[0209]
<Nineteenth embodiment>
FIG. 47 is a circuit diagram schematically showing a memory LSI compatible with a daisy chain-connected transmission system according to the nineteenth embodiment.
[0210]
This example is different from the memory LSI according to the thirteenth embodiment shown in FIG. 38 in that data input and data output are performed on the data transmission side 301 from the controller provided in the memory chip. For this reason, a circuit similar to the circuit shown in FIG. 38 is arranged on the data transmission side 301.
[0211]
A current transfer circuit 303 having a circuit configuration similar to that of the current transfer circuit 244 is disposed on the data feedback side 302 to the controller. The current transfer circuit 303 is different from the current transfer circuit 244 in that it always transfers a data current.
[0212]
As shown in FIG. 47, the current transfer circuit 303 includes an NMOS for current input, a transistor 304, an NMOS transistor 305 that is current-mirror connected to the NMOS transistor 304, and a path through which the current of the NMOS transistor 305 flows. A PMOS transistor 306 having a gate and a drain connected thereto, a PMOS transistor 307 having a current mirror connection to the PMOS transistor 306, a drain connected to the PMOS transistor and a current output node, and a gate connected to an in-circuit ground potential VSS And a PMOS transistor 308 for receiving. There is no problem even if the PMOS transistor 308 is omitted and the PMOS transistor 308 is directly connected to the output.
[0213]
<20th Embodiment>
FIG. 48 is a circuit diagram schematically showing a memory LSI compatible with a daisy chain-connected transmission system according to the twentieth embodiment.
[0214]
This example is different from the memory LSI according to the nineteenth embodiment shown in FIG. 47 in that data input and data output are performed on the data feedback side 302 from the controller provided in the memory chip. Therefore, a circuit similar to the circuit shown in FIG. On the data transmission side 301 from the controller, a current transfer circuit 303 that always transfers a data current is arranged.
[0215]
<Twenty-first embodiment>
FIG. 49 is a circuit diagram schematically showing a memory LSI compatible with a daisy chain-connected transmission system according to the twenty-first embodiment.
[0216]
This example is different from the memory LSI according to the nineteenth embodiment shown in FIG. 47 in that data input is performed on the data transmission side 301 and data output is performed on the data feedback side 302. Therefore, in the current transfer circuit 303, the PMOS transistors 307 and 308 constituting the output stage are arranged on the data transmission side 301, and the NMOS and the transistors 304 and 305 and the PMOS transistor 306 constituting the input stage are arranged on the data feedback side 302. Has been placed.
[0217]
Also, as in this example, when data input is performed on the data transmission side 301 and data output is performed on the data feedback side 302, it is important to adjust the data output timing. This is because the latency seen from the controller is adjusted in each of a plurality of memory chips connected in a daisy chain. Therefore, in this example, a delay circuit 311 is provided at the output portion of the memory cell array 242. The delay circuit 311 is controlled by delay data stored in the register 312, for example. Then, the data output from the memory cell array 242 is delayed so that the latency seen from the controller matches each of the plurality of memory chips connected in a daisy chain. Delay data is stored by daisy chain initialization along with chip-ID set. The nearest memory is set to the highest latency. The delay data setting method is the same as the chip-ID setting method. The unit delay time corresponding to the delay data is designed so that the latency seen from the controller matches.
[0218]
<Twenty-second embodiment>
FIG. 50 is a circuit diagram schematically showing a memory LSI compatible with a daisy chain-connected transmission system according to the twenty-second embodiment.
[0219]
In the nineteenth, twentieth and twenty-first embodiments, the data path portion has been exemplified. In this example, the address / command path portion is illustrated.
[0220]
This embodiment is different from the nineteenth embodiment shown in FIG. 47 in that the ADC 19a that AD converts the address signal and the command signal, and the voltage data output from the ADC 19a are decoded and the address signal and the command signal are output. A decoder 272 that performs processing.
[0221]
Further, the current transfer circuit 244 ′ is configured to always transfer current by supplying the in-circuit ground potential VSS to the gate of the PMOS transistor 248 ′ constituting the output stage.
[0222]
<23rd Embodiment>
FIG. 51 is a circuit diagram schematically showing a memory LSI suitable for a daisy chain-connected transmission system according to the twenty-third embodiment.
[0223]
This example is different from the memory LSI according to the twenty-second embodiment shown in FIG. 50 in that data input and data output are performed on the data feedback side 302 from the controller provided in the memory chip. For this reason, a circuit similar to the circuit disposed on the data transmission side 301 in FIG. 50 is disposed in the data feedback 302. On the data transmission side 301 from the controller, a current transfer circuit 303 that always transfers a data current is arranged.
[0224]
<24th Embodiment>
FIG. 52 is a circuit diagram schematically showing a memory LSI compatible with a daisy chain-connected transmission system according to the twenty-fourth embodiment.
[0225]
This example is different from the memory LSI according to the twenty-second embodiment shown in FIG. 50 in that a current output node 319 and a current input node 320 are connected to each other by a transfer gate circuit 321. The transfer gate circuit 321 is controlled by control signals EDGE and / EDGE output from the register 322. When the control signal EDGE is “HIGH” and the control signal / EDGE is “LOW”, the current output node 319 is connected to the current input node 320. Therefore, the current output can be folded back from the data transmission side 301 to the data feedback side 302 within the memory chip. Further, when the control signal EDGE is “LOW” and the control signal / EDGE is “HIGH”, the current output node 319 is separated from the current input node 320. The state of the control signal EDGE is set by daisy chain initialization.
[0226]
This example is effective when the end of the daisy chain is closed as in the eighteenth embodiment shown in FIG. 46, for example. That is, this embodiment can be used in an edge chip without requiring external connection between its output and input.
[0227]
<25th Embodiment>
FIG. 53 is a circuit diagram schematically showing a memory LSI compatible with a daisy chain-connected transmission system according to the twenty-fifth embodiment.
[0228]
47 differs from the memory LSI according to the nineteenth embodiment shown in FIG. 47 in that, like the twenty-fourth embodiment, a current output node 319 and a current input node 320 are connected to each other by a transfer gate circuit 321. It is connected.
[0229]
Also in this example, when the control signal EDGE is “HIGH” and the control signal / EDGE is “LOW”, the current output node 319 is connected to the current input node 320. The side 302 can be folded back within the memory chip. Therefore, this is effective when the end of the daisy chain is closed as in the eighteenth embodiment shown in FIG. 46, for example.
[0230]
<Twenty-sixth embodiment>
FIG. 54 is a circuit diagram schematically showing a memory LSI compatible with a daisy chain-connected transmission system according to the twenty-sixth embodiment.
[0231]
In the above embodiment, an example in which data is transmitted and received and an example in which an address and a command are transmitted and received have been described.
[0232]
However, it is also possible to transmit / receive a packet in which data, an address, and a command are grouped together. This example relates to an example adapted for such packet transmission / reception.
[0233]
This example is different from the memory LSI according to the nineteenth embodiment shown in FIG. 47 in that it includes a packet decoder 323, an address decoder 324, a command decoder 325, a register 326, and a packet encoder 327.
[0234]
The packet decoder 323 decodes the input packet and classifies it into data, address and command. The classified data is input to the memory cell array 242. Similarly classified addresses and commands are input to the address decoder 324 and the command decoder 324, respectively.
[0235]
The address decoder 324 decodes the input address and outputs the decoded address to the memory cell array 242 and the register 326.
[0236]
The command decoder 325 decodes the input command and outputs internal control signals (PASS, / PASS, WRITE, READ, INIT) based on the decoded command.
[0237]
The register 326 stores the chip-ID. The chip-ID is an ID address registered in each chip in order to identify the controller and a plurality of memory chips connected to the controller in a daisy chain. In the above embodiment, detailed description of the chip-ID is omitted, but it is needless to say that it is also registered in the above embodiment. An example of chip-ID assignment method is as follows.
[0238]
First, the chip-ID of the controller is set to “0000” and registered in the controller. The controller transmits chip-ID “0000” to the first memory chip connected in a daisy chain. The memory chip that has received this chip-ID “0000” adds “1” to this and registers “0001” as its own chip-ID. The memory chip in which the chip-ID “0001” is registered transmits the chip-ID “0001” to the next memory chip connected in a daisy chain. The memory chip that has received this chip-ID “0001” adds “1” to this and registers “0010” as its own chip-ID. By sequentially performing such processing for all the memory chips connected in a daisy chain, different chip-IDs can be registered in the controller and each memory chip. The registered chip-ID is included in the address or command during data processing and transmitted. Data processing is performed in a memory chip having a chip-ID that matches the transmitted chip-ID.
[0239]
The register 326 stores such a chip-ID. When the transmitted chip-ID matches the chip-ID stored in the register 326, a chip-ID indicating the controller and a code indicating data output to the controller are output. This is to prevent other memory chips connected in a daisy chain from receiving data output from the memory chip.
[0240]
The packet encoder 327 encodes the data output from the memory cell array 242, the chip-ID indicating the controller chip output from the register 326, and the code indicating data output to the controller into packets. The packet is input to the DAC 14, DA-converted as in the above embodiment, and then output.
[0241]
<Twenty-seventh embodiment>
FIG. 55 is a circuit diagram schematically showing a memory LSI suitable for a transmission system connected in a daisy chain according to the twenty-seventh embodiment.
[0242]
This example differs from the twenty-sixth embodiment shown in FIG. 54 in that data input is performed on the data transmission side 301 and data output is performed on the data feedback side 302 as in the twenty-first embodiment. Yes, the rest is almost the same configuration.
[0243]
As mentioned above, although this invention was demonstrated by 1st-27th embodiment, this invention is not limited to each of these embodiment, In the implementation, in the range which does not deviate from the summary of invention. Various modifications are possible.
[0244]
The first to twenty-seventh embodiments can of course be implemented alone or in appropriate combination.
[0245]
Further, the first to twenty-seventh embodiments include various stages of the invention, and various stages of the invention can be extracted by appropriately combining a plurality of constituent elements disclosed in the embodiments. is there.
[0246]
【The invention's effect】
As described above, according to the data / signal transmission system and the semiconductor integrated circuit device of the present invention, the amount of current, not the voltage potential, is handled as transmission data. In addition, by performing multi-value current data, multi-value data transmission is performed without increasing the number of data lines / signal lines even in current transfer in which the transmission side and the reception side correspond one-to-one. It becomes possible.
[0247]
When such multi-valued current data is used, the current is additive, and the multi-valued current has the advantage that the voltage noise margin is wider than the multi-valued voltage. Therefore, it becomes easy to withstand a decrease in the power supply voltage and the amplitude voltage of the external signal line accompanying the miniaturization of LSI elements. Even when a low-speed synchronous clock is transmitted, a large amount of data can be transmitted / received due to the multi-valued current.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a part of an LSI according to a first embodiment.
FIG. 2 is a block diagram showing a part of an LSI according to a second embodiment.
FIG. 3 is a block diagram showing a part of an LSI according to a third embodiment.
FIG. 4 is a block diagram showing a part of an LSI according to a fourth embodiment.
FIG. 5 is a block diagram showing a transmission system according to a fifth embodiment.
6 is a waveform diagram showing an operation example of the transmission system shown in FIG. 5. FIG.
FIG. 7 is a block diagram showing a transmission system according to a sixth embodiment.
FIG. 8 is a block diagram showing a transmission system according to a seventh embodiment.
9 is a waveform diagram showing an operation example of the transmission system shown in FIG. 8. FIG.
FIG. 10 is a block diagram showing a transmission system according to an eighth embodiment.
FIG. 11 is a circuit diagram showing a circuit example of a DAC according to a ninth embodiment.
FIG. 12 is a circuit diagram showing a circuit example of an ADC according to the tenth embodiment.
FIG. 13 is a circuit diagram showing a circuit example of an ADC according to the tenth embodiment.
FIG. 13 is a circuit diagram showing a circuit example of an ADC according to the tenth embodiment.
FIG. 15 is a circuit diagram showing a circuit example of a reference current source (constant current source).
FIG. 16 is a circuit diagram showing a circuit example of a current drive circuit according to an eleventh embodiment.
FIG. 17 is a waveform diagram showing an operation example when the strobe signal is current-driven.
FIG. 18 is a circuit diagram schematically showing a transmission path of a strobe signal current in a daisy chain-connected transmission system according to an eleventh embodiment.
19A is a circuit diagram schematically showing a transmission path of a strobe signal current in a daisy chain connection transmission system according to a twelfth embodiment, and FIG. 19B is a circuit showing a modification of the transmission path shown in FIG. 19A. FIG. 19C is a circuit diagram showing another modification of the transmission path shown in FIG. 19A.
FIG. 20 is a circuit diagram showing an example of a DAC.
FIG. 21 is a circuit diagram showing an example of an ADC.
FIG. 22 is a circuit diagram showing an example of an ADC.
FIG. 23 is a circuit diagram showing an example of an ADC.
FIG. 24 is a circuit diagram showing an example of an ADC.
FIG. 25 is a waveform diagram showing an operation example of the daisy chain-connected transmission system shown in FIG. 19A.
FIG. 26 is a circuit diagram showing a first modification of the DAC.
FIG. 27 is a circuit diagram showing a second modification of the DAC.
FIG. 28 is a circuit diagram showing a first modification of the ADC.
FIG. 29 is a circuit diagram showing a first modification of the ADC.
FIG. 30 is a circuit diagram showing a first modification of the ADC.
FIG. 31 is a circuit diagram showing a second modification of the ADC.
FIG. 32 is a circuit diagram showing a second modification of the ADC.
FIG. 33 is a circuit diagram showing a second modification of the ADC.
FIG. 34 is a circuit diagram showing a second modification of the ADC.
FIG. 35 is a circuit diagram showing a first modification of the reference current source.
FIG. 36 is a circuit diagram showing a second modification of the reference current source.
FIG. 37 is a circuit diagram showing a third modification of the reference current source.
FIG. 38 is a circuit diagram schematically showing a memory LSI suitable for a daisy chain-connected transmission system according to a thirteenth embodiment.
FIG. 39 is a circuit diagram schematically showing a memory LSI compatible with a daisy chain-connected transmission system according to a fourteenth embodiment.
FIG. 40 is a circuit diagram schematically showing a memory LSI according to a modification of the fourteenth embodiment.
FIG. 41 is a circuit diagram schematically showing a memory LSI compatible with a daisy chain-connected transmission system according to a fifteenth embodiment.
FIG. 42 is a circuit diagram schematically showing a memory LSI suitable for a star-connected transmission system according to a sixteenth embodiment.
FIG. 43 is a block diagram showing a daisy chain-connected transmission system according to a seventeenth embodiment.
44 is a waveform diagram showing an example of operation when a data current is superimposed on a clock signal current in the transmission system shown in FIG. 43. FIG.
FIG. 45 is a circuit diagram showing a modification of the seventeenth embodiment.
FIG. 46 is a block diagram showing a transmission system according to an eighteenth embodiment.
FIG. 47 is a circuit diagram schematically showing a memory LSI suitable for a daisy chain-connected transmission system according to a nineteenth embodiment.
FIG. 48 is a circuit diagram schematically showing a memory LSI compatible with a daisy chain-connected transmission system according to a twentieth embodiment.
FIG. 49 is a circuit diagram schematically showing a memory LSI compatible with a daisy chain-connected transmission system according to a twenty-first embodiment.
FIG. 50 is a circuit diagram schematically showing a memory LSI compatible with a daisy chain-connected transmission system according to a twenty-second embodiment.
FIG. 51 is a circuit diagram schematically showing a memory LSI suitable for a transmission system connected in a daisy chain according to a twenty-third embodiment;
FIG. 52 is a circuit diagram schematically showing a memory LSI compatible with a daisy chain-connected transmission system according to a twenty-fourth embodiment.
FIG. 53 is a circuit diagram schematically showing a memory LSI compatible with a daisy chain-connected transmission system according to a twenty-fifth embodiment.
FIG. 54 is a circuit diagram schematically showing a memory LSI suitable for a transmission system connected in a daisy chain according to a twenty-sixth embodiment;
FIG. 55 is a circuit diagram schematically showing a memory LSI suitable for a daisy chain-connected transmission system according to a twenty-seventh embodiment.
FIG. 56 is a block diagram showing an example of a conventional transmission system.
FIG. 57 is a block diagram showing another example of a conventional transmission system.
[Explanation of symbols]
1, 1a, 1b ... external data lines,
11, 21, 31, 41... First LSI,
12, 22, 32, 42 ... second LSI,
13: Internal circuit,
14, 23 ... DAC,
15 ... PMOS transistor for output buffer,
16 ... NMOS transistor for input buffer,
18 ... internal circuit,
19, 27 ... ADC,
43, 46 ... Output switch transistors,
44, 47 ... Input switch transistors,
50, 100 ... external bus,
51, 101 ... Memory controller,
52, 102 ... DRAM,
54 ... Data line for input,
55 ... Output data line,
104, 105 ... data lines,
106: Strobe signal line.

Claims (15)

A data input circuit having an AD converter that converts multi-valued current data input from the outside into an aggregate of binary voltage level data;
An internal circuit to which binary voltage level data is supplied from the data input circuit;
A data output circuit that includes a DA converter that multi-values a collection of binary voltage level data supplied from the internal circuit, and outputs the multi-value current data to the outside;
A current transfer circuit that transfers the current data input from the outside into multi-valued current data as a current output to a subsequent stage ;
The current transfer circuit includes a first transistor that is current-mirror connected to a current input transistor that receives multi-valued current data input from the outside at one end and a gate of a current path;
A second transistor having one end of the current path and a gate connected to one end of the current path of the first transistor;
And a third transistor that is current-mirror connected to the second transistor and transfers multi-valued current data input from the outside as a current output to a subsequent stage. A data input circuit having an AD converter that converts multi-valued current data input from the outside into an aggregate of binary voltage level data;
An internal circuit to which binary voltage level data is supplied from the data input circuit;
A data output circuit that includes a DA converter that multi-values a collection of binary voltage level data supplied from the internal circuit, and outputs the multi-value current data to the outside;
The AD converter and the DA converter use a clock signal current as a current source, a semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 2 , wherein the clock signal current used as the current source is a current generated by a current mirror from the clock signal current used for transmission / reception of the current data. A data input circuit having an AD converter that converts multi-valued current data input from the outside into an aggregate of binary voltage level data;
An internal circuit to which binary voltage level data is supplied from the data input circuit;
A data output circuit that includes a DA converter that multi-values a collection of binary voltage level data supplied from the internal circuit, and outputs the multi-value current data to the outside;
An operation mode for outputting multi-valued current data input from the outside to the outside via the AD converter and the DA converter;
A semiconductor integrated circuit device comprising: a current transfer mode in which the multi-valued current data input from the outside is output to the outside without passing through the AD converter and the DA converter. A data input circuit having an AD converter that converts multi-valued current data input from the outside into an aggregate of binary voltage level data;
An internal circuit to which binary voltage level data is supplied from the data input circuit;
A data output circuit that includes a DA converter that multi-values a collection of binary voltage level data supplied from the internal circuit, and outputs the multi-value current data to the outside;
The clock signal input from the outside or output to the outside is a current-controlled clock signal current.
As a circuit for outputting the clock signal current to the outside, a reference current source connected between a power supply node and a ground node, a first transistor to which a clock control signal is applied to a gate, and a drain / gate are connected. A first current mirror circuit that outputs a second transistor and a clock signal current obtained by folding back the current of the second transistor to an external signal line;
As a circuit to which the clock signal current is inputted from the outside, a drain and a gate are connected to each other, a clock signal current inputted from an external clock signal line is inputted to the drain, and a current of the transistor is turned back to return the clock signal current. A semiconductor integrated circuit device comprising: a second current mirror circuit for extracting the current. A data input circuit having an AD converter that converts multi-valued current data input from the outside into an aggregate of binary voltage level data;
An internal circuit to which binary voltage level data is supplied from the data input circuit;
A data output circuit that includes a DA converter that multi-values a collection of binary voltage level data supplied from the internal circuit, and outputs the multi-value current data to the outside;
The data output circuit includes a clock signal and outputs the current data superimposed with the clock signal current to the outside when the DA converter converts the binary voltage level data into multiple values. And
The data input circuit takes out the clock signal current at the same time when the current data input on which the clock signal current is superimposed is converted into a data set of binary voltage levels by the AD converter. Semiconductor integrated circuit device. The DA converter
A reference current source transistor;
A current mirror connection is made to each of the reference current source transistors, and the first to nth elements are sized so as to have a current value weighted by 2 ^n-1 times the current value of the reference current source transistor. A weighted current source transistor;
A clock current source transistor that is current mirror connected to the reference current source transistor and is sized to have a current value equal to the current value of the reference current source transistor;
One end is connected to each of the first to nth weighted current source transistors, and the other end is connected to the output node in a lump and is sized so as to have a current value weighted by 2 ^n-1 times. Are set, and the first to nth switching transistors to which the least significant bit to the most significant bit of the n-bit binary voltage data corresponding to each gate are input,
7. The semiconductor integrated circuit device according to claim 6 , further comprising: a clock switch transistor connected between the output node and the clock current source transistor and receiving a DA conversion input clock signal at a gate. . The DA converter
A reference current source transistor;
Each of the reference current source transistors is current mirror-connected, and the first to (n + 1) th (n + 1) th sizes are set so as to have a current value weighted 2 ⁿ times as much as the current value of the reference current source transistor. A weighted current source transistor;
One end is connected to each of the first to (n + 1) th weighted current source transistors, and the other end is connected to the output node in a lump so as to have a current value weighted by 2 ⁿ times. And the first to (n + 1) th switching transistors to which the least significant bit to the most significant bit and the clock bit of the n-bit binary voltage data are input corresponding to each gate. 7. The semiconductor integrated circuit device according to claim 6 , wherein: The DA converter
A reference current source transistor;
A current mirror connection is made to each of the reference current source transistors, and the size is set so that the current values are weighted by 2 ^n-1 times and 1/2 times the current values of the reference current source transistors. 1st to (n + 1) th weighted current source transistors;
One end is connected to each of the first to (n + 1) th weighted current source transistors, and the other end is connected to the output node in a lump and weighted by 2 ^n-1 times and 1/2 times. The first to (n + 1) th switches for which the size is set to have a current value and the least significant bit to the most significant bit and the clock bit of n-bit binary voltage data are input corresponding to each gate. The semiconductor integrated circuit device according to claim 6 , further comprising: a transistor. The AD converter is
The current value weighted to 2 ^n-1 times the reference current flowing in response to the comparison enable signal is compared with the input current, and the logic of the nth bit which is the most significant bit of the n-bit binary data is compared. A first comparison circuit for determining a level;
Depending on the logic level of the nth bit, the input current minus the current value 2 ^n-1 times the reference current or the input current, and 2 ^{n-2 of the} reference current flowing in response to the comparison enable signal A second comparison circuit for comparing the magnitude with a double current and determining the logic level of the (n-1) th bit of the binary data;
Current obtained by subtracting a current value that is a multiple of the input current from the combination of the logic levels of the upper bits of the reference current, or input current and 2 ^n-3 times to 1 time the reference current that flows in response to the comparison enable signal And a third comparison circuit to an nth comparison circuit for determining the logical level of the (n−2) th to the least significant bit of the binary data. 7. The semiconductor integrated circuit device according to claim 6 , wherein: The AD converter is
The current value weighted to 2 ^n-1 +1 times the reference current flowing in response to the comparison enable signal is compared with the input current, and the n-th bit which is the most significant bit of the n-bit binary data is compared. A first comparison circuit for determining a logic level;
Depending on the logic level of the nth bit, the input current minus 2 ⁿ times the current value of the reference current or the input current and 2 ^{n−2 of the} reference current flowing in response to the comparison enable signal A second comparison circuit for comparing the magnitude with a current of +1 times and determining the logic level of the (n-1) th bit of the binary data;
A current value corresponding to a multiple corresponding to the combination of the logical levels of the upper bits with respect to the reference current is obtained by subtracting the input current from the input current, or 2 ^{n of the} reference current flowing in response to the comparison enable signal. ⁻³ +1 times to 2 ⁰ +1 times the magnitude of the current corresponding to each other, and a third comparison circuit for determining the logic level of the (n−2) th to the least significant bit of the binary data An nth comparison circuit;
A value obtained by subtracting from the input current a current value corresponding to a multiple of the reference current according to a combination of logic levels of the most significant bit to the least significant bit of the reference current, or the comparison enable signal 7. A semiconductor integrated circuit device according to claim 6 , further comprising: a clock signal comparison circuit that compares a magnitude of a reference current that flows in response to the current and determines a logic level of the clock signal. . The AD converter is
A comparison circuit for a clock signal that compares the magnitude of a current value weighted by 2 ⁿ times the reference current flowing in response to the comparison enable signal with the input current and determines the logic level of the clock signal;
The current value weighted to (2 ⁿ +2 ^n-1 ) times the reference current flowing in response to the clock signal is compared with the input current, and the nth bit which is the most significant bit of the n-bit binary data is compared. A first comparator for determining the logic level of the bits of
Depending on the logic level of the nth bit, the input current minus 2 ^n-1 times the current value of the reference current or the input current and the reference current flowing in response to the clock signal (2 ⁿ +2 ⁿ⁻² ) times the magnitude of the current and a second comparison circuit for determining the logic level of the (n−1) th bit of the binary data;
A current value corresponding to a multiple corresponding to the combination of the logic levels of the upper bits with respect to the reference current is subtracted from the input current, or (2 ⁿ +2) of the reference current that flows in response to the input current and the clock signal. ^n-3 ) to (2 ⁿ +1) times the magnitude of the current corresponding to each other, and a third comparison for determining the logic level of the (n−2) th to the least significant bits of the binary data The semiconductor integrated circuit device according to claim 6 , further comprising: a circuit to an nth comparison circuit. The AD converter is
The current value weighted to 2 ^n-1 +1/2 times the reference current flowing in response to the comparison enable signal is compared with the input current, and the nth bit which is the most significant bit in the n-bit binary data is compared. A first comparator that determines the logic level of the bits;
Depending on the logic level of the n-th bit, the input current minus 2 ^n-1 times the current value of the reference current or the input current and 2 ^{n of the} reference current flowing in response to the comparison enable signal ^A second comparison circuit that compares the current level with ^-2 +1/2 times the current and determines the logic level of the (n-1) th bit of the binary data;
A current value corresponding to a multiple corresponding to the combination of the logical levels of the upper bits with respect to the reference current is obtained by subtracting the input current from the input current, or 2 ^{n of the} reference current flowing in response to the comparison enable signal ⁻³ +1/2 times to 2 ⁰ + ½ times the current corresponding to each other, and the third to determine the logic level of the (n−2) th to the least significant bits of the binary data Comparison circuit to n-th comparison circuit,
A value obtained by subtracting a current value corresponding to a multiple corresponding to a combination of logic levels of the most significant bit to the least significant bit with respect to the reference current from the input current or the input current and the comparison enable signal The semiconductor integrated circuit device according to claim 6 , further comprising: a clock signal comparison circuit that compares the current level with a current that is ½ times the flowing reference current and determines a logic level of the clock signal. The value of the reference current to be used in the AD converter, the greater than half the value of the reference current used in the DA converter, according to claim 6 or any one of claims 13, characterized in that less than 2-fold A semiconductor integrated circuit device according to 1. 15. The semiconductor integrated circuit device according to claim 14 , wherein the reference current used in the AD converter and the DA converter is generated by transistors having different sizes that receive a reference current from a reference current source.

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