KR101385744B1 - Array Substrate of In-Plane Switching Mode Liquid Crystal Display Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transverse electric field type liquid crystal display device, and more particularly, to improving production yield by reducing the number of mask processes of an array substrate for a transverse electric field type liquid crystal display device.

An array substrate for a transverse electric field type liquid crystal display device according to the present invention includes a substrate; A semiconductor layer on the substrate; A first insulating film on the semiconductor layer; Gate wiring formed in one direction on the first insulating film, and common wiring spaced in parallel with the gate wiring; A pixel electrode designed on the first insulating film in a plate pattern corresponding to the pixel region; A second insulating film including a source and a drain hole exposing the semiconductor layer on the pixel electrode, a first common hole exposing the common wiring, and a pixel open hole exposing the pixel electrode; A data line perpendicular to the gate line on the second insulating layer, a source electrode in contact with the semiconductor layer, and a drain electrode spaced apart from the source electrode; Third and fourth insulating films including the data lines, second common holes, and photosensitive patterns on the source and drain electrodes; And a common electrode in contact with the common wiring on the third and fourth insulating layers.

Description

[0001] The present invention relates to an array substrate for a lateral electric field type liquid crystal display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transverse electric field type liquid crystal display device, and more particularly, to improving production yield by reducing the number of mask processes of an array substrate for a transverse electric field type liquid crystal display device.

Recently, with increasing interest in information display and increasing demand for the use of portable information carriers, research and commercialization of lightweight thin-film flat panel display devices, which replace the existing display device, the Cathode Ray Tube (CRT) It is done.

In particular, active driving liquid crystal display devices have become mainstream in such flat panel displays. In an active driving liquid crystal display device, a thin film transistor is used as a switching element to change the transmittance of a pixel by adjusting a voltage applied to a liquid crystal of one unit pixel.

Hydrogenated amorphous silicon is mainly used as the switching device, because it is easy to manufacture in large area, and thus productivity is high, and it is possible to deposit at a low substrate temperature of 350 ^° C. or less, so that an inexpensive insulating substrate can be used.

However, hydrogenated amorphous silicon has a weak bond and dangling bond due to disordered atomic arrangements, and thus changes to metastable state when irradiated with light or applied with an electric field.

In particular, an amorphous silicon thin film transistor substrate connects an insulating board and a printed circuit board (PCB) using a tape carrier package (TCP) driving IC (Integrated Circuit), and a large portion of the cost is used for driving ICs and actual equipment.

In addition, when the resolution of the liquid crystal panel for a liquid crystal display device is increased, the pad pitch outside the substrate for connecting the gate wiring and the data wiring of the thin film transistor substrate to the TCP becomes short, which makes TCP bonding itself difficult.

The polysilicon in such a polycrystalline state has an advantage in that a driving circuit can be made on a substrate because the field effect mobility is larger than that of amorphous silicon.

Hereinafter, a conventional transverse electric field type liquid crystal display device will be described with reference to the accompanying drawings.

1 is a plan view showing a unit pixel of a conventional array substrate for a transverse electric field type liquid crystal display device.

As shown in the drawing, the gate wiring 20 and the data wiring 30 defining the pixel region P are vertically intersected with the gate wiring 20 in one direction on the substrate 10.

The common wiring 50 spaced apart from the gate wiring 20 in parallel with each other and a plurality of common electrodes 80 vertically branched from the common wiring 50 in the pixel area P direction are formed.

The thin film transistor T is formed at an intersection point of the gate line 20 and the data line 30. The thin film transistor T may include a gate electrode 25 extending from the gate line 20, a semiconductor layer 40 disposed on an upper portion overlapping the gate electrode 25, and an upper portion of the semiconductor layer 40. A source electrode 32 extending from the data line 30 positioned therein, and a drain electrode 34 spaced apart from the source electrode 32. The semiconductor layer 40 is made of polysilicon.

The pixel electrode 70 which is in contact with the drain electrode 34 through the drain contact hole CH1 exposing a part of the drain electrode 34 corresponds to the pixel region P. [ The pixel electrode 70 includes an extension part 70a in contact with the drain electrode 34, a plurality of vertical parts 70b vertically branched from the extension part 70a in the direction of the pixel region P, and the plurality of extension parts 70a. It includes a horizontal portion (70c) for connecting the vertical portion (70b) of the one. The pixel electrode vertical part 70b and the common electrode 80 are alternately disposed in the pixel area P. FIG.

In this case, the horizontal portion 70c of the pixel electrode is used as the first electrode, and the common wiring 50 positioned below the first electrode is overlapped with the second electrode, and the first and second electrodes overlap each other. The storage capacitor Cst which uses the insulating film interposed in the interspace which is made into a dielectric layer is comprised.

In general, an array substrate for a transverse electric field type liquid crystal display device having the above-described configuration is manufactured by an 8 or 9 mask process.

Hereinafter, a manufacturing method of an array substrate for a transverse electric field type liquid crystal display device according to the related art will be described with reference to the accompanying drawings.

2A to 2H are cross-sectional views illustrating a process sequence by cutting along the line II-II ′ of FIG. 1.

2A is a process cross sectional view showing a first mask process step;

As shown, the step of defining the switching region S, the pixel region P, the common region C, and the data region D on the substrate 10 is performed.

When a polysilicon layer (not shown) is formed and patterned on the substrate 10 in which the plurality of regions S, P, C, and D are defined, the semiconductor layer 40 corresponds to the switching region S. FIG. Is formed.

The first insulating layer 45 is formed on the entire upper surface of the substrate 10 on which the semiconductor layer 40 is formed, selected from a group of inorganic insulating materials such as silicon nitride (SiNx) and silicon oxide (SiO ₂ ).

2B is a process cross-sectional view illustrating a second mask process step.

As shown, a conductive metal group such as copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd), and chromium (Cr) on the substrate 10 on which the first insulating film 45 is formed. When a gate metal layer (not shown) is formed and patterned with one selected from among, a gate wiring 20 in FIG. 1 is formed. In this case, a part of the gate wiring corresponding to the portion overlapping with the semiconductor layer 40 is used as the gate electrode 25.

2C is a process cross sectional view showing a third mask process step;

As illustrated, the second insulating layer 46 is selected from a group of inorganic insulating materials, such as silicon nitride (SiNx) and silicon oxide (SiO ₂ ), on the substrate 10 on which the gate electrode 25 and the gate wiring are formed. Is formed.

Next, when the second insulating film 46 and the first insulating film 45 on the semiconductor layer 40 are sequentially patterned, source and drain holes SH and DH exposing portions of both sides of the semiconductor layer 40, respectively. ) Is formed.

2D is a process cross sectional view showing a fourth mask process step;

As illustrated, copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd), and chromium (Cr) are formed on the second insulating layer 46 including the source and drain holes SH and DH. When one selected from the group of conductive metals, such as, is deposited to form a source and drain metal layer (not shown), and the pattern is patterned, the data line defining the pixel region P by vertically crossing the gate line (20 in FIG. 1). 30, a source electrode 32 extending from the data line 30 and contacting the semiconductor layer 40 through the source hole SH, and spaced apart from the source electrode 32 and drain hole DH. Each of the drain electrodes 34 in contact with the semiconductor layer 40 is formed through the.

The gate electrode 25, the semiconductor layer 40, and the source and drain electrodes 32 and 34 form a thin film transistor (T).

2E is a process cross sectional view showing a fifth mask process step;

As illustrated, the third insulating layer 47 is formed of one selected from the group of inorganic insulating materials including silicon nitride and silicon oxide on the entire upper surface of the substrate 10 on which the data line 30 and the thin film transistor T are formed. do.

Subsequently, a fourth insulating film 48 is formed on the substrate 10 on which the third insulating film 47 is formed by selecting one of a group of organic insulating materials including photoacryl or benzocyclobutene (BCB). In this case, a process step of forming the third insulating layer 47 may be omitted.

Next, when the fourth insulating film 48 and the third insulating film 47 corresponding to the drain electrode 34 are sequentially patterned, the first drain contact hole CH1 exposing a part of the drain electrode 34. Is formed.

2F is a process cross sectional view showing a sixth mask process step;

As illustrated, a transparent metal layer is selected from a transparent conductive metal group such as indium tin oxide (ITO) or indium zinc oxide (IZO) on the substrate 10 on which the drain contact hole CH1 is formed. When the pattern is formed and patterned, the common wiring 50 spaced in parallel with the gate wiring and the plurality of common electrodes 80 vertically branched from the common wiring 50 in the pixel region P direction are formed. do.

Although not shown in the drawings, the common wiring 50 and the common electrode 80 may be made of the same material or different layers as the gate wiring. In this case, when the common wiring 50 and the common electrode 80 are formed in different layers, an additional mask process for exposing a part of the common wiring 50 is required.

2G is a process cross sectional view showing a seventh mask process step;

As illustrated, a fifth insulating layer 49 is formed on the substrate 10 having the common wiring 50 and the common electrode 80 selected from a group of inorganic insulating materials including silicon oxide and silicon nitride. In this case, the drain electrode 34 is covered by the fifth insulating layer 49.

Next, when the fifth insulating layer 49 covering the drain electrode 34 is patterned, a second drain contact hole CH2 exposing the drain electrode 34 is formed.

2H is a process sectional view showing an eighth mask process step;

As shown, one selected from a group of transparent conductive metals such as indium tin oxide (ITO) or indium zinc oxide (IZO) on the fifth insulating layer 49 including the second drain contact hole CH2. When the transparent metal layer (not shown) is formed and patterned, the pixel electrode 70 in contact with the drain electrode 34 is formed corresponding to the pixel region P. FIG.

The pixel electrode 70 includes an extension part 70a in contact with the drain electrode 34, a plurality of vertical parts 70b vertically branched from the extension part 70a in the direction of the pixel region P, and the plurality of extension parts 70a. It includes a horizontal portion (70c) for connecting the vertical portion (70b) of the one.

In this case, the horizontal portion 70c of the pixel electrode is used as the first electrode, and the common wiring 50 overlapping the first electrode is used as the second electrode, and the space between the first and second electrodes is overlapped. A storage capacitor Cst having the interposed fifth insulating film 49 as a dielectric layer is formed.

As described above, the array substrate for a transverse electric field type liquid crystal display device according to the related art can be manufactured by an eight mask process.

However, the conventional 8 or 9 mask process acts as a cause of increasing the initial investment cost and manufacturing cost of the equipment according to the increase in the number of masks, causing a problem of inhibiting the production yield.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to improve production yield by reducing the number of mask processes in manufacturing an array substrate for a transverse electric field type liquid crystal display device.

According to an aspect of the present invention, there is provided an array substrate for a transverse electric field type liquid crystal display, comprising: a substrate; A semiconductor layer on the substrate; A first insulating film on the semiconductor layer; Gate wiring formed in one direction on the first insulating film, and common wiring spaced in parallel with the gate wiring; A pixel electrode designed on the first insulating film in a plate pattern corresponding to the pixel region; A second insulating film including a source and a drain hole exposing the semiconductor layer on the pixel electrode, a first common hole exposing the common wiring, and a pixel open hole exposing the pixel electrode; A data line perpendicular to the gate line on the second insulating layer, a source electrode in contact with the semiconductor layer, and a drain electrode spaced apart from the source electrode; Third and fourth insulating films including the data lines, second common holes, and photosensitive patterns on the source and drain electrodes; And a common electrode in contact with the common wiring on the third and fourth insulating layers.

The third insulating layer is formed of one selected from the group of inorganic insulating materials including silicon oxide and silicon nitride, and the fourth insulating layer is selected from the group of organic insulating materials including photoacryl and benzocyclobutene.

In this case, the common electrode includes an extension part contacting the common wire through the first and second common holes, and a plurality of vertical parts vertically branched from the extension part toward the pixel area. The photosensitive pattern lowers parasitic capacitance between the data line and the vertical portion of the common electrode.

Only the third insulating layer is interposed between the pixel electrode corresponding to the pixel area and the vertical portion of the common electrode, and the semiconductor layer is made of polysilicon.

A method of manufacturing an array substrate for a transverse electric field type liquid crystal display device according to a first embodiment of the present invention for achieving the above object comprises the steps of forming a semiconductor layer on the substrate; Forming a first insulating film on the semiconductor layer; Forming a gate wiring in one direction on the first insulating film and a common wiring spaced in parallel with the gate wiring; Forming a pixel electrode designed in a plate pattern on a substrate on which the gate wiring and the common wiring are formed; Forming a second insulating layer including a source and a drain hole, a first common hole, and a pixel open hole respectively exposing the semiconductor layer, the pixel electrode, and the common wiring; A data line vertically intersecting the gate line on the second insulating layer, a source electrode extending from the data line and in contact with the semiconductor layer, and a drain spaced apart from the source electrode and in contact with the semiconductor layer and the pixel electrode, respectively. Forming an electrode; Forming a third insulating film including a second common hole exposing the common line on the substrate on which the data line and the source and drain electrodes are formed; Forming a fourth insulating film on the substrate on which the third insulating film is formed, the fourth insulating film including a photosensitive pattern corresponding to an upper portion overlapping the data line; Forming a common electrode in contact with the common wiring through the second common hole.

The first to third insulating films are formed of one selected from the group of inorganic insulating materials including silicon oxide and silicon nitride, and the fourth insulating film is formed from one selected from the group of organic insulating materials including photoacryl and benzocyclobutene. It features. In this case, the fourth insulating film is formed of a material having a lower dielectric constant than the third insulating film.

The semiconductor layer may be made of polysilicon, and the common electrode may include an extension part contacting the common wiring through the first and second common holes, and a plurality of vertical branches branched from the extension part toward the pixel region. It includes a vertical portion.

In this case, in the forming of the second common hole and the photosensitive pattern, a third insulating film and a fourth insulating film are sequentially formed on the substrate on which the data line, the source and the drain electrode are formed, and the mask includes a transmissive part, a transflective part, and a blocking part. Sorting; Exposing and developing the upper portion of the mask to form first to third photosensitive patterns, respectively; Using the first to third photosensitive patterns as a mask, patterning the third insulating film corresponding to the common wiring to form a common hole exposing the common wiring; The first to third photosensitive patterns are ashed to reduce the thickness of the first and second photosensitive patterns, and the third photosensitive pattern is removed to expose the third insulating layer under the third photosensitive pattern. It comprises the step of.

According to a second aspect of the present invention, there is provided a method of manufacturing an array substrate for a transverse electric field type liquid crystal display device, the method including: forming a semiconductor layer on the substrate; Forming a gate wiring in one direction on the semiconductor layer, a common wiring spaced in parallel with the gate wiring, and a pixel electrode designed in a plate pattern corresponding to the pixel region; Forming a first insulating film on the substrate on which the gate wiring, the common wiring and the pixel electrode are formed; Patterning the first insulating film to form source and drain holes, a first common hole, and a pixel open hole exposing the semiconductor layer, the common wiring, and the pixel electrode, respectively; A source electrode on the first insulating layer including the source and drain holes, the first common hole, and the pixel open hole, a data line extending in a direction perpendicular to the gate line, and a source electrode extending from the data line and in contact with the semiconductor layer. Forming a drain electrode spaced apart from the source electrode and in contact with the semiconductor layer and the pixel electrode, respectively; Sequentially forming a second insulating film and a third insulating film on the substrate on which the data line and the source and drain electrodes are formed; Selectively patterning the third insulating film and the fourth insulating film to form a second common hole exposing the common wiring and a photosensitive pattern on the data wiring; Forming a common electrode in contact with the common wiring through the second common hole.

At this time, the gate wiring and the common wiring are formed by laminating a first metal layer and a second metal layer in order. The pixel electrode is formed of a first metal layer.

The first metal layer is selected from a transparent conductive metal group including indium tin oxide or indium zinc oxide, and the second metal layer is selected from among a conductive metal group including copper, molybdenum, aluminum, an aluminum alloy, and chromium. Each selected one.

In the present invention, first, there is an advantage that the production yield can be improved by manufacturing an array substrate for a transverse electric field type liquid crystal display device in a 6 or 7 mask process.

Second, even if the number of mask processes is reduced, the parasitic capacitance between the data line and the common electrode does not increase.

Third, there is an advantage that the storage capacitance between the pixel electrode and the common electrode can be sufficiently secured by an exposure process using a halftone mask.

--- Example 1 ---

The first embodiment of the present invention is characterized in that an array substrate for a transverse electric field type liquid crystal display device can be manufactured in a seven mask process without increasing parasitic capacitance between the data line and the common electrode.

Hereinafter, a transverse electric field type liquid crystal display device according to the present invention will be described with reference to the accompanying drawings.

3 is a plan view illustrating unit pixels of an array substrate for a transverse electric field type liquid crystal display device according to a first exemplary embodiment of the present invention.

As shown in the drawing, the gate line 120 and the data line 130 defining the pixel area P are formed to cross the gate line 120 in one direction on the substrate 100.

The common wiring 150 is spaced apart from and parallel to the gate wiring 120. A plurality of common electrodes 180 connected to the common wiring 150 are formed through the first and second common holes CMH1 and CMH2 exposing portions of the common wiring 150. The plurality of common electrodes 180 may extend the extension part 180a in contact with the common wire 150 and the plurality of vertical parts 180b vertically branched from the extension part 180a in the pixel area P direction. Include. In this case, the common electrode vertical part 180b is designed to overlap the data line 130.

A thin film transistor T is formed at an intersection of the gate line 120 and the data line 130. The thin film transistor T is a gate electrode 125 that is a part of the gate wiring 120, a semiconductor layer 140 positioned on the upper portion overlapping the gate electrode 125, and an upper portion of the semiconductor layer 140. A source electrode 132 extending from the data line 130, and a drain electrode 134 spaced apart from the source electrode 132. The semiconductor layer 140 is made of polysilicon.

In addition, the pixel electrode 170 is formed in a plate-shaped pattern corresponding to the pixel region P. The pixel electrode 170 is in direct contact with the drain electrode 134 through the pixel open hole POH.

The above-described configuration includes a pixel electrode 170 designed in a flat form corresponding to a kind of island pattern structure corresponding to the pixel region P, and a plurality of slits in which the bar-shaped patterns are spaced in parallel with each other. The common electrode vertical portion 180b of the structure is arranged to overlap with an insulator therebetween, and a strong transverse electric field is formed to control liquid crystal molecules corresponding to the diagonal direction between the electrodes.

Particularly, in the first embodiment of the present invention, a parasitic capacitance between the data line 130 and the common electrode vertical portion 180b is reduced while the array substrate for the transverse electric field type liquid crystal display device is manufactured in a seven mask process, and the pixel region is reduced. It is characterized by providing a pixel design that can sufficiently secure the strip capacitance between the pixel electrode 170 and the common electrode vertical portion 180b corresponding to (P).

Hereinafter, a method of manufacturing an array substrate for a transverse electric field type liquid crystal display device according to the present invention will be described with reference to the accompanying drawings.

4A to 4I and FIGS. 5A to 5I are cross-sectional views illustrating a process sequence by cutting along lines IV-IV ′ and V-V ′ of FIG. 3, respectively.

4A and 5A are cross-sectional views illustrating a first mask process step.

As shown in FIGS. 4A and 5A, a step of defining a switching region S, a pixel region P, a common region C, and a data region D on the substrate 100 is performed.

The semiconductor layer 140 corresponding to the switching region S is formed by forming and patterning a polysilicon layer (not shown) on the substrate 100 in which the plurality of regions S, P, C, and D are defined. Form.

Next, the first insulating layer 145 is formed on the entire upper surface of the substrate 100 on which the semiconductor layer 140 is formed, selected from a group of inorganic insulating materials such as silicon nitride (SiNx) and silicon oxide (SiO ₂ ).

4B and 5B are cross-sectional views illustrating a second mask process step.

4B and 5B, copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd), and chromium (Cr) are formed on the substrate 100 on which the first insulating layer 145 is formed. The gate metal layer (not shown) is formed with one selected from a group of conductive metals such as) and patterned to form the gate metal layer 120 (in FIG. 3) and the common wire 150 spaced in parallel with the gate wire in one direction. Form. In this case, a part of the gate wiring overlapping the semiconductor layer 140 is used as the gate electrode 125.

4C and 5C are cross-sectional views illustrating a third mask process step.

As shown in FIGS. 4C and 5C, indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on the substrate 100 on which the gate electrode 125, the gate wiring, and the common wiring 150 are formed. A transparent metal layer (not shown) is formed and patterned with one selected from a group of transparent conductive metals such as) to form a pixel electrode 170 designed in a plate shape in the pixel region P.

4D and 5D are cross-sectional views illustrating a fourth mask process step.

As shown in FIGS. 4D and 5D, the second insulating layer may be selected from a group of inorganic insulating materials such as silicon nitride (SiNx) and silicon oxide (SiO ₂ ) on the substrate 100 on which the pixel electrode 170 is formed. 146).

Next, the second insulating layer 146 and the first insulating layer 145 corresponding to the semiconductor layer 140 and the common wiring 150 are sequentially patterned to expose portions of both sides of the semiconductor layer 140, respectively. And drain holes SH and DH.

In addition, the second insulating layer 146 corresponding to the common wiring 150 and the pixel electrode 170 is patterned to expose the first common hole CMH1 exposing the common wiring 150 and the pixel electrode 170. Each pixel open hole POH is formed.

4E and 5E are cross-sectional views illustrating a fifth mask process step.

As shown, copper (Cu), molybdenum (Mo) on the second insulating layer 146 including the source and drain holes (SH, DH), the first common hole (CMH1) and the pixel open hole (POH). And depositing one selected from a group of conductive metals such as aluminum (Al), aluminum alloy (AlNd), and chromium (Cr) to form a source and drain metal layer (not shown), and pattern the gate wiring (120 of FIG. 3). ) And a data line 130 defining a pixel area P perpendicularly intersect with each other, and a source electrode 132 extending from the data line 130 and contacting the semiconductor layer 140 through the source hole SH. ) And the drain electrode 134 spaced apart from the source electrode 132 and in contact with the semiconductor layer 140 through the drain hole DH and directly in contact with the pixel electrode 170 through the pixel open hole POH. Form each.

The gate electrode 125, the semiconductor layer 140, and the source and drain electrodes 132 and 134 form a thin film transistor (T).

4F through 4H and 5F through 5H are cross-sectional views illustrating a sixth mask process step.

As shown in FIGS. 4F and 5F, a third one selected from the group of inorganic insulating materials including silicon nitride and silicon oxide on the entire upper surface of the substrate 100 on which the data line 130 and the thin film transistor T are formed. An insulating film 147 is formed.

Subsequently, a fourth insulating layer 148 is formed on the substrate 100 on which the third insulating layer 147 is formed by selecting one of a group of organic insulating materials including photoacryl or benzocyclobutene (BCB). In this case, a process step of forming the third insulating layer 147 may be omitted.

In this case, the fourth insulating layer 148 is formed of one selected from the group of organic insulating materials that are sensitive to photoreaction and have a lower dielectric constant than the inorganic insulating material.

Next, the step of aligning the halftone mask (HTM) consisting of a transmission portion (T1), a semi-transmissive portion (T2) and a blocking portion (T3) on the spaced apart from the substrate 100 on which the fourth insulating film 148 is formed. Proceed.

The halftone mask HTM functions to form a semi-transparent film on the transflective portion T2 to lower the intensity of light or to reduce the amount of light transmitted so that the fourth insulating layer 147 may be incompletely exposed. In this case, a slit mask may be used to adjust the amount of light transmitted through the transflective portion T2 in addition to the halftone mask HTM.

In addition, the blocking unit T3 functions to completely block light, and the transmitting unit T1 transmits light and completely exposes the light by chemical change of the fourth insulating layer 148 exposed to light.

In this case, the blocking portion T3 is disposed in the data region D, the transflective portion T2 is disposed in the pixel region P, and the transmissive portion T1 is disposed in the common region C, respectively.

Next, as shown in FIGS. 4G and 5G, a process of exposing and developing the upper portion of the halftone mask (HTM of FIGS. 4F and 5F) is performed to perform the blocking portion (T3 of FIGS. 4F and 5F). Correspondingly, a first photosensitive pattern 148a having no thickness change and a second photosensitive pattern 148b having a thickness lowered by about half in correspondence with the transflective portions (T2 in FIGS. 4F and 5F) are formed. At this time, all of the fourth insulating films 148 of FIGS. 4F and 5F corresponding to the transmission part T1 of FIGS. 4F and 5F are removed, and the third insulating film 147 below is exposed.

Next, using the first and second photosensitive patterns 148a and 148b as masks, the exposed third insulating layer 147 is patterned by a dry etching process to expose a second common wiring 150. The hole CMH2 is formed.

As shown in FIGS. 4H and 5H, when the first and second photosensitive patterns (148a and 148b of FIGS. 4G and 5G) are ashed, the first photosensitive pattern 148a is half in thickness. As a result, the second photosensitive pattern (148b of FIGS. 4G and 5G) is removed to expose the lower third insulating layer 147.

4I and 5I are cross-sectional views illustrating a seventh mask process step.

As shown in FIGS. 4I and 5I, indium tin oxide (ITO) or indium zinc oxide (IZO) may be formed on the second common hole CMH2, the first photosensitive pattern, and the third insulating layer 147. A transparent metal layer (not shown) is formed and patterned with one selected from a group of transparent conductive metals such as the same, thereby forming a common electrode 180 in contact with the common wire 150.

The common electrode 180 includes an extension 180a in contact with the common wire 150 and a plurality of vertical parts 180b vertically branched from the extension 180a to the pixel area.

In this case, the above-described configuration includes a pixel electrode 170 designed in a flat form corresponding to a kind of island pattern structure corresponding to the pixel region P, and a plurality of slits in which the rod-shaped patterns are spaced in parallel with each other. ) Is a structure in which a vertical portion of the common electrode is overlapped with the third insulating layer 147 interposed therebetween, and a strong transverse electric field is formed to control liquid crystal molecules corresponding to the diagonal direction between the electrodes through a fringe field. Will be.

In particular, in the present invention, a parasitic between the data line 130 and the common electrode vertical portion 180b through the first photosensitive pattern 148a made of an organic insulating material having a lower dielectric constant than the inorganic insulating material corresponding to the data region D. FIG. This can prevent problems such as signal delay caused by capacitance.

In this case, in the first exemplary embodiment of the present invention, a structure in which the data line 130 and the common electrode vertical part 180b are overlapped with each other is described as an example. Since the parasitic capacitance is also not negligible, the first photosensitive pattern 184a should be designed in the space between the data line 130 and the common electrode vertical portion 180b.

In addition, a third insulating layer is disposed in a space between the pixel electrode 170 and the common electrode vertical portion 180b by removing all of the second photosensitive patterns (148b of FIGS. 4G and 5G) corresponding to the pixel region P. FIG. By designing only 147 to exist, the storage capacitance between the pixel electrode 170 and the common electrode vertical part 180b may be sufficiently secured.

As described above, the array substrate for the transverse electric field type liquid crystal display device according to the first embodiment of the present invention can be manufactured by a seven mask process.

--- Example 2 ---

The second embodiment of the present invention relates to fabricating an array substrate for a transverse electric field type liquid crystal display device in a six mask process, and the description of the plan view will be omitted since the construction of the plan view does not have much difference from the first embodiment.

Hereinafter, a method of manufacturing an array substrate for a transverse electric field type liquid crystal display device according to a second embodiment of the present invention will be described with reference to the accompanying drawings.

6A to 6D and FIGS. 7A to 7D are cross-sectional views illustrating cutting processes taken along lines IV-IV 'and V-V' of FIG. 3, respectively, in order to show the same names as those in the first embodiment. Add 100 to the number to indicate it.

6A and 7A are cross-sectional views illustrating a first mask process step.

As shown in FIGS. 6A and 7A, a step of defining a switching region S, a pixel region P, a common region C, and a data region D is performed on the substrate 200.

A polysilicon layer (not shown) is formed on the substrate 200 in which the plurality of regions S, P, C, and D are defined and patterned to form the semiconductor layer 240 corresponding to the switching region S. Form.

Next, the first insulating layer 245 is formed on the entire upper surface of the substrate 200 on which the semiconductor layer 240 is formed, selected from a group of inorganic insulating materials such as silicon nitride (SiNx) and silicon oxide (SiO ₂ ).

6B to 6D and 7B to 7D are cross-sectional views illustrating a second mask process step.

6B and 7B, the substrate 200 on which the first insulating layer 245 is formed is selected from a transparent conductive metal group such as indium tin oxide (ITO) or indium zinc oxide (IZO). The transparent metal layer 270a is formed.

Subsequently, one selected from the group of conductive metals such as copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd) and chromium (Cr) on the substrate 200 on which the transparent metal layer 270a is formed. The gate metal layer 225a is formed.

Next, a photoresist is formed on the substrate 200 on which the transparent metal layer 270a and the gate metal layer 225a are formed to form a photosensitive layer 290, and a transmissive portion T1 is formed on the photosensitive layer 290. The halftone mask HTM including the transflective part T2 and the blocking part T3 is aligned.

In this case, the blocking part T3 is positioned to correspond to a part of the switching area S and the common area C, respectively, and the transflective part T2 is positioned in the pixel area P. The region allows the transmissive portion T1 to be located.

6C and 7C, a process of exposing and developing the upper halftone mask (HTM of FIGS. 6B and 7B) is performed to correspond to the switching area S and the common area C. First and second photosensitive patterns 292 and 294 having no thickness change, and third photosensitive patterns 296 having a thickness lowered by about half in correspondence to the pixel region P are formed, respectively. At this time, all of the photosensitive layer (290 of FIGS. 6B and 7B) corresponding to the transmission part (T1 of FIGS. 6B and 7B) are removed and the gate metal layer 225a of the lower portion thereof is exposed.

6D and 7D, the first to third photosensitive patterns 292, 294, and 296 are used as masks, and the exposed gate metal layer 225a and the transparent metal layer 270a are sequentially patterned. 3, a gate electrode 120 in FIG. 3, a pixel electrode 270 designed in a plate shape corresponding to the pixel region P, and a common wiring 250 corresponding to the common region C are formed.

In this case, a part of the gate wire disposed in the upper portion overlapping the semiconductor layer 240 is used as the gate electrode 225. The gate electrode 225, the pixel electrode 270, and the common electrode 280 have a double layer structure in which a transparent pattern 270b and a gate pattern 225b are sequentially stacked.

6D and 7D, when the first to third photosensitive patterns (292, 294 and 296 of FIGS. 6C and 7C) are ashed, the first and second photosensitive patterns (FIG. 6C) are performed. And 292 and 294 of FIG. 7C are reduced to about half thickness, and the third photosensitive pattern (296 of FIGS. 6C and 7C) is removed to expose the lower gate pattern (225b of FIGS. 6C and 7C). do.

Next, the gate pattern corresponding to the pixel region P (225b of FIGS. 6C and 7C) is patterned by a wet etching process so that the transparent pattern (270b of FIGS. 6C and 7C) is exposed. As a result, the pixel electrode 270 formed of a single layer of the transparent pattern (270b of FIGS. 6C and 7C) is formed in the pixel region P. Referring to FIG.

The second mask process step is finally completed by removing the first and second photosensitive patterns 292 and 294 of FIGS. 6C and 7C through a strip process.

Since the third to sixth mask process steps of the second embodiment of the present invention correspond to the fourth to seventh mask process steps of the first embodiment, duplicate description thereof will be omitted.

Accordingly, in the second embodiment of the present invention, the array substrate for the transverse electric field type liquid crystal display device can be manufactured in the six mask process by forming the gate wiring and the pixel electrode in one mask process.

In the first and second embodiments of the present invention, the coplanar structure has been described as an example, but it will be well known that various applications such as a top gate structure and a bottom gate structure can be applied.

Therefore, the present invention is not limited to the first and second embodiments, and it will be apparent that various changes and modifications can be made without departing from the spirit and the spirit of the present invention.

1 is a plan view showing a unit pixel of a conventional array substrate for a transverse electric field type liquid crystal display.

2A to 2H are cross-sectional views illustrating a process sequence by cutting along the line II-II ′ of FIG. 1.

3 is a plan view illustrating unit pixels of an array substrate for a transverse electric field type liquid crystal display device according to a first exemplary embodiment of the present invention.

4A to 4I are cross-sectional views taken along line IV-IV ′ of FIG. 3 and shown in a process sequence.

5A to 5I are cross-sectional views illustrating a process sequence by cutting along the line VV ′ of FIG. 3.

6A to 6D are cross-sectional views illustrating a process sequence by cutting along line IV-IV ′ of FIG. 3.

7A to 7D are cross-sectional views illustrating a process sequence by cutting along the line VV ′ of FIG. 3.

Description of the Related Art [0002]

100: substrate 120: gate wiring

125: gate electrode 130: data wiring

132: source electrode 134: drain electrode

140: semiconductor layer 150: common wiring

170: pixel electrode 180: common electrode

POH: pixel open hole CMH1, CMH2: first and second common holes

SH: source hole DH: drain hole

P: pixel area

Claims (18)

A substrate; A semiconductor layer on the substrate; A first insulating film on the semiconductor layer; Gate wiring formed in one direction on the first insulating film, and common wiring spaced in parallel with the gate wiring; A pixel electrode designed on the first insulating film in a plate pattern corresponding to the pixel region; A second insulating film including a source and a drain hole exposing the semiconductor layer on the pixel electrode, a first common hole exposing the common wiring, and a pixel open hole exposing the pixel electrode; A data line perpendicular to the gate line on the second insulating layer, a source electrode in contact with the semiconductor layer, and a drain electrode spaced apart from the source electrode; Third and fourth insulating films including the data lines, second common holes, and photosensitive patterns on the source and drain electrodes; A common electrode in contact with the common wiring on the third and fourth insulating films And a plurality of pixel electrodes formed on the substrate. The method of claim 1, And the third insulating layer is one selected from the group of inorganic insulating materials including silicon oxide and silicon nitride. The method of claim 1, And the fourth insulating layer is one selected from the group of organic insulating materials including photoacryl and benzocyclobutene. The method of claim 1, The common electrode includes an extension part in contact with the common wiring through the first and second common holes, and a plurality of vertical parts vertically branched from the extension part toward the pixel area. Array substrate for display device. 5. The method of claim 4, And the photosensitive pattern lowers the parasitic capacitance between the data line and the vertical portion of the common electrode. The method of claim 1, And only the third insulating layer is interposed between the pixel electrode corresponding to the pixel region and the vertical portion of the common electrode, wherein only the third insulating layer is interposed therebetween. The method of claim 1, And the semiconductor layer is made of polysilicon. Forming a semiconductor layer on the substrate; Forming a first insulating film on the semiconductor layer; Forming a gate wiring in one direction on the first insulating film and a common wiring spaced in parallel with the gate wiring; Forming a pixel electrode designed in a plate pattern on a substrate on which the gate wiring and the common wiring are formed; Forming a second insulating layer including a source and a drain hole, a first common hole, and a pixel open hole respectively exposing the semiconductor layer, the pixel electrode, and the common wiring; A data line vertically intersecting the gate line on the second insulating layer, a source electrode extending from the data line and in contact with the semiconductor layer, and a drain spaced apart from the source electrode and in contact with the semiconductor layer and the pixel electrode, respectively. Forming an electrode; Forming a third insulating film including a second common hole exposing the common line on the substrate on which the data line and the source and drain electrodes are formed; Forming a fourth insulating film on the substrate on which the third insulating film is formed, the fourth insulating film including a photosensitive pattern corresponding to an upper portion overlapping the data line; Forming a common electrode in contact with the common wiring through the second common hole Wherein the first substrate and the second substrate are bonded to each other. Claim 9 has been abandoned due to the setting registration fee. 9. The method of claim 8, And the first to third insulating films are each formed of one selected from the group of inorganic insulating materials including silicon oxide and silicon nitride. Claim 10 has been abandoned due to the setting registration fee. 9. The method of claim 8, And the fourth insulating film is formed of one selected from the group of organic insulating materials including photoacryl and benzocyclobutene. 9. The method of claim 8, And the fourth insulating film is formed of a material having a lower dielectric constant than the third insulating film. Claim 12 is abandoned in setting registration fee. 9. The method of claim 8, The semiconductor layer is a method of manufacturing an array substrate for a transverse electric field type liquid crystal display device, characterized in that made of polysilicon. Claim 13 has been abandoned due to the set registration fee. 9. The method of claim 8, The common electrode includes an extension part in contact with the common wiring through the first and second common holes, and a plurality of vertical parts vertically branched from the extension part toward the pixel area. Method of manufacturing array substrate for display device. 9. The method of claim 8, Forming the second common hole and the photosensitive pattern, Forming a third insulating film and a fourth insulating film in order on the substrate on which the data line and the source and drain electrodes are formed, and aligning a mask including a transmissive part, a transflective part, and a blocking part; Exposing and developing the upper portion of the mask to form first to third photosensitive patterns, respectively; Using the first to third photosensitive patterns as a mask, patterning the third insulating film corresponding to the common wiring to form a common hole exposing the common wiring; The first to third photosensitive patterns are ashed to reduce the thickness of the first and second photosensitive patterns, and the third photosensitive pattern is removed to expose the third insulating layer under the third photosensitive pattern. Letting step Wherein the first substrate and the second substrate are bonded to each other. Forming a semiconductor layer on the substrate; Forming a gate wiring in one direction on the semiconductor layer, a common wiring spaced in parallel with the gate wiring, and a pixel electrode designed in a plate pattern corresponding to the pixel region; Forming a first insulating film on the substrate on which the gate wiring, the common wiring and the pixel electrode are formed; Patterning the first insulating film to form source and drain holes, a first common hole, and a pixel open hole exposing the semiconductor layer, the common wiring, and the pixel electrode, respectively; A source electrode on the first insulating layer including the source and drain holes, the first common hole, and the pixel open hole, a data line extending in a direction perpendicular to the gate line, and a source electrode extending from the data line and in contact with the semiconductor layer. Forming a drain electrode spaced apart from the source electrode and in contact with the semiconductor layer and the pixel electrode, respectively; Sequentially forming a second insulating film and a third insulating film on the substrate on which the data line and the source and drain electrodes are formed; Selectively patterning the third insulating film and the fourth insulating film to form a second common hole exposing the common wiring and a photosensitive pattern on the data wiring; Forming a common electrode in contact with the common wiring through the second common hole Wherein the first substrate and the second substrate are bonded to each other. 16. The method of claim 15, And the gate wiring and the common wiring are formed by sequentially stacking a first metal layer and a second metal layer. 16. The method of claim 15, And the pixel electrode is formed of a first metal layer. 17. The method of claim 16, The first metal layer is selected from a group of transparent conductive metals including indium tin oxide or indium zinc oxide, and the second metal layer is selected from a group of conductive metals including copper, molybdenum, aluminum, aluminum alloy and chromium. A method of manufacturing an array substrate for a transverse electric field type liquid crystal display device, characterized in that each formed one.

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