KR101284243B1 - Cross share grid of pcb tester - Google Patents

Abstract

PURPOSE: A cross share grid of unequipped printed circuit board inspection apparatus is provided to reduce overlapped use of pin by sharing with pins utmost distant sides. CONSTITUTION: A real point grid pin is arranged on a 35-mil grid. A grid pin region arranges the real point grid pin. The grid pin region arranges a shared point grid pin. First, second, third and fourth sections (S1-S4) are successively configured in a first row. Fifth, sixth, seventh and eighth sections (S5-S8) are successively configured in a second row. [Reference numerals] (S1) First division section; (S2) Second division section; (S3) Third division section; (S4) Fourth division section; (S5) Fifth division section; (S6) Sixth division section; (S7) Seventh division section; (S8) Eighth division section

Description

CROSS SHARE GRID OF PCB TESTER}

The present invention relates to an unmounted printed circuit board inspection apparatus, and more particularly, in a board inspection apparatus for inspecting whether a printed circuit board is defective in a state in which no parts are mounted, a 35 mil grid is installed in a center of 25 mil grid. A cross-share grid of an unmounted printed circuit board inspection device that cross-shares grid pins disposed in an area and grid pins disposed in an edge area so that a 35 mil grid and a 25 mil grid can be used.

A printed circuit board is used to form a circuit by electrically connecting each input / output terminal of electronic parts through soldering by mounting electronic components by coating copper foil on a resin substrate and removing the remaining parts. Since the wiring pattern provided on the board needs to accurately transmit electrical signals to electronic components such as semiconductor chips mounted on the printed circuit board, when the printed circuit board is manufactured, the wiring pattern is formed through the board inspection apparatus before the application to the actual product. It should be tested whether it is formed according to the design criteria and operates normally.

Generally, the substrate inspection apparatus can be divided into a group having a finger tester and a group having a parallel tester. The parallel tester is a tester which is brought into contact with all the check points of the circuit board under test or at least the majority of the circuit board check points by an adapter, and the finger tester is a test tester for an unmounted or mounted circuit board. The tester scans each checkpoint using the fingers in sequence.

In addition, the parallel tester type substrate inspection apparatus may be divided into a universal type as shown in (a) of FIG. 1 and a dedicated type as shown in (b) of FIG. 1. The universal type is generally composed of a fixture 11, a grid 12, and a scan card 13, but the grid 12 and the scan card 13 are in a separated state. The pin 14 is made to be in contact with each contact point of the scan card 13, the decisive type consists of the fixture 11 and the grid 12 and the scanner block 20, the grid of the grid 12 The pin 14 extends into the wire 141 and is directly connected to the scanner block 20.

The grid pin 14 is elastically wound in the form of a coil so that it can apply a uniform pressure in all the contact areas when it is in contact with the test pins 15 of the fixture 11, the fixture 11 is one The plurality of inspection pins 15 are coupled to the above plate so that the inspection substrate 30 and the grid pin 14 can be electrically connected to each other to inspect whether the inspection substrate 30 is defective.

That is, in the substrate inspection apparatus 10 as described above, the inspection pins 15 are respectively contacted with the inspection pins at both ends of the wiring pattern to be measured, and a predetermined level of current is applied, and the voltage generated between the inspection pins 15 is applied. It was determined whether the inspection target substrate is defective by measuring the resistance value.

Recently, due to the diversification of functions of electronic products, a large number of electronic components are mounted in circuit boards, and the size of electronic components is reduced and the spacing between mounting components is narrowed to reduce the volume. Since the checkpoints set on the substrate having a small area are made thinner or smaller due to complexity or miniaturization, the diameters of the test pins 15 and the grid pins 14 installed on the fixture 11 and the grid 12 are also smaller. It is a situation that is formed and densely arranged.

On the other hand, when designing electronic components, the pitch spacing of terminals derived from the components to the outside is mainly designed in mils, and correspondingly, pads in which the terminals of the electronic components are inserted or soldered in a printed circuit board on which the electronic components are mounted are correspondingly. The location is also designed in mils, which is narrowing down from 100 mils to 70 mils, 50 mils and 35 mils. mil is an abbreviation for milli inch as a unit of length, and 1 mil is 0.0254 mm.

As the printed circuit board is designed in mils, the test pins and grid pins arranged in the fixture or grid of the board inspection apparatus are also designed in mils. At present, the universal type board inspection apparatus has been developed up to a grid of 35 mils apart. If you want to inspect printed circuit boards with narrow pitch spacing as the same board inspection device as the next step of 35 mil spacing, the pin spacing of fixture and grid should be arranged more closely at 25 mil spacing. The problem that the area of N becomes narrow arises.

FIG. 2 is a diagram illustrating a pitch spacing structure of grid pins in a grid, and FIG. 2 (a) illustrates a 50 mil pitch spacing, (b) a 35 mil pitch spacing, and (c) a 25 mil pitch spacing structure. The 50 mil grid has a pitch interval of 50 mil units between each grid pin (shown as a circular diagram), as shown in FIG. 2 (a), and the 35 mil grid has a 50 mil grid as shown in FIG. 2 (b). Additional grid pins are placed in the center of each grid pin in the diagonal direction (added grid pins are displayed in a rectangular shape), so the pitch interval between grid pins is 35 mil.

Similarly, to implement a 25 mil grid, additional grid pins can be placed in the middle of each grid pin in the 35 mil grid (additional positions are shown in triangles) or in the middle of the vertical, horizontal and diagonal directions in a 50 mil grid. Additional grid pins shall be arranged (additional positions shown in triangular and square).

In other words, the number of inspection points that can be inspected in the substrate inspection apparatus is limited, but the denser the pitch interval between the inspection pins or grid pins, the narrower the area that can be inspected at once.

Thus, in the related art, as shown in FIG. 3, the grid connection unit between the measuring unit 40 and the grid 12a of the grid 12a is not configured in a 1: 1 connection. Instead, two grid pins are connected to one measuring point. A shared shared grid has been proposed. The illustrated example divides the grid 12a into area A and area B, grid pin A11 in area A and grid pin B11 in area B, grid pin A12 in area A and grid pin B12 in area B. ), A structure in which all grid pins in the A region and the B region are shared one by one, such as the grid pin A13 in the A region and the grid pin B13 in the B region.

Since the share grid is equivalent to measuring two grids having the same pin pitch spacing, the measurement area can be doubled. However, this share structure is a flexible structure that can extend the measurement area compared to the grid of 1: 1 connection method, but if one grid pin is shared among the shared grid pins, other grid pins cannot be used. There is a problem that the expansion effect is not relatively high because the number of grid pins overlapped in the shared grid pins during the actual substrate inspection.

The present invention is invented to solve the above problems, in the substrate inspection apparatus using a 35 mil grid, the grid is composed of 25 mil grid, while dividing the grid into 4 × 2 regions, located as far as possible with respect to each divided region. By sharing the grid pins in correspondence with each other, but sharing the grid pins with the grid pins as far away as possible, reducing the probability of overlapping shared pins when inspecting a printed circuit board, and using a 35mil grid. An object of the present invention is to provide a cross-share grid of an unmounted printed circuit board inspection apparatus that can exhibit the effect of using a 25mil grid in the inspection apparatus.

In order to achieve the above object, the cross-sharing grid of the non-mounted printed circuit board inspection apparatus of the present invention has a shared point in the middle of the diagonal direction of each real point grid pin on a 35 mil grid in which real point grid pins are arranged at 35 mil pin pitch intervals. Grid pins are additionally arranged to form a grid of 25 mil pin pitch spacing, and the grid pin area in which the real point grid pins and the shared point grid pins are arranged is equally divided into 4 × 2 areas to form a grid. The first, second, third, and fourth partitions are set in turn, and the fifth, sixth, seventh, and eighth partitions are sequentially set in the second row, and the first partition and the seventh partition are made. Grid share between the shared regions by setting the second and eighth partitions, the third and fifth partitions, and the fourth and sixth partitions as mutually shared areas. By mutually connecting each other to form a 35 mil grid using the real point grid pins, and combining the real point grid pins and the shared point grid pins to form a 25 mil grid, which can be used as a 35 mil grid and a 25 mil grid. have.

The shared wiring of the grid pins between the shared areas may be shared by sequentially connecting the grid pins of the same row between the shared areas, but connecting the real point grid pins and the shared point grid pins sequentially from the top to the bottom of each row.

According to the present invention, an additional grid pin (shared point grid pin) is placed on the 35 mil grid in the board inspection apparatus for inspecting whether the printed circuit board is defective using the 35 mil grid while forming a grid having a 25 mil pin pitch interval. By sharing with the 35mil grid pin of the cross share method, it is possible to solve the problem of no overlap between share points, which is a weak point of the share method, since the check points that are actually used are concentrated in the center of the grid, which is an area required for actual board inspection. Therefore, it is possible to inspect printed circuit boards with 25 mil pin pitch in the board inspection apparatus using the 35 mil grid, and overcome the problem of fewer points in the board inspection apparatus using the 35 mil grid. There is an advantage to inspect the printed circuit board.

1 is a schematic diagram of a general parallel tester type substrate inspection apparatus, Figure 1 (a) is a universal type, Figure 1 (b) is a diagram showing a dedicate type,
2 is a view illustrating a pitch spacing structure of grid pins in a general grid;
3 is a view for explaining a conventional grid pin share structure,
4 is a diagram for explaining a cross share grid according to the present invention;
5 is an exemplary use of the present invention.

Hereinafter, the configuration and operation of an embodiment of the present invention will be described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and those skilled in the art to which the present invention pertains. It is provided to those skilled in the art to easily understand the scope of the invention, which is defined by the description of the claims. On the other hand, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

4 is a view for explaining a cross-share grid according to the present invention.

As shown in FIG. 4, the region 14 in which the grid pins are disposed in the grid 12 is equally divided into first through eighth divided regions S1 through S8 having a 4 × 2 shape, and thus, the first The fourth to fourth regions S1 to S4 are disposed on the upper side, and the fifth to eighth regions S5 to S8 are disposed on the lower side.

Real point grid pins are placed at 35 mil pin pitch intervals over the entire area of grid 12 (S1 to S8) to form a 35 mil grid (see FIG. 2 (b)). As a pin directly connected to the measuring unit 40 to implement, it is shown as a circle filled in black in FIG.

In addition, a shared point grid pin is additionally disposed in the middle of the diagonal direction of each real point grid pin constituting the 35 mil grid over the entire area (S1 to S8) of the grid 12, so that the real point grid pin and the shared point are respectively disposed. The grid pins combine to form a grid of 25 mil pin pitch spacing (see FIG. 2 (c)).

The shared point grid pin is a pin connected to the measurement unit 40 by being co-wired with the real point grid pin in order to implement a function similar to a 25 mil grid, and is illustrated as an empty circle in FIG. 4.

As part of the fourth divided area S4 and the eighth divided area S8 is illustrated, the real point grid pins and the shared point grid pins are continuously arranged in alternating top, bottom, left and right directions.

Further, according to the present invention, the first partition S1, the seventh partition S7, the second partition S2, and the eighth partition in order to share the real point grid pin and the shared point grid pin in a cross share manner. The grid pins between the shared areas are mutually set by setting the area S8, the third partition S3 and the fifth partition S5, and the fourth partition S4 and the sixth partition S6 as mutually shared areas. By sharing connection, each sharing area is shared by cross sharing.

Referring to FIG. 4, the first real point grid pin in the first column of the first partition S1 may be connected to the first shared point grid pin below the first real point grid pin in the first column of the seventh partition S7. The first real point grid pin in the first row of the seventh partition S7 is shared and the first shared point grid pin below the first real point grid pin in the first row of the first partition S1. do.

Also, although not shown, the second real point grid pin in the first column of the first partition S1 may be different from the second shared point grid pin below the second real point grid pin in the first column of the seventh partition S7. The second real point grid pin of the first row of the seventh partition S7 is shared and the second shared point grid pin below the second real point grid pin of the first row of the first partition S1. do.

The cross share sharing connection is repeatedly performed from the first column of the first divided region S1 and the seventh divided region S7 to the lowest end, and similarly, the first divided region S1 and the seventh divided region S7 The cross share shared wiring is done on the grid pins of all rows in the same way.

Furthermore, similarly to the cross share shared wiring structure between the first divided area S1 and the seventh divided area S7, the second divided area S2, the eighth divided area S8, and the third divided area S3 and the third divided area S7 are similar to the cross share shared wiring structure. The cross share sharing connection is made in the same manner with respect to each of the grid fins of the fifth division S5 and the fourth division S4 and the sixth division S6.

As described above, the present invention forms a 25 mil grid by combining the real point grid pins arranged at 35 mil pin pitch intervals with the shared point grid pins disposed in the middle thereof, but the shared point grid pins are shared by the real point grid pins. Because of its shape, it doesn't actually have the same performance as a 25mil grid. However, when inspecting the actual printed circuit board, the printed circuit board is mostly placed in the center of the grid and is not located to the edge, and thus almost the same performance as the 25 mil grid is obtained.

Therefore, in the substrate inspection apparatus using the 35mil grid according to the present invention, the substrate can be inspected by using both 35mil grid and 25mil grid, and the inspection area can be expanded by software and hardware in a small number of substrate inspection apparatus. Will be.

Figure 5 shows an example of the use of the present invention.

As shown in FIG. 5, when inspecting the inspection target plate 30 (indicated by the dotted lines) using the grid 12, the inspection target plate 30 mainly corresponds to the central region of the grid 12. It does not correspond to the whole area of (12).

Therefore, the grid pin actually used during the inspection of the board uses only the central part of the grid 12 intensively and rarely the one arranged at the edge. It does not occur. In particular, in sharing the grid pins, the entire area of the grid is divided into a plurality of areas, and then the central area and the edge area are shared, but the lower area is cross-shared so as to be shared with the upper area, so that the shared grid pins are used repeatedly. The probability is lowered further.

In the above embodiment, a 35 mil grid and a 25 mil grid are used in a substrate inspection apparatus using a 35 mil grid. However, the embodiment is not limited thereto, and the 25 mil grid and the grid of a lower stage or a higher stage are used. It will be apparent to those skilled in the art that the same technical concept can be applied to them and used interchangeably.

In the above embodiment, the grid pin area is equally divided into 4 × 2 areas as an example, but the present invention is not limited thereto. It will be apparent to those skilled in the art that a divided region such as a compartment may be modified to be cross-shared in a manner similar to the above.

10-board inspection device, 11-fixtures,
12, 12a-grid, 13-scan card,
14-grid pin, 141-wire,
15-test pin, 20-scanner block,
30-the substrate to be tested, 40-the measuring part of the board inspection apparatus,
S1 to S8-first to eighth divided regions,

Claims (2)

In the 35 mil grid where the real point grid pins are arranged at 35 mil pin pitch intervals, additional shared point grid pins are arranged in the middle of each real point grid pin diagonally to form a grid having 25 mil pin pitch intervals. Evenly divide the pin and the grid pin area in which the shared point grid pins are arranged into 4 × 2 areas to set the first, second, third, and fourth partitions in the first row, and then in the second row. The fifth, sixth, seventh, and eighth partitions are set in order, and the first partition, the seventh partition, the second partition, the eighth partition, the third partition, the fifth partition, and the fifth partition. While the fourth and sixth partitions are set as mutually shared areas, the grid pins between the shared areas are mutually shared in a cross share manner to form a 35 mil grid using the real point grid pins, Based real-pin grid points and the grid point share The combined pin 25mil form a grid, the grid cross shares of unequipped printed circuit board testing device made to serve as the grid and 35mil 25mil grid combination. The shared wiring of the grid pins between the shared areas is shared by sequentially connecting the grid pins of the same row between the shared areas, and connects the real point grid pins and the shared point grid pins sequentially from the top to the bottom of each row. Cross-share grid of an unmounted printed circuit board inspection apparatus, characterized in that.

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