JP2019219368A - Probe card - Google Patents

Abstract

To obtain a probe card which can simultaneously cope with an inspection of a semiconductor chip having multi-row narrow pitches and a multi-pin alignment, a simultaneous inspection of a plurality of semiconductor chips, an inspection of a semiconductor chip having a high-frequency signal path, an inspection in a wide-range temperature environment and so forth, and to provide the inexpensive probe card which has been solved in a problem of connection with a probe and wiring.SOLUTION: A wiring film in which a plurality of conductive conductor patterns are formed on one insulation film has, at one end of the conductor pattern, single-row probe aggregate alignment means, and direction conversion means for folding a single-row probe aggregate to a substantially-vertical direction with respect to an XY-plane, and placing it. Since the wiring film also has external terminal connection means and conductor pattern expansion means at the other end, a probe card having the same conductor pattern, and serving as a function of a probe and a function of a wiring pattern can be obtained. Furthermore, there is arranged a multilayer wiring film which is formed by laminating a plurality of wiring films, thus coping with a complicated semiconductor chip terminal alignment such as a staggered alignment, a lattice alignment or the like.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a probe card used for circuit inspection of a plurality of semiconductor chips formed on a semiconductor wafer.

  Probe cards used for testing semiconductor circuits are required to have a higher density of probe arrangements in order to cope with an increase in the number of terminal pads on a semiconductor chip, a reduction in pad area, and a reduction in the pitch between pads. At present, an example of an IC having the narrowest pitch pad and a large number of terminals is an IC mainly used for driving a liquid crystal panel (hereinafter, LCD driver IC). In particular, for terminal pad rows that output signals corresponding to all pixels of the liquid crystal, ICs with more than 2,000 terminals with a pad pitch of 15 μm or less using a plurality of rows of staggered arrangements have been developed, resulting in higher image quality. There is a tendency for the pitch to be narrower and the number of pins to be increased in accordance with the trend toward more pins.

  In addition, for the purpose of improving device characteristics, reducing power consumption, and saving space, a technology for three-dimensionally mounting a plurality of IC chips using through silicon vias (TSVs) has been developed. As a typical example, an IC for a central processing unit (CPU) and a plurality of semiconductor memories (for example, DRAMs) used for a smartphone or an image device and the like, which are three-dimensionally mounted by TSV, are being put to practical use. A three-dimensional mounting IC using a TSV is characterized by a narrow pitch lattice-like arrangement at a pitch of 40 μm, which makes the arrangement more and more difficult.

  The probe card must be efficiently wired from each probe terminal in a multi-pin probe assembly arranged at a narrow pitch to an external tester connection terminal installed at a relatively coarse pitch around the probe card, The smaller the pitch of the probe terminals and the greater the number of probe terminals, the more the wiring board has a multilayer structure.

  In the inspection of a memory IC or the like, it is general to inspect a plurality or all of the chips on a semiconductor wafer at the same time in order to reduce the inspection cost. For this purpose, it is necessary to dispose probes corresponding to a wide area of the entire semiconductor wafer and to improve mutual arrangement accuracy including a change in temperature of the inspection environment.

  Further, as the operating speed of the IC increases, the signal frequency of a specific input / output pin tends to increase in a sophisticated IC, and a probe card having excellent high-frequency characteristics is required. As a high-frequency pattern on a printed wiring board used in a conventional probe card, a microstrip line structure or a strip line structure is generally used, and a multi-layered structure is formed together with a ground layer or a power supply layer above and below each signal line. Has become. Particularly, in a signal line having a high signal frequency, a shielded coaxial line having a characteristic impedance is often used in many cases, and there is a problem how to maintain the impedance matching right up to the probe needle.

  As described above, there is a demand for a probe card technology that can respond to a variety of requirements, such as narrowing the number of pins of pins and increasing the speed of signals, which are common issues of next-generation semiconductor devices that are small and have high functionality. .

  As an efficient probe assembly for a pad arrangement including a narrow pitch staggered arrangement and an efficient wiring method from a narrow pitch probe arrangement to a wiring board, for example, as disclosed in JP-A-2006-206160, One or more wiring pattern sheets are provided on the surface layer of the substrate, in which a copper foil sheet is processed to form a wiring pattern for connecting the probe and the interface section, and one end of the wiring pattern is electrically connected to the probe terminal section. In the manufacture of a probe, a plurality of probes including a vertical probe part, a probe deformation part, a probe conductor pattern part and a probe terminal part are collectively micro-processed from a conductive metal foil and attached to an insulating film. A probe assembly arranged on the same plane, and the distance between the tips of the probe vertical portions of the probe assembly is Is identical to either the pad spacing of de row, all probes contour in one of the probe assemblies, those having a unit to be processed continuously from one conductive metal foil.

  In JP-A-2006-206160, a metal conductor sheet is adhered to one or both surfaces of a probe conductor pattern portion via an insulating layer of polyimide or the like, and a grounding vertical probe portion and a grounding probe terminal portion are attached to the conductor sheet. Means for providing, means for attaching a copper foil sheet on one or both sides of the wiring pattern sheet via an insulating layer of polyimide or the like to provide a wiring pattern for grounding, and the grounding probe terminal portion is part of the wiring pattern for grounding. By having the connecting means, a combination of the signal line pattern and the grounding pattern can be applied to both the probe and the wiring pattern, so that a structure having excellent electrical characteristics such as a high-frequency signal can be obtained. It has become.

  Furthermore, as disclosed in Japanese Patent Application Laid-Open No. 2014-202739, the number of layers can be reduced by performing wire wiring on the surface of the substrate without connecting the wiring inside the substrate and connecting the probe terminal portion and one end of the wire. There is a substrate that facilitates wiring connection.

JP-A-2006-206160 JP 2014-202739 A

  However, according to the method disclosed in JP-A-2006-206160, it is difficult to connect the narrow-pitch probe group and the pattern on the substrate, which causes an increase in non-connection portions, A problem arises in that the occurrence of electrical discontinuities leads to variations in resistance values and deterioration due to reflection of high-frequency characteristics. Further, according to the method disclosed in JP-A-2014-202739, there is a problem that it takes time for the wire connection process. Further, these problems become more conspicuous as the number of terminal arrangements of semiconductor chips or the number of semiconductor chips to be inspected simultaneously on a semiconductor wafer increases.

  The present invention has been made in order to simultaneously solve the common problems in the probe card, and has been made in order to simultaneously inspect a semiconductor chip having a plurality of rows of a narrow pitch and a multi-pin array, a simultaneous inspection of a plurality of semiconductor chips, and a high-frequency signal path. It is intended to provide a probe card which can cope with a semiconductor chip inspection having inspection, an inspection under a wide temperature environment, and the like, and also provides an inexpensive probe card which solves a problem of connection between a probe and a wiring.

  The present invention is a wiring film in which a plurality of conductive conductor patterns are provided on one insulating film, and a probe assembly alignment means at one end of the conductor pattern on the wiring film plane (XY plane); Since the probe assembly has a direction changing means, an external terminal connection means at the other end of the conductor pattern, and a conductor pattern expansion means between the probe assembly and the external connection terminal, the pitch is reduced. A connection step between the probe group and the wiring pattern is not required, and an electrically stable and inexpensive probe card can be supplied.

  The present invention also provides a single-row probe assembly in which a part or all of the probe tips in the probe assembly are arranged on an arbitrary straight line in the wiring film plane (XY plane). Is the same as the arrangement interval of the target semiconductor electrode terminal to be inspected in the XY plane coordinates, and the center axis is a straight line on the conductor pattern at an arbitrary distance from the straight axis connecting the probe tips. Since the single-row probe assembly has direction changing means for bending and installing the single-row probe assembly in a direction substantially perpendicular to the XY plane, a highly accurate probe tip arrangement can be realized.

  The present invention also provides a second single-row probe assembly, which is linearly arranged substantially in parallel with the first single-row probe assembly, and a straight-line shape substantially perpendicular to the first single-row probe assembly. , The third or fourth single-row probe assembly, wherein the arrangement intervals in the XY plane coordinates of the tips of some or all of the first to fourth single-row probe assemblies are of interest. Since there is a means that is the same as the arrangement interval of the semiconductor electrode terminals to be inspected on the XY plane coordinates, it is possible to realize a probe assembly that can easily correspond to the electrode terminals of the semiconductor device in any arrangement.

  Further, the present invention has a means for forming the conductor pattern as one or more arbitrary probes in the single-row probe and one or more external connection terminals at the other end, so that the same conductor The pattern can have both the function of the probe and the function of the wiring pattern, so that a probe card having a small electric resistance and a small number of wiring layers can be realized.

  Further, according to the present invention, the conductor pattern is formed of a linear assembly, and the pitch between the conductor patterns or the conductor pattern width increases stepwise from the probe to the external connection terminal, or Part or the entire shape of the pattern is a continuous curve, and since there is means for continuously increasing the pitch between the conductor patterns or the width of the conductor pattern from the probe to the external connection terminal, the electric resistance is low. It is possible to realize a wiring pattern with a small number of wiring layers.

  Further, the present invention has means for arranging two or more probe assemblies by a multilayer wiring film obtained by laminating one or more of the wiring films on a part or all of one of the wiring films, In a multilayer wiring film, in a probe assembly in which two or more single-row probe assemblies are stacked, a part or all of the probe tips have the same vertical position (Z direction), and the probe tip has an XY plane. Since the arrangement interval in the coordinates is the same as the arrangement interval of the target semiconductor electrode terminals to be inspected in the XY plane coordinates, a probe assembly that can easily correspond to the electrode terminals of the semiconductor device in any arrangement is realized. be able to.

  Also, the present invention provides a dimensional relationship (for example, conductor pattern width, thickness, insulation layer thickness, etc.) in a cross-sectional direction between a part or all of the conductor pattern of the wiring film, the insulating layer, and the ground pattern layer, and Has a means for setting the electrical characteristics (e.g., relative permittivity, etc.) of the probe to a predetermined characteristic impedance value in advance, so that there is no discontinuity from the probe tip to the end of the wiring pattern, and the probe has excellent high-frequency characteristics. A card can be realized.

  In addition, the present invention has a means for providing a ground wiring pattern near the conductor pattern via an air layer or an insulating layer such as polyimide on the same plane as part or all of the conductor pattern. It is possible to realize a probe card having extremely small leakage current required for measurement.

  Further, the present invention is a relay wiring film in which one or a plurality of conductor patterns and a relay electrode terminal are provided at both ends of the conductor pattern on one insulating film, and one end of the relay electric terminal is provided. Since it has means for connecting to the connection terminal provided on the wiring film and connecting the other end to the other connection terminal provided on the wiring film, a plurality of wiring patterns intersect on the XY plane. However, it is possible to form an efficient wiring pattern using a small number of wiring films.

  Further, in the present invention, in the single-row probe assembly of the wiring film, a support is provided along the probe placement direction (X direction) in parallel with a probe placement surface (XZ plane), and a part of the probe is provided. Alternatively, a material is provided in which all X-direction positions have a means for following the X-direction displacement caused by thermal contraction of the support, and a material whose linear expansion coefficient of the support is close to the linear expansion coefficient of the semiconductor wafer to be inspected is selected. By doing so, it is possible to realize a probe card that can support inspection under a wide range of temperature environments.

  According to the probe card of the present invention, there is provided a wiring film in which a plurality of conductive conductive patterns are provided on one insulating film, and a probe assembly at one end of the conductive pattern on the wiring film plane (XY plane). Alignment means, direction change means of the probe assembly, external terminal connection means at the other end of the conductor pattern, by having a conductor pattern expansion means between the probe assembly and the external connection terminal, In addition to realizing a probe card capable of responding to a semiconductor chip inspection having a plurality of rows of a narrow pitch and a multi-pin array, a simultaneous inspection of a plurality of semiconductor chips, a semiconductor chip inspection having a high-frequency signal path, an inspection in a wide temperature environment, and the like. An object of the present invention is to provide an inexpensive probe card which solves the problem of connection between a probe and wiring.

  FIG. 1 is a perspective view illustrating a basic configuration of a probe card according to an embodiment of the present invention.   It is a top view showing the basic structure of the wiring film which is an embodiment of the present invention.   FIG. 2 is a partial detailed view of a wiring film according to an embodiment of the present invention.   FIG. 3 is a diagram illustrating an arrangement relationship of a probe assembly according to an embodiment of the present invention.   It is a figure which shows the multiple lamination structure of the wiring film which is embodiment of this invention.   It is a figure showing the example of the probe assembly in the multilayer wiring film which is an embodiment of the present invention.   It is a figure showing the example of the probe assembly in the multilayer wiring film which is an embodiment of the present invention.   It is a figure showing the example of the probe assembly in the multilayer wiring film which is an embodiment of the present invention.   It is a figure showing the example of the probe assembly in the multilayer wiring film which is an embodiment of the present invention.   It is a figure showing the example of the probe assembly in the multilayer wiring film which is an embodiment of the present invention.   It is a figure showing the example of the probe assembly in the multilayer wiring film which is an embodiment of the present invention.   It is a figure showing composition of a probe aggregate for high frequency signals which is an embodiment of the present invention.   It is a figure showing the lamination state of the wiring film for high frequency signals which is an embodiment of the present invention.   It is a figure showing the structure of the wiring film for microcurrent measurement which is an embodiment of the present invention.   It is a figure showing a manufacturing method and structure of a conductor pattern which is an embodiment of the present invention.   It is a figure showing the probe deformation part structure of the wiring film which is an embodiment of the present invention.   FIG. 4 is a diagram illustrating behavior of a probe assembly due to thermal expansion in the probe assembly.   It is a figure explaining the probe assembly by the heat shrink following structure which is the embodiment of the present invention.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a perspective view showing a basic configuration of a probe card according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a probe card according to an embodiment of the present invention, which is used for inspection of a semiconductor chip 5 to be inspected manufactured on a semiconductor wafer 50. The probe card 1 is mainly composed of a probe assembly 2, a main board 3, and a wiring film 4, and the main board 3 is generally a multilayer wiring board made of an insulating material (for example, FR-4 or the like). There are a circular type and a rectangular type as shown in the illustrated example. An external connection terminal 311 is provided at a peripheral portion of the main board 3 and transmits and receives an inspection signal to and from an external inspection device (not shown) via a through hole in the main board 3. Of the interface unit 301 of FIG.

  In addition, the wiring film 4 is provided on the surface layer (upper surface) 31 of the main board 3 with the probe assembly 2 and the external connection terminals 311 or the electric terminals 302 or the electric components 305 or the connectors 306 on the main board 3. One or a plurality of the wiring films 4 on which a wiring pattern 42 made of a conductive material connected to the wiring board 42 are formed, are connected to a wiring pattern on a surface layer (upper surface) 31, an intermediate layer 35 or a surface layer (lower surface) 32 formed on the main substrate 3. And is installed on the main board 3 independently.

  FIG. 2 is a diagram showing the basic configuration of one wiring film 4 in detail. FIG. 2A shows the overall configuration of the wiring film 4, and FIG. 2B shows one form of the conductor pattern 41. 2A and 2B, reference numeral 40 denotes an insulating film (for example, a polyimide film); 41, a plurality of conductor patterns made of a conductive material provided on the insulating film 40; Is a terminal connection part 43. The probe unit 20 forms a probe assembly 210 including at least one single-row probe assembly, and the figure shows an example in which four single-row probe assemblies 211 to 214 are arranged to face each other.

  The present invention is characterized in that the probe section 20 is continuously integrated with the wiring pattern 4 as a part of the conductor pattern 41.

  The wiring film 4 is mainly composed of the plurality of conductor patterns 41 on the insulating film 40 as described above, and one end is arranged to match the position of the electrode terminal of the semiconductor chip 5 to be inspected on the wafer. The other end constitutes a connection terminal 431 for connecting to the external connection terminal 311 and the like. A cutout 401 is provided in the insulating film 40 to enable a solder connection 308 between the connection terminal 431 and the external connection terminal 311.

  The configuration of the other end of the probe portion 20 of the conductor pattern 41 includes an electric terminal 302 on the main substrate 3 (for example, a through hole connected to the surface layer (lower surface) 32 or the intermediate layer 35 of the main substrate 3). ) Is provided together with the notch 402, and is provided with a connection terminal 434 for connecting to a chip resistor, a chip capacitor, etc. (not shown), or a connection for connecting to a connector, etc. (not shown). The terminals 433 can be formed at the same time. The connection terminals 431 to 434 are arranged in advance at the same positions as the external connection terminals 311, the electric terminals 302, and the like on the XY plane coordinates of the plane of the main substrate 3 so that each of the connection terminals 431 to 434 is provided. The alignment of 434 is unnecessary.

  In the probe card 1, the probe units 20 are generally formed at a narrow pitch (for example, at intervals of several tens of μm), while at the interface unit 301 of the main board 3, a relatively coarse pitch (for example, at intervals of several mm) is used. It is composed of

  On the other hand, FIG. 2A shows an example in which the conductor pattern 41 is constituted by an aggregate of several curves. FIG. 2B shows two adjacent conductor patterns 41. As shown in FIG. 2B, the conductor pattern 41 extends from the probe unit 20 to the connection terminal 431 connected to the interface unit 311. Up to this point, it is possible to set a continuous curve (for example, a spline curve) connecting a plurality of points, and to continuously increase the conductor pattern width Wp and the conductor pattern pitch Pp. As described above, by increasing the conductor pattern width Wp and the conductor pattern interval Pp stepwise or continuously, a pattern having a small electric resistance is realized, and therefore, there is an effect that the reflection loss or the like in a high-frequency signal is easily reduced.

  The wiring film 4 is obtained by forming the conductive pattern 41 of a conductive metal (for example, copper, nickel, or an alloy thereof) on the insulating film 40. The method of manufacturing the conductive pattern 41 is a method of manufacturing a conductive metal sheet by etching or laser processing, or a method of forming a pattern made of a conductive metal material on an electrode substrate, which will be described later, by electroforming. There is a method of attaching.

  FIG. 3 is a partial detailed view of the wiring film 4 in FIG. FIG. 3A shows the probe unit 20, which is an example in which four single-row probe assemblies 211 to 214 are arranged to face each other. The single-row probe assemblies 211 and 212 are arranged such that the probe tip rows 21-1 and 21-2 formed by the respective probe tip portions 21 are linear in the X direction on the wiring film 4 plane (XY plane). The single-row probe assemblies 213 and 214 are arranged such that the probe tip rows 21-3 and 21-4 are linear in the Y direction on the XY plane, and constitute a substantially quadrilateral. At this time, as described later with reference to FIG. 4, the probe tips 21 are installed so that the respective arrangement intervals are the same as the arrangement intervals in the XY plane coordinates of the electrode terminal pads 51 of the target semiconductor chip 5 to be inspected. You. That is, in the probe unit 20, the number of probes and the pitch between probes are determined based on the electrode terminal pad arrangement of the target semiconductor to be inspected.

  In FIG. 2, reference numeral 45 denotes a relay wiring film. S1-1 and the like indicate the terminal numbers of the external connection terminals 311. In the terminal numbers S “m” to “n”, “m” indicates a column number of the external connection terminal 311, and “n” indicates a number of the arbitrary column of the external connection terminal 311 from the inside of the main substrate 3. Show. Rows S1 to S17 show an example in which the probes of the probe assembly 210 are sequentially assigned to S1-1 to S17-5.

  FIG. 3B is a detailed view including the relay wiring film 45. The relay wiring film 45 has a configuration in which a plurality of wiring patterns 452 and relay connection terminals 451 are provided on both ends of the wiring pattern 452 on one insulating film 453.

  The conductor patterns 41-2 to 41-5 are sequentially connected to the terminal numbers S18-2 to 18-5 of the external connection terminals 311. The conductor pattern 41-1 is connected to the terminal number S21-1. Should be. At this time, in the relay wiring film 45, the relay connection terminal 451a installed at one end of the wiring pattern 452 and the connection terminal 435a of the conductor pattern 41-1 were connected, and installed at the other end of the wiring pattern 452. The relay connection terminal 451b and the connection terminal 435b communicating with the terminal number S21-1 were connected. By installing the relay wiring film 45, an efficient wiring means when the conductor patterns cross each other can be provided.

  FIG. 4 illustrates the positional relationship between the probe tip rows 21-1 to 21-4 in the probe assemblies 211 to 214 and the electrode terminal pads 51 in the semiconductor chip 5 to be inspected.

  In the probe tip rows 21-1 to 21-4 installed on the XY plane shown in FIG. 3A, a straight line on the conductor pattern at a fixed distance d from a linear axis connecting the probe tips is centered. FIG. 4 shows a state in which the single-row probe assemblies 211 to 214 are bent in a direction substantially perpendicular to the XY plane as axes, thereby changing the direction of the probe tip rows 21-1 to 21-4. Since the probe tip rows 21-1 to 21-4 come into contact with the terminals on the semiconductor chip 5 to be inspected in a direction substantially perpendicular to the plane of the main substrate 3, at least the probe tip 21 and the probe deforming section 22 and a part or all of the probe conductor pattern portion 23 are arranged in a direction substantially perpendicular to the plane of the main substrate 3.

  In FIG. 4, the single-row probe assembly 211 includes one pad row 51-1 of the electrode terminal pad 51, the single-row probe assembly 212 includes a pad row 51-2, and the single-row probe assembly 213. In order to correspond to the pad row 51-3 and the single-row probe assembly 214 to the pad row 51-4, the arrangement interval of the probe tip rows 21-1 to 21-4 in the XY plane coordinates is set as a target object. The arrangement interval of the inspection semiconductor electrode terminals was the same as the arrangement interval in the XY plane coordinates. Thereby, a so-called peripheral array probe assembly 251 corresponding to the array of the electrode terminal pads 51 can be formed.

  FIG. 5 shows a multilayer wiring film configuration in which a plurality of the probe assemblies 210 are stacked. In FIG. 5, two single-row probe assemblies are further laminated on the single-row probe assembly 211 to form three-row single-row probe assemblies 211-1, 211-2, and 211-3. FIG. 6 shows the effect of this configuration.

  In FIG. 6, reference numeral 52 denotes a semiconductor to be inspected having four electrode terminal pad rows 52-1 to 52-4. This example is an electrode terminal pad arrangement often found in a liquid crystal drive (LCD driver) IC or the like. The electrode terminal pad row 52-4 is an electrode terminal pad row that controls output to a liquid crystal pixel, whereas the electrode terminal pad row 52-1 to 52-3 is an electrode terminal pad row that controls output to a liquid crystal pixel. A few hundreds of electrode terminal pad rows arranged in a narrow pitch of several tens μm are installed in two or three stages, and the respective electrode terminal pad rows are arranged in parallel in a positional relationship mutually shifted by a pad width p substantially. In other words, a so-called staggered arrangement is formed to cope with the narrow pitch multi-pin output signal to the liquid crystal screen.

  The lower part of FIG. 6 shows the mutual positional relationship of the probe assemblies 211-1 to 211-3 in the X direction. A dummy pattern portion 270 is provided in each of the probe assemblies 211-1 to 211-3, and reference holes 271 and 272 are provided in the dummy pattern portion 270. The dummy pattern unit 270 may be manufactured on the same surface of each of the probes 211-1 to 211-3 by the same manufacturing method using the same metal material.

  By setting the distances from the left ends of the probes of the probe assemblies 211-1 to 211-3 to the reference holes 271 as Xr0 + 2p, Xr0 + p, and Xr0, respectively, the probe assemblies 211-1 to 211-3 are provided. And the relative positional relationship in the X direction between the inter-probe distances and the inter-pad distances of the electrode terminal pad rows 52-1 to 52-3.

  FIG. 7 shows a means for positioning the probe assemblies 211-1 to 211-3 and 211-4 in the Y direction. The spacers 280-1, 280-2, and 280-3 are inserted into the electrode terminal pad rows 52-1 to 52-4 so as to match the distances between the respective pad rows, Yr 1, Yr 2, and Yr 3. A fixing pin 282 is passed through each of the reference holes 271 and 272 of -1 to 211-3, and is fixed to the main board 3 together with the housing 260 by a fixing screw 281.

  Thus, for the electrode terminal pad rows 52-1 to 52-4, for example, the tip of the probe assembly 211-1 is in the pad row 52-1 and the tip of the probe 211-2 is in the pad row 52-1. -2, the tip of the probe 211-3 can contact the pad row 52-3 and the tip of the probe 211-4 can contact the pad row 52-4 with high accuracy.

  FIG. 8 shows a means for constructing a grid-arranged probe assembly 254 having a multilayer wiring film structure in which a plurality of the probe assemblies 210 are stacked. Reference numeral 54 denotes a grid-type electrode terminal pad array, which is composed of an 8 × 8 grid-like pad row composed of pad rows 54-11 to 54-88, the pitch in the X direction being Px and the pitch in the Y direction being Py.

  The probe assembly 254 corresponding to the electrode terminal pad arrangement 54 includes eight single-row probe assemblies 215-1 to 215-8, and each of the probe assemblies 215-1 to 215-8 has 8 For example, the probe assembly 215-1 has probe tips 21-11 to 21-18 at a pitch of Px.

  Further, the probe assemblies 215-1 to 215-8 are provided at Py intervals by a spacer (not shown) for determining the interval between the probe assemblies, similarly to the method described with reference to FIG. The probe assembly 215-1 corresponds to the pad rows 54-11 to 54-18, the probe assembly 215-2 corresponds to the pad rows 54-21 to 54-28, and similarly the probe assembly 215-3. 215-8 correspond to the rows of the pad rows 54-31 to 54-81.

  With the probe assembly 254 configured as described above, all of the probe tips 21-11 to 21-88 can contact all of the pads 54-11 to 54-88 at once with high accuracy. .

  One ends (not shown) of the conductor patterns 41-11 to 41-18 and the like continuing from the probe aggregates 215-1 to 215-8 form the connection terminals 431 and the like, and the connection portions of the main substrate 3 are formed. It is possible to connect to

  FIG. 9 shows a constitutional means of a probe assembly for simultaneously inspecting a plurality of semiconductor chips 53-1 to 53-3 to be inspected on a semiconductor wafer. In semiconductor wafer inspection, a method of simultaneously inspecting a plurality of semiconductor chips to be inspected is often employed as an effective means for shortening the inspection time.

  In FIG. 9, reference numeral 216-1 denotes a probe assembly formed by a conductor pattern formed on one insulating film, and 216-2 denotes a probe assembly formed by a conductor pattern formed on another insulating film. The multilayer wiring film is formed by laminating. The probe tip 21-21 to 21-23 of the probe assembly 216-1 includes a row 53A including all the electrode terminal pads of one of the semiconductor chips 53-1 to 53-3 to be inspected, and the probe assembly 21A. The probe tips 21-21 to 21-23 of 216-2 are stacked so as to match the row 53B including all the other electrode terminal pads of the semiconductor chips 53-1 to 53-3 to be inspected. By this means, a probe assembly capable of contacting a plurality of electrode terminal pads of the semiconductor to be inspected can be installed on the same wiring film, and a high-precision probe array can be manufactured collectively.

  FIG. 10 shows a wiring film 4-10 including a probe assembly capable of simultaneously inspecting a plurality of semiconductor chips to be inspected described in FIG. The method shown in FIG. 9 is an example in which the conductor patterns of the probe assemblies 216-1 and 216-2 extend in the same direction. However, the method of FIG. An example in which the conductor pattern of No. 216-2 extends in the opposite direction is shown. According to this means, it is possible to form a wiring film that can contact the electrode terminal pad rows of the semiconductor chips 53-1 to 53-4 in one row with one wiring film.

  FIG. 11 shows a constitutional means of a probe assembly for simultaneously inspecting all the semiconductor chips to be inspected on the semiconductor wafer 50. In FIG. 11, reference numerals 53-11 to 53-29 denote semiconductor chip arrays to be inspected in the X direction. For example, the wiring film corresponding to all the electrode terminal pads of the semiconductor chip row 53-11 at the center of the semiconductor wafer is designated as 4-11, and the electrode terminal pad row of the semiconductor chip row 53-11 is placed on one insulating film. And a conductor pattern extending in the + Y direction. Similarly, the wiring films corresponding to all the electrode terminal pad rows of the semiconductor chip rows 53-12 to 53-20 are referred to as 4-12 to 4-20 to constitute a multilayer wiring film.

  On the other hand, wiring films corresponding to all the electrode terminal pad rows of the semiconductor chip rows 53-12 to 53-29 are designated as 4-21 to 4-29 (only 4-21 and 4-22 are shown). A multilayer wiring film is constituted by a probe portion that matches the pitch in the X direction of the electrode terminal pad row and a conductor pattern extending in the −Y direction.

  According to this means, a probe assembly for simultaneously inspecting all the semiconductor chips to be inspected on the semiconductor wafer 50 can be manufactured at low cost with a plurality of wiring films. The other end of the probe portion of each of the wiring films 4-11 to 4-29 is connected to a connection terminal on the main board 3 or connected to an external connection terminal by a connector independently of the main board 3. It is possible to do.

  In this example, as shown in the flash memory IC inspection, an example is shown in which the electrode terminal pad row in one semiconductor chip is one row on one side. However, even if the electrode terminal pad row in one semiconductor chip is plural rows, This can be realized by increasing the number of corresponding wiring films.

  FIG. 12 is a diagram illustrating the configuration of a high-frequency signal probe assembly and a wiring pattern sheet. 12, a high-frequency signal probe assembly 220 includes a signal layer probe assembly 221, ground layer probe assemblies 222 and 223, and insulating films 40-2 and 40-3. In the signal layer probe assembly 221, probes 201-1 to 201-6 are provided on an insulating film 40-1, and in this example, the probes 201-1, 201-2, 201-4, and 201-5 are provided. An example is shown in which the probes 201-3 and 201-6 are used for grounding, respectively, for the signal lines.

  On the other hand, the ground layer probe assembly 222 integrally forms the ground layer probes 202-1 to 202-4 from the copper foil sheet 410, and includes all the grounding probes including the ground layer probes 202 to 1 to 202-4. The probe assembly 222 is used for grounding.

  Similarly, the ground layer probe assembly 223 similarly forms the ground layer probes 203-1 to 203-4 from the copper foil sheet 410, and includes all the ground layer probes 203-1 to 203-4. The ground layer probe assembly 223 is used for grounding.

  Also, the signal layer probe assembly 221 continuously installs the conductor patterns 42-1 to 42-6 installed on the wiring film, and connects the conductor patterns 42-1, 42-2, 42-4, and 42-5. The conductor patterns 42-3, 42-6 were used for signal lines, and the conductor patterns 42-3, 42-6 were used for grounding.

  When the wiring films including the signal layer probe assembly 221 and the ground layer probe assemblies 222 and 223 configured as described above are overlapped, the result is as shown in FIG. As shown in FIG. 13A, the ground layer probes 202-1 and 203-1 and the ground layer probes 202-2 and 203-2 are located on both sides of the signal layer probes 201-1 and 201-2. And make them in advance. Further, the ground layer probes 202-3 and 203-3 and the ground layer probes 202-4 and 203-4 are previously arranged and manufactured at positions corresponding to the X direction positions of the signal layer probes 201-3 and 201-6. I do. Each probe of the high-frequency signal probe assembly 220 configured as described above comes into contact with a position indicated by a black circle in the electrode terminal pad rows 53-31 to 53-38 in FIG. .

  The effect of the structure of the high-frequency signal probe assembly 220 will be described with reference to the cross-sectional view taken along the line AA of FIG. The cross section AA (1) shows the signal layer probes 201-1 and 201- of a portion composed of the probes 201-1, 201-2, 202-1, 202-2, 203-1 and 203-2. 2 is a sectional view of FIG. In this example, by appropriately selecting the width w, the thickness t, the distance c, and the distance h between the copper foil sheets 410 of the signal layer probes 201-1 and 201-2, the characteristic impedance of the differential strip line is obtained. Can be provided in the wiring structure.

  Also, the cross section AA (2) shows the signal layer probes 201-3 to 201-3 of the portion composed of the probes 201-3 to 201-6, 202-3, 202-4, 203-3, and 203-4. FIG. 20 shows a cross-sectional view at 201-6. In the present embodiment, by appropriately selecting the width w, the thickness t, the intervals c1, c2, and the distance h between the copper foil sheets 410 of the signal layer probes 201-3 to 201-6, the coplanar differential strip is used. It is possible to provide a wiring structure in which the characteristic impedance of the line is secured.

  FIG. 13B shows a high-frequency wiring film 420 including the high-frequency signal probe assembly 220 described in FIG. 13A. In FIG. 13B, the signal line wiring patterns 42-1 and 42-2 or 42-4 and 42-5 continuously extended from the high-frequency signal probe assembly 220 are used for signal lines on the main board 3. It is soldered (308) to the connection terminal 307 and connected to another circuit or the like via the through hole 303 or the like. The wiring patterns 42-3 and 42-6 for grounding and the copper foil 410 forming the grounding layer are soldered (308) to the grounding connection terminals 317 on the main substrate 3.

  As described above, according to the high-frequency signal probe assembly 220 or the high-frequency wiring film 420 structure, the impedance-matched wiring with few discontinuous points from the probe tip to the connection portion on the main board can be easily configured. And a structure suitable for a high-frequency signal can be obtained.

  FIG. 14 is a diagram illustrating a configuration of a wiring film including a probe assembly for measuring a minute current. In FIG. 14, a probe assembly 230 for measuring a small current is provided with signal line probes 205-1 to 205-8, and grounded in parallel near both sides of each of the signal line probes 205-1 to 205-8. Patterns 206a and 206b are provided. For example, the ground patterns 206-1a and 206-1b are provided on both sides of the signal line probe 205-1.

  On the wiring film, conductor patterns 46-1 to 46-8 are provided, one end of which is connected to the signal line probes 205-1 to 205-8, respectively, and the other end is, for example, a through hole 46-11. To a main board (not shown). Further, grounding patterns 47-1 to 47-8 are provided in the vicinity of substantially the entire circumference of each of the conductor patterns 46-1 to 46-8, and one ends thereof are connected to the grounding patterns 206a and 206b, respectively. . The ground patterns 47-1 to 47-8 are connected to ground patterns such as a main board (not shown) through through holes 47-11. The through hole 47-11 can be connected to the ground pattern on the main substrate by means such as thermocompression bonding of a bump provided on the back surface of the ground pattern 47-1.

  As described above, according to the wiring film structure including the microcurrent measurement probe assembly 230, the leakage current between the adjacent signal lines can be reduced, for example, as in a parametric test in an initial step of semiconductor wafer inspection. In addition, a probe card having a wiring structure with extremely small leakage current when measuring a very small current can be realized.

  FIG. 15 is a view for explaining a method and configuration for forming the conductor pattern 41 made of two or more metal materials by electroforming. In FIG. 15A, reference numeral 490 denotes a conductive substrate which is an electrode for electroforming, on which a first conductive metal 411 is first formed, and a first conductive metal 411 is formed on the first conductive metal 411. Then, a second conductive metal 412 is formed.

  In order to form the wiring film 4, the first and second conductive metals 411 and 412 are removed from the electrode 490 and attached on the insulating film 40, as shown in FIG. It is.

  In the probe card, the probe must be made of a metal material having a sufficient contact force for an appropriate stroke in order to maintain stable electrical contact with the semiconductor electrode pad. On the other hand, the wiring pattern on the probe card including the probe is desirably a metal material having excellent conductivity in order to reduce electric resistance. Further, a probe and a wiring pattern that control a power supply line and the like must be formed of a conductor having a sufficient thickness.

  As shown in FIG. 15B, in the probe 20 having the probe deformation portion 22 of the conductor pattern 41, only the first conductive metal 411 made of a material having a sufficient elastic deformation region is used. The second conductive metal 412 made of a material having good conductivity is laminated on other portions of the conductive pattern 41 (mainly, the portions constituting the wiring pattern 42). Examples of the first conductive metal 411 include a beryllium copper alloy, a nickel-cobalt alloy, and an iron-nickel alloy. Further, as an example of the second conductive metal 412, copper or gold can be used. With this configuration, it is possible to form the conductor pattern 41 having excellent probe characteristics in the probe section 20 and excellent conductivity in the wiring pattern 42.

  FIG. 15C is a view showing a method of increasing the tip thickness Tp of the probe tip portion 21. The second conductive metal 412 forms the area of the probe portion 20, and thereafter, It is possible to control the thickness up to Tp by etching.

  Further, FIG. 15D is a diagram showing a configuration of the third conductive metal 413 having both the spring characteristics and the conductivity, and the third conductive metal 413 is provided over the entire area of the conductive pattern 41. It is also possible to form the film and then control it to a desired thickness by etching. As an example of the third conductive metal 413, an iron-nickel alloy or the like can be used.

  FIG. 16 shows an embodiment for making the spring characteristics of the probe deforming portion 22 more effective. FIG. 16A shows that at least the probe distal end portion 21 and the probe deforming portion 22 are inclined by θ ° with respect to a vertical axis (Z axis) by an angle setting spacer 263 in advance to form the insulating film 40. This is installed in the housing 261 through the intermediary. Thus, after the probe tip 21 starts to contact the electrode pad 55, the deformation of the probe deforming portion 22 can be made more reliable.

  FIG. 16B shows a state in which the probe deforming section 22 has been deformed in advance and then installed in the housing 262. Similarly, after the probe tip 21 starts to contact the electrode pad 55, the deformation of the probe deforming portion 22 can be more reliably performed.

  FIGS. 16C to 16D are views showing the deformation operation of the probe tip 21 due to the eccentric load. FIG. 16C is a diagram showing a state before contact with the electrode pad 55. The conductor of the probe 20 constituting the probe unit 20 and the insulating film 40 are fixedly installed on the housing 264 via the insulating film 40-6. The insulating film 40 is exposed from the housing 264 by the length of L2 from the housing 264, and the conductor of the probe unit 20 is exposed from the insulating film 40 by the length of L1. When the conductor of the probe unit 20 and the insulating film 40 are attached to each other and considered to be integrated, the electrode pad 55 and the probe center axis Cp passing through the center of gravity obtained by combining the L1 and L2 portions of the probe unit 20 are considered. The center axis C21 of the probe tip passing through the contacting probe tip 21 is eccentric by ΔCp. Therefore, when the probe tip 21 starts to contact the electrode pad 55, the L1 and L2 portions of the probe unit 20 operate as eccentric loads.

  The deformation operation of the probe tip 21 due to the eccentric load will be described with reference to FIG. When the probe tip 21 comes into contact with the electrode pad 55, a counterclockwise rotational moment acts on the probe tip 21 because it is eccentric by ΔCp. Accordingly, when the contact with the electrode pad 55 progresses, the probe tip portion 21 is deformed in the −Y direction, and the L1 and L2 portions of the probe portion 20 are deformed as the probe deforming portion 22 as illustrated. .

  When the contact with the electrode pad 55 further proceeds, the probe tip 21 is further deformed in the −Y direction, and the distance Sc between the probe tip central axis C21 and the probe tip 21, that is, the scrub length increases. Then, there arises a problem that the probe tip 21 comes off the electrode pad 55. To prevent this, as shown in FIG. 16 (e), the housing 264 a in the direction of deformation of the probe tip 21 (left side in the figure) is extended to the vicinity of the probe tip 21, thereby making the scrub more than necessary. It is possible to suppress the operation.

  Generally, the probe card is installed in a prober device together with the semiconductor wafer to be inspected, and the inspection is performed. The inside of the prober device is in a relatively high temperature state (for example, around 85 ° C.) at the time of inspection, so that the semiconductor to be inspected and the probe card are also in an environment of the same temperature. In addition, the commercialized semiconductor chips are often used at high operating temperatures (for example, 100 ° C. or higher), and inspections in accordance with actual environmental temperatures are also required. At this time, the problem as a probe card is that the tip of the probe must be able to follow the positional fluctuation between the electrode pads due to the thermal expansion of the semiconductor due to the temperature change.

  FIG. 17 shows an example of a behavior due to thermal expansion of the probe unit 20 in the probe assembly 210 according to the embodiment of the present invention. In the probe assembly 210 shown in FIG. 17C, both ends of the probe assembly 210 are moved at least in the X direction to the housing 265 by the fixing pins 282 with reference to the reference hole 273 provided in the dummy pattern portion 270. A description will be given of the case where the fixing is performed.

  In FIG. 17A, when the semiconductor chip 5 to be inspected having the electrode pad row 53 is at normal temperature (i) (for example, at 25 ° C.), the distance between the electrode pads # 1 and # 16 is Lt0, and at high temperature (ii). Assuming that the electrode pad # 16 moves Δt1 from a position at normal temperature with respect to the electrode pad # 1 with respect to the electrode pad # 1 due to thermal expansion of the semiconductor chip 5 to be inspected (for example, at 125 ° C.), the electrode pads # 1- # The distance between 16 is Lt1 = Lt0 + Δt1.

  FIG. 17B shows the behavior of the probe tip 21 of the probe assembly 210 due to the temperature change. As shown in FIGS. 17B and 17I, the distance between # 1 and # 16 of the probe tip 21 is set as Lp0 so as to match the distance Lt0 between # 1 and # 16 of the electrode pad 53 at normal temperature. The behavior of the probe tip 21 at a high temperature in the probe assembly 210 described above will be described with reference to FIGS.

The insulating film 40 of the probe assembly 210 is generally made of a material such as polyimide. The linear expansion coefficient of polyimide is about 40 to 54 (× 10 ⁻⁶ / ° C.), and silicon as a material of a semiconductor wafer is used. Has a linear expansion coefficient of about 20 times that of about 2.5 (× 10 ⁻⁶ / ° C.). Therefore, the tip movement amount Δp2 of the probe unit 20 mounted on the insulating film 40 alone is much larger than the movement amount of the electrode pad 53 by # 16. Further, as shown in FIGS. 17 (b) and (ii), when both ends of the probe section 20 are fixed to the housing 265 by the fixing pins 282, the amount of movement due to thermal expansion of the housing 265 (right end of the housing) In this case, the probe section 20 is distorted together with the insulating film 40, and the probe tip comes off the electrode pad.

  FIG. 18 is a diagram for explaining a probe assembly having a heat shrink following structure according to the embodiment of the present invention. FIG. 18A shows a distance between # 1 and # 16 of the electrode pads 53 of the semiconductor chip 5 having the electrode pad rows 53 with respect to a temperature change between a normal temperature and a high temperature, similarly to FIG. It shows the relationship (Lt1 = Lt0 + Δt1). FIGS. 18B and 18C show the structure of the probe assembly 256 and the wiring pattern continuing to the probe unit 20 with respect to a temperature change between normal temperature and high temperature. 42 shows the behavior of the second embodiment.

  In FIGS. 18B and 18C, reference numeral 240 denotes a probe assembly constituting the heat shrinkable probe assembly 256, which has the probe unit 20 and the wiring pattern 42 on an insulating film 40-4. 266a and 266b are supports, and the probe assembly 240 is mechanically sandwiched together with the insulating film 40-5, and fixed by the fixing pins 282. As shown in FIG. 18 (c), the insulating films 40-4 and 40-5 are provided with a stress relaxation slit 404 between each probe of the probe unit 20 to provide a plurality of probes (see FIG. 18). The slit 405 for holding the insulating film is provided at every eight in the example. On the other hand, the supporting body 266a or 266b is provided with a protrusion 266s, and each is fitted with the insulating film holding slit 405, and the position of the insulating film holding slit 405 to be restrained by the protrusion 266s in at least the X direction. The size is set.

  The operation of the heat shrinkable probe assembly 256 having the above configuration will be described with reference to FIG. The distance Lp0 between # 1 and # 16 of the probe tip portion 21 in the probe assembly 240 is set to match the distance Lt0 between # 1 and # 16 of the electrode pad 53 at normal temperature (i). When the temperature rises and the temperature is high (ii), the supports 266a and 266b expand and move in the X direction (movement Δeh2 as the right ends of the supports), and the protrusions 266s provided on the supports 266a and 266b Since the slits 405 are fitted with the slits 405 for holding the insulating film, the slits 405 for holding the insulating film restrain the insulating films 40-4 and 40-5 in the X direction, and the support members 266a and 266b move in the X direction. (The Δep2 movement as an insulating film).

  On the other hand, the internal distortion due to the thermal expansion of the polyimide as described above with reference to FIG. 17B is caused by the mechanical pressing force of the supports 266a and 266b against the probe unit 20 and the distance between the probes of the probe unit 20. The stress relaxation slits 404 installed in each of the above-described components facilitate the generation of the bending 40b between the probes, and can alleviate internal stress due to thermal expansion. The wiring pattern 42 does not need high-precision position accuracy in the X direction as in the probe unit 20, and thus does not need to be restricted in the X direction, and the expansion Lp 2 due to thermal expansion of the wiring pattern 42 occurs. There is no effect on the probe unit 20.

With the configuration of the probe assembly 256 as described above, the X-direction position of the probe tip 21 can follow the X-direction displacement accompanying the thermal expansion of the supports 266a and 266b. it can. Further, as a material of the supports 266a and 266b, an iron-nickel alloy whose linear expansion coefficient is close to the linear expansion coefficient of the semiconductor silicon wafer to be inspected (nickel content: 36%: invar, linear expansion coefficient about 2 (× 10 ⁻⁶ / ° C.)) is most appropriate.

In wafer inspection of a memory IC or the like, it is common to inspect a plurality or all of the chips on a semiconductor wafer simultaneously in order to reduce the inspection cost. For this purpose, the probe corresponding to the distance between the electrode pads corresponding to a wide range of the entire semiconductor wafer (for example, the approximate diameter corresponding to a wafer having a diameter of 300 mm) must follow the movement amount of the electrode pads. When the iron-nickel alloy (nickel content: 36%: Invar) is applied, when the distance between the electrode pads is 300 mm and the relative temperature change is 100 ° C., the electrode pads on the semiconductor silicon wafer (linear expansion coefficient about 2.5 (× 10 ⁻⁶ / ° C.)) is about 0.075 mm, while the corresponding probe can have a maximum movement of about 0.06 mm, which is a typical electrode pad width dimension of 50 to 80 μm. Can be sufficiently followed. Therefore, the configuration of the probe assembly 256 following the heat shrinkage is very effective for semiconductor wafer inspection over a wide area.

  According to the embodiment described above, according to the probe card of the present invention, it is a wiring film in which a plurality of conductive conductor patterns are provided on one insulating film, and the conductive film is provided on the wiring film plane (XY plane). Probe assembly alignment means at one end of the pattern, direction change means of the probe assembly, external terminal connection means at the other end of the conductor pattern, and conductor pattern expansion between the probe assembly and the external connection terminal Means for testing semiconductor chips with multiple rows of narrow pitches and multiple pins, simultaneous testing of multiple semiconductor chips, testing of semiconductor chips with high-frequency signal paths, testing in a wide temperature environment, etc. Probe card that realizes a simple probe card and solves the problem of connection between probe and wiring. It is intended to provide.

  The present invention can be applied to a probe card used for electrical inspection of a semiconductor having a multi-pin narrow-pitch inspection terminal including a high-frequency band signal on a semiconductor wafer.

DESCRIPTION OF SYMBOLS 1 Probe card 2 Probe assembly 20 Probe part 21 Probe tip parts 21-1-4, 21-11-88, 21-21, 22 Probe tip row 22 Probe deformation part 23 Probe conductor pattern parts 201-1, 2, 4 , 5 signal line probe 201-3,6 grounding probe 202-1,4 grounding probe 203-1,4 grounding probe 205-1-8 signal line probe 206-1-8 grounding pattern 210 probe assembly 211 , 212, 213, 214 Single row probe assembly 211-1-3 Single row probe assembly 215-1-8 Single row probe assembly 216-1, 2 Single row probe assembly 220 High frequency signal probe assembly 221 signal Layer probe assembly 222, 223 Ground layer probe assembly 230 Microcurrent measurement probe assembly 240 Type probe assembly 251 Peripheral array probe assembly 252 Staggered array probe assembly 254 Grid array probe assembly 256 Heat shrinkable probe assembly 260, 261, 262, 264, 265 Housing 263 Angle setting spacer 266a, 266b Support 266s Projecting portion 270 Dummy pattern portion 271, 272, 273 Reference hole 280, 280-1 to 3 Spacer 281 Fixing screw 282 Fixing pin 3 Main substrate 31 Surface layer (top surface)
32 surface layer (lower surface)
35 Intermediate layer 301 Interface unit 311 External connection terminal 312 Tester connection terminal 302 Electric terminal 303 Through hole 305 Electric component 306 Connector 307, 317 Electric terminal 308 Solder 311 External connection terminal 4 Wiring film 4-10, 4-11-22 Wiring film 40, 40-1-6 Insulating film 40b Flexures 41, 41-1-5, 41-11-18 Conductive pattern 42 Wiring pattern 42-1-6 Wiring pattern 45 Relay wiring film 46-1-8 Conductive pattern 46-11-18 Through-holes 47-1-8 Grounding patterns 47-11-18 Grounding through-holes 401, 402 Notch 404 Stress relaxation slit 405 Insulating film holding slit 410 Copper foil 411 First conductive metal 412 Second conductive metal 413 Third Conductive metal 420 high-frequency signal wiring film 431 to 434 connecting terminal 435 connection terminal (junction interconnection film)
436 Through hole 451 Connection terminal 452 Wiring pattern 453 Insulating film 490 Electrode plate 5 Semiconductor 50 to be inspected Semiconductor wafer 51 Electrode terminal pad 51-1 to 4 Electrode terminal pad row 52 Semiconductor to be inspected 52-1 to 4-4 Electrode terminal pad row 53 Electrode Terminal pad rows 53A, B Electrode terminal pad rows 53-1-4 Semiconductors under test 53-11-22 Semiconductor rows under test 54 Semiconductors under test 54-11-88 Electrode terminal pad rows 55 Electrode terminal pads

Claims (36)

A probe card having a probe group in contact with a semiconductor terminal to be inspected and an interface unit with an external inspection device is composed of a wiring film in which a plurality of conductive conductor patterns are provided on one insulating film, and the wiring film plane (XY) On the plane)
Probe assembly alignment means at one end of the conductor pattern,
Turning means of the probe assembly,
External terminal connection means at the other end of the conductor pattern,
Conductive pattern extending means between the probe assembly and the external connection terminal,
A probe card comprising: A part or all of the probe tips in the probe assembly are composed of a single row probe assembly arranged on an arbitrary straight line in the wiring film plane (XY plane),
2. The probe card according to claim 1, wherein an arrangement interval in the XY plane coordinates of the probe tip is the same as an arrangement interval in the XY plane coordinates of the target semiconductor electrode terminal to be inspected. In the wiring film plane (XY plane), there is provided a second single-row probe assembly which is linearly arranged substantially parallel to the first single-row probe assembly,
The arrangement interval in the XY plane coordinates of a part or all of the probe tips of the first and second single-row probe assemblies is the same as the arrangement interval in the XY plane coordinates of the target semiconductor terminal to be inspected. The pro-card according to claim 1, wherein In the wiring film plane (XY plane), a second single-row probe assembly, which is linearly arranged substantially parallel to the first single-row probe assembly, and the first single-row probe assembly. A probe assembly that forms a substantially quadrilateral by a third or fourth single-row probe assembly arranged linearly in a perpendicular direction,
The arrangement interval in the XY plane coordinates of a part or all of the probe tips of the first to fourth single-row probe assemblies is the same as the arrangement interval in the XY plane coordinates of the target semiconductor terminal to be inspected. The pro-card according to claim 1, wherein In one or all of the single-row probe assemblies on the XY plane, the single-row probe assembly is moved with respect to the XY plane, with a straight line on the conductor pattern at an arbitrary distance from a linear axis connecting the probe tips as a central axis. 2. The probe card according to claim 1, wherein the probe assembly is turned in a substantially vertical direction so as to change the direction of the probe assembly. A probe assembly in which one or a plurality of the single-row probe assemblies are combined, wherein the arrangement intervals in the XY plane coordinates of some or all of the probe tips of the probe assembly are the target semiconductor electrode terminals to be inspected. 2. The probe card according to claim 1, wherein the arrangement interval is the same as the arrangement interval in the XY plane coordinates. 2. The probe card according to claim 1, wherein a part or the entirety of said probe in said probe assembly is provided in advance with respect to a vertical direction of said wiring film. 2. The probe card according to claim 1, wherein said probe in said probe assembly is provided with a deformation portion in advance. In the probe of the probe assembly, there is an eccentricity between a central axis passing through a contact portion of the probe tip with the semiconductor terminal to be inspected and a central axis passing through the center of gravity of the probe deforming portion. The pro-card according to claim 1, wherein 2. The probe card according to claim 1, wherein one end is formed as one or more arbitrary probes in the single-row probe, and the other end is formed as one or more external connection terminals to form the conductor pattern. The probe card according to claim 1, wherein the external connection terminal in the conductor pattern is a connector device. 2. The probe card according to claim 1, wherein the external connection terminals in the conductor pattern are conductor pads that enable soldering. 2. The probe card according to claim 1, wherein the external connection terminal in the conductor pattern is a through hole transmitting to a back surface of the insulating film. 2. The probe card according to claim 1, wherein an arrangement interval of some or all of the external connection terminals in the XY plane coordinate in the conductor pattern is the same as an arrangement interval of the interface unit in the XY plane coordinate. 3. 2. The probe card according to claim 1, wherein the conductor pattern is formed of a linear assembly, and the pitch between the conductor patterns or the conductor pattern width increases stepwise from the probe to the external connection terminal. . It is assumed that a part or the whole shape of the conductor pattern is a continuous curve (for example, a spline curve), and that the pitch between the conductor patterns or the width of the conductor pattern continuously increases from the probe to the external connection terminal. 2. The professional card according to claim 1, wherein: 2. The device according to claim 1, further comprising means for arranging two or more probe assemblies by a multilayer wiring film in which one or a plurality of the wiring films are laminated on a part or all of the one wiring film. Pro card. The multilayer wiring film, wherein in the probe assembly two or more single-row probe assembly laminated,
The vertical or Z-direction positions of some or all of the probe tips are the same, and the arrangement intervals of the probe tips in the XY plane coordinates are the same as the arrangement intervals of the target semiconductor electrode terminals to be inspected in the XY plane coordinates. 2. The pro-card according to claim 1, wherein: The multilayer wiring film, wherein two or three or more of the single-row probe assemblies are stacked, and a probe assembly in which probe tips of a plurality of the probe assemblies are closely arranged in parallel,
The tip of the first single-row probe assembly and the tip of the second single-row probe assembly are shifted from each other by a constant value in a linear direction (X direction) connecting the tip of the probe, and
Some or all of the probe tips have the same vertical (Z-direction) position, and the arrangement intervals of the probe tips in the XY plane coordinates are the same as the arrangement intervals of the target semiconductor electrode terminals to be inspected in the XY plane coordinates. The pro-card according to claim 1, wherein The multi-layer wiring film, wherein a probe assembly is formed by laminating N single-row probe assemblies, and proximately juxtaposing probe tips of first to N-th single-row probe assemblies at equal intervals or at arbitrary intervals. At
Some or all of the probe tips have the same vertical (Z-direction) position, and the arrangement intervals of the probe tips in the XY plane coordinates are the same as the arrangement intervals of the target semiconductor electrode terminals to be inspected in the XY plane coordinates. The pro-card according to claim 1, wherein 2. The probe card according to claim 1, wherein a dummy pattern having a positioning hole is provided near the tip of the probe on the same plane of the single-row probe assembly. A housing for fixing the vicinity of the probe of the single-row probe assembly in a plurality of the wiring films to form the probe assembly, the fixing holes having the same pitch as the positioning holes provided on the dummy pattern. 2. The pro-card according to claim 1, comprising: The housing that fixes the vicinity of the probe of the single-row probe assembly in the plurality of wiring films and forms the probe assembly,
By disposing a spacer having a predetermined thickness in the vicinity of the single-row probe assembly between the wiring films in the probe assembly, an arrangement interval in the XY plane coordinates of a part or the entire probe tip of the probe assembly 2. The probe card according to claim 1, wherein the means is the same as the arrangement interval of the target semiconductor electrode terminals to be inspected in the XY plane coordinates. A plurality of the probe assemblies are formed on one wiring film plane (XY plane), and the arrangement intervals of the tip ends of some or all of the probe assemblies in XY plane coordinates on the target semiconductor wafer are plural. 2. The probe card according to claim 1, wherein the arrangement intervals of the respective electrode terminals of the semiconductor device to be inspected in the XY plane coordinates are the same. All the conductor patterns in one wiring film are formed by electroforming a layer made of one or more metal materials or an alloy material of two or more metals on a conductive substrate. The probe card according to claim 1, wherein The probe card according to claim 1, wherein the probe including at least the probe deforming portion in the conductor pattern is made of a spring material that can be electrically connected. The probe card according to claim 1, wherein a plurality of the wiring films are overlapped with each other via an insulating layer made of a non-conductive sheet such as polyimide or a resin. The probe card according to claim 1, wherein a metal conductor sheet is attached to one or both surfaces of the wiring film via the insulating layer, and a ground pattern layer is provided. A dimensional relationship (for example, a conductor pattern width, a thickness, an insulating layer thickness, etc.) of a part or all of the conductor pattern of the wiring film, the insulating layer, and the ground pattern layer in the cross-sectional direction, and respective electric characteristics (for example, 2. The probe card according to claim 1, wherein the relative dielectric constant and the like are set in advance so as to have a predetermined characteristic impedance value. 2. The probe card according to claim 1, wherein a ground wiring pattern is provided in the vicinity of the conductor pattern via an air layer or an insulating layer made of polyimide or the like on the same plane of some or all of the conductor patterns. . A relay wiring film in which one or a plurality of conductor patterns and relay electrode terminals are provided at both ends of the conductor pattern on one insulating film, and one end of the relay electric terminals is mounted on the wiring film. The probe card according to claim 1, wherein the probe card is connected to the connection terminal, and the other end is connected to another connection terminal provided on the wiring film. In the single-row probe assembly of the wiring film, a support is installed in the probe placement direction (X direction) in parallel with the probe placement surface (XZ plane), and a part or the whole of the probe in the X direction position is provided. The probe card according to claim 1, wherein the probe card has means for following a displacement in the X direction accompanying thermal contraction of the support. 33. The probe card according to claim 32, wherein the support is pressed mechanically from one side or both sides of the single-row probe assembly in a direction of the probe arrangement surface (XZ plane). In the insulating film of the single-row probe assembly, a slit was provided between some or all of the probes to reduce transmission of internal stress of the insulating film to the probes due to thermal expansion of the insulating film. 33. The probe card according to claim 32, wherein: In the insulating film of the single-row probe assembly, a slit is provided between some or all of the probes, a protrusion is provided on the probe side of the support, and the slit and the protrusion are fitted together. 33. The probe card according to claim 32, wherein: 33. The probe card according to claim 32, wherein a linear expansion coefficient of the support is close to a linear expansion coefficient of the semiconductor wafer to be inspected.