KR101254067B1 - 절차 리턴 시퀀스들을 가속하기 위한 방법 및 시스템 - Google Patents

절차 리턴 시퀀스들을 가속하기 위한 방법 및 시스템 Download PDF

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Publication number
KR101254067B1
KR101254067B1 KR1020107012265A KR20107012265A KR101254067B1 KR 101254067 B1 KR101254067 B1 KR 101254067B1 KR 1020107012265 A KR1020107012265 A KR 1020107012265A KR 20107012265 A KR20107012265 A KR 20107012265A KR 101254067 B1 KR101254067 B1 KR 101254067B1
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South Korea
Prior art keywords
instruction
logic circuit
return
command
instructions
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KR1020107012265A
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English (en)
Korean (ko)
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KR20100087357A (ko
Inventor
마이클 윌리엄 모로우
제임스 노리스 디펜더퍼
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퀄컴 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
KR1020107012265A 2007-11-02 2008-10-31 절차 리턴 시퀀스들을 가속하기 위한 방법 및 시스템 Expired - Fee Related KR101254067B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/934,264 US8341383B2 (en) 2007-11-02 2007-11-02 Method and a system for accelerating procedure return sequences
US11/934,264 2007-11-02
PCT/US2008/081947 WO2009059100A1 (en) 2007-11-02 2008-10-31 A method and a system for accelerating procedure return sequences

Publications (2)

Publication Number Publication Date
KR20100087357A KR20100087357A (ko) 2010-08-04
KR101254067B1 true KR101254067B1 (ko) 2013-04-12

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Application Number Title Priority Date Filing Date
KR1020107012265A Expired - Fee Related KR101254067B1 (ko) 2007-11-02 2008-10-31 절차 리턴 시퀀스들을 가속하기 위한 방법 및 시스템

Country Status (6)

Country Link
US (1) US8341383B2 (enExample)
EP (1) EP2220556B1 (enExample)
JP (3) JP5301554B2 (enExample)
KR (1) KR101254067B1 (enExample)
CN (1) CN101884025B (enExample)
WO (1) WO2009059100A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7587580B2 (en) * 2005-02-03 2009-09-08 Qualcomm Corporated Power efficient instruction prefetch mechanism
US8341383B2 (en) * 2007-11-02 2012-12-25 Qualcomm Incorporated Method and a system for accelerating procedure return sequences
US9411590B2 (en) * 2013-03-15 2016-08-09 Qualcomm Incorporated Method to improve speed of executing return branch instructions in a processor
US9703948B2 (en) 2014-03-28 2017-07-11 Intel Corporation Return-target restrictive return from procedure instructions, processors, methods, and systems
GB2542831B (en) * 2015-09-30 2018-05-30 Imagination Tech Ltd Fetch unit for predicting target for subroutine return instructions
GB2551548B (en) 2016-06-22 2019-05-08 Advanced Risc Mach Ltd Register restoring branch instruction
US11055098B2 (en) * 2018-07-24 2021-07-06 Advanced Micro Devices, Inc. Branch target buffer with early return prediction
WO2021141760A1 (en) * 2020-01-06 2021-07-15 Quadric. Io, Inc Systems and methods for optimizing nested loop instructions in pipeline processing stages
US11586440B2 (en) * 2021-06-01 2023-02-21 International Business Machines Corporation Link stack based instruction prefetch augmentation

Citations (2)

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US5812813A (en) * 1996-07-29 1998-09-22 Integrated Device Technology, Inc. Apparatus and method for of register changes during execution of a micro instruction tracking sequence
US20030120906A1 (en) 2001-12-21 2003-06-26 Jourdan Stephan J. Return address stack

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EP0417916B1 (en) * 1989-09-13 1998-12-16 Digital Equipment Corporation Procedure state descriptor system for digital data processors
JPH06131250A (ja) * 1992-10-20 1994-05-13 Toshiba Corp データ処理装置
JPH07239782A (ja) * 1994-02-28 1995-09-12 Toshiba Corp 演算処理装置
JPH07281892A (ja) * 1994-04-06 1995-10-27 Hitachi Ltd 情報処理装置
JP2735523B2 (ja) * 1995-11-29 1998-04-02 日本電気アイシーマイコンシステム株式会社 プロシージャ・ステップ処理方法
US6151671A (en) * 1998-02-20 2000-11-21 Intel Corporation System and method of maintaining and utilizing multiple return stack buffers
US6094716A (en) 1998-07-14 2000-07-25 Advanced Micro Devices, Inc. Register renaming in which moves are accomplished by swapping rename tags
US6363473B1 (en) * 1999-04-01 2002-03-26 Compaq Information Technologies Group, L.P. Simulated memory stack in a stackless environment
JP3723019B2 (ja) * 1999-09-29 2005-12-07 富士通株式会社 サブルーチンリターン相当の命令の分岐予測を行う装置および方法
GB2358261B (en) * 2000-01-17 2004-06-09 Advanced Risc Mach Ltd Data processing with native and interpreted program instruction words
US6848044B2 (en) * 2001-03-08 2005-01-25 International Business Machines Corporation Circuits and methods for recovering link stack data upon branch instruction mis-speculation
US7017030B2 (en) * 2002-02-20 2006-03-21 Arm Limited Prediction of instructions in a data processing apparatus
US7996659B2 (en) * 2005-06-06 2011-08-09 Atmel Corporation Microprocessor instruction that allows system routine calls and returns from all contexts
US7478228B2 (en) * 2006-08-31 2009-01-13 Qualcomm Incorporated Apparatus for generating return address predictions for implicit and explicit subroutine calls
US8341383B2 (en) * 2007-11-02 2012-12-25 Qualcomm Incorporated Method and a system for accelerating procedure return sequences

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Publication number Priority date Publication date Assignee Title
US5812813A (en) * 1996-07-29 1998-09-22 Integrated Device Technology, Inc. Apparatus and method for of register changes during execution of a micro instruction tracking sequence
US20030120906A1 (en) 2001-12-21 2003-06-26 Jourdan Stephan J. Return address stack

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Microprocessor Report 1994, Mike Johnson, An Alternative to RISC: The Intel 80x86(1994) *

Also Published As

Publication number Publication date
JP5301554B2 (ja) 2013-09-25
CN101884025B (zh) 2014-04-09
JP2011503718A (ja) 2011-01-27
JP5815596B2 (ja) 2015-11-17
WO2009059100A1 (en) 2009-05-07
US20090119486A1 (en) 2009-05-07
KR20100087357A (ko) 2010-08-04
CN101884025A (zh) 2010-11-10
JP2015133126A (ja) 2015-07-23
EP2220556A1 (en) 2010-08-25
EP2220556B1 (en) 2019-03-06
JP2013211023A (ja) 2013-10-10
US8341383B2 (en) 2012-12-25

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