KR101252698B1 - 클록 게이팅 시스템 및 방법 - Google Patents

클록 게이팅 시스템 및 방법 Download PDF

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Publication number
KR101252698B1
KR101252698B1 KR1020107026818A KR20107026818A KR101252698B1 KR 101252698 B1 KR101252698 B1 KR 101252698B1 KR 1020107026818 A KR1020107026818 A KR 1020107026818A KR 20107026818 A KR20107026818 A KR 20107026818A KR 101252698 B1 KR101252698 B1 KR 101252698B1
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KR
South Korea
Prior art keywords
input
clock signal
terminal
coupled
circuit
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KR1020107026818A
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English (en)
Korean (ko)
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KR20110031907A (ko
Inventor
마틴 사인트-로렌트
바삼 자밀 모흐드
폴 바셋트
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퀄컴 인코포레이티드
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Priority claimed from US12/431,992 external-priority patent/US7902878B2/en
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20110031907A publication Critical patent/KR20110031907A/ko
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Publication of KR101252698B1 publication Critical patent/KR101252698B1/ko

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    • Y02B60/50—

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Logic Circuits (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
KR1020107026818A 2009-04-29 2009-05-14 클록 게이팅 시스템 및 방법 KR101252698B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/431,992 2009-04-29
US12/431,992 US7902878B2 (en) 2008-04-29 2009-04-29 Clock gating system and method
PCT/US2009/043913 WO2009135226A2 (en) 2008-04-29 2009-05-14 Clock gating system and method

Publications (2)

Publication Number Publication Date
KR20110031907A KR20110031907A (ko) 2011-03-29
KR101252698B1 true KR101252698B1 (ko) 2013-04-09

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KR1020107026818A KR101252698B1 (ko) 2009-04-29 2009-05-14 클록 게이팅 시스템 및 방법

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KR (1) KR101252698B1 (zh)
CN (1) CN102016749B (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8981815B2 (en) * 2013-04-01 2015-03-17 Mediatek Singapore Pte. Ltd. Low power clock gating circuit
US10020809B2 (en) * 2016-09-19 2018-07-10 Globalfoundries Inc. Integrated level translator and latch for fence architecture
US9941881B1 (en) * 2017-03-23 2018-04-10 Qualcomm Incorporated Apparatus and method for latching data including AND-NOR or OR-NAND gate and feedback paths
US10963265B2 (en) * 2017-04-21 2021-03-30 Micron Technology, Inc. Apparatus and method to switch configurable logic units
US10516391B2 (en) * 2017-12-12 2019-12-24 Micron Technology, Inc. Apparatuses and methods for data transmission offset values in burst transmissions
US11196422B2 (en) 2018-02-09 2021-12-07 National University Of Singapore Multi-mode standard cell logic and self-startup for battery-indifferent or pure energy harvesting systems
US10819342B2 (en) * 2018-12-20 2020-10-27 Samsung Electronics Co., Ltd. Low-power low-setup integrated clock gating cell with complex enable selection
KR20210046454A (ko) 2019-10-18 2021-04-28 에스케이하이닉스 주식회사 메모리 장치 및 그 동작 방법
KR20210142986A (ko) 2020-05-19 2021-11-26 에스케이하이닉스 주식회사 전압 생성기 및 이를 포함하는 메모리 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6552572B1 (en) 2001-10-24 2003-04-22 Lsi Logic Corporation Clock gating cell for use in a cell library
WO2005036422A1 (en) 2003-09-16 2005-04-21 Pdf Solutions, Inc. Integrated circuit design to optimize manufacturability
KR20060040384A (ko) * 2004-11-05 2006-05-10 삼성전자주식회사 고속 저전력 클록 게이티드 로직 회로
JP2007329586A (ja) 2006-06-06 2007-12-20 Sanyo Electric Co Ltd 半導体集積回路装置並びにその設計装置及び設計方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5598112A (en) * 1995-05-26 1997-01-28 National Semiconductor Corporation Circuit for generating a demand-based gated clock
JP3528413B2 (ja) * 1996-04-19 2004-05-17 ソニー株式会社 関数クロック発生回路並びにそれを用いたイネーブル機能付きｄ型フリップフロップおよび記憶回路
US6703883B2 (en) * 2001-03-29 2004-03-09 Koninklijke Philips Electronics N.V. Low current clock sensor
KR100425446B1 (ko) * 2001-04-27 2004-03-30 삼성전자주식회사 캘리브레이션 될 소정의 클럭신호를 선택하는클럭선택회로를 구비하는 반도체 메모리 장치의 입력회로및 소정의 클럭신호를 선택하는 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6552572B1 (en) 2001-10-24 2003-04-22 Lsi Logic Corporation Clock gating cell for use in a cell library
WO2005036422A1 (en) 2003-09-16 2005-04-21 Pdf Solutions, Inc. Integrated circuit design to optimize manufacturability
KR20060040384A (ko) * 2004-11-05 2006-05-10 삼성전자주식회사 고속 저전력 클록 게이티드 로직 회로
JP2007329586A (ja) 2006-06-06 2007-12-20 Sanyo Electric Co Ltd 半導体集積回路装置並びにその設計装置及び設計方法

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CN102016749A (zh) 2011-04-13
KR20110031907A (ko) 2011-03-29
CN102016749B (zh) 2014-04-23

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