US6552572B1 - Clock gating cell for use in a cell library - Google Patents
Clock gating cell for use in a cell library Download PDFInfo
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- US6552572B1 US6552572B1 US09/999,726 US99972601A US6552572B1 US 6552572 B1 US6552572 B1 US 6552572B1 US 99972601 A US99972601 A US 99972601A US 6552572 B1 US6552572 B1 US 6552572B1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
A clock gating cell and a method of manufacturing the same. In one embodiment, the clock gating cell includes: (1) gate signal and clock signal inputs configured to receive gate enable and clock input signals, respectively, and (2) a gated clock signal output configured to generate a gated clock signal that is a function of states of the gate enable and clock signals, the clock gating cell treated as an atomic entity in a cell library.
Description
The present invention is directed, in general, to a gated clock, and more specifically, to an “atomic” gated clock cell.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Cell placement in semiconductor fabrication involves determining placement of particular cells on the surface of an integrated circuit, such as an application-specific integrated circuit (ASIC). Cell placement is one of the steps necessary for the fabrication of the ASIC. The ASIC has cells and connections between the cells, formed on a surface of a semiconductor substrate. The ASIC may include a large number of cells and require complex connections between the cells.
Due to the large number of components and the exacting details required by the fabrication process, a physical design of the ASIC is not practical without the aid of computers. As a result, most phases of physical design extensively use Computer Aided Design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance.
However, the ASIC may have a large number, which can be tens of thousands, hundreds of thousands or even millions or more of small cells. Each cell represents a single logic element, such as a gate, or several logic elements interconnected in a standardized manner to perform a specific function. Cells are often arranged into cell libraries to facilitate their repeated use.
One goal of cell placement is to find a minimum area arrangement for the cells that allows completion of interconnections between the cells. Placement is typically done in two phases. In the first phase, an initial placement is created. In the second phase, the initial placement is evaluated and iterative improvements are made until the layout has minimum area and conforms to design specifications.
One such functionality that may be desired from the interactions and interconnections of the cells is that of forming a gated clock. A gated clock may generally be defined as a clock that generates a clock pulse that is substantially synchronous to a source clock signal when a gating signal is also asserted. The source clock signal is generally propagated throughout an ASIC in what is colloqially known as a “clock tree.” A gated clock may consist of a latch, perhaps an active low latch, and an AND gate.
In the ASIC world, a clock gating module is usually made up of two standard cells, such as an AND gate and a latch, which should ideally be placed very close to each other in the layout. A problem arose in the prior art when a cell placement tool placed clock gating modules far apart or sourced clock gating modules from different branches of the clock tree (a risk realized when clock gating modules are tied to different ASIC pins). Any resulting clock skew or propagation delay in the gating signal between the latch and the gate can cause a “race condition” for the AND gate. An unwanted glitch can occur as a result of such race condition. The unwanted glitch may manifest as an additional undesired positive gated pulse, for instance. This problem is particularly annoying when there are a number of gated clocks in an ASIC design. To remedy this misplacement of the cells, the ASIC designer has been required manually to move the AND gate cell and the latch cell closer together.
For more information about cells, please see U.S. Pat. No. 6,243,849B1 to Singh, et al., which is hereby incorporated by reference in its entirety. Also for more information about clocks, please see U.S. Pat. No. 6,246,278B1 to Anderson, et al., which is hereby incorporated by reference in its entirety.
Accordingly, what is needed in the art is a gated clock that overcomes the limitations of the prior art. What is also needed is such gated clock that is employable as an atomic cell in a cell library.
To address the above-discussed deficiencies of the prior art, the present invention provides a clock gating cell and a method of manufacturing the same. In one embodiment, the clock gating cell includes: (1) gate signal and clock signal inputs configured to receive gate enable and clock input signals, respectively, and (2) a gated clock signal output configured to generate a gated clock signal that is a function of states of the gate enable and clock signals, the clock gating cell treated as an atomic entity in a cell library.
The present invention therefore introduces the concept of a unitary (“atomic”) clock gating cell that is to be handled as an inseparable, indivisible entity in a cell library, thereby ensuring its proper operation. The present invention enjoys substantial utility in that it avoids race conditions that may otherwise occur when clock gating circuitry is divided between two or more cells.
Prior art clock gating circuits were not defined as a single cell and therefore risked being separated during compiling or being tied to different branches of a clock tree. Unfortunately, designers of such circuits were not motivated to recast such circuits as atomic entities, because separation did not always occur, and the risk was therefore unappreciated. Further, such separate circuits contained no motivation or suggestion that they could be recast as atomic entities.
In one embodiment of the present invention, internal circuitry of the clock gating cell comprises a latch configured to receive the gate enable and clock input signals and generate therefrom a latch enable signal. In an embodiment to be illustrated and described, the clock input signal is passed through a transparent low latch.
In one embodiment of the present invention, internal circuitry of the clock gating cell comprises combinatorial logic that generates the gated clock signal directly from the clock signal. In a more specific embodiment, the internal circuitry further comprises combinatorial logic that generates the gated clock signal from the latch enable and the clock input signal. In an embodiment to be illustrated and described, the combinatorial logic comprises an AND gate.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates one embodiment of a unitary “atomic” clock gating cell built according to the principles of the present invention; and
FIG. 2 illustrates a method of manufacturing a unitary “atomic” clock gating cell according to the principles of the present invention.
Referring initially to FIG. 1, disclosed is one embodiment of a unitary “atomic” (i.e., indivisible) clock gating cell 100 built according to the principles of the present invention. A silicon compiler treats the unitary clock gating cell 100 as an atomic entity. A silicon compiler may be generally defined as a computer program that generates IC layouts, such as application-specific integrated circuit (ASIC) layouts, from a high-level specification. One example of employing the unitary clock gating cell 100 as an atomic entity by the silicon compiler is during the design and implementation of the ASIC.
The unitary clock gating cell 100 has a gate enable input 105 and a clock signal input 110 configured to receive gate and clock input signals, respectively. The unitary clock gating cell 100 also has a gated clock signal output 112 that is configured to generate a gated clock signal as a function of states of the gate enable 105 and the clock signal 110. The unitary clock gating cell 100 is a cell such as may be employed in the design of an ASIC.
The clock gating cell 100, although treated as an indivisible and atomic entity by the silicon compiler which creates the ASIC, has an internal circuitry 113. The internal circuitry 113 has a latch 115, such as transparent low latch, although other latches (such as falling edge latches) are well within the scope of the present invention. The latch 115 also has an inverter 117, which inverts a high clock input signal 110 to low, and a low clock input signal 110 to high. The latch 115 allows the gate enable signal 105 to pass through the latch 115 to a latch enable signal 120 when the latch is enabled (i.e, due to the inverter 117, when the clock input signal is low), but the latch 115 freezes the latch enable signal 120 at its last output value when the latch 115 is disabled (i.e, due to the inverter 117, when the clock input signal is high.)
The internal circuitry 113 also has an AND gate 125. The AND gate 125 is a source within the internal circuitry 113, and ultimately a source of the clock gating cell 100, of the gated clock signal output 112. The AND gate 125 combines the latch enable signal 120 and the clock input signal 110. This combinatorial logic, of combining within the AND gate 125 the clock input signal 110 and the latch enable signal 120, generates the gated clock signal 112 directly from the clock input signal 110. In a further embodiment, the combinatorial logic within the AND gate 125 generates the gated clock signal 112 from the latch enable signal 120 and the clock input signal 115.
Turning now to FIG. 2, disclosed is a method of manufacturing 200 the clock gating cell 100 according to the principles of the present invention. After executing a step start 210, the silicon compiler then defines the unitary “atomic” clock gating cell 100 as having the gate input signal 105 and the clock input signal 110 in a step 220.
After the step 220, the silicon compiler then defines the gated clock signal 112 output configured to generate a gated clock signal that is a function of states of the gate enable signal 120 and the input clock signal 110 in a step 230. At all times, the clock gating cell 100 is treated as an atomic entity by the silicon compiler.
After the step 230, the silicon compiler then defines the internal circuitry 113 of the unitary clock gating cell 100 in a step 240. The step 240 creates the internal circuitry 113 having a latch configured to receive the gate enable signal 120 and clock input signal 110 to generate therefrom the latch enable signal 120. The clock input signal 110 is provided to the latch 115. The latch 115 may be a transparent low latch, although other latches (such as falling edge latches) are well within the principles of the present invention. The combinational logic of the internal circuitry 113 will also have defined an AND gate 125. The internal circuitry 113 also has combinatorial logic that generated the gated clock signal 112 directly from the input clock signal 110. The internal circuitry 113 also generates the gated clock 112 signal from the combination of the latch enable circuit 120 and the input signal 110.
Finally, after the silicon compiler has performed the above steps in defining a unitary “atomic” gating clock 100 in the method of manufacturing 200, the silicon compiler executes a stop step 250.
Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form.
Claims (18)
1. A clock gating cell, comprising:
gate signal and clock signal inputs configured to receive gate enable and clock input signals, respectively; and
a gated clock signal output configured to generate a gated clock signal that is a function of states of said gate enable and clock signals, said clock gating cell treated as an atomic entity in a cell library.
2. The clock gating cell as recited in claim 1 wherein internal circuitry of said clock gating cell comprises a latch configured to receive said gate enable and clock input signals and generate therefrom a latch enable signal.
3. The clock gating cell as recited in claim 1 wherein internal circuitry of said clock gating cell comprises combinatorial logic that generates said gated clock signal directly from said clock signal.
4. The clock gating cell as recited in claim 2 wherein said internal circuitry further comprises combinatorial logic that generates said gated clock signal from said latch enable and said clock input signal.
5. The clock gating cell as recited in claim 3 wherein said combinatorial logic comprises an AND gate.
6. The clock gating cell as recited in claim 2 wherein said clock input signal is passed through a transparent low latch.
7. The clock gating cell as recited in claim 2 wherein said latch is a transparent low latch.
8. A method of manufacturing a clock gating cell, comprising:
defining gate signal and clock signal inputs configured to receive gate enable and clock input signals, respectively; and
defining a gated clock signal output configured to generate a gated clock signal that is a function of states of said gate enable and clock signals, said clock gating cell treated as an atomic entity in a cell library.
9. The method as recited in claim 8 further comprising defining internal circuitry of said clock gating cell that comprises a latch configured to receive said gate enable and clock input signals and generate therefrom a latch enable signal.
10. The method as recited in claim 8 further comprising defining internal circuitry of said clock gating cell that comprises combinatorial logic that generates said gated clock signal directly from said clock signal.
11. The method as recited in claim 9 wherein said defining said internal circuitry further comprises defining combinatorial logic that generates said gated clock signal from said latch enable and said clock input signal.
12. The method as recited in claim 10 wherein said combinatorial logic comprises an AND gate.
13. The method as recited in claim 9 wherein said clock input signal is passed through a transparent low latch.
14. The method as recited in claim 9 wherein said latch is a transparent low latch.
15. A clock gating cell, comprising:
a latch configured to receive gate enable clock input signals and derive a latch signal therefrom; and
combinatorial logic, coupled to said latch, configured to receive said latch and clock input signals and generate a gated clock signal therefrom, said latch and said combinatorial logic treated as an atomic entity in a cell library.
16. The clock gating cell as recited in claim 15 wherein said combinatorial logic comprises an AND gate.
17. The clock gating cell as recited in claim 15 wherein said clock input signal is passed through a transparent low latch.
18. The clock gating cell as recited in claim 15 wherein said latch is a transparent low latch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/999,726 US6552572B1 (en) | 2001-10-24 | 2001-10-24 | Clock gating cell for use in a cell library |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/999,726 US6552572B1 (en) | 2001-10-24 | 2001-10-24 | Clock gating cell for use in a cell library |
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| US6552572B1 true US6552572B1 (en) | 2003-04-22 |
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| US09/999,726 Expired - Lifetime US6552572B1 (en) | 2001-10-24 | 2001-10-24 | Clock gating cell for use in a cell library |
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Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040150427A1 (en) * | 2003-01-20 | 2004-08-05 | Wilcox Stephen Paul | Clock gating for synchronous circuits |
| EP1612936A2 (en) * | 2004-06-30 | 2006-01-04 | Infineon Technologies AG | Device for clock control |
| US7042267B1 (en) * | 2004-05-19 | 2006-05-09 | National Semiconductor Corporation | Gated clock circuit with a substantially increased control signal delay |
| US20060097754A1 (en) * | 2004-11-05 | 2006-05-11 | Min-Su Kim | Gated clock logic circuit |
| US20070008024A1 (en) * | 2005-07-11 | 2007-01-11 | Chi-Ting Cheng | Gate Clock Circuit and Related Method |
| US20070008025A1 (en) * | 2005-07-11 | 2007-01-11 | Po-Yo Tseng | Gate Clock Circuit and Related Method |
| US20090006012A1 (en) * | 2007-06-20 | 2009-01-01 | Kabushiki Kaisha Toshiba | Power consumption analyzing apparatus and power consumption analyzing method |
| US20090267649A1 (en) * | 2008-04-29 | 2009-10-29 | Qualcomm Incorporated | Clock Gating System and Method |
| US20100109707A1 (en) * | 2008-11-03 | 2010-05-06 | Freescale Semiconductror, Inc | Low power, self-gated, pulse triggered clock gating cell |
| US7884649B1 (en) * | 2009-02-27 | 2011-02-08 | Magma Design Automation, Inc. | Selection of optimal clock gating elements |
| KR101252698B1 (en) | 2009-04-29 | 2013-04-09 | 퀄컴 인코포레이티드 | Clock gating system and method |
| US8434047B1 (en) | 2007-05-29 | 2013-04-30 | Synopsys, Inc. | Multi-level clock gating circuitry transformation |
| US8643411B1 (en) * | 2012-10-31 | 2014-02-04 | Freescale Semiconductor, Inc. | System for generating gated clock signals |
| US10423215B2 (en) | 2017-05-15 | 2019-09-24 | Cavium, Llc | Methods and apparatus for adaptive power profiling in a baseband processing system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6318911B1 (en) * | 1997-04-01 | 2001-11-20 | Kabushiki Kaisha Toshiba | Gated clock design supporting method, gated clock design supporting apparatus, and computer readable memory storing gated clock design supporting program |
-
2001
- 2001-10-24 US US09/999,726 patent/US6552572B1/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6318911B1 (en) * | 1997-04-01 | 2001-11-20 | Kabushiki Kaisha Toshiba | Gated clock design supporting method, gated clock design supporting apparatus, and computer readable memory storing gated clock design supporting program |
Cited By (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040150427A1 (en) * | 2003-01-20 | 2004-08-05 | Wilcox Stephen Paul | Clock gating for synchronous circuits |
| US7095251B2 (en) * | 2003-01-20 | 2006-08-22 | Azuro (Uk) Limited | Clock gating for synchronous circuits |
| US7042267B1 (en) * | 2004-05-19 | 2006-05-09 | National Semiconductor Corporation | Gated clock circuit with a substantially increased control signal delay |
| DE102004031669B3 (en) * | 2004-06-30 | 2006-02-09 | Infineon Technologies Ag | Clock control cell |
| US20060001468A1 (en) * | 2004-06-30 | 2006-01-05 | Sascha Siegler | Clock control cell |
| EP1612936A3 (en) * | 2004-06-30 | 2007-07-25 | Infineon Technologies AG | Device for clock control |
| US7274240B2 (en) | 2004-06-30 | 2007-09-25 | Infineon Technologies Ag | Clock control cell |
| EP1612936A2 (en) * | 2004-06-30 | 2006-01-04 | Infineon Technologies AG | Device for clock control |
| US20060097754A1 (en) * | 2004-11-05 | 2006-05-11 | Min-Su Kim | Gated clock logic circuit |
| US7365575B2 (en) * | 2004-11-05 | 2008-04-29 | Samsung Electronics Co., Ltd. | Gated clock logic circuit |
| US20070008024A1 (en) * | 2005-07-11 | 2007-01-11 | Chi-Ting Cheng | Gate Clock Circuit and Related Method |
| US20070008025A1 (en) * | 2005-07-11 | 2007-01-11 | Po-Yo Tseng | Gate Clock Circuit and Related Method |
| US8434047B1 (en) | 2007-05-29 | 2013-04-30 | Synopsys, Inc. | Multi-level clock gating circuitry transformation |
| US20090006012A1 (en) * | 2007-06-20 | 2009-01-01 | Kabushiki Kaisha Toshiba | Power consumption analyzing apparatus and power consumption analyzing method |
| US7908100B2 (en) * | 2007-06-20 | 2011-03-15 | Kabushiki Kaisha Toshiba | Power consumption analyzing apparatus and power consumption analyzing method |
| US20090267649A1 (en) * | 2008-04-29 | 2009-10-29 | Qualcomm Incorporated | Clock Gating System and Method |
| WO2009135226A3 (en) * | 2008-04-29 | 2010-09-10 | Qualcomm Incorporated | Clock gating system and method |
| US7902878B2 (en) | 2008-04-29 | 2011-03-08 | Qualcomm Incorporated | Clock gating system and method |
| JP2011526091A (en) * | 2008-04-29 | 2011-09-29 | クゥアルコム・インコーポレイテッド | Clock gating system and method |
| WO2009135226A2 (en) * | 2008-04-29 | 2009-11-05 | Qualcomm Incorporated | Clock gating system and method |
| EP2620833A1 (en) * | 2008-04-29 | 2013-07-31 | Qualcomm Incorporated | Clock gating system and method |
| US7808279B2 (en) | 2008-11-03 | 2010-10-05 | Freescale Semiconductor, Inc. | Low power, self-gated, pulse triggered clock gating cell |
| US20100109707A1 (en) * | 2008-11-03 | 2010-05-06 | Freescale Semiconductror, Inc | Low power, self-gated, pulse triggered clock gating cell |
| US7884649B1 (en) * | 2009-02-27 | 2011-02-08 | Magma Design Automation, Inc. | Selection of optimal clock gating elements |
| KR101252698B1 (en) | 2009-04-29 | 2013-04-09 | 퀄컴 인코포레이티드 | Clock gating system and method |
| US8643411B1 (en) * | 2012-10-31 | 2014-02-04 | Freescale Semiconductor, Inc. | System for generating gated clock signals |
| US10423215B2 (en) | 2017-05-15 | 2019-09-24 | Cavium, Llc | Methods and apparatus for adaptive power profiling in a baseband processing system |
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