KR101252698B1 - Clock gating system and method - Google Patents

Abstract

A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input receiving at least one input signal and having an output coupled to an internal enable node. The keeper circuit includes at least one switching element that responds to a gated clock signal, which is coupled to selectively hold a logical voltage level at the internal enable node. The system includes a gating element responsive to the logical voltage level and an input clock signal at the internal enable node to generate the gated clock signal.

Description

CLOCK GATING SYSTEM AND METHOD

This specification, filed April 29, 2008, claims the benefit of a US provisional application with provisional application number 61 / 048,661, which is incorporated herein by reference in its entirety.

This disclosure generally relates to clock gating.

Advances in technology have resulted in smaller and more powerful personal computing devices. For example, there are currently a variety of portable personal computing devices, including wireless computing devices such as portable wireless telephones, personal digital assistants (PDAs), and paging devices that are small, lightweight, and easily carried by users. More specifically, portable wireless telephones, such as cellular telephones and Internet Protocol (IP) telephones, can communicate voice and data over a wireless network. Many of these cordless telephones also include other types of devices incorporated therein. For example, a cordless phone may also include a digital still camera, a digital video camera, a digital recorder, and an audio file player. Such wireless telephones can also process executable instructions including software applications such as web browser applications that can be used to access the Internet. However, the power consumption of such portable devices quickly drains the battery and reduces the user experience.

One power saving feature is the use of clock gating in one or more clock trees. A clock tree or clock distribution network distributes one or more clock signals to other circuit elements that receive the clock signal from a common point. Clock trees often consume a significant portion of the power consumed by semiconductor devices, and unnecessary power consumption can occur in the branches of the clock tree when the output of the branch is not needed. A technique called clock gating to conserve power is often used to turn off these areas if they are not used. However, clock gating cells used to perform clock gating also consume power.

In a particular embodiment, the clock gating system incorporates circuitry that functions as a set-reset latch instead of a general pass-gate for holding an enable signal in the clock gating circuit. The set-reset latch includes a pair of cross-coupled NOT-AND (NAND) gates. One of the NAND gates is integrated as the NAND gate blocks the clock. Clock gating systems reduce the number of transistors and have a smaller area compared to cells using pass-gate latches. The clock gating system can reduce the number of transistors to toggle whenever the clock signal toggles, and can reduce dynamic power consumption compared to conventional clock gating cells.

In a particular embodiment, the clock gating circuit includes an input logic circuit having at least one input receiving at least one input signal and having an output coupled to an internal enable node. The clock gating circuit also includes a keeper circuit coupled to selectively maintain a logical voltage level at the internal enable node. The keeper circuit includes at least one switching element responsive to a gated clock signal. The clock gating circuit also includes a gating element responsive to the logical voltage level and an input clock signal at the internal enable node to generate the gated clock signal.

In another particular embodiment, a system is disclosed that includes a NAND logic circuit having an output coupled to provide a gated clock signal with a first input coupled to receive a clock signal. The system includes a keeper circuit coupled to provide an enable signal to a second input of the NAND logic circuit. Less than nine but less than four transistors toggle with each clock signal transition.

In another particular embodiment, a method begins with receiving at least one input signal at an input logic circuit having at least one input receiving at least one input signal and having an output coupled to an internal enable node. do. The method also includes generating a gated clock signal at a gating element responsive to an input clock signal and a logical voltage level at the internal enable node. The method further includes selectively maintaining the logical voltage level at the internal enable node in response to the gated clock signal.

In a particular embodiment, the method includes selecting one of a first clock gating cell having a first keeper circuit or a second clock gating cell having a second keeper circuit, wherein the selection is based on at least one design criterion. do. In one embodiment, the first clock gating cell may include nine transistors that toggle in response to each clock signal toggle. In another embodiment, less than half of the transistors of the second keeper circuit toggles in response to each clock signal toggle. In another embodiment, the design criteria include power consumption, operating speed, regions of the first clock gating cell or second clock gating cell, and any combination thereof.

One particular advantage provided by at least one of the disclosed embodiments is the reduced power consumption of the clock gating circuit. Another particular advantage provided by at least one of the disclosed embodiments is a reduced footprint of the clock gating circuit. Another particular advantage provided by at least one of the disclosed embodiments is that fewer transistors switch using each clock cycle.

Other aspects, advantages, and features of the present specification will become apparent after a review of the entire specification, including the following sections: Brief Description of the Drawings, Detailed Description, and the Claims.

1 is a block diagram of a particular illustrative embodiment of a clock gating system.
2 is a circuit diagram of a first exemplary embodiment of a clock gating cell for use in a clock gating system.
3 is a circuit diagram of a second exemplary embodiment of a clock gating cell for use in a clock gating system.
4 is a flow chart of a particular illustrative embodiment of a method of generating a gated clock signal.
5 is a block diagram of an example communications device including a clock gating circuit having four transistor toggle operation.
6 is a block diagram of an exemplary embodiment of a fabrication process including a clock gating circuit having four toggling transistors.

Referring to FIG. 1, an exemplary embodiment of a system for generating a gated clock signal is shown and generally indicated at 100. System 100 includes a clock gating cell 102 coupled to gated circuit 104. Clock gating cell 102 receives clock input 106 and first input! 08. Clock gating cell 102 may also receive one or more additional inputs, such as second input 110. Clock gating cell 102 provides gated clock signal 112 to gated circuit 104. Clock gating cell 102 includes clock gating circuit 128.

Clock gating circuit 128 includes an input logic circuit 114 connected to an internal enable node 107. The keeper circuit 120 and the gating element 122 are also connected to the internal enable node 107. The keeper circuit 120 includes at least one switching element 128 responsive to the gating clock signal 120. Since the switching element 128 responds to the gated clock signal 112 instead of the input clock signal received at the clock input 106, the switching element 128 switches less frequently than other elements responsive to the input clock signal. (I.e. show fewer toggles).

The input logic circuit 114 can function as any logic circuit that produces an output based on variables of one or more inputs. By way of example, the input logic circuit 114 may include an inverter, NOT OR (NOR) gate, NOT AND (NAND) gate, AND OR INVERT (AOI) gate, and OR AN IN INVERT (OAI) gate, multiplexer, exclusive OR (XOR). May function as a gate and any other type of logic circuit, but is not limited thereto. In a particular embodiment, the input logic circuit 114 includes a first circuit 116 that performs a first logical function f connected to a second circuit that performs a third logical function not (f), Here, the second logical function is an inverse of the first logical function. The first circuit 116 may be formed of a p-channel metal-oxide-semiconductor (PMOS) element, and the second circuit 118 may be formed of an n-channel metal-oxide-semiconductor (NMOS) element. Input logic circuit 116 has an output 126 that is connected to an internal enable node 107. The input logic circuit 114 is internally enabled at a logical voltage level, such as a logic "0" level or a logic "1" level, in response to the first and second logical functions of the one or more input signals 108-110. Can be configured to bias 107.

In a particular embodiment, the keeper circuit 120 operates substantially as a set-reset latch or a pass-gate latch. The keeper circuit 120 selectively maintains a logical voltage level at the internal enable node 107 or allows the input logic circuit! 14 to control the voltage level at the internal enable node 107. Respond to 106 and the gated clock signal 112. The keeper circuit 120 includes a switching element 128 responsive to the gating clock signal 112. Since the switching element 128 responds to the gating clock signal 112, the switching element 128 switches less frequently than the switching element responsive to the input clock signal, reducing the dynamic power consumption of the system 100. For example, system 100 provides lower power for typical clock gating cells with nine transistors that toggle when the input clock signal toggles. For illustration purposes, not more than four transistors in system 100 may toggle with each clock signal transition.

Gating element 122 has a first input coupled to receive input clock signal 106. The gating element 122 also has a second input coupled to receive the enable signal 124 induced by the logical voltage level at the internal enable node 107. Gating element 122 responds to an input clock signal 106 and a logical voltage level at internal enable node 107 to produce a gated clock signal 112. As described, the gating element 122 can include circuitry such as an AND gate, which can selectively propagate the input clock signal or convert the input clock signal 106 as a function of the first and second inputs. Block to generate the gated clock output 112.

In a first mode of operation in which the internal enable signal 124 from the internal enable node 107 is a logical " 0 " state (i.e., biased with a voltage representing a logical low value), gating is the output of the gating element 122. Clock signal 112 is maintained in a logical state, such as a logical " 0 " state, independent of other inputs. In a second mode of operation (ie, biased with a voltage representing a logical high value) in which the internal enable signal 124 from the internal enable node 107 is in a logical " 1 " state, the gated clock signal 112 The value of is dependent on clock input 106 and will be in a logical "0" or logical "1" state. One or more inputs 108-110 to the input logic circuit 114 may change the logical state of the internal enable node 107 while the input clock signal 106 is low (ie, in a logical "0" state). Can be used for In particular, these inputs may include one or more multiple signals that force the enable node 107 to a specific value during the test mode. When the input clock signal 106 is high (ie, a logical "1" state), the keeper circuit 120 maintains the state of the internal enable signal 124 in a logical "0" or logical "1" state.

2, a first particular illustrative embodiment of a clock gating system is disclosed and generally designated 200. The clock gating system 200 may operate in a manner that is logically equivalent to the clock gating circuit 128 of FIG. 1. System 200 includes a gating element that includes a NOT-AND (NAND) logic circuit 202 having a first input 204 coupled to receive an input clock signal 208. NAND logic circuit 202 has a second input 206 coupled to receive an enable signal from internal enable node 207. NAND logic circuit 202 provides a gated clock signal at node (n) 222. The gated clock signal at node 222 is inverted with respect to the input clock signal 208. Inverter 236 coupled to node 222 generates a second gated clock signal as an output signal 238 that is not inverted with respect to input clock signal 208. The gated clock signal at node 222 may be used as an output signal having the opposite polarity of output signal 238. Optionally, in certain embodiments, inverter 236 may be replaced by a buffer to change the polarity of output signal 238. In a particular embodiment, the gating element that includes the NAND logic circuit 202 corresponds to the gating element of FIG. 1.

The input logic circuit includes a pullup circuit 210 and a pulldown circuit 212 connected in series through an internal enable node 207. In a particular embodiment, the input logic circuit having the pull up circuit 210 and the pull down circuit 212 may correspond to the input logic circuit 114 of FIG. 1 using the first circuit 116 and the second circuit 118. have. The pull up circuit 210 may operate to selectively provide a low-impedance path between the supply and the internal enable node 207. Pull-down circuit 212 may operate to selectively provide a low-impedance path between internal enable node 207 and ground.

Pull-up circuit 210 and pull-down circuit 212 may be coupled to first isolation element 234 and second isolation element 214 to selectively prevent current flow through pull-up and pull-down circuits 210 and 212, respectively. The same input logic isolation elements can be connected in series. At least one isolation element 214, 234 may respond to a gated clock signal rather than an input clock signal 208. For example, the first isolation element 234 can be configured to selectively prevent the pull-up circuit 210 from biasing the internal enable node 207 at a logical high voltage level. The second isolation element 214 can be configured to prevent the pull down circuit from biasing the internal enable node 207 to a logical low voltage level.

The first isolated element is shown as a switching element having a first terminal connected to the supply and a control terminal connected to the input clock signal 208. In a particular embodiment, the first isolation element 234 is a p-channel metal-oxide-semiconductor (PMOS) transistor. The first isolation element 234 has a second terminal connected to the pull up circuit 210. Although the pull up circuit 210 and the first isolation element 234 are shown connected in series with the first isolation element 234 connected to the supply, the pull up circuit 210 and the first isolation element 234 function as a circuit. Can be rearranged without changing. In a particular embodiment, the first isolation element 234 is a first field effect transistor (FET).

In the illustrated embodiment, the pull up circuit 210 is connected to the first terminal of the internal enable node 207 and the second isolation element 214. In a particular embodiment, the second isolation element 214 is an n-channel MOS (NMOS) transistor having a first terminal coupled to the internal enable node and a second terminal coupled to the pulldown circuit 212. In another particular embodiment, the second isolation element 214 is a second FET.

Pull-up circuit 210 has control terminals or inputs that are connected to receive first signal 216. Pull-up circuit 210 may receive one or more additional inputs, such as second signal 218. In a particular embodiment, the first signal 216 and optionally the second signal 218 cause the output signal 238 to follow the input clock during the test mode, and optionally, output signal 238 during the test mode. It includes a signal to disable. Pull-down circuit 212 also has control terminals or inputs that are connected to receive first signal 216. Pull-down circuit 212 may also receive one or more additional inputs, such as second signal 218.

By way of example, as a non-limiting example, an input logic circuit including pull-up circuit 210 and pull-down circuit 212 may operate as a dual-input NAND logic circuit. For example, the pull-up circuit 210 may include a pair of PMOS transistors (not shown) connected in parallel between the first isolation element 234 and the second isolation element 214, each PMOS transistor. Responds to the corresponding input signal 216,218. Pull-down circuit 212 may include a pair of NMOS transistors (not shown) connected in series between the second isolation element 214 and ground, each NMOS transistor coupled to a corresponding input signal 216, 218. Answer.

The switching element may be used in a keeper circuit having at least one switching element responsive to a gated clock signal. For example, the keeper circuit may include a first switching element, such as a PMOS transistor 224, which has a first terminal connected to the supply and a second terminal connected to the enable node 207. PMOS transistor 224 has a control terminal coupled to node 222 that will respond to a gated clock signal.

The keeper circuit also includes a first NMOS transistor 230 having a first terminal connected to the second terminal of the PMOS transistor 224 through a second isolation element 214. Inverter 228 has an input coupled to enable node 207 and an output coupled to a control terminal of first NMOS transistor 230. The first NMOS transistor 230 has a second terminal connected to the first terminal of the second NMOS transistor 232. The second NMOS transistor 232 has a second terminal connected to ground. The control terminal of the second NMOS transistor 232 is connected in response to the clock signal 208. Although the first NMOS transistor 230 and the second NMOS transistor 232 are shown as being connected in series in a particular order, in other embodiments, the serial order of the first NMOS transistor 230 and the second NMOS transistor 232 is shown. Can be changed without changing the performance of the keeper circuit.

The inverter 228 and the first NMOS transistor 230 are internal enable nodes due to current flow through the keeper circuit during the delay associated with the gating element when the input signal 208 transitions from the low logic level to the high logic level. At 207, form a keeper isolation element configured to prevent the logical voltage level from changing. For illustrative purposes, when the internal enable node 207 is biased to a logic high level and the input clock signal 208 transitions to a high logic level, it may enter the NAND logic circuit 22 for a brief period. Both the input and the output of the NAND logic circuit 202 will be at a high logic level. This condition will persist for a delay of the NAND logic circuit 202 until the output of the NAND logic circuit 202 transitions to a low logic level. During this delay period, both the second isolation element 214 and the second NMOS transistor 232 may be on. However, the first NMOS transistor 230 will remain off and will prevent current flow from the enable node 207 through the keeper circuit and thus prevent discharge of the internal enable node 207.

During operation, when the input clock signal 208 is in a logical "0" state, the node 222 is in a logical "1" state by the operation of the NAND logic circuit 202. The first isolation element 234 is on and the second isolation element 214 is on, causing the pull up circuit 210 and pull down circuit 212 to be set to a logical voltage level at the internal enable node 207. In addition, the PMOS transistor 224 and the second NMOS transistor 232 are off. Thus, the enable node 207 may be biased to a logic level representing the result of the logical functions implemented by the pull up and pull down circuits 210 and 212 as a function of the values of the one or more signals 216-218. However, NAND logic circuit 202 maintains node 222 in a logical " 1 "state, and inverter 236 maintains output signal 238 in a logical " 0 " state.

When the input clock signal 208 is in a logical "1" state, the voltage of the enable node 207 remains in a logical "0" state or a logical "1" state, and the first isolation element 234 is off, The second NMOS transistor 232 is on. The enable node 207 is in a logical "1" state, the node 222 is in a logical "0" state, the PMOS transistor 224 is on while the second isolation element 214 is off, and the enable node ( Keep 207 in a logical " 1 " state. When the enable node 207 is in a logical "0" state, the node 222 is in a logical "1" state, and the PMOS transistor 224 is the second isolation element 214, the first NMOS transistor 230. And off while the second NMOS transistor 232 is on, keeping the enable node 207 in a logical " 0 " state. One or more signals 216-218 may change logical states without disturbing the states of enable node 207, node 222, and output signal 238, respectively.

When the input clock signal 208 is in a logical "0" state, such that the gated clock signal at the node 222 is in a logical "1" state, the voltage at the enable node 207 is equal to the inputs a _1. It is determined by the logical response of the pullup circuit 210 and the inverse response of the pulldown circuit 212 for -a _k . For example, the logical response of the pull-up circuit 210 to a particular set of inputs a _{1-a k} results in a low-impedance path between the enable node 207 and the supply voltage node, and pull-down circuit 212. The inverse response of V < + > results in a high-impedance path to ground, and the enable node 207 will be biased to a logical " 1 " state. As another example, if a particular set of a _{1-a k} causes pull-up circuit 210 to form a high-impedance path to the supply voltage node and pull-down circuit 212 forms a low-impedance path to ground, Enable node 207 may be biased to a logical "0" state. If clock signal 208 rises from a logical "0" state to a logical "1" state and enable node 207 is biased to a logical "0" state, the bias at node 222 is logical. Transition from the " 1 " state to the logical " 0 " state after a delay associated with the NAND logic circuit 202. The " 1 "

Clock gating system 200 may provide several advantages. For example, clock gating system 200 reduces the number of transistors in the clock gating cell from 20 to 17. In addition, the clock gating system 200 has a smaller area and consumes less leakage power compared to circuits using pass-gate latches. As another example, the clock gating system 200 has fewer than nine transistors to toggle when the input clock signal 208 toggles, thus reducing the robbery power consumption compared to a pass-gate latch circuit. In a particular embodiment, the clock gating system 200 may include no more than four transistors to toggle when the input clock signal 208 toggles, which is the PMOS transistor 234 and the second NMOS transistor 232. And two transistors (not shown) of the NAND logic circuit 202.

In a particular embodiment, the clock gating system 200 consumes about 7% less power in the enabled state, and in the disabled state than the clock gating circuit having nine transistors that toggle with each transition of the input clock. It can consume about three times less power. Clock gating system 200 may use fewer devices and occupy about one third smaller area than that of a typical clock gating circuit. In another particular embodiment, the input capacitance of clock gating system 200 is about 1.7 femtofarads (fF) and the input capacitance of clock gating system 200 is about 2.1 fF. The setup time required to allow input 216 to reach enable node 207 is about 200 picograms for clock gating system 200 while operating at 125 C technology at 1.1 volts (V), 65-nm. It may be slower in seconds (ps). The clock gating system 200 may thus allow the design flow to optimize or improve the clock gating path based on area / speed / power tradeoffs.

In the described embodiment, a keeper circuit isolation element comprising an inverter 228 and a first NMOS transistor 230 is enabled for node 207 for both the input clock signal 208 and node 22 in a logical " 1 " state. While preventing discharge during the phosphorus delay period, in other embodiments, clock gating system 200 may not include a keeper circuit isolation element (ie, not include an inverter, first NMOS 230, or both). Can be). For example, the keeper circuit may include a PMOS transistor 224 and a second NMOS transistor 232 without including the first NMOS transistor 230 and the inverter 228. The second NMOS transistor 232 may be connected to the PMOS transistor 224 through the second isolation element 214. For example, the second NMOS transistor 232 may be connected to the second isolation element 214 without intervention of the first NMOS transistor 230. Residual transistors of clock gating system 200 may be sized to slow discharge of internal enable node 207 to maintain a logical " 1 " state at the internal enable node for a delay period associated with the gating element.

Those skilled in the art will recognize alternative embodiments of clock gating system 200 that function equivalently to clock gating system 200. For example, as mentioned previously, various series connected elements may be rearranged without affecting the operation of the clock gating system 200. In addition, a buffer may be added to delay the input clock signal 208 to transistor 232 and / or transistor 234 prior to coupling it. As another example, a dual version of clock gating system 200 may be created by replacing all PMOS transistors of clock gating system 200 with NMOS transistors, replacing all NMOS transistors with PMOS transistors, and swapping supply and ground. have. In this dual version, the NAND gate 202 may be a NOR gate, the output clock 238 stops high when the node 207 is high, and the keeper isolation element causes the input clock signal 208 to be at a high logic level. Transitioning to a low logic level will prevent a logical voltage level at the internal enable node 207 due to current flow through the keeper circuit causing a change in the internal enable node 207 during the delay associated with the gating element. .

With reference to FIG. 3, a second particular illustrative embodiment of a clock gating system is disclosed and generally designated 300. Clock gating system 300 includes circuit elements of clock gating system 200 of FIG. 2, where common elements are denoted by common reference numerals, and are logically equivalent to clock gating system 200 of FIG. 2. It works.

The keeper circuit of clock gating system 300 is connected to enable node 207, as opposed to first NMOS transistor 230 of FIG. 2, which is connected to enable node 207 through second isolation element 214. A first NMOS transistor 330 having one terminal is included. In a particular embodiment, the keeper isolation element operates substantially similar to the keeper isolation element including the first NMOS transistor 230 and inverter 228 depicted in connection with FIG.

4, a particular illustrative embodiment of a method of generating a gated clock signal is shown and is generally designated 400. In one exemplary embodiment, the method 400 may be performed by the system 100 of FIG. 1, the system 200 of FIG. 2, or the system 300 of FIG. 3.

In a particular embodiment, at 402, at least one input signal is received at an input logic circuit having at least one input and having an output coupled to an internal enable node. For example, first input signal 216 and second input signal 218 are received at an input logic circuit including pull-up circuit 210 and pull-down circuit 212, as shown in FIG. Continuing to 404, a gated clock signal is generated at a gating element responsive to an input clock signal and a logical voltage level at an internal enable node. For example, a gating element comprising the NAND logic gate 202 of FIG. 2 may be a node 222 as shown in FIG. 2 in response to the input clock signal 208 and the voltage at the internal enable node 207. Generate a gated clock signal. Moving to 406, the logical voltage level is optionally maintained at the internal enable node in response to the gated clock signal. For example, a keeper circuit including a PMOS transistor 224 and NMOS transistors 230 and 232 may have an internal enable node (i. Optionally maintain a logical voltage level at 207.

In a particular embodiment, one of the first clock gating cell having the first keeper circuit or the second clock gating cell having the second keeper circuit can be selected based on at least one design criterion, wherein the first clock gating cell is Fewer transistors than the second clock gating cell toggle with each input clock signal toggle. In a particular embodiment, the at least one design criterion is power consumption, speed of operation, area of the first clock gating cell or area of the second clock gating cell.

In another particular embodiment, the first clock gating cell includes less than nine but less than four transistors that toggle in response to each clock signal toggle. For example, the NAND logic circuit 202 of FIG. 2 is implemented using two NMOS transistors, two PMOS transistors, and two of the transistors of the NAND logic circuit 202 are a PMOS transistor 234 and an NMOS. In addition to the transistor 232, in response to the input clock signal 208, only four transistors are allowed to toggle in response to all input clock transitions. Other transistors, such as the PMOS transistor 224 and the isolated NMOS transistor 214 responsive to the gated clock signal, do not toggle with the input clock signal when the enabled signal is in a logical “0” state, due to reduced switching. Resulting in a corresponding reduction in power consumption.

In another particular embodiment, less than half of the transistors in the first keeper circuit toggle in response to each input signal toggle. For example, only the second NMOS transistor 232 of the keeper circuit of FIG. 2 toggles with each transition of the input clock signal 208. Conversely, PMOS transistor 224 responds to the clock signal gated at node 222 and will therefore not toggle when the clock signal is gated. As such, the first NMOS transistor 230 is controlled based on a bias at the internal enable node 207 rather than the input clock signal 208.

5 is a block diagram of an example embodiment of a wireless communication device. The wireless communication device 500 includes a processor, such as a digital signal processor (DSP) that includes a clock gating circuit 564 with four transistor toe operations per clock toggle. In certain embodiments, clock gating circuit 564 may include system 100 of FIG. 1, system 200 of FIG. 2, system 300 of FIG. 3, or any combination thereof. Although clock gating circuit 564 has been described as being within DSP 510, in other embodiments, clock gating circuit 564 may be used with one or more other components of wireless communication device 500. The wireless communication device 500 may be a cellular telephone, terminal, handset, "personal digital assistant" (PDA), wireless modem, or other wireless device.

5 also indicates that display controller 526 is connected to DSP 510 and display 528. Additionally, memory 532 is coupled to DSP 510. In a particular embodiment, the memory 532 may be a computer readable tangible medium that stores instructions executable by a computer, such as the DSP 510, to generate a gated clock signal based on at least one input signal. At least one input signal is provided to an input logic circuit of a clock gating cell of clock gating circuit 564. Coder / decoder (CODEC) 534 is also coupled to DSP 510. Speaker 536 and microphone 538 are coupled to CODEC 534. The wireless controller 540 is also coupled to the DSP 510 and the wireless antenna 542. In a particular embodiment, the power supply 544 and the input device 530 are connected to the on-chip system 522. In a particular embodiment, as shown in FIG. 5, display 528, input device 530, speaker 536, microphone 538, wireless antenna 542, power supply 544 are on-chip systems. Outside of 522. However, each is connected to a component of the on-chip system 522.

The devices and functions described above may be designed and configured as computer files (eg, RTL, GDSII, GERBER, etc.) stored on a computer readable medium. Some or all of these files may be provided to a manufacturing manager who manufactures devices based on these files. The resulting products include semiconductor wafers that are cut into semiconductor dies and packaged on semiconductor chips. The chips are then used in the devices described above. 6 illustrates certain example embodiments of an electronic device manufacturing process 600.

Physical device information 602 is received in manufacturing process 600 as in research computer 606. Physical device information 602 may include at least one physical of a system used in a semiconductor device, such as system 100 of FIG. 1, system 200 of FIG. 2, system 300 of FIG. 3, or any combination thereof. It may include design information indicating the characteristic. For example, the physical device information 602 can include physical parameters, material properties, and structural information input through a user interface 604 coupled to the research computer 606. Research computer 606 includes a processor 608, such as one or more processing cores, coupled to a computer readable medium, such as memory 610. The memory 610 may store computer readable instructions executable to cause the processor 608 to convert the physical device information 602 to conform to the file format and generate the library file 612.

In certain embodiments, library file 612 includes at least one data file that contains converted design information. For example, library file 612 is provided for use with system 100 of FIG. 1, system 200 of FIG. 2, system 300 of FIG. 3, or electronic design automation (EDA) tool 620. It can include a library of semiconductor devices including any combination of these.

Library file 612 can be used with EDA tool 620 in design computer 614 that includes a processor 616, such as one or more processing cores coupled to memory 618. EDA tool 620 allows a user of design computer 614 to use system 100 of FIG. 1, system 200 of FIG. 2, system 300 of FIG. 3, or any combination thereof in library file 612. And as processor executable instructions in memory 618 to design the circuit. For example, a user of the design computer 614 may enter circuit design information 622 through a user interface 624 connected to the design computer 614. Circuit design information 622 may include design information indicative of at least one physical characteristic of system 100 of FIG. 1, system 200 of FIG. 2, system 300 of FIG. 3, or any combination thereof. Can be. For illustrative purposes, the circuit design characteristic may include identifications of specific circuits and relationships with other elements in the circuit design, location information, feature size information, interconnect information, or other information indicative of the physical characteristics of the semiconductor device. . Design computer 614 may select a clock gating system based on design criteria such as power consumption, area, operating speed, or any combination thereof.

The design computer 614 may be configured to convert design information including circuit design information 622 to match the file format. For illustrative purposes, the file formation may include a database binary file format representing other information about the circuit layout in a hierarchical format such as two-dimensional geometric form, text labels, and a Graphic Data System (GDSII) file format. Design computer 614 includes information depicting system 100 of FIG. 1, system 200 of FIG. 2, system 300 of FIG. 3, or any combination thereof in addition to other circuits or information. It can be configured to generate a data file containing the converted design information, such as GDSII file 626. For illustrative purposes, the data file may include any additional electronic circuits and components within the system 100 of FIG. 1, the system 200 of FIG. 2, the system of FIG. 3, or a system-on-chip (SOC). It may include information corresponding to the SOC including a combination of.

GDSII file 626 is manufactured to produce system 100 of FIG. 1, system 200 of FIG. 2, system of FIG. 3, or any combination thereof, in accordance with the converted information of GDSII file 626. May be received in process 628. For example, the device production process provides the GDSII file 626 to the mask producers 630 to generate one or more masks, such as masks to be used for photolithography processing, shown as representative mask 632. It may include doing. Mask 632 may be used during the fabrication process to create one or more wafers 634, which may be tested and separated into dies, such as representative die 636. Die 636 includes circuitry including system 100 of FIG. 1, system 200 of FIG. 2, system of FIG. 3, or any combination thereof.

Die 636 may be provided to a packaging process 638 in which die 636 is integrated into representative package 640. For example, package 640 may include a single die 636 or multiple dies, such as a system-in-package (SIP) arrangement. Package 640 may be configured to conform to one or more standards or specifications, such as Joint Electron Device Engineering Council (JEDEC) standards.

Information related to package 640 may be distributed to various product designers, such as through a component library stored on computer 646. Computer 646 can include a processor 648, such as one or more processing cores, coupled to memory 610. Printed circuit board (PCB) tools may be stored as processor executable instructions in memory 610 to process PCB design information 642 received from a user of computer 646 via user interface 644. PCB design information 642 may include physical location information of a semiconductor device packaged on a circuit board, and the packaged platen device may include system 100 of FIG. 1, system 200 of FIG. 2, and FIG. 3. Corresponds to a package 640 that includes a system, or any combination thereof.

Computer 646 uses data such as GERBER file 652 with data including layouts of electrical connections, such as traces or vias, as well as physical location information of a semiconductor device packaged on a circuit board. Can be configured to convert PCB design information to generate a file, wherein the packaged conductor device is the system 100 of FIG. 1, the system 200 of FIG. 2, the system of FIG. 3, or any combination thereof. Corresponds to the package 640 including. In other embodiments, the data file generated by the converted PCB design information may have a format other than the GERBER format.

GERBER file 652 may be used to generate representative PCB 656 and thin PCBs, manufactured according to design information stored within GERBER file 652, and may be received in substrate assembly process 654. For example, the GERBER file 652 may be uploaded to one or more machines for performing the various steps of the PCB production process. PCB 656 may be populated with electronic components including package 640 to form a printed circuit assembly (PCA) 658 represented.

The PCA 658 may be installed with one or more electronic devices, such as the first representative electronic device 662 and the second representative electronic device 664 and received in the product manufacturing process 660. As one example, in a non-limiting example, the first representative electronic device 662, the second representative electronic device 664, or both, may be a set top box, music player, video player, entertainment unit, navigation device, communication device, It may be selected from a group of personal digital assistants, fixed location data units, and computers. In another example, in a non-limiting example, one or more of the electronic devices 662 and 664 are mobile telephones, hand-held personal communication systems (PCS) units, portable data units such as PDAs, global positioning System (GPS) capable devices, navigation devices, fixed position data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or remote units such as any combination thereof. Can be. Although the system 100 of FIG. 1, the system 200 of FIG. 2, the system of FIG. 3, or any combination thereof may be implemented as a remote unit in accordance with the instructions herein, the present disclosure is illustrative. It is not limited to units that have been built. Embodiments herein can be suitably used in any device including active integrated circuits including memory and on-chip circuits for testing and characterization.

Thus, the system 100 of FIG. 1, the system 200 of FIG. 2, the system 300 of FIG. 3, or any combination of these may be manufactured, processed, and described as described in the illustrative process 600. It can be installed in an electronic device. One or more aspects of the embodiments described in connection with FIGS. 1-5 may include memory 610 of research computer 606 as well as within library file 612, GDSII file 626, and GERBER file 652. Memory of one or more other computers or processors (not shown) used in various stages, such as memory 618 of design computer 614, memory 650 of computer 646, substrate assembly process 654. And other products, such as mask 632, die 636, package 640, PCA 658, prototype circuits or devices (not shown), Or one or more other physical embodiments, such as any combination thereof. While various representative stages of the product from the physical device design for the final product are shown, in other embodiments fewer stages may be used or additional stages may be included. Similarly, process 600 may be performed by a single entity or may be performed by one or more entities that perform the various steps of process 600.

Those skilled in the art will appreciate that the various exemplary logical blocks, modules, circuits, and algorithm steps described above may be implemented as electronic hardware, computer software, or combinations thereof. Various illustrative components, blocks, configurations, modules, circuits, and steps have been described in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement these functions in varying ways for each particular application, but such implementation decisions are not necessarily outside the scope of the invention.

The steps and algorithms of the methods described above may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules include random access memory (RAM); Magnetoresistive read-only memory (NRAM), flash memory; A read only memory (ROM); An electrically programmable ROM (EPROM); Electrically erasable programmable ROM (EEPROM); register; Hard disk; Portable disk; Compact disk ROM (CD-ROM); Or in any form of known tangible storage media. An exemplary storage medium is coupled to the processor such that the processor reads information from, and writes information to, the storage medium. In the alternative, the storage medium may be integral to the processor. These processors and storage medium are located in the ASIC. The ASIC may be located at the user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

The description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features presented herein.

Claims (47)

A clock gating circuit,
An input logic circuit having at least one input receiving at least one input signal and having an output coupled to an internal enable node;
A keeper circuit coupled to selectively hold a logical voltage level at the internal enable node, the keeper circuit including at least one switching element responsive to a gated clock signal; And
A gating element responsive to the logical voltage level and an input clock signal at the internal enable node to generate the gated clock signal,
The keeper circuit is configured to prevent a logical voltage level change at the internal enable node due to a current flow through the keeper circuit during a delay associated with the gating element. 2. The apparatus of claim 1, wherein the input logic circuit comprises a pullup circuit serially connected to a pulldown circuit through the internal enable node,
A first isolation element configured to selectively prevent the pull-up circuit from biasing an internal enable node at a logical high voltage level; And
A second isolation element configured to selectively prevent the pulldown circuit from biasing an internal enable node to a logical low level,
Wherein at least one of the first isolated element and the second isolated element is responsive to the gated clock signal. 2. The apparatus of claim 1, wherein the keeper circuit is configured to change a logical voltage level change at the internal enable node due to current flow through the keeper circuit during a delay period associated with the gating element when the input clock signal transitions. And a keeper isolation element configured to prevent. 2. The clock gating circuit of claim 1, wherein fewer than nine transistors toggle with each input clock signal transition. The keeper circuit of claim 1, wherein the keeper circuit
A p-channel metal-oxide-semiconductor (PMOS) transistor having a first terminal coupled to a supply, a control terminal coupled to receive the gated clock signal and a second terminal coupled to an input logic isolation element;
A first n-channel metal-oxide-semiconductor (NMOS) transistor having a first terminal coupled to the second terminal of the PMOS transistor;
An inverter having an input connected to a second terminal of the PMOS transistor and further having an output connected to a control terminal of the first NMOS transistor; And
A second NMOS transistor having a first terminal coupled to the first NMOS transistor and having a second terminal coupled to ground, the control terminal of the second NMOS transistor coupled to receive the input clock signal Clock gating circuit. 6. The clock gating circuit of claim 5 wherein the first terminal of the first NMOS transistor is coupled to the second terminal of the PMOS transistor via the input logic isolation element. The method of claim 1,
The keeper circuit
A PMOS transistor having a first terminal coupled to a supply, a control terminal coupled to receive the gated clock signal, and a second terminal coupled to an input logic isolation element; And
An NMOS transistor having a first terminal connected to the second terminal of the PMOS transistor via the input logic isolation element and having a second terminal connected to ground, wherein the control terminal of the NMOS transistor is configured to receive the clock signal. Coupled—clock gating circuit. As a system,
A NAND logic circuit having a first input coupled to receive a clock signal, an output coupled to provide a gated clock signal with a second input coupled to the first node; And
A keeper circuit coupled to provide an enable signal to the second input of the NAND logic circuit, wherein less than nine but less than four transistors toggle at each clock signal transition, and the And a keeper circuit is configured to prevent a logical voltage level change at the first node due to current flow through the keeper circuit during a delay associated with the NAND logic circuit. 9. The apparatus of claim 8, wherein the keeper circuit is
A PMOS transistor having a first terminal coupled to a supply and a control terminal coupled to receive the gated clock signal, the PMOS transistor having a second terminal coupled to an input logic isolation element;
A first NMOS transistor having a first terminal coupled with the second terminal of the PMOS transistor via the input logic isolation element;
An inverter having an input connected to a second terminal of the PMOS transistor and further having an output connected to a control terminal of the first NMOS transistor; And
A second NMOS transistor having a first terminal coupled to the first NMOS transistor and having a second terminal coupled to ground, wherein a control terminal of the second NMOS transistor is coupled to receive the clock signal. 9. The apparatus of claim 8, wherein the keeper circuit is
A PMOS transistor having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;
A first NMOS transistor having a first terminal coupled to the second terminal of the PMOS transistor;
An inverter having an input connected to a second terminal of the PMOS transistor and further having an output connected to a control terminal of the first NMOS transistor; And
A second NMOS transistor having a first terminal coupled to the first NMOS transistor and having a second terminal coupled to ground, wherein a control terminal of the second NMOS transistor is coupled to receive the clock signal. As an apparatus,
An input logic circuit having at least one input receiving at least one input signal and an output coupled to an internal enable node;
A keeper circuit coupled to selectively maintain a logical voltage level at the internal enable node, the keeper circuit including at least one switching element responsive to a gated clock signal; And
A semiconductor device comprising a gating element responsive to an input clock signal and the logical voltage level at the internal enable node to generate the gated clock signal;
And the keeper circuit is configured to prevent a logical voltage level change at the internal enable node due to the keeper circuit keeper circuit current flow during a delay associated with the gating element. The apparatus of claim 11 installed in a system-on-chip device. The apparatus of claim 11, wherein the input logic circuit, the keeper circuit, and the gating element are included in a communication device or computer in which the semiconductor device is installed. 12. The apparatus of claim 11, wherein not more than four transistors, the keeper circuit, and the gating element of the input logic circuit toggle with each input clock signal transition. 12. The keeper circuit of claim 11, wherein the keeper circuit is:
A first switching element having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal, the first switching element having a second terminal coupled to an input logic isolation element;
A second switching element having a first terminal connected to the first switching element via the input logic isolation element;
An inverter having an input connected to the second terminal of the first switching element and further having an output connected to the control terminal of the second switching element; And
A third switching element having a first terminal connected to the second switching element and having a second terminal connected to ground, wherein a control terminal of the third switching element is connected to receive the input clock signal. The method of claim 15,
The first switching element is a PMOS transistor;
The second switching element is an NMOS transistor; And
And the third switching element is a second NMOS transistor. 12. The apparatus of claim 11, wherein the keeper circuit is
A first field effect transistor (FET) having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;
A second FET having a first terminal coupled to the second terminal of the first FET through the input isolation element;
An inverter having an input connected to a second terminal of the first FET and further having an output connected to a control terminal of the second FET; And
A third FET having a first terminal coupled to the second FET and having a second terminal coupled to ground, wherein a control terminal of the third FET is coupled to receive the input clock signal. The method of claim 11, wherein the keeper circuit,
A PMOS transistor having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;
A first NMOS transistor having a first terminal coupled to the second terminal of the PMOS transistor;
An inverter having an input connected to a second terminal of the PMOS transistor and further having an output connected to a control terminal of the first NMOS transistor; And
A second NMOS transistor having a first terminal connected to the first NMOS transistor and having a second terminal connected to ground, wherein a control terminal of the second NMOS transistor is coupled to receive the input clock signal. 12. The apparatus of claim 11, wherein the keeper circuit is
A PMOS transistor having a first terminal coupled to a supply and a control terminal coupled to receive the gated clock signal;
A first NMOS transistor having a first terminal coupled with a second terminal of the PMOS transistor via an input logic isolation element;
An inverter having an input connected to a second terminal of the PMOS transistor and further having an output connected to a control terminal of the first NMOS transistor; And
A second NMOS transistor having a first terminal connected to the first NMOS transistor and having a second terminal connected to ground, wherein a control terminal of the second NMOS transistor is coupled to receive the input clock signal. As an apparatus,
Input logic means for receiving at least one input signal and providing an output coupled to an internal enable node;
Keeper means for selectively maintaining a logical voltage level at the inner enable node, the keeper means including at least one switching element responsive to a gated clock signal; And
Gating means for generating the gated clock signal;
The gating means responsive to the logical voltage level and an input clock signal at the inner enable node, and the keeper means at the inner enable node due to current flow through the keeper means during a delay associated with the gating means. And to prevent a logical voltage level change. The apparatus of claim 20 installed in a system-on-chip device. The apparatus of claim 20, wherein the apparatus is a semiconductor device installed in a communication device or a computer. 21. The method of claim 20,
The wikikeeper means,
First means for switching having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;
Second means for switching having a first terminal connected to a second terminal of the first means for switching;
Means for inverting having an input connected to a second terminal of the first means for switching and further having an output connected to a control terminal of the first means for switching;
Third means for switching having a first terminal connected to the first means for switching and having a second terminal connected to ground, the control terminal of the second means for switching being connected to receive the input clock signal; Which includes. As a method,
Receiving at least one input signal at an input logic circuit having at least one input and an output coupled to an internal enable node;
Generating a gated clock signal at a gating element responsive to a logical voltage level and an input clock signal at the internal enable node;
Selectively maintaining said logical voltage level at said internal enable node in response to said gated clock signal;
The selectively maintaining prevents a logical voltage level change at the inner enable node during a delay associated with the gating element. 25. The method of claim 24, wherein receiving the at least one input signal, selectively maintaining the logical voltage level, and generating the gated clock signal are performed in a processor installed in an electronic device. 25. The method of claim 24, further comprising selecting one of a first clock gating cell having a first keeper circuit or a second clock gating cell having a second keeper circuit based on at least one design criterion. And one clock gating cell comprises fewer transistors to toggle with each input clock signal toggle than the second clock gating cell. 27. The method of claim 26, wherein the at least one design criterion comprises power consumption. 27. The method of claim 26, wherein the at least one design criterion comprises an operating speed. 27. The method of claim 26, wherein the at least one design criterion comprises an area of the first clock gating cell or an area of a second clock gating cell. 27. The method of claim 26, wherein the first clock gating cell comprises no more than four transistors to toggle in response to each input clock signal toggle. 27. The method of claim 26, wherein less than half of the transistors of the first keeper circuit toggle in response to each input clock signal toggle. The method of claim 26, wherein the first keeper circuit,
A first field effect transistor (FET) having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;
A second FET having a first terminal coupled to the second terminal of the first FET through the input logic isolation element;
An inverter having an input connected to a second terminal of the first FET and further having an output connected to a control terminal of the second FET; And
A third FET having a first terminal coupled to the second FET and having a second terminal coupled to ground, wherein a control terminal of the third FET is coupled to receive the input clock signal. The method of claim 26,
The first keeper circuit,
A PMOS transistor having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;
A first NMOS transistor having a first terminal coupled to the second terminal of the PMOS transistor;
An inverter having an input connected to a second terminal of the PMOS transistor and further having an output connected to a control terminal of the first NMOS transistor; And
A second NMOS transistor having a first terminal connected to the first NMOS transistor and having a second terminal connected to ground, wherein a control terminal of the second NMOS transistor is coupled to receive the input clock signal. The method of claim 26,
The first keeper circuit,
A PMOS transistor having a first terminal coupled to a supply and a control terminal coupled to receive the gated clock signal;
A first NMOS transistor having a first terminal coupled with a second terminal of the PMOS transistor via an input logic isolation element;
An inverter having an input connected to a second terminal of the PMOS transistor and further having an output connected to a control terminal of the first NMOS transistor; And
A second NMOS transistor having a first terminal connected to the first NMOS transistor and having a second terminal connected to ground, wherein a control terminal of the second NMOS transistor is coupled to receive the input clock signal. As a method,
A first step of receiving at least one input signal in an input logic circuit having at least one input and an output coupled to an internal enable node;
A second step of generating a gated clock signal at a gating element responsive to an input clock signal and a logical voltage level at the internal enable node; And
A third step of selectively maintaining said logical voltage level at said internal enable node in response to said gated clock signal,
Maintaining the selectively prevents a logical voltage level change at the inner enable node during a delay associated with the gating element. 36. The method of claim 35, wherein the first step, the second step, and the third step are performed by a processor installed in an electronic device. A computer-readable tangible medium storing instructions executable by a computer, wherein the instructions are
Instructions executable by the computer to provide the at least one input signal to an input logic circuit of a clock gating cell to generate a gated clock signal based on at least one input signal, the input logic circuit being internal Has an output connected to the enable node,
The clock gating cell comprises a keeper circuit for selectively maintaining a logical voltage level at the internal enable node using at least one switching element in response to a gated clock signal;
The clock gating cell comprises gating circuitry configured to generate the gated clock signal in response to the logical voltage level and an input clock signal at the internal enable node;
And the keeper circuit is configured to prevent a logical voltage level change at the internal enable node due to a current flow through the keeper circuit during a delay associated with the gating element. 38. The computer-readable medium of claim 37, wherein the instructions are executable by a processor installed in a communication device or computer. As a method,
Receiving design information indicative of at least one physical property of the semiconductor device;
Converting the design information to conform to a file format; And
Generating a data file including the converted design information,
Wherein the semiconductor device
An input logic circuit having at least one input receiving at least one input signal and an output coupled to an internal enable node;
A keeper circuit coupled to selectively maintain a logical voltage level at the internal enable node, the keeper circuit including at least one switching element responsive to a gated clock signal; And
A gating element responsive to the logical voltage level and an input clock signal at the internal enable node to generate the gated clock signal;
And the keeper circuit is configured to prevent a logical voltage level change at the internal enable node due to current flow through the keeper circuit during a delay associated with the gating element. 40. The method of claim 39, wherein the data file comprises a GDSII format. 40. The method of claim 39, further comprising manufacturing the semiconductor device in accordance with the converted design information. As a method,
Receiving design information including physical placement information of a packaged semiconductor device on a circuit board; And
Converting the design information to produce a data file,
The packaged semiconductor device,
An input logic circuit having at least one input receiving at least one input signal and an output coupled to an internal enable node;
A keeper circuit coupled to selectively maintain a logical voltage level at the internal enable node, the keeper circuit including at least one switching element responsive to a gated clock signal; And
A gating element responsive to the logical voltage level and an input clock signal at the internal enable node to generate the gated clock signal;
And the keeper circuit is configured to prevent a logical voltage level change at the inner enable node due to a current flow through the keeper circuit during a delay associated with the gating element. 43. The method of claim 42, wherein the data file has a GERBER format. 43. The method of claim 42, further comprising manufacturing the circuit board configured to receive the packaged semiconductor device in accordance with the converted design information. 45. The method of claim 44, further comprising installing the circuit board in a communication device or computer. As a system,
An input logic circuit of a clock gating cell, the input logic circuit having at least one input for receiving at least one input signal and an output coupled to an internal enable node;
A keeper circuit of the clock gating cell coupled to selectively maintain a logical voltage level at the internal enable node, the keeper circuit including at least one switching element responsive to a gated clock signal generated at the clock gating cell Wherein the clock gating cell comprises no more than four transistors toggling at each transition of an input clock signal,
And the keeper circuit is configured to prevent a logical voltage level change at the internal enable node due to current flow through the keeper circuit during a delay associated with the generation of a gated clock signal in the clock gating cell. 47. The apparatus of claim 46, wherein the keeper circuit is
A PMOS transistor having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;
A first NMOS transistor having a first terminal coupled to the second terminal of the PMOS transistor;
An inverter having an input connected to a second terminal of the PMOS transistor and further having an output connected to a control terminal of the first NMOS transistor; And
A second NMOS transistor having a first terminal coupled to the first NMOS transistor and having a second terminal coupled to ground, wherein a control terminal of the second NMOS transistor is coupled to receive the input clock signal.

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