KR101251994B1 - Liquid crystal display - Google Patents

Abstract

The present invention includes a substrate, a pixel electrode formed on the substrate, the pixel electrode including first and second subpixel electrodes, and a common electrode facing the pixel electrode, wherein the first subpixel electrode faces each other. A first side opposite to the side and the second side, and a pair of first hypotenuses formed at an oblique angle with the first side and the second side and meeting the first side and parallel to each other, wherein the second subpixel electrode faces each other And a second side, and a pair of first hypotenuses that meet the first side and are substantially parallel or perpendicular to a first hypotenuse of the first subpixel electrode, wherein the first side of the first and second subpixel electrodes is formed. The sides adjacent to each other, the length of the first side of the first and second subpixel electrodes are different from each other, and the first hypotenuse of the first subpixel electrode and the first hypotenuse of the second subpixel electrode are crossed with each other. to be. In the present invention, it is possible to make the electrode which can improve the aperture ratio while improving visibility. In addition, the liquid crystal control power is enhanced, and the response speed and transmittance are remarkably improved. And it can prevent image quality deterioration and it is easy to balance the colors.

LCD, Transmittance, Lateral Field, Zcell, 6 Holes, Visibility Structure

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of two subpixels of a liquid crystal display according to an exemplary embodiment of the present invention.

3 to 5 are layout views of a pixel electrode and a common electrode of a liquid crystal panel assembly according to various embodiments of the present disclosure.

6 is a plan view of a unit electrode that is the basis of various subpixel electrodes illustrated in FIGS. 3 to 5;

7A and 7B are layout views of a pixel electrode and a common electrode of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

8 is an equivalent circuit diagram of one pixel of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

9 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

FIG. 10 is a cross-sectional view of the liquid crystal panel assembly of FIG. 9 taken along the line X-X.

11 is an equivalent circuit diagram of one pixel of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

12 is a layout view of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

FIG. 13 is a cross-sectional view of the liquid crystal panel assembly of FIG. 12 taken along the line XIII-XIII.

14 is an equivalent circuit diagram of one pixel of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

15 is a layout view of a lower panel of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

16 is a layout view of an upper panel of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

FIG. 17 is a layout view of a liquid crystal panel assembly including the lower panel of FIG. 15 and the upper panel of FIG. 16.

FIG. 18 is a cross-sectional view of the liquid crystal panel assembly of FIG. 17 taken along the line XVIII-XVIII.

19 is a layout view of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

20 is an equivalent circuit diagram of one pixel of a liquid crystal display according to another exemplary embodiment of the present invention.

21 and 22 are layout views of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

<Description of Drawing>

12, 22: polarizing plates 11, 21: alignment film

71-79, 71c, 71e, 71g, 72d, 72f, 72h, 73d, 73f, 73h: common electrode incision

91-95, 91c, 91e, 91g, 92d, 93d, 92f, 93f, 92h, 93h: pixel electrode cutout

81, 81a, 81b, 82, 82a, 82b: contact auxiliary member

110, 210: substrate

121, 121a, 121b, 129a, 129b: gate line

124, 124a-124e: gate electrode 131, 131a-131e: sustain electrode line

137, 137a1, 137a2, 137b, 137ca, 137cb, 137d-137f: sustain electrode

140: gate insulating film 154, 154a-154e: semiconductor

163b, 163e, 165a, 165b, 165e: resistive contact member

171, 171a, 171b, 179, 179a, 179b: data line

173, 173a-173e: source electrode

175, 175a-175e, 177, 177a-177e, 178: drain electrode

180: shield

181a, 181b, 182, 182a, 182b, 185, 185a, 185b, 185c, 185d: contact hole

191, 191a-191h, 193: pixel electrode

220: light blocking member 230: color filter

250: overcoat 270: common electrode

300: liquid crystal panel assembly 400: gate driver

500: Data driver 600: Signal controller

800: a gradation voltage generating section

The present invention relates to a liquid crystal display device.

The liquid crystal display device is one of the most widely used flat panel display devices, and includes two display panels having an electric field generating electrode such as a pixel electrode and a common electrode, and a liquid crystal layer interposed therebetween. The liquid crystal display displays an image by applying a voltage to the electric field generating electrode to generate an electric field in the liquid crystal layer, thereby determining the orientation of the liquid crystal molecules in the liquid crystal layer and controlling the polarization of the incident light.

The liquid crystal display device further includes a switching element connected to each pixel electrode, and a plurality of signal lines such as a gate line and a data line for controlling the switching element to apply a voltage to the pixel electrode.

Among such liquid crystal display devices, a liquid crystal display device having a vertically aligned mode in which the long axis of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels without an electric field applied to the liquid crystal display device is gaining attention due to its large contrast ratio and wide reference viewing angle. . Herein, the reference viewing angle means a viewing angle with a contrast ratio of 1:10 or a luminance reversal limit angle between gradations.

Specific methods for implementing a wide reference viewing angle in a vertical alignment liquid crystal display include a method of forming an incision in the field generating electrode and a method of forming protrusions on or under the field generating electrode. Since the cutout and the protrusion determine the tilt direction of the liquid crystal molecules, the reference viewing angle can be widened by appropriately arranging them and dispersing the tilt direction of the liquid crystal molecules in various directions.

However, the portion with the protuberance and the incision is difficult to transmit light, and the larger the number, the lower the aperture ratio. In order to increase the aperture ratio, an ultra-high opening ratio structure in which a pixel electrode is widened is proposed. However, in this case, the distance between the pixel electrodes is close and the distance between the pixel electrode and the data line is also close, so that a strong lateral field is formed near the edge of the pixel electrode. Due to this lateral electric field, the alignment of the liquid crystal molecules is disturbed, resulting in texture or light leakage and a long response time.

In addition, the liquid crystal display of the vertical alignment mode is less lateral visibility than the front visibility. For example, in the case of a patterned vertically aligned (PVA) type liquid crystal display device having an incision, the image becomes brighter toward the side, and in severe cases, the luminance difference between the high grays is disappeared, and the picture may be clumped.

SUMMARY OF THE INVENTION It is an object of the present invention to improve the response rate and transmittance while increasing the aperture ratio of a liquid crystal display device.

Another technical problem to be achieved by the present invention is to improve side visibility.

A liquid crystal display according to an exemplary embodiment of the present invention includes a substrate, a pixel electrode formed on the substrate, the pixel electrode including first and second subpixel electrodes, and a common electrode facing the pixel electrode. The pixel electrode has a first side and a second side facing each other, and a pair of first hypotenuses that form an oblique angle with the first side and the second side and meet the first side and are parallel to each other. The electrode has a first side and a second side facing each other, and a pair of first hypotenuses that meet with the first side and are substantially parallel or perpendicular to a first hypotenuse of the first subpixel electrode. First sides of the second subpixel electrodes are adjacent to each other, lengths of the first sides of the first and second subpixel electrodes are different from each other, and a first hypotenuse of the first subpixel electrode and a first side of the second subpixel electrode are different from each other. 1 hypotenuses are staggered.

The light emitting device may further include a polarizer having a polarization axis substantially 45 ° with the first hypotenuse of the first subpixel electrode and the first hypotenuse of the second subpixel electrode.

The center of the first side of the first subpixel electrode may be aligned with the center of the first side of the second subpixel electrode.

The first subpixel electrode may further have a pair of second hypotenuses that meet at a right angle with the first hypotenuse of the first subpixel electrode, wherein the second subpixel electrode is the first of the second subpixel electrode. It may further have a pair of second hypotenuses that meet at a right angle to the hypotenuse. The first hypotenuse of the first subpixel electrode may be perpendicular to the first hypotenuse of the second subpixel electrode.

The second subpixel electrode may include first and second electrode pieces separated from each other with the first subpixel electrode interposed therebetween.

The first electrode piece may have a first hypotenuse of the second subpixel electrode, and the second electrode piece may have a pair of second hypotenuses perpendicular to the first hypotenuse of the second subpixel electrode.

The first hypotenuse of the first subpixel electrode may be parallel to the first hypotenuse of the second subpixel electrode.

The height of the first subpixel electrode and the height of the second subpixel electrode may be substantially the same.

The length of the first side of the second subpixel electrode may be 1.8 to 2 times the length of the second side of the first subpixel electrode.

The distance between the first subpixel electrode and the second subpixel electrode may be 5.5-7.5 μm.

The method may further include a first inclination direction determining member formed on the common electrode.

The first oblique direction determining member may include a plurality of first cutouts that cross each of the first and second subpixel electrodes and have diagonal portions that are substantially parallel to first hypotenuses of the first and second subpixel electrodes. Can be.

The first cutout may have a width of 9.5-10.5 μm.

The first cutout may be connected to an oblique part of the first cutout part and overlap a first side and a second side of the first and second subpixel electrodes and have an angle greater than 135 degrees with the diagonal part. The branch may further comprise a termination.

The display apparatus may further include a second oblique direction determining member formed on the second subpixel electrode.

The second oblique direction determining member may include a second cutout that bisects the second subpixel electrode and has an oblique portion that is substantially parallel to the first hypotenuse of the second subpixel electrode.

The width of the second cutout may be 8-10 μm.

A sustain electrode formed on the substrate, wherein the sustain electrode is positioned at a boundary between a first subpixel electrode and a second subpixel electrode adjacent in a row direction, and an end portion of the first cutout overlaps the sustain electrode; The distance between the side of the sustain electrode and the side of the terminal adjacent thereto may be 1 μm or more.

The distance between the oblique portion of the first cutout portion and the first hypotenuse of the first or second subpixel electrode, and the distance between the diagonal portion of the second cutout portion and the diagonal portion of the first cutout portion may be 25-40 μm.

The distance between the first cutout and the second cutout may be shorter than a distance between the first cutout and a first hypotenuse of the first or second subpixel electrode.

The distance between the oblique portion of the second incision and the oblique portion of the first incision may be 20-30 μm, and the distance between the first hypotenuse of the second subpixel electrode and the oblique portion of the first incision may be 30-40 μm. .

The diagonal portion of the second cutout portion may be connected to the diagonal portion of the first cutout portion crossing the first subpixel electrode.

Voltages of the first subpixel electrode and the second subpixel electrode may be different from each other.

An area of the first subpixel electrode may be smaller than an area of the second subpixel electrode, and a voltage of the first subpixel electrode may be higher than a voltage of the second subpixel electrode.

An area of the second subpixel electrode may be 1.8 to 2 times the area of the first subpixel electrode.

The first subpixel electrode and the second subpixel electrode may receive different data voltages obtained from one image information.

A first thin film transistor connected to the first subpixel electrode, a second thin film transistor connected to the second subpixel electrode, a first signal line connected to the first thin film transistor, and connected to the second thin film transistor The display device may further include a second signal line and a third signal line connected to the first and second thin film transistors and intersecting the first and second signal lines.

The first and second thin film transistors may be turned on according to signals from the first and second signal lines, respectively, to transmit signals from the third signal line.

The first and second thin film transistors may be turned on according to signals from the third signal line, respectively, to transmit signals from the first and second signal lines.

The first subpixel electrode and the second subpixel electrode may be capacitively coupled.

The first thin film transistor is connected to the first subpixel electrode, the first signal line is connected to the first thin film transistor, and the second signal line is connected to the first thin film transistor and crosses the first signal line. It may include.

The first and second subpixel electrodes may be connected to each other.

A liquid crystal display according to another exemplary embodiment of the present invention includes a pixel electrode including a first and second subpixel electrodes each having a pair of parallel hypotenuses facing each other and arranged in a direction forming an oblique angle with the hypotenuse, the pixel A common electrode facing the electrode, a liquid crystal layer interposed between the pixel electrode and the common electrode, provided in the second subpixel electrode, parallel to the hypotenuse, and determining the inclination direction of the liquid crystal molecules of the liquid crystal layer; A plurality of first oblique direction determining members, and a first portion provided on the common electrode and substantially parallel to the hypotenuse, and disposed between the hypotenuse or between the hypotenuse and the first oblique direction determining member And a plurality of second oblique direction determining members for determining oblique directions of liquid crystal molecules of the liquid crystal layer, and before the first and second subpixels. Is divided into a plurality of subregions by the first and second oblique direction determining members and the hypotenuse, respectively, and the subregion number of the first subpixel electrode and the subregion number of the second subpixel electrode are different from each other. The hypotenuse of the first subpixel electrode and the hypotenuse of the second subpixel electrode are staggered from each other.

The light emitting device may further include a polarizer having a polarization axis substantially 45 ° with the first hypotenuse of the first subpixel electrode and the first hypotenuse of the second subpixel electrode.

The area of the subregion may be substantially the same.

The area of the subregion may be smaller as it is farther from the hypotenuse.

A liquid crystal display according to another exemplary embodiment of the present invention includes a substrate, a first pixel electrode formed on the substrate, the first pixel electrode including first and second subpixel electrodes, and a third and fourth subpixel electrode formed on the substrate. A second pixel electrode including a second electrode; and a common electrode facing the first and second pixel electrodes, wherein the first and third subpixel electrodes face each other; The first side and the second side has a pair of first hypotenuses formed at an oblique angle with one side and a second side and meet with the first side and parallel to each other, wherein the second and fourth subpixel electrodes face each other, and the A pair of first hypotenuses that meet the first side and are substantially parallel or perpendicular to a portion of the first hypotenuse of the first and third subpixel electrodes, wherein the first sides of the first and second subpixel electrodes are mutually Adjacent and first shifts of the third and fourth subpixel electrodes Adjacent to each other, lengths of first sides of the first and second subpixel electrodes are different from each other, lengths of first sides of the third and fourth subpixel electrodes are different from each other, and first hypotenuses of the first subpixel electrode And the first hypotenuse of the second subpixel electrode are staggered with each other, and the first hypotenuse of the third subpixel electrode is staggered with each other.

The first to fourth subpixel electrodes further have a pair of second hypotenuses that meet at a right angle with the first hypotenuse of the first to fourth subpixel electrodes, and include the first and third subpixel electrodes. The hypotenuses are perpendicular to the first hypotenuse of the second and fourth subpixel electrodes, respectively, and the first and second hypotenuses of the first subpixel electrode and the first and second hypotenuses of the third subpixel electrode, respectively. Adjacent to the first and second hypotenuses of the fourth subpixel electrode and the first and second hypotenuses of the second subpixel electrode, respectively, and the center of the first side of the first subpixel electrode is the second The center of the first side of the subpixel electrode may be aligned, and the center of the first side of the third subpixel electrode may be aligned with the center of the first side of the fourth subpixel electrode.

The second subpixel electrode includes first and second electrode pieces separated from each other with the first subpixel electrode interposed therebetween, and the fourth subpixel electrode is disposed between the third subpixel electrode. A first and second subpixel electrodes separated from each other, wherein the first and third subpixel electrodes further include a pair of second hypotenuses that meet at a right angle with the first hypotenuse of the first and third subpixel electrodes. The first electrode piece has a first hypotenuse of the second and fourth subpixel electrodes, and the second electrode piece is a pair of second perpendicular to the first hypotenuse of the second and fourth subpixel electrodes. The first hypotenuse of the first and third subpixel electrodes is parallel to the first hypotenuse of the second and fourth subpixel electrodes, and has a first hypotenuse of the first electrode piece of the second subpixel electrode. And the first hypotenuse of the first electrode piece of the fourth subpixel electrode are adjacent to each other, and the first and the first subpixel electrodes of the first subpixel electrode. The second hypotenuse and the first and second hypotenuses of the third subpixel electrode may be adjacent to each other.

The first side or the second side of the first to fourth subpixel electrodes and the first side or the second side may be substantially 45 ° or 135 °.

The heights of the first to fourth subpixel electrodes may be substantially the same.

The length of the first side of the second and third subpixel electrodes may be 1.8 to 2 times the length of the second side of the first and fourth subpixel electrodes.

A liquid crystal display according to another exemplary embodiment of the present invention includes a substrate, a pixel electrode formed on the substrate, the pixel electrode including first and second subpixel electrodes, and a common electrode facing the pixel electrode. The first and second subpixel electrodes each have a pair of curved sides parallel to each other, the common electrode includes a first cutout, the first and second subpixel electrodes include a second cutout, and the second The width of the incision is greater than the width of the first incision.

The width of the second cutout may be 1-2 μm greater than the width of the first cutout.

The width of the first cutout may be 9.5-10.5 μm, and the width of the second cutout may be 8-10 μm.

The distance between the first subpixel electrode and the second subpixel electrode may be 5.5-7.5 μm.

A sustain electrode formed on the substrate and positioned at a boundary portion between the first subpixel electrode and the second subpixel electrode, wherein the first cutout portion or the second cutout portion overlaps the sustain electrode; The distance between the side of the sustain electrode and the side of the portion where the first cutout portion or the second cutout portion overlaps with the sustain electrode may be 1 μm or more.

A portion overlapping the sustain electrode in the first cutout or the second cutout may be narrower toward the end.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

First, a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2. FIG.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of two subpixels of the liquid crystal display according to an exemplary embodiment of the present invention.

1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400 connected to the liquid crystal panel assembly 300, a data driver 500, a data driver A gradation voltage generator 800 connected to the gradation voltage generator 500, and a signal controller 600 for controlling the gradation voltage generator 800 and the gradation voltage generator 800.

The liquid crystal panel assembly 300 includes a plurality of signal lines (not shown) and a plurality of pixels PX connected to the plurality of signal lines (not shown) and arranged in a substantially matrix form when viewed in an equivalent circuit. 2, the liquid crystal display panel assembly 300 includes lower and upper display panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal line includes a plurality of gate lines (not shown) that transmit gate signals (also referred to as " scan signals ") and a plurality of data lines (not shown) that transmit data signals. The gate lines extend substantially in the row direction and are substantially parallel to each other, and the data lines extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX includes a pair of subpixels, and each subpixel includes liquid crystal capacitors C _LC a and C _LC b. At least one of the two subpixels includes a switching element (not shown) connected to the gate line, the data line, and the liquid crystal capacitors C _LC a and C _LC b.

The liquid crystal capacitor C _LC a / C _LC b has a sub-pixel electrode PEa / PEb of the lower panel 100 and a common electrode CE of the upper panel 200 as two terminals, and the sub-pixel electrodes PEa / PEb. And the liquid crystal layer 3 between the common electrode CE function as a dielectric. The pair of subpixel electrodes PEa and PEb are separated from each other and form one pixel electrode PE. The common electrode CE is formed on the entire surface of the upper panel 200 and receives the common voltage Vcom. The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 may be aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of primary colors (space division), or each pixel PX alternately displays a basic color (time division) So that the desired color is recognized by the spatial and temporal sum of these basic colors. Examples of basic colors include red, green, and blue. 2 illustrates that each pixel PX includes a color filter CF representing one of the primary colors in an area of the upper panel 200 as an example of spatial division. Unlike FIG. 2, the color filter CF may be formed above or below the subpixel electrodes PEa and PEb of the lower panel 100.

Polarizers (not shown) are provided on the outer surfaces of the display panels 100 and 200, and one of the two polarizers may be omitted in the case of a reflective liquid crystal display. The polarization axes of the two polarizers may be orthogonal, and in the case of the orthogonal polarizer, incident light entering the liquid crystal layer 3 having no electric field is blocked.

Referring back to FIG. 1, the gray voltage generator 800 generates a plurality of gray voltages (or reference gray voltages) related to the transmittance of the pixel PX.

The gate driver 400 is connected to the gate line of the liquid crystal panel assembly 300 to apply a gate signal Vg formed by a combination of the gate on voltage Von and the gate off voltage Voff to the gate line.

The data driver 500 is connected to a data line of the liquid crystal panel assembly 300 and selects a gray scale voltage from the gray voltage generator 800 and applies it to the data line as a data signal. However, when the gradation voltage generator 800 provides only a predetermined number of reference gradation voltages instead of providing all the voltages for all gradations, the data driver 500 divides the reference gradation voltage and supplies the gradation voltage And selects a data signal among them.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be directly mounted on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown) Or may be attached to the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP), or may be mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300. In addition, the drivers 400, 500, 600, 800 may be integrated into a single chip, in which case at least one of them, or at least one circuit element constituting them, may be outside of a single chip.

Next, detailed structures of the pixel electrode, the common electrode, and the color filter of the liquid crystal panel assembly described above will be described with reference to FIGS. 3 to 7B.

3 to 5 are layout views of a pixel electrode and a common electrode of a liquid crystal panel assembly according to various embodiments of the present invention, and FIG. 6 is a plan view of a unit electrode that is the basis of various subpixel electrodes illustrated in FIGS. 3 to 5. 7A and 7B are layout views of a pixel electrode and a common electrode of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

As shown in FIG. 3 to FIG. 7B, each pixel electrode 191 of the liquid crystal display according to the exemplary embodiment of the present invention is separated from each other and adjacent to each other in a pair of first and second columns. Sub-pixel electrodes 191a and 191b. The first and second subpixel electrodes 191a and 191b have cutouts 91, 92, 93, 94, and 95, and the common electrode 270 is formed with the first and second subpixel electrodes 191a and 191b. With opposing cutouts 71, 72, 73, 74, 75, 76, 77, 78, 79. In addition, the red, green, and blue color filters 230R, 230G, and 230B extend along the adjacent pixel electrodes 191 in the column direction.

The first subpixel electrode 191a and the second subpixel electrode 191b constituting one pixel electrode 191 may be connected to separate switching elements (not shown). Alternatively, the first subpixel electrode 191a may be connected to a switching element (not shown), and the second subpixel electrode 191b may be capacitively coupled to the first subpixel electrode 191a. Each switching element is connected to one gay line and one data line. 3 through 5, reference numeral 171 denotes a data line when two subpixel electrodes 191a and 191b are connected to their switching elements, respectively.

First, the arrangement shown in FIGS. 3 and 4 will be described.

3 and 4, the first and second subpixel electrodes 191a and 191b have the same shape as the unit electrode 193 illustrated in FIG. 6, or a pair of unit electrodes 193 adjacent in the row direction may be used as an example. For example, the shape is connected to the upper and lower ends, and the cutouts 71-73 of the common electrode 270 are substantially congruent with the cutout 70 shown in FIG. 6. The arrangement of the subpixel electrodes 191a and 191b and the cutouts 71-73 and 91-93 illustrated in FIGS. 3 and 4 is performed by arranging the unit electrodes 193 and the cutout 70 illustrated in FIG. 6. It is made repeatedly in the direction and column direction.

As shown in FIG. 6, the unit electrode 193 has a pair of curved edges 193o1 and 193o2 and a pair of transverse edges 193t and is approximately chevron. A pair of curved edges are convex edges 193o1 that meet the horizontal side (193t) and obtuse angle, for example, about 135 °, and concave edges that meet the acute angle, eg about 45 °, with the horizontal edge (193t). (concave edge) 193o2. The curved edges 193o1 and 193o2 have a pair of hypotenuses formed at substantially right angles so that the angle of bending is approximately right angles. The unit electrode 193 is formed with an incision 90 extending from the concave vertex CV on the concave side 193o2 to the convex vertex VV on the convex side 193o1 to approximately the center of the unit electrode 193. .

The cutout 70 of the common electrode 270 has a bent portion 70o having a bend point CP, a central horizontal portion 70t1 connected to a bend point CP of the bent portion 70o, and a bent portion 70o. It includes a pair of end horizontal portion 70t2 connected to both ends of the. The bent portion 70o of the incision 70 consists of a pair of oblique portions that meet at right angles and is substantially parallel to the bent sides 193o1 and 193o2 of the unit electrode 193, and the unit electrode 193 is left and right half. Divide into wealth The central horizontal portion 70t1 of the cutout 70 forms an obtuse angle, for example, about 135 ° with the bent portion 70o and extends toward the convex vertex VV of the unit electrode 193. The terminal horizontal portion 70t2 is aligned with the horizontal side 193t of the unit electrode 193 and forms an obtuse angle, for example, about 135 ° with the bent portion 70o.

The unit electrode 193 is divided into four sub-areas S1, S2, S3, and S4 by the cutouts 90 and 70, and each subregion S1-S4 is a cutout 70. Has two primary edges defined by the bent portion 70o and the bent edge 193o of the unit electrode 193. The distance between the periphery, i.e. the width W of the subregion, is preferably about 25-40 m.

The unit electrode 193 and the cutout 70 are approximately inverted symmetric with respect to an imaginary straight line (hereinafter referred to as a "horizontal center line") connecting the convex vertex (VV) and the concave vertex (CV) of the unit electrode 193.

3 and 4, the second subpixel electrode 191b has a shape in which two unit electrodes 193 are connected at an upper end and a lower end such that a concave side and a convex side are adjacent to each other. The gap and the cutout 90 connected to this gap form a new cutout 92. The cutout 92 may be regarded as including a bent portion and a horizontal portion connected to the second subpixel electrode 191b, which is bisected into a left half portion and a right half portion.

As shown in Fig. 6, the length L of the horizontal side 193t is defined as the length of the unit electrode, and the distance H between the horizontal side 193t is defined as the height of the unit electrode, and the subpixel including the unit electrode is shown. If the length and height of the electrode are also defined in the same manner, the heights of the first subpixel electrode 191a and the second subpixel electrode 191b illustrated in FIGS. 3 and 4 are substantially the same, and the second subpixel electrode 191b is the same. ) Is approximately 1.8 to 2 times the length L of the first subpixel electrode 191a. Therefore, the area of the second subpixel electrode 191b is approximately 1.8 to 2 times the area of the first subpixel electrode 191a.

3 and 4, the first subpixel electrode 191a and the second subpixel electrode 191b are alternately arranged in a row direction and a column direction.

In the row arrangement of the subpixel electrodes 191a and 191b, the horizontal centerline of the first subpixel electrode 191a and the horizontal centerline of the second subpixel electrode 191b are positioned on the same straight line, and the first subpixel is disposed on the same straight line. The convex side of the electrode 191a and the concave side of the second subpixel electrode 191b are adjacent, and the concave side of the first subpixel electrode 191a and the convex side of the second subpixel electrode 191b are adjacent.

In the column direction, since the lengths of the two subpixel electrodes 191a and 191b are different, various types of arrangements may be considered. One of them causes the curved sides of the two subpixel electrodes 191a and 191b to cross each other. In the example shown in FIG. 3, the first subpixel electrode 191a is aligned with the center of the second subpixel electrode 191b. It is arranged to be. The other is that one of two curved sides of the subpixel electrodes 191a and 191b are connected to each other. In the example shown in FIG. 4, the first subpixel electrode 191a and the second subpixel electrode 191b are connected to each other. The convex side (left side) and the concave side (right side) of are alternately arranged.

Specifically, in the example shown in FIG. 3, the bent portion of the cut portion 71 that bisects the second subpixel electrode 191b into the bent portion of the cut portion 71 that bisects the first subpixel electrode 191a. Leads to. Therefore, the convex side and the concave side of the first subpixel electrode 191a are connected to the bent portions of the cutouts 72 and 73 which bisect the unit electrodes of the second subpixel electrode 191b, respectively. In other words, the curved edges of the subpixel electrodes 191a and 191b or the curved portion of the cutout 92 in the two adjacent subpixel rows are connected to the curved portions of the cutouts 71-73 of the common electrode 270.

In contrast, in the example illustrated in FIG. 4, the convex side of the first subpixel electrode 191a of the cutout 92 dividing the convex side of the second subpixel electrode 191b or the second subpixel electrode 191 is bisected. The concave side of the first subpixel electrode 191a is connected to the concave side of the bent portion 92 of the cutout 92 of the second subpixel electrode 191b or the concave side of the second subpixel electrode 191b. In other words, the curved edges of the subpixel electrodes 191a and 191b or the curved portions of the cutout 92 are connected to each other in the two adjacent subpixel rows, and the curved portions of the cutouts 71-73 of the common electrode 270 are also connected to each other.

In FIG. 3, since the first subpixel electrode 191a and the second subpixel electrode 191b are aligned at the center, the data lines 171 are also regularly arranged at regular intervals. However, in FIG. 4, since the first subpixel electrode 191a having the length of 1: 2 and the second subpixel electrode 191b are alternately arranged left and right, the interval between the data lines 171 is also alternated at a ratio of 1: 2. appear.

Next, the arrangement shown in FIG. 5 will be described.

In the example illustrated in FIG. 5, one of the first and second subpixel electrodes 191a and 191b of each pixel electrode 191 illustrated in FIG. 3 is a pair of electrode pieces 191a1, 191a2, 191b1, and 191b2. The cut portions 71-73 of the common electrode 270 corresponding to the separated subpixel electrodes 191a and 191b, which are separated from each other and disposed above and below the other ones, are also cut in the same manner as the cut portions 74, 75, and 76. , 77, 78, 79, and are arranged at corresponding positions. The pair of separated electrode pieces 191a1, 191a2, 191b1, and 191b2 are electrically connected to each other.

Each of the electrode pieces 191a1, 191a2, 191b1, and 191b2 and the cut portions 74-79 transversely cut the subpixel electrodes 191a and 191b shown in FIG. 3 into the cut portions 91 and 93 or the cut portions 92. It is separated along the horizontal center line connecting the horizontal parts of the.

Each of the electrode pieces 191a1, 191a2, 191b1, and 191b2 has a pair of transverse sides substantially parallel to each other, and a pair of hypotenuses substantially parallel to each other, and are substantially parallelograms. In addition, the horizontal portions of the horizontal cutouts 91 and 93 or the cutouts 92 extending along the dividing line serve as boundaries between the electrode pieces 191a1, 191b1, 191a2 and 191b2, and are cut by the dividing line ( The two oblique portions forming the bent portion of 92 are oblique cut portions 94 and 95. Similarly, the cutout portions 74-79 of the common electrode 270 cut along the separation line include diagonal portions and horizontal portions at both ends thereof. The horizontal portions of the cutout portions 74-79 form obtuse angles with the oblique portions, and extend along the horizontal sides of the electrode pieces 191a1, 191a2, 191b1, and 191b2 while overlapping with each other. The arrangement shown in Figs. 7A and 7B will be described. do.

7A and 7B are basically the same as those shown in FIGS. 3 and 5, respectively, but the size of the subregion on the second subpixel electrode 191b is not constant. Specifically, the width of the subregion on the second subpixel electrode 191b is not uniform. Referring to the drawings, of the four subregions arranged in the row direction, the width L1 of the two subregions SA1 on the inner side is smaller than the width L2 of the two subregions SA2 on the outer side. Preferably, the width L1 of the inner subregion SA1 is about 20-30 μm, and the width L2 of the outer subregion SA2 is about 30-40 μm.

In this arrangement, the first and second subpixel electrodes 191a and 191b are alternately arranged in the row direction or the column direction so that the overall balance is well balanced and the subpixel electrodes 191a and 191b having an area ratio of 1: 2 are arranged. It can be arranged tightly without throwing away space and the opening ratio is high.

In addition, since the area of each color filter 230R, 230G, 230B is the same, it is easy to balance the colors.

Next, the operation of the liquid crystal display shown in Figs. 1 to 7B will be described in detail.

The signal controller 600 receives an input control signal for controlling the display of the input image signals R, G, and B from an external graphic controller (not shown). The input image signals R, G, and B contain luminance information of each pixel PX, and the luminance is a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ), or 64 (= 2 ⁶ ) It has gray. Examples of the input control signal include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 applies the input image signals R, G, and B to the operating conditions of the liquid crystal panel assembly 300 and the data driver 500 based on the input image signals R, G, and B and the input control signal. After appropriately processing and generating the gate control signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are processed. ) Is output to the data driver 500. The output video signal DAT has a predetermined number of values (or gradations) as a digital signal.

The gate control signal CONT1 includes at least one clock signal for controlling the output period of the scan start signal STV indicating the start of scanning and the gate-on voltage Von. The gate control signal CONT1 may further include an output enable signal OE that defines the duration of the gate on voltage Von.

The data control signal CONT2 is a horizontal synchronization start signal STH indicating the start of transmission of image data to a group of subpixels, a load signal LOAD and a data clock signal for applying a data signal to the liquid crystal panel assembly 300. (HCLK). The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " RVS) may be further included.

In response to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for a group of subpixels, and the gray level corresponding to each digital image signal DAT. By selecting the voltage, the digital image signal DAT is converted into an analog data signal and then applied to the corresponding data line.

The gate driver 400 applies a gate-on voltage Von to the gate line according to the gate control signal CONT1 from the signal controller 600 to turn on the switching element connected to the gate line. Then, the data signal applied to the data line is applied to the corresponding subpixel through the turned-on switching element.

3 to 7B, when the first subpixel electrode 191a and the second subpixel electrode 191b constituting one pixel electrode 191 are connected to separate switching elements, that is, each subpixel is connected to each other. In the case of having the switching element, the two subpixels may receive separate data voltages through the same data line at different times or through different data lines at the same time.

In contrast, when the first subpixel electrode 191a is connected to a switching element (not shown) and the second subpixel electrode 191b is capacitively coupled with the first subpixel electrode 191a, Only the subpixel including the first subpixel electrode 191a is applied with the data voltage through the switching element, and the subpixel including the second subpixel electrode 191b is changed according to the voltage change of the first subpixel electrode 191a. May have a varying voltage. In this case, the voltage of the first subpixel electrode 191a having a relatively small area is higher than the voltage of the second subpixel electrode 191b having a relatively large area.

In this way, when a potential difference occurs between both ends of the first or second liquid crystal capacitors C _LC a and C _LC b, a primary electric field substantially perpendicular to the surfaces of the display panels 100 and 200 is generated. Is generated). [Hereinafter, the pixel electrode 190 and the common electrode 270 will be referred to as " field generating electrode. &Quot; The angle of inclination is perpendicular, and the degree of change in polarization of incident light in the liquid crystal layer 3 varies according to the degree of inclination of the liquid crystal molecules. This change in polarization is represented by a change in transmittance by the polarizer, through which the liquid crystal display displays an image.

The angle at which the liquid crystal molecules are inclined depends on the intensity of the electric field. Since the voltages of the two liquid crystal capacitors C _LC a and C _LC b are different from each other, the angles at which the liquid crystal molecules are inclined are different, and thus the luminance of the two subpixels is different. Therefore, if the voltage of the first liquid crystal capacitor C _LC a and the voltage of the second liquid crystal capacitor C _LC b are properly adjusted, the image viewed from the side can be as close as possible to the image viewed from the front, that is, the side gamma curve Can be as close as possible to the front gamma curve, thereby improving side visibility.

In addition, when the area of the first subpixel electrode 191a to which a high voltage is applied is smaller than the area of the second subpixel electrode 191b, the side gamma curve may be closer to the front gamma curve. In particular, since the area ratio of the first and second subpixel electrodes 191a and 191b is approximately 1: 2, the side gamma curve becomes closer to the front gamma curve, thereby improving side visibility.

The direction in which the liquid crystal molecules are inclined is primarily referred to as the incisions 91-93 and 71-73 and the incisions 94 and 95 of the field generating electrodes 191 and 270 (in addition to the incision and the incision forward). Distortion) and subpixel electrodes 191a, 191b and electrode pieces 191a1, 191a2, 191b1, 191b2 (also referred to as "subpixel electrodes" together with subpixel electrodes and electrode pieces in the future) It is determined by the horizontal component produced. The horizontal component of the main electric field is substantially perpendicular to the sides of the cutouts 91-95 and 71-79 and the sides of the subpixel electrodes 191a, 191b, 191a1, 191a2, 191b1, and 191b2.

3 to 7B, since the liquid crystal molecules on each of the subregions divided by the cutouts 91-95 and 71-79 are inclined in a direction perpendicular to the periphery, the four directions are approximately four. Direction. When the direction in which the liquid crystal molecules are tilted is varied in this way, the reference viewing angle of the liquid crystal display device is increased.

The width of the subregion, that is, between the oblique portion of the cutouts 71-79 of the common electrode 270 and the hypotenuse or cutouts 91-95 of the subpixel electrodes 191a, 191b, 191a1, 191a2, 191b1, and 191b2. As described above, the interval of is preferably about 25-40 μm. In this way, while lowering the aperture ratio due to the cutouts 71-79, 91-95 and the like, the horizontal component of the main electric field can be appropriately utilized.

On the other hand, the direction of the secondary electric field generated by the voltage difference between the neighboring pixel electrode 191 is perpendicular to the periphery of the subregion. Thus, the direction of the negative electric field coincides with the direction of the horizontal component of the main electric field. As a result, the negative electric field between neighboring pixel electrodes 191 acts to strengthen the crystal in the oblique direction of the liquid crystal molecules. Therefore, the liquid crystal control power is enhanced compared to the pixel electrode of other structure, and even if the width of the subregion is widened as necessary, the response speed delay due to the increase in texture can be prevented.

However, the inner subregions of the second subpixel electrodes 191b, 191b1, and 191b2 are far from the boundary of the pixel electrode 191, and thus are less affected by the negative electric field. Therefore, as shown in FIGS. 7A and 7B, the width L1 of the inner subregion SA1 is narrower than the width of the outer subregion L2 so that the liquid crystals of the inner subregion SA1 and the outer subregion SA2 are reduced. All of the molecules can be properly controlled.

The operation of the liquid crystal display is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE). If a data signal is applied once), an image of one frame is displayed.

At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled such that the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame ( "Frame inversion").

In this case, the polarities of the data signals flowing through one data line are changed (eg, row inversion and point inversion) according to the characteristics of the inversion signal RVS within one frame, or the polarities of the data signals applied to a group of pixels are also different from each other. Can be different (eg invert columns, invert points). Among these, in the case of point inversion or the like, the polarities of the data voltages flowing to adjacent data lines are reversed, and the voltages of the respective data lines continue to reciprocate with positive and negative polarities. For example, in FIG. 3 and FIG. 4, the data voltage flowing to the left and right data lines 171 is positive (+), while the data voltage flowing to the middle data line 171 is negative (−). But their polarities are soon reversed and repeat over and over.

However, the adjacent pixel electrode 191 and the data line 171 form a parasitic capacitor, and the voltage of the pixel electrode 191 fluctuates due to the parasitic capacitor. For example, when the voltage of the data line 171 increases, the voltage of the pixel electrode 191 increases, and conversely, when the voltage of the data line 171 decreases, the voltage of the pixel electrode 191 also increases. Therefore, when the voltage of the data line 171 changes from negative polarity to positive polarity, the voltage of the pixel electrode 191 increases. On the contrary, when the voltage of the data line 171 changes from positive polarity to negative polarity, the voltage of the pixel electrode 191. This will descend. In the structures shown in FIGS. 3 and 4, since one pixel electrode 191 overlaps or adjoins two data lines 171 having different polarities, the parasitic capacitor with one data line 171 is the pixel electrode 191. The parasitic capacitor with the other data line 171 acts to lower the voltage of the pixel electrode 191.

The voltage variation of the pixel electrode 191 depends on the parasitic capacitance between the pixel electrode 191 and the data line 171, and the parasitic capacitance is proportional to the overlapping area of the pixel electrode 191 and the data line 171.

In FIG. 3 and FIG. 4, one pixel electrode 191 overlaps two data lines 171. However, in FIG. 3, the pixel electrode 191 is connected to two data lines 171. Since the overlapping area is almost the same, the voltage rise and voltage fall due to the parasitic capacitor cancel each other out so that the voltage variation of the pixel electrode 191 is small.

On the other hand, when a voltage is applied across the liquid crystal capacitors C _LC a and C _LC b, the liquid crystal molecules of the liquid crystal layer 3 try to rearrange the liquid crystal molecules in a stable state corresponding to the voltage, because the response speed of the liquid crystal molecules is slow. It takes some time to reach a stable state. If the voltage applied to the liquid crystal capacitors C _LC a and C _LC b is continuously maintained, the liquid crystal molecules continue to move to a stable state, during which the light transmittance (or luminance) also changes. The light transmittance also becomes constant when the liquid crystal molecules reach a stable state and no longer move.

When the pixel voltage in the stable state is called "target pixel voltage" and the light transmittance at this time is called "target light transmittance", the target pixel voltage and the target light transmittance have a one-to-one correspondence.

However, since the time for applying the data voltage by turning on the switching element of each pixel PX is limited, it is difficult for the liquid crystal molecules to reach a stable state while applying the data voltage. However, even when the switching element is turned off, the voltage difference across the liquid crystal capacitors C _LC a and C _LC b still exists and thus the liquid crystal molecules continue to move toward a stable state. As such, when the arrangement state of the liquid crystal molecules is changed, the dielectric constant of the liquid crystal layer 3 is changed, thereby changing the capacitance of the liquid crystal capacitors C _LC a and C _LC b. When the switching element is turned off, one terminal of the liquid crystal capacitors C _LC a and C _LC b is in a floating state. Therefore, if the leakage current is not taken into account, the liquid crystal capacitors C _LC a and C _LC b The stored total charge remains constant. Therefore, the capacitance change of the liquid crystal capacitor (C _LC a, _LC b C) results in a voltage, i.e. the pixel voltage variation across the liquid crystal capacitor (C _LC a, _LC b C).

Therefore, if the data voltage corresponding to the target pixel voltage on the basis of the stable state (hereinafter referred to as the "target data voltage") is applied to the pixel PX as it is, the actual pixel voltage will be different from the target pixel voltage. Can not get In particular, as the target transmittance differs from the transmittance originally possessed by the subpixel, the difference between the actual pixel voltage and the target pixel voltage becomes more severe.

Therefore, it is necessary to make the data voltage applied to the subpixel larger or smaller than the target data voltage. One of the methods is dynamic capacitance compensation (DCC).

The DCC is performed by the signal controller 600 or a separate image signal corrector, and the video signal of one frame (hereinafter referred to as "current image signal") for any subpixel is immediately before the subpixel. Based on the frame's video signal (hereafter referred to as the "previous image signal"), a corrected current image signal (hereafter referred to as the "modified image signal") is produced. The corrected video signal is basically determined by the experimental result, and the difference between the corrected current video signal and the previous video signal is generally larger than the difference between the current video signal before the correction and the previous video signal. However, when the current video signal and the previous video signal are the same or the difference between the two is small, the corrected video signal may be the same as the current video signal (that is, may not be corrected).

In this case, the data voltage applied to each subpixel by the data driver 500 becomes a voltage higher or lower than the target data voltage.

However, even with this method, it may be difficult to obtain the target transmittance. In this case, the liquid crystal molecules are inclined in advance by giving a voltage of a predetermined magnitude in advance (this is called pretilt and the voltage applied at this time is called pretilt voltage). ] Apply the voltage again.

To this end, the signal controller 600 or the image signal corrector may correct not only an image signal of a previous frame but also an image signal of a next frame (hereinafter, referred to as a "next image signal") when correcting an image signal of a current frame. Consider. For example, if the current video signal is the same as the previous video signal, but the next video signal is much different from the current video signal, the current video signal is corrected to prepare for the next frame.

The correction of the video signal and the data voltage may or may not be performed for the highest or lowest gray scale among the gray scales that the video signal can represent. Range of target data voltages necessary to obtain a target luminance range (or target transmittance range) that the gray level of the image signal is represented by the gray level voltage range generated by the gray voltage generator 800 to correct the highest gray level or the lowest gray level. You can use a wider method.

As described above, when the DCC is applied to the liquid crystal display according to the present exemplary embodiment, the response speed of the liquid crystal may be increased, thereby increasing the width of the subregion, thereby increasing the aperture ratio.

Next, a liquid crystal panel assembly according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 8 to 10 and FIGS. 1, 2, and 5 described above.

8 is an equivalent circuit diagram of one pixel of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

Referring to FIG. 8, the liquid crystal panel assembly according to the present exemplary embodiment includes a signal line including a plurality of pairs of gate lines GLa and GLb, a plurality of data lines DL, and a plurality of storage electrode lines SL, and a plurality of signal lines connected thereto. The pixel PX is included.

Each pixel PX includes a pair of subpixels PXa and PXb, and each subpixel PXa / PXb is a switching element connected to a corresponding gate line GLa / GLb and a data line DL, respectively. Qa / Qb, the liquid crystal capacitor C _LC a / C _LC b connected thereto, and the storage capacitor C _ST a / C connected to the switching element Qa / Qb and the storage electrode line SL. _ST b).

Each switching element Qa / Qb is a three-terminal element such as a thin film transistor provided in the lower panel 100, and a control terminal thereof is a gate line GLa / GLb. ), An input terminal is connected to the data line DL, and an output terminal is connected to the liquid crystal capacitors C _LC a / C _LC b and the storage capacitors C _ST a / C _ST b.

In the storage capacitor C _ST a / C _ST b, which serves as an auxiliary part of the liquid crystal capacitors C _LC a / C _LC b, the storage electrode line SL and the pixel electrode PE of the lower display panel 100 are insulated from each other. Are overlapped with each other, and a predetermined voltage such as the common voltage Vcom is applied to the storage electrode line SL. However, the storage capacitors C _ST a and C _ST b may be formed such that the subpixel electrodes PEa and PEb overlap the front gate line directly above the insulator.

Since the liquid crystal capacitors C _LC a and C _LC b have been described above, detailed descriptions thereof will be omitted.

In the liquid crystal display including the liquid crystal panel assembly, the signal controller 600 receives the input image signals R, G, and B for one pixel PX and outputs the two subpixels PXa and PXb. The image signal DAT may be converted and transmitted to the data driver 500. Alternatively, the gray voltage generator 800 separately sets the gray voltage sets for the two subpixels PXa and PXb and alternately provides them to the data driver 500, or alternately selects them in the data driver 500. Different voltages may be applied to the subpixels PXa and PXb. In this case, however, it is preferable to correct the image signal or to generate a set of gray voltages so that the composite gamma curve of the two subpixels PXa and PXb is close to the reference gamma curve at the front. For example, the composite gamma curve at the front side matches the reference gamma curve at the front side determined to be most suitable for this liquid crystal panel assembly, and the composite gamma curve at the side side is closest to the reference gamma curve at the front side.

Next, an example of the liquid crystal panel assembly illustrated in FIG. 8 will be described in detail with reference to FIGS. 9 and 10.

FIG. 9 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention, and FIG. 10 is a cross-sectional view of the liquid crystal panel assembly of FIG. 9 taken along the line X-X.

9 and 10, the liquid crystal panel assembly according to the present exemplary embodiment includes a lower panel 100 and an upper panel 200 facing each other and a liquid crystal layer 3 interposed between the two display panels 100 and 200. It includes.

First, the lower panel 100 will be described.

A plurality of pairs of first and second gate lines 121a and 121b and a plurality of pairs of first and second storage electrode lines 131a on an insulating substrate 110 made of transparent glass or plastic. , A plurality of gate conductors including 131b are formed.

The first and second gate lines 121a and 121b transmit gate signals and extend mainly in the horizontal direction, and are positioned above and below, respectively.

The first gate line 121a includes a plurality of first gate electrodes 124a protruding downward and a wide end portion 129a for connection with another layer or the gate driver 400. The second gate line 121b includes a plurality of second gate electrodes 124b protruding upward and a wide end portion 129b for connection with another layer or the gate driver 400. When the gate driver 400 is integrated on the substrate 110, the gate lines 121a and 121b may extend to be directly connected to the gate driver 400.

The first and second storage electrode lines 131a and 131b receive a predetermined voltage such as the common voltage Vcom, and the stem lines extending substantially in parallel with the gate lines 121a and 121b and the plurality of storage electrodes 137a1 and the plurality of the storage electrodes 137a1, 137a2, 137b). The first and second storage electrode lines 131a and 131b are positioned between the first gate line 121a and the second gate line 121b, and the stem line of the first storage electrode line 131a is the first gate line 121a. ) And the stem line of the second storage electrode line 131b is close to the second gate line 121b. The distance between the adjacent gate lines 121a and 121b and the storage electrode lines 131a and 131b and the distance between the adjacent storage electrode lines 131a and 131b are approximately equal.

The first storage electrode line 131a includes a plurality of pairs of first and second storage electrodes 137a1 and 137a2 extending straight down and up. The second storage electrode line 131b includes a plurality of third storage electrodes 137b extending straight down, and the third storage electrode 137b is positioned substantially in line with the second storage electrode 137a2. However, the shape and arrangement of the storage electrode lines 131a and 131b including the storage electrodes 137a1, 137a2 and 137b may be modified in various ways.

The gate conductors 121a, 121b, 131a, and 131b include aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper-based metals such as copper (Cu) and copper alloys, It may be made of molybdenum-based metals such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta), and titanium (Ti). However, they may have a multi-film structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having a low resistivity, for example, an aluminum-based metal, a silver-based metal, or a copper-based metal to reduce signal delay and voltage drop. Alternatively, the other conductive film is made of a material having excellent physical, chemical and electrical contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum metal, chromium, tantalum and titanium. A good example of such a combination is a chromium bottom film, an aluminum (alloy) top film, an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate conductors 121a, 121b, and 131 may be made of various other metals or conductors.

Side surfaces of the gate conductors 121a, 121b, 131a, and 131b are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate conductors 121a, 121b, 131a, and 131b.

On the gate insulating layer 140, a plurality of first and second island-like semiconductors 154a and 154b made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si), polycrystalline silicon, or the like are formed. It is. The first and second semiconductors 154a and 154b are positioned on the first and second gate electrodes 124a and 124b, respectively.

A pair of island-like ohmic contacts (not shown) are formed on each of the first semiconductors 154a, and a pair of island-like ohmic contacts 163b and 165b are formed on each of the second semiconductors 154b. ) Is formed. The ohmic contacts 163b and 165b may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are heavily doped, or may be made of silicide.

Side surfaces of the semiconductors 154a and 154b and the ohmic contacts 163b and 165b are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

Data including a plurality of data lines 171 and a plurality of pairs of first and second drain electrodes 175a and 175b on the ohmic contacts 163b and 165b and the gate insulating layer 140. A conductor is formed.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate lines 121a and 121b and the storage electrode lines 131a and 131b. Each data line 171 extends toward the first and second gate electrodes 124a and 124b, respectively, and has a plurality of pairs of first and second source electrodes 173a and 173b that are bent in a U or C shape. It includes an end portion 179 having a large area for connection with another layer or data driver 500. When the data driver 500 is integrated on the substrate 110, the data line 171 may be extended and directly connected thereto.

The first and second drain electrodes 175a and 175b are separated from each other and also separated from the data line 171. The first and second drain electrodes 175a and 175b face the first and second source electrodes 173a and 173b with respect to the first and second gate electrodes 124a and 124b.

The first drain electrode 175a extends straight up and down along the first storage electrode 137a1 starting from one end partially surrounded by the first source electrode 173a. The first drain electrode 175a includes an extension part 177a extending left and right along the first storage electrode line 131a near an intersection point with the first storage electrode line 131a.

The second drain electrode 175b extends along the third storage electrode 137b and the second storage electrode 137a2 starting from one end partially surrounded by the second source electrode 173b to extend the first gate line 121a. Ends across. The second drain electrode 175b includes an extension part 177b1 extending left and right along the second storage electrode line 131b near an intersection point with the second storage electrode line 131b, and the first gate line 121a. The opposite end portion 177b2 is slightly wider.

The first and second gate electrodes 124a and 124b, the first and second source electrodes 173a and 173b, and the first and second drain electrodes 175a and 175b are formed of the first and second semiconductors 154a and 154b. Together with the first and second thin film transistors (Qa / Qb), the channels of the first and second thin film transistors (Qa / Qb) are formed of the first and second source electrodes ( The first and second semiconductors 154a and 154b are formed between 173a and 173b and the first and second drain electrodes 175a and 175b.

The data conductors 171, 175a, and 175b are preferably made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof, and include a refractory metal film (not shown) and a low resistance conductive film ( It may have a multi-layer structure (not shown). Examples of the multilayer structure include a double film of a chromium or molybdenum (alloy) lower film and an aluminum (alloy) upper film, a molybdenum (alloy) lower film, an aluminum (alloy) intermediate film and a molybdenum (alloy) upper film. However, the data conductors 171, 175a, and 175b may be made of various other metals or conductors.

The data conductors 171, 175a, and 175b also preferably have their side surfaces inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 165a and 165b exist only between the semiconductors 154a and 154b below and the data conductors 171, 175a and 175b thereon and lower the contact resistance therebetween. The semiconductors 154a and 154b have portions exposed between the source electrodes 173a and 173b and the drain electrodes 175a and 175b and not covered by the data conductors 171, 175a and 175b.

A passivation layer 180 is formed on the data conductors 171, 175a, and 175b and the exposed semiconductors 154a and 154b. The protective film 180 is made of an inorganic insulating material or an organic insulating material and may have a flat surface. The organic insulator preferably has a dielectric constant of 4.0 or less, and may have photosensitivity. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portions of the semiconductors 154a and 154b while maintaining excellent insulating properties of the organic layer.

The passivation layer 180 includes a plurality of contact holes 182 exposing the end portion 179 of the data line 171 and a plurality of contact holes exposing the extension 177a of the first drain electrode 175a. 185a and a plurality of pairs of contact holes 185b1 and 185b2 exposing the extension portion 177b1 and the end portion 177b2 of the second drain electrode 175b, respectively. In the passivation layer 180 and the gate insulating layer 140, a plurality of contact holes 181a and 181b respectively exposing the end portions 129a and 129b of the gate lines 121a and 121b are formed.

A plurality of pixel electrodes 191 and a plurality of contact assistants 81a, 81b, and 82 are formed on the passivation layer 180. They may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver, chromium or an alloy thereof.

Each pixel electrode 191 includes first and second subpixel electrodes 191a and 191b, and the second subpixel electrode 191b includes lower and upper electrode pieces 191b1 and 191b2. A cutout 91a is formed in the first subpixel electrode 191a, and cutouts 92b and 93b are formed in the lower and upper electrode pieces 191b1 and 191b2, respectively.

The first subpixel electrode 191a is connected to the first drain electrode 175a through the contact hole 185a, and the first and second electrode pieces 191b1 and 191b2 of the second subpixel electrode 191b are connected to each other. The second drain electrode 175b is connected to each other through contact holes 185b1 and 185b2, respectively.

The first storage electrode line 131a, the extension 177a of the first drain electrode 175a, and the contact hole 185a are positioned on a straight line connecting the bending points of the first subpixel electrode 191a, and the second The storage electrode line 131b, the extended portion 177b1 of the second drain electrode 175b, and the contact hole 185b1 are positioned near the boundary between the first subpixel electrode 191a and the lower electrode piece 191b1. In addition, the first gate line 121a is positioned at the boundary between the first subpixel electrode 191a and the upper electrode piece 191b1, and the second gate line 131b is positioned at the boundary of the pixel electrode 191. The line connecting the bend points of the first subpixel electrode 191a or the boundary between the first and second subpixel electrodes 191a and 191b is the boundary of the subregion described above, and the arrangement of the liquid crystal molecules is disturbed in this portion. This arrangement can improve the aperture ratio while masking the texture.

Other shapes and arrangements of the pixel electrode 191 have been described above with reference to FIG. 5, and thus a detailed description thereof will be omitted.

The first and second subpixel electrodes 191a and 191b and the common electrode 270 of the upper panel 200 have a first and second liquid crystal capacitors C _LC a / C together with portions of the liquid crystal layer 3 therebetween. _LC b) is applied to maintain the applied voltage even after the thin film transistors Qa / Qb are turned off.

The first subpixel electrode 191a and the first drain electrode 175a connected thereto overlap the first storage electrode line 131a including the first storage electrode 137a1 with the gate insulating layer 140 therebetween to hold the first subpixel electrode 191a and the first drain electrode 175a therebetween. Form a capacitor (C _ST a). In addition, the second subpixel electrode 191b and the second drain electrode 175b connected thereto include a second storage electrode line including the second storage electrode 137a2 and the third storage electrode 137b with the gate insulating layer 140 interposed therebetween. Overlapping with 131b forms a second storage capacitor C _ST b. This first / second holding capacitor C _ST a / C _ST b enhances the voltage holding capability of the first / second liquid crystal capacitor C _LC a / C _LC b.

The contact auxiliary members 81a, 81b, and 82 are end portions 129a and 129b of the gate lines 121a and 121b and end portions 179 of the data line 171 through the contact holes 181a, 181b, and 182, respectively. Connected with The contact auxiliary members 81a, 81b, and 82 compensate for and protect the adhesion between the end portions 129a and 129b of the gate lines 121a and 121b and the end portions 179 of the data line 171 and the external device. do.

Next, the upper display panel 200 will be described.

A light blocking member 220 is formed on an insulating substrate 210 made of transparent glass or plastic. The light blocking member 220 may include a bent portion (not shown) corresponding to the curved side of the pixel electrode 191 and a rectangular portion (not shown) corresponding to the thin film transistor, and include light leakage between the pixel electrodes 191. And an opening region facing the pixel electrode 191 is defined.

A plurality of color filters 230 is also formed on the substrate 210 and the light blocking member 220. The color filter 230 is mostly present in an area surrounded by the light blocking member 230, and may extend long along the column of pixel electrodes 191. Each color filter 230 may display one of primary colors such as three primary colors of red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light blocking member 220. The cover film 250 can be made of (organic) insulation and prevents the color filter 230 from being exposed and provides a flat surface. The overcoat 250 may be omitted.

A common electrode 270 is formed on the lid 250. The common electrode 270 is made of a transparent conductor such as ITO or IZO and has a plurality of cutouts 71a, 72b, and 73b.

Shapes and arrangements of the cutouts 71a, 72b, and 73b of the common electrode 270 have been described above with reference to FIG. 3, and thus a detailed description thereof will be omitted.

The number of cutouts 71a, 72b, and 73b may vary depending on the design element, and the light blocking member 220 overlaps the cutouts 71a, 72b, and 73b so that light leakage near the cutouts 71a, 72b, and 73b may occur. Can be blocked.

Alignment layers 11 and 21 are formed on inner surfaces of the display panels 100 and 200, and they may be vertical alignment layers.

Polarizers 12 and 22 are provided on the outer surfaces of the display panels 100 and 200, and the polarization axes of the two polarizers 12 and 22 are orthogonal to each other and the curved sides of the subpixel electrodes 191a and 191b are approximately equal to each other. It is desirable to achieve an angle of 45 degrees. In the case of the reflection type liquid crystal display device, one of the two polarizers 12 and 22 may be omitted.

The liquid crystal display may include a polarizer 12 and 22, a phase retardation film, display panels 100 and 200, and a backlight unit (not shown) for supplying light to the liquid crystal layer 3.

The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 are aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field.

The cutouts 71a, 72b, 73b may be replaced by protrusions (not shown) or depressions (not shown). The protrusions may be made of organic or inorganic materials and may be disposed above or below the field generating electrodes 191 and 270.

Next, a liquid crystal panel assembly according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 11 to 13, and FIGS. 1, 2, and 5 described above.

11 is an equivalent circuit diagram of one pixel of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

Referring to FIG. 11, a liquid crystal panel assembly according to the present exemplary embodiment includes a signal line including a plurality of gate lines GL, a plurality of pairs of data lines DLa and DLb, and a plurality of storage electrode lines SL, and a plurality of signal lines connected thereto. The pixel PX is included.

Each pixel PX includes a pair of subpixels PXc and PXd, and each subpixel PXc / PXd is a switching element connected to a corresponding gate line GL and data line DLa / DLb, respectively. Qc / Qd, the liquid crystal capacitor C _LC c / C _LC d connected thereto, and the storage capacitor C _ST c / C _ST d connected to the switching element Qc / Qd and the storage electrode line SL. Include.

Each switching element Qc / Qd is also a three-terminal element such as a thin film transistor provided in the lower display panel 100, the control terminal of which is connected to the gate line GL, and the input terminal of the data line DLa / DLb. ), And the output terminal is connected to the liquid crystal capacitor (C _LC c / C _LC d) and the holding capacitor (C _ST c / C _ST d).

Operation of the liquid crystal display including the liquid crystal capacitors C _LC c and C _LC d and the storage capacitors C _ST c and C _ST d and the liquid crystal panel assembly as described above is substantially the same as in the previous embodiment, and thus the detailed description thereof will be omitted. Omit. However, in the liquid crystal display illustrated in FIG. 7, the two subpixels PXa and PXa constituting one pixel PX receive a data voltage with a parallax, whereas in the present embodiment, the two subpixels PXc and PXd The data voltage is applied at the same time.

Next, an example of the liquid crystal panel assembly illustrated in FIG. 11 will be described in detail with reference to FIGS. 12 and 13.

12 is a layout view of a liquid crystal panel assembly according to another exemplary embodiment of the present invention, and FIG. 13 is a cross-sectional view of the liquid crystal panel assembly of FIG. 12 taken along the line XIII-XIII.

12 and 13, the liquid crystal panel assembly according to the present exemplary embodiment includes a lower panel 100 and an upper panel 200 facing each other, a liquid crystal layer 3 and a display panel between the two panels. 100, 200) and a pair of polarizers 12, 22 attached to the outer surface.

The layered structure of the liquid crystal panel assembly according to the present embodiment is usually the same as that of the liquid crystal panel assembly shown in FIGS. 9 and 10.

Referring to the lower panel 100, a plurality of gate conductors including a plurality of gate lines 121 and a plurality of pairs of first and second storage electrode lines 131c and 131d are formed on the insulating substrate 100. . Each gate line 121 includes a plurality of pairs of first and second gate electrodes 124c and 124d and an end portion 129. The first storage electrode line 131c includes a plurality of first and second storage electrodes 137c1 and 137c2, and the second storage electrode line 131d includes a plurality of third storage electrodes 137d. The gate insulating layer 140 is formed on the gate conductors 121, 131c, and 131d. A plurality of linear semiconductors 151 including first and second protrusions 154c and 154d are formed on the gate insulating layer 140, and a plurality of linear ohmic contacts 161 having protrusions 163c thereon. A plurality of island type ohmic contact members 165c are formed. A data conductor including a plurality of pairs of first and second data lines 171a and 171b and a plurality of first and second drain electrodes 175c and 175d is formed on the ohmic contacts 161 and 165c. The first and second data lines 171a and 171b include a plurality of first and second source electrodes 173c and 173d and end portions 179a and 179b, respectively, and the first drain electrode 175c extends. 177c, and the second drain electrode 175d includes an extension 177d1 and an end portion 171d2. The passivation layer 180 is formed on the data conductors 171a, 171b, 175c, and 175d and the exposed semiconductors 154c and 154d, and the contact layer 181 is formed in the passivation layer 180 and the gate insulating layer 140. 182a, 182b, 185c, 185d1, and 185d2 are formed. The plurality of pixel electrodes 191 including the first and second subpixel electrodes 191c and 191d and the plurality of contact auxiliary members 81, 82a, and 82b are formed on the passivation layer 180. The second subpixel electrode 191d includes lower and upper electrode pieces 191d1 and 191d2, a cutout 91c is formed in the first subpixel electrode 191c, and a second subpixel electrode 191d. Incisions 92d and 93d are formed in the grooves. An alignment layer 11 is formed on the pixel electrode 191, the contact auxiliary members 81a, 81b, and 82, and the passivation layer 180.

Referring to the upper panel 200, a common electrode having a light blocking member 220, a plurality of color filters 230, an overcoat 250, and cutouts 71c, 72d, and 73d may be disposed on the insulating substrate 210. 270 and the alignment film 21 are formed.

However, in the liquid crystal panel assembly according to the present exemplary embodiment, the number of gate lines 121 is half and the number of data lines 171a and 171b is twice as compared with the liquid crystal panel assemblies shown in FIGS. 9 and 10. The first and second thin film transistors Qc and Qd connected to the first and second subpixel electrodes 191c and 191d forming one pixel electrode 191 have the same gate line 121 and different data lines ( 171a, 171b.

The first thin film transistor Qc is positioned on the right side of the first data line 171a, and the second thin film transistor Qd is positioned on the left side of the second data line 171b.

In addition, the semiconductors 154c and 154d extend along the data line 171 and the drain electrodes 175c and 175d to form the linear semiconductor 151, and the ohmic contact 163c extends along the data line 171. A linear ohmic contact 161 is formed. The linear semiconductor 151 has substantially the same planar shape as the data conductors 171a, 171b, 175c, and 175d and the ohmic contacts 161 and 165c thereunder.

In the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention, the data lines 171c and 171d, the drain electrodes 175c and 175c, the semiconductor 151 and the ohmic contacts 161 and 165c are photographed once. Form by process.

The photosensitive film used in such a photo process differs in thickness according to a position, and especially includes a 1st part and a 2nd part in order of decreasing thickness. The first portion is positioned in the wiring region occupied by the data lines 171c and 171d and the drain electrodes 175c and 175d, and the second portion is positioned in the channel region of the thin film transistor.

There may be various methods of varying the thickness of the photoresist film according to the position. For example, a method of providing a translucent area in addition to a light transmitting area and a light blocking area in a photomask is possible. have. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits or the distance between the slits is smaller than the resolution of the exposure machine used for the photographic process. Another example is a method using a reflowable photoresist. That is, a reflowable photoresist film is formed with a normal exposure mask having only a light-transmitting region and a light-shielding region, and then reflowed to flow into a region where the photoresist film is not left, thereby forming a thin portion.

In this way, a one-time photographic process can be reduced, thereby simplifying the manufacturing method.

Many features of the liquid crystal panel assembly shown in FIGS. 9 and 10 can also be applied to the liquid crystal panel assembly shown in FIGS. 12 and 13.

Next, a liquid crystal panel assembly according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 14 to 18 and FIGS. 1 to 3 described above.

14 is an equivalent circuit diagram of one pixel of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

Referring to FIG. 14, the liquid crystal panel assembly according to the present exemplary embodiment includes a signal line including a plurality of gate lines GL and a plurality of data lines DL and a plurality of pixels PX connected thereto.

Each pixel PX includes a pair of first and second subpixels PXe and PXf and a coupling capacitor Ccp connected between the two subpixels PXe and PXf.

The first subpixel PXe includes a switching element Q connected to a corresponding gate line GL and a data line DL, a first liquid crystal capacitor C _LC e, and a storage capacitor C _ST connected thereto. The second subpixel PXf includes a second liquid crystal capacitor C _LC f connected to the coupling capacitor Ccp.

The switching element Q is also a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line GL, and the input terminal of which is connected to the data line DL. The output terminal is connected to the liquid crystal capacitor C _LC e, the storage capacitor C _ST e and the coupling capacitor Ccp.

The switching element Q applies the data voltage from the data line DL to the first liquid crystal capacitor C _LC e and the coupling capacitor Ccp according to the gate signal from the gate line GL, and the coupling capacitor Ccp. ) Transfers this voltage to the second liquid crystal capacitor C _LC f.

The storage capacitor (C _ST e) applying the common voltage (Vcom) to be a capacitor (C _LC e, C _ST e, C _LC f, Ccp) and If represents the capacitance by the same reference numerals, and a first LC capacitor (C The voltage Ve charged in _LC e) and the voltage Vf charged in second liquid crystal capacitor C _LC f have the following relationship.

Vf = Ve ㅧ [Ccp / (Ccp + C _LC f)]

Since the value of Ccp / (Ccp + C _LC f) is less than 1, the voltage Vf charged in the second liquid crystal capacitor C _LC f is equal to the voltage Ve charged in the first liquid crystal capacitor C _LC e. Always small compared to This relationship holds true even when the voltage applied to the storage capacitor C _ST e is not the common voltage Vcom.

An appropriate ratio of the first liquid crystal capacitor C _LC e voltage Ve and the second liquid crystal capacitor C _LC f voltage Vf can be obtained by adjusting the capacitance of the coupling capacitor Ccp.

Next, the structure of the liquid crystal panel assembly will be described in detail with reference to FIGS. 15 to 19.

FIG. 15 is a layout view of a lower panel of the liquid crystal panel assembly according to another exemplary embodiment of the present invention, FIG. 16 is a layout view of an upper panel of the liquid crystal panel assembly according to another exemplary embodiment of the present invention, and FIG. 17 is a lower panel of FIG. 15. And a top view of the liquid crystal panel assembly including the upper panel of FIG. 16, FIG. 18 is a cross-sectional view of the liquid crystal panel assembly of FIG. 17 taken along the line XVIII-XVIII, and FIG. 19 is a liquid crystal display according to another exemplary embodiment of the present invention. It is a layout view of a display panel assembly.

15 to 19, the liquid crystal panel assembly according to the present exemplary embodiment also includes a lower panel 100 and an upper panel 200 facing each other and a liquid crystal layer 3 interposed between the two display panels.

First, the lower panel 100 will be described with reference to FIGS. 15 and 17 to 19.

A plurality of gate conductors including a plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the insulating substrate 110.

The gate line 121 mainly includes a plurality of gate electrodes 124e and end portions 129 extending in a horizontal direction and protruding up and down.

Each storage electrode line 131 extends substantially in parallel with the gate line 121 and is positioned at substantially the same distance from two adjacent gate lines 121. In the case of FIG. 17, the storage electrode line 131 includes a first type of sustain electrode 137e extending downward and a second type of sustain electrode 137f extending upward, and two types of sustain electrodes ( 137e and 137f are alternately arranged. In the case of FIG. 19, the storage electrode line 131 includes storage electrodes 137e and 137f extending upwards and downwards.

A gate insulating layer 140 is formed on the gate conductors 121 and 131, and a plurality of island-like semiconductors 154e are formed thereon. The semiconductor 154e is positioned over the gate electrode 124e.

A plurality of pairs of island type ohmic contact members 163e and 165e are formed on the semiconductor 154e.

A data conductor including a plurality of data lines 171 and a plurality of drain electrodes 175e and 175f is formed on the ohmic contacts 163e and 165e and the gate insulating layer 140.

The data line 171 mainly extends in the vertical direction and crosses the gate line 121 and the storage electrode line 131. Each data line 171 includes a plurality of curved portions protruding to the left, and each curved portion includes a pair of diagonal portions connected to each other to form a chevron, and the diagonal portion is connected to the gate line 121. Make an angle of about 45 degrees

Each data line 171 includes a plurality of source electrodes 173e and a wide end portion 179 extending toward the gate electrode 124e.

The drain electrodes 175e and 175f are separated from the data line 171 and face the source electrode 173 around the gate electrode 124. There are two types.

The first type of drain electrode 175e includes first and second bends 176e and 178 and an extension 177e. One end of the first bent portion 176e is partially surrounded by the source electrode 173e bent about the gate electrode 124e, and the other end is connected to the expansion portion 177e. The extension 177e is connected to the first and second bends 176e and 178 and overlaps the first type of storage electrode 137e. The second bend 178 extends upward from the extension 177e to the vicinity of the upper gate line 121. Each of the first and second bent portions 176e and 178 is connected to each other to form a pair of diagonal lines forming a chevron shape or an inequality (<) shape, and the pair of diagonal lines has an angle of about 45 degrees with the gate line 121. To achieve.

On the other hand, the second type drain electrode 175f includes only the bent portion 176f partially surrounded by the source electrode 173e and the extension portion 177f connected thereto. The bend 176f is also bent in an inequality (<) shape, and the extension 177f overlaps the second type of sustain electrode 137f.

The gate electrode 124e, the source electrode 173e, and the drain electrodes 175e and 175f form the thin film transistor Q together with the semiconductor 154e, and the channels of the thin film transistor Q are the source electrode 173e and the drain electrode. It is formed in the semiconductor 154e between 175e.

The passivation layer 180 is formed on the data conductors 171 and 175e and the exposed portion of the semiconductor 154e.

The passivation layer 180 is provided with a plurality of contact holes 182, 185e, and 185f exposing the end portions 179 of the data line 171 and the extended portions 177e and 177f of the drain electrodes 175e and 175f, respectively. In the passivation layer 180 and the gate insulating layer 140, a plurality of contact holes 181 exposing the end portions 129 of the gate line 121 are formed.

A plurality of pixel electrodes 191 and a plurality of contact auxiliary members 81a, 81b, and 82 are formed on the passivation layer 180.

Each pixel electrode 191 includes first and second subpixel electrodes 191e and 191f, and cutouts 91e, 92f and 93f are formed in each of the subpixel electrodes 191e and 191f.

The data line 171 passes through the row direction boundary of the pixel electrode 191, and particularly, the bent portion of the data line 171 is bent along the row direction boundary of the pixel electrode 191. When the data line 171 extends along the boundary of the pixel electrode 191, the horizontal component of the electric field generated between the data line 171 and the subpixel electrodes 191a and 191b is in the same direction as the horizontal component of the main electric field. Therefore, it acts to strengthen the crystal in the oblique direction of the liquid crystal molecules. Not only that, of course, a high aperture ratio can be ensured.

In addition, the storage electrode line 131 may be positioned near the boundary between the first and second subpixel electrodes 191a and 191b to cover the texture and improve the aperture ratio.

In the case of FIG. 19, the first subpixel electrode 191e includes a portion protruding upward or downward toward the sustain electrodes 137e and 137f.

Other shapes and arrangements of the pixel electrode 191 have been described above with reference to FIG. 3, and thus a detailed description thereof will be omitted.

The first subpixel electrode 191e is connected to the drain electrodes 175e and 175f through the contact holes 185e and 185f. In the example shown in FIG. 19, the protrusion of the first subpixel electrode 191e is connected to the drain electrodes 175e and 175f through the contact holes 185e and 185f. In addition, the bent portions 178 and 176f of the drain electrodes 175e and 175f overlap the second subpixel electrode 191f to form a coupling capacitor Ccp.

The first and second subpixel electrodes 191e and 191f and the common electrode 270 of the upper panel 200 have a first and second liquid crystal capacitor C _LC e / C together with a portion of the liquid crystal layer 3 therebetween. _LC f) is applied to maintain the applied voltage even after the thin film transistor Q is turned off.

The extended portions 177e and 177f of the drain electrode 175e connected to the first subpixel electrode 191e overlap the storage electrodes 137e and 137f with the gate insulating layer 140 interposed therebetween, and the storage capacitor C _ST e. To enhance the voltage holding capability of the liquid crystal capacitor (C _LC e).

The contact auxiliary members 81a, 81b, and 82 are end portions 129a and 129b of the gate lines 121a and 121b and end portions 179 of the data line 171 through the contact holes 181a, 181b, and 182, respectively. Connected with The contact auxiliary members 81a, 81b, and 82 compensate for and protect the adhesion between the end portions 129a and 129b of the gate lines 121a and 121b and the end portions 179 of the data line 171 and the external device. do.

Next, the upper panel 200 will be described with reference to FIGS. 16 to 19.

The light blocking member 220 is formed on the insulating substrate 210. The light blocking member 220 includes a horizontal portion corresponding to the gate line 121, a curved portion corresponding to the curved side of the pixel electrode 191, and a wide portion corresponding to the thin film transistor, and includes light leakage between the pixel electrode 191. And an opening region facing the pixel electrode 191.

A plurality of color filters 230 are further formed on the substrate 210 and the light blocking member 220, and an overcoat 250 is formed on the color filter 230 and the light blocking member 220. The common electrode 270 is formed on the overcoat 250 and has a plurality of cutouts 71e, 72f, and 73f.

Shapes and arrangements of the cutouts 71e, 72f, and 73f of the common electrode 270 have been described above with reference to FIG. 3, and thus a detailed description thereof will be omitted.

Alignment layers 11 and 21 are formed on inner surfaces of the display panels 100 and 200, and polarizers 12 and 22 are provided on outer surfaces of the display panels 100 and 200.

Many features of the liquid crystal panel assembly shown in FIGS. 9 and 10 may also be applied to the liquid crystal panel assembly shown in FIGS. 14 to 19.

Next, a liquid crystal panel assembly according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 20 to 22 and FIGS. 1 to 3 described above.

20 is an equivalent circuit diagram of one pixel of a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 20, the liquid crystal panel assembly according to the present exemplary embodiment includes lower and upper panel 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The lower panel 100 includes a signal line including a plurality of gate lines GL, a plurality of data lines DL, and a plurality of storage electrode lines SL, and each pixel includes a switching element Q and a liquid crystal connected thereto. A capacitor C _LC , and a storage capacitor C _ST connected to the switching element Q and the storage electrode line SL.

The switching element Q is also a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line GL, and the input terminal of which is connected to the data line DL. The output terminal is connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals, a pixel electrode PE of the lower panel 100 and a common electrode CE of the upper panel 200, and a liquid crystal layer between the pixel electrode PE and the common electrode CE. (3) functions as a dielectric. The common electrode CE is formed on the entire surface of the upper panel 200 and receives the common voltage Vcom. The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 may be aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field.

Since the operation of the liquid crystal display including the storage capacitor C _ST and the liquid crystal panel assembly as described above is substantially the same as in the previous embodiment, detailed description thereof will be omitted. However, in the liquid crystal display shown in FIG. 20, one pixel PX is not separated but connected to each other.

Next, an example of the liquid crystal panel assembly illustrated in FIG. 20 will be described in detail with reference to FIGS. 21 and 22.

21 and 22 are layout views of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

Referring to FIGS. 21 and 22, the liquid crystal panel assembly according to the present exemplary embodiment also includes a lower panel (not shown) and an upper panel (not shown) facing each other, and a liquid crystal layer (not shown) between the two display panels. ).

The layered structure of the liquid crystal panel assembly according to the present embodiment is usually the same as the layered structure of the liquid crystal panel assembly shown in FIGS. 15 to 19.

To describe the lower panel, a plurality of gate conductors including a plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate (not shown). Each gate line 121 includes a gate electrode 124 and an end portion 129 and each sustain electrode line 131 includes a sustain electrode 137. The gate insulating layer 140 is formed on the gate conductors 121 and 131. A plurality of semiconductors 154 are formed on the gate insulating layer 140, and a plurality of ohmic contacts (not shown) are formed thereon. A data conductor including a plurality of data lines 171 and a plurality of drain electrodes 175 is formed on the ohmic contact member and the gate insulating layer 140. The data line 171 includes a plurality of source electrodes 173 and end portions 179, and the drain electrode 175 includes a wide end portion 177. A passivation layer 180 is formed on the data conductors 171 and 175 and the exposed semiconductor 154, and a plurality of contact holes 181, 182, and 185 are formed in the passivation layer 180 and the gate insulating layer 140. It is. On the passivation layer 180, a plurality of pixel electrodes 191 including first and second subpixel electrodes 191g and 191h connected to each other and a plurality of contact assistants 81 and 82 are formed. A cutout 91g is formed in the first subpixel electrode 191g, and cutouts 92h and 93h are formed in the second subpixel electrode 191h. An alignment layer (not shown) is formed on the pixel electrode 191, the contact assistants 81 and 82, and the passivation layer 180.

An upper display panel (not shown) will be described. A light blocking member, a plurality of color filters, an overcoat, a common electrode having cutouts 71g, 72h, and 73h, and an alignment layer are formed on an insulating substrate.

However, in the liquid crystal panel assembly according to the present exemplary embodiment, as compared with the liquid crystal panel assembly illustrated in FIGS. 15 to 18, the storage electrode 137 extends up and down on the storage electrode line 131, and the neighboring pixel electrode 191 is also extended. It has the same shape. In addition, the first subpixel electrode 191g and the second subpixel electrode 191h of the pixel electrode 191 are connected to each other, and the bent portion 178 of the drain electrode 175e shown in FIGS. 15 to 19 is formed. There is no liquid crystal panel assembly according to the present embodiment. Therefore, the first and second subpixel electrodes 191g and 191h receive the same voltage.

In addition, the width of the cutouts 91g, 92h and 93h of the pixel electrode 191 is narrower than that of the cutout of the common electrode 270 when compared to the liquid crystal panel assembly illustrated in FIG. 21. The interval between the first subpixel electrode 191g and the second subpixel electrode 191h adjacent in the column direction is also narrower. Preferably, the distance or interval between the first subpixel electrode 191g and the second subpixel electrode 191h is about 5.5-7.5 μm.

As such, by reducing the gap between the cutouts 91g, 92h and 93h of the pixel electrode 191 and the gap between the subpixel electrodes 191g and 191h, the transmittance may be increased by increasing the actual transmission area of the light.

In addition, as shown in FIG. 22, the terminal horizontal portions of the cutouts 71g 72h and 73h of the common electrode 270 overlap with the pixel electrode 191 and have an angle greater than 135 degrees with the bent portion. In this way, the horizontal component of the main electric field near the terminal horizontal portion is closer to the direction in which most of the liquid crystal molecules are inclined over the corresponding subregion, thereby reducing the texture that may appear in the arrangement. The widths of the cutouts 71g 72h and 73h of the common electrode 270 are preferably about 9.5-10.5 μm.

The width of the cutouts 91g, 92h, and 93h is about 8-10 μm, and in particular, by narrowing to 8-9 μm, the transmittance can be increased by increasing the actual transmission area of light.

In addition, the width of the storage electrode 137 is narrower than that of the liquid crystal panel assembly illustrated in FIG. 21, and the boundary and the edges of the terminal horizontal portions of the cutouts 71g, 72h, 73h, and 92h positioned on the storage electrode 137 are also narrow. The distance between the boundaries of the electrodes 137 is 1 μm or more. That is, Lb> Laμ1μm. In this way, image quality deterioration due to texture occurring near the cutouts 71g, 72h, 73h, 92h can be prevented.

Many of the features of the liquid crystal panel assembly shown in Figs. 15 to 19 can be applied to the liquid crystal panel assembly shown in Figs. 20 to 22. The features of the liquid crystal panel assembly shown in Fig. 22 are shown in Figs. It may also be applied to a liquid crystal panel assembly or a liquid crystal panel assembly of any other structure.

As described above, in the present invention, it is possible to make the electrode which can improve the aperture ratio while improving visibility. In addition, the liquid crystal control power is enhanced, and the response speed and transmittance are remarkably improved. And it can prevent image quality deterioration and it is easy to balance the colors.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (50)

A first substrate and a second substrate facing each other, A pixel electrode formed on the first substrate and including first and second subpixel electrodes; and A common electrode on the second substrate and facing the pixel electrode / RTI &gt; The first subpixel electrode has a pair of first hypotenuses facing each other and a pair of first hypotenuses formed at an oblique angle with the first side and the second side and meeting the first side and being parallel to each other. The second subpixel electrode has a first side and a second side facing each other, and a pair of first hypotenuses that meet with the first side and are substantially parallel to or perpendicular to the first hypotenuse of the first subpixel electrode. , First sides of the first and second subpixel electrodes are adjacent to each other, The lengths of the first sides of the first and second subpixel electrodes are different from each other, The first hypotenuse of the first subpixel electrode and the first hypotenuse of the second subpixel electrode are crossed with each other. Liquid crystal display device. In claim 1, And a polarizer having a polarization axis substantially 45 ° with the first hypotenuse of the first subpixel electrode and the first hypotenuse of the second subpixel electrode. In claim 1, The center of the first side of the first subpixel electrode is aligned with the center of the first side of the second subpixel electrode. In claim 1, The first subpixel electrode further includes a pair of second hypotenuses that meet at a right angle with the first hypotenuse of the first subpixel electrode. In claim 4, The second subpixel electrode further includes a pair of second hypotenuses that meet at a right angle with the first hypotenuse of the second subpixel electrode. The method of claim 5, The first hypotenuse of the first subpixel electrode is perpendicular to the first hypotenuse of the second subpixel electrode. In claim 4, The second subpixel electrode includes first and second electrode pieces separated from each other with the first subpixel electrode interposed therebetween. 8. The method of claim 7, And the first electrode piece has a first hypotenuse of the second subpixel electrode, and the second electrode piece has a pair of second hypotenuses perpendicular to the first hypotenuse of the second subpixel electrode. In claim 8, The first hypotenuse of the first subpixel electrode is parallel to the first hypotenuse of the second subpixel electrode. The method according to any one of claims 1 to 9, The height of the first subpixel electrode and the height of the second subpixel electrode are substantially the same. In claim 10, The first side length of the second subpixel electrode is 1.8 to 2 times the length of the second side of the first subpixel electrode. The method according to any one of claims 1 to 9, The distance between the first subpixel electrode and the second subpixel electrode is 5.5-7.5μm. The method according to any one of claims 1 to 9, And a first oblique direction determining member formed on the common electrode. The method of claim 13, The first oblique direction determining member includes a plurality of first cutouts that cross each of the first and second subpixel electrodes and have oblique portions substantially parallel to first hypotenuses of the first and second subpixel electrodes. Liquid crystal display. The method of claim 14, The first cutting portion has a width of 9.5-10.5 μm. The method of claim 14, The first cutout is connected to an oblique part of the first cutout part and overlaps the first and second sides of the first and second subpixel electrodes, and has a side having an angle greater than 135 degrees with the oblique part. Containing more wealth Liquid crystal display device. The method of claim 14, And a second oblique direction determining member formed on the second subpixel electrode. The method of claim 17, And the second oblique direction determining member includes a second cutout that bisects the second subpixel electrode and has an oblique portion substantially parallel to a first hypotenuse of the second subpixel electrode. The method of claim 18, A width of the second cutout is 8-10 μm. The method of claim 18, A sustain electrode formed on the first substrate; The sustain electrode is positioned at a boundary between the first subpixel electrode and the second subpixel electrode adjacent to each other in a row direction. The first cutout further includes a termination connected to the diagonal portion, An end of the first cutout overlaps the sustain electrode; The distance between the side of the sustain electrode and the side of the terminal adjacent thereto is 1 μm or more. Liquid crystal display device. The method of claim 18, The distance between the oblique portion of the first cutout portion and the first hypotenuse of the first or second subpixel electrode, and the distance between the diagonal portion of the second cutout portion and the diagonal portion of the first cutout portion is 25-40 μm. . The method of claim 18, The distance between the first cutout and the second cutout is shorter than the distance between the first cutout and a first hypotenuse of the first or second subpixel electrode. The method of claim 22, The distance between the oblique portion of the second incision and the oblique portion of the first incision is 20-30 μm, The distance between the first hypotenuse of the second subpixel electrode and the oblique portion of the first cutout is 30-40 μm. Liquid crystal display device. The method of claim 18, The diagonal portion of the second cutout portion is connected to the diagonal portion of the first cutout portion that crosses the first subpixel electrode. The method according to any one of claims 1 to 9, The first subpixel electrode and the second subpixel electrode have different voltages. The method of claim 25, The area of the first subpixel electrode is smaller than the area of the second subpixel electrode, and the voltage of the first subpixel electrode is higher than the voltage of the second subpixel electrode. 26. The method of claim 26, The area of the second subpixel electrode is 1.8 to 2 times the area of the first subpixel electrode. The method of claim 25, The first subpixel electrode and the second subpixel electrode receive different data voltages obtained from one image information. The method of claim 28, A first thin film transistor connected to the first subpixel electrode, A second thin film transistor connected to the second subpixel electrode, A first signal line connected to the first thin film transistor, A second signal line connected to the second thin film transistor, and A third signal line connected to the first and second thin film transistors and intersecting the first and second signal lines Liquid crystal display further comprising. The method of claim 29, And the first and second thin film transistors are turned on according to the signals from the first and second signal lines, respectively, to transfer the signals from the third signal line. The method of claim 29, And the first and second thin film transistors are turned on in response to a signal from the third signal line, respectively, to transmit a signal from the first and second signal lines. The method of claim 25, The first subpixel electrode and the second subpixel electrode are capacitively coupled. 33. The method of claim 32, A first thin film transistor connected to the first subpixel electrode, A first signal line connected to the first thin film transistor, and A second signal line connected to the first thin film transistor and intersecting the first signal line Liquid crystal display further comprising. The method according to any one of claims 1 to 9, The first and second subpixel electrodes are connected to each other. A pixel electrode having a pair of parallel hypotenuses facing each other and including first and second subpixel electrodes arranged in a direction forming an oblique angle with the hypotenuse; A common electrode facing the pixel electrode; A liquid crystal layer interposed between the pixel electrode and the common electrode, A plurality of first inclined direction determining members provided in the second subpixel electrode, parallel to the hypotenuse, and configured to determine the inclined direction of the liquid crystal molecules of the liquid crystal layer, and A first portion provided in the common electrode and substantially parallel to the hypotenuse, and disposed between the hypotenuse or between the hypotenuse and the first oblique direction determining member, wherein the inclination of the liquid crystal molecules of the liquid crystal layer is inclined A plurality of second oblique direction determining members for determining the direction / RTI &gt; The first and second subpixel electrodes are divided into a plurality of subregions by the first and second oblique direction determining members and the hypotenuse, respectively. The subregion number of the first subpixel electrode and the subregion number of the second subpixel electrode are different from each other, The hypotenuse of the first subpixel electrode and the hypotenuse of the second subpixel electrode are staggered from each other. Liquid crystal display device. 35. The method of claim 35, And a polarizer having a polarization axis substantially 45 ° with the hypotenuse of the first subpixel electrode and the hypotenuse of the second subpixel electrode. 35. The method of claim 35, The area of the subregion is substantially the same. 35. The method of claim 35, The area of the subregion is smaller as it is farther from the hypotenuse. A first substrate and a second substrate facing each other, A first pixel electrode formed on the first substrate and including first and second subpixel electrodes; A second pixel electrode formed on the first substrate and including third and fourth subpixel electrodes, and A common electrode on the second substrate and facing the first and second pixel electrodes / RTI &gt; The first and third subpixel electrodes have a pair of first hypotenuses facing each other and a pair of first hypotenuses that form an oblique angle with the first and second sides and meet the first side and are parallel to each other. , The second and fourth subpixel electrodes may meet with the first and second sides facing each other and the first side and are substantially parallel or perpendicular to a portion of the first hypotenuse of the first and third subpixel electrodes. With a pair of first hypotenuses, First sides of the first and second subpixel electrodes are adjacent to each other, First sides of the third and fourth subpixel electrodes are adjacent to each other, The first side lengths of the first and second subpixel electrodes are different from each other, The first side lengths of the third and fourth subpixel electrodes are different from each other, The first hypotenuse of the first subpixel electrode and the first hypotenuse of the second subpixel electrode are alternated with each other, and the first hypotenuse of the third subpixel electrode and the first hypotenuse of the fourth subpixel electrode are alternated with each other. Liquid crystal display device. The method of claim 39, The first to fourth subpixel electrodes further have a pair of second hypotenuses that meet at a right angle with the first hypotenuse of the first to fourth subpixel electrodes. The first hypotenuse of the first and third subpixel electrodes is perpendicular to the first hypotenuse of the second and fourth subpixel electrodes, respectively, First and second hypotenuses of the first subpixel electrode and the first and second hypotenuses of the third subpixel electrode are adjacent to each other, and the first and second hypotenuses of the fourth subpixel electrode and the second portion The first and second hypotenuses of the pixel electrode are adjacent to each other, The center of the first side of the first subpixel electrode is aligned with the center of the first side of the second subpixel electrode, and the center of the first side of the third subpixel electrode is the first side of the fourth subpixel electrode. Aligned with the center Liquid crystal display device. The method of claim 39, The second subpixel electrode includes first and second electrode pieces separated from each other with the first subpixel electrode interposed therebetween, The fourth subpixel electrode includes first and second electrode pieces separated from each other with the third subpixel electrode interposed therebetween, The first and third subpixel electrodes further have a pair of second hypotenuses that meet at a right angle with the first hypotenuse of the first and third subpixel electrodes. The first electrode piece has a first hypotenuse of the second and fourth subpixel electrodes, and the second electrode piece is a pair of second hypotenuses perpendicular to the first hypotenuse of the second and fourth subpixel electrodes. To have, First hypotenuses of the first and third subpixel electrodes are parallel to first hypotenuses of the second and fourth subpixel electrodes, A first hypotenuse of the first electrode piece of the second subpixel electrode and a first hypotenuse of the first electrode piece of the fourth subpixel electrode are adjacent, The first and second hypotenuses of the first subpixel electrode and the first and second hypotenuses of the third subpixel electrode are adjacent to each other. Liquid crystal display device. 43. The method of claim 40 or 41 wherein The first side or the second side of the first to fourth sub-pixel electrode and the first side or the second side of the hypotenuse substantially constitute 45 ° or 135 °. 42. The method of any of claims 39-41, The first to fourth subpixel electrodes have substantially the same height as each other. The method of claim 43, The first side length of the second and third subpixel electrodes is 1.8 to 2 times the length of the first side of the first and fourth subpixel electrodes. delete delete delete delete delete delete

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