KR20070051036A - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device. The liquid crystal display according to the present invention includes a substrate, a plurality of pixel electrodes formed on the substrate and including first and second subpixel electrodes, respectively, and a plurality of data lines overlapping the pixel electrodes and extending in a straight line. The two data lines adjacent to each other overlap with the first subpixel electrode.

Column inversion, vertical crosstalk, data line, pixel electrode, parasitic capacitance

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of two subpixels of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is an equivalent circuit diagram of one pixel of a liquid crystal panel assembly according to an embodiment of the present invention.

4 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

5 and 6 are cross-sectional views of the liquid crystal display shown in FIG. 4 taken along the lines VV and VIVI.

7A to 7C are layout views of electrode pieces serving as a basis for the subpixel electrode of the liquid crystal panel assembly shown in FIGS. 4 to 6.

8 is a layout view of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

FIG. 9 is a layout view illustrating a pixel electrode of the liquid crystal panel assembly of FIG. 8. FIG.

10 is a layout view of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

11 is a layout view of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

<Description of Drawing>

12, 22: polarizing plates 11, 21: alignment film

71Ra1, 71Rb2, 71Ga, 71Gb, 71Ba, 71Bb2: common electrode cutout

91a-91b, 92: pixel electrode cutout

81, 81a, 81b, 82: contact auxiliary member

110 and 210: substrate 121a and 121b: gate line

124a and 124b: gate electrode

131a, 131b, 137a, and 137b: sustain electrode line 140: gate insulating film

154a. 154d: semiconductor

161, 163a, 163b, 165a, 165b: resistive contact member

171: data lines 173a and 173b: source electrode

175a, 175d, 176a, 176b, 177a, 177b: drain electrode

180: shield

181a, 181b, 182, 185a, 185b: contact hole

191Ra, 191Rb1, 191Rb2, 191Ga, 191Gb, 191Ba, 191Bb1, 191Bb2: pixel electrode

220: light blocking member 230: color filter

250: overcoat 270: common electrode

300: liquid crystal panel assembly 400: gate driver

500: data driver 600: signal controller

800: gray voltage generator

The present invention relates to a liquid crystal display device.

The liquid crystal display is one of the flat panel display devices most widely used. The liquid crystal display includes two display panels on which field generating electrodes, such as a pixel electrode and a common electrode, are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of the liquid crystal molecules of the liquid crystal layer and controlling the polarization of incident light to display an image.

The liquid crystal display also includes a switching element connected to each pixel electrode and a plurality of signal lines such as a gate line and a data line for controlling the switching element and applying a voltage to the pixel electrode.

Among such liquid crystal display devices, a liquid crystal display device having a vertically aligned mode in which the long axis of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels without an electric field applied to the liquid crystal display device is gaining attention due to its large contrast ratio and wide reference viewing angle. . Here, the reference viewing angle refers to a viewing angle having a contrast ratio of 1:10 or a luminance inversion limit angle between gray levels.

Means for implementing a wide viewing angle in a vertical alignment mode liquid crystal display include a method of forming a cutout in the field generating electrode and a method of forming a protrusion on the field generating electrode. Since the inclination and the projection can determine the direction in which the liquid crystal molecules are tilted, the reference viewing angle can be widened by using these to disperse the oblique directions of the liquid crystal molecules in various directions.

In the case of a patterned vertically aligned (PVA) type liquid crystal display with cutouts, in order to improve side visibility, one pixel is divided into two subpixels, two subpixels are capacitively coupled, and one subpixel is The method of applying the direct voltage and causing the voltage drop by capacitive coupling to the other subpixel to change the voltage of the two subpixels has been proposed to change the transmittance.

In such a liquid crystal display, a voltage is applied to two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. In this case, in order to prevent degradation caused by an electric field applied to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row by pixel, or pixel by pixel.

On the other hand, in a liquid crystal display, parasitic capacitance is generated between data lines of pixel electrodes. The parasitic capacitance affects the pixel electrode voltage. In particular, when the low gray voltage is applied, the luminance is changed by changing the subpixel electrode voltage to which the high voltage of the subpixel is applied. As a result, vertical cross talk occurs, and the vertical cross talk serves to deteriorate the quality of the liquid crystal display.

Accordingly, an object of the present invention is to prevent the generation of vertical crosstalk in the liquid crystal display.

According to an aspect of the present invention, there is provided a liquid crystal display device including a substrate, a plurality of pixel electrodes formed on the substrate, each pixel including first and second subpixel electrodes, and a plurality of linear electrodes overlapping the pixel electrodes. And an area where two adjacent data lines overlap each other with the first subpixel electrode.

The distance between neighboring data lines among the plurality of data lines may be different.

The pixel electrode includes first, second, and third pixel electrodes adjacent to each other, and the data line includes first, second, and third data lines connected to the first to third pixel electrodes, respectively. The distance between the first data line and the second data line may be shorter than the distance between the second data line and the third data line.

And a fourth data line adjacent to the third data line, wherein a distance between the second data line and the third data line is longer than a distance between the third data line and the fourth data line.

The display device may further include a plurality of branch parts connected to each of the data lines and overlapping the pixel electrode.

The pixel electrode includes first and second pixel electrodes adjacent to each other, the data line includes first and second data lines connected to the first and second pixel electrodes, respectively, and the first data. An area where a line overlaps the first subpixel electrode of the first pixel electrode may be the same as an area where a branch portion of the second data line overlaps the first subpixel electrode of the first pixel electrode.

The display device may further include an organic layer formed between the pixel electrode and the data line.

Each of the pixel electrodes includes at least two first electrodes and at least one second electrode adjacent to each other up and down, and each of the first and second electrodes includes at least two parallelogram electrodes having different inclination directions, The first subpixel electrode may include the first electrode, and the second subpixel electrode may include at least one of the first electrode and the second electrode.

The height of the first electrode and the height of the second electrode may be different from each other.

The first electrode of the first subpixel electrode may be adjacent to the left and right of the first electrode of the second subpixel electrode.

The electrode piece may include a pair of hypotenuses parallel to each other, and the hypotenuse of the electrode piece of the first electrode may be alternately arranged with the hypotenuse of the electrode piece of the second electrode.

Each of the pixel electrodes includes at least one first electrode and at least one second electrode adjacent to each other up and down, and each of the first and second electrodes includes at least two parallelogram electrodes having different inclination directions. The height of the first electrode and the height of the second electrode may be different from each other.

The first subpixel electrode may include the first electrode, and the second subpixel electrode may include two or more second electrodes.

The second subpixel electrode may include three second electrodes adjacent to each other and connected to each other, and the first subpixel electrode may be aligned with a second electrode positioned at the center of the second electrodes.

Each of the first and second subpixel electrodes includes at least two parallelogram electrodes having different inclination directions, and at least one of the electrode pieces of the second subpixel electrode is above or below the first subpixel electrode. It can be located at

The first subpixel electrode includes one right inclination parallelogram electrode piece and one left inclination parallelogram electrode piece, and the second subpixel electrode is three right inclination parallelogram electrode piece and three left inclination parallelogram shape. It may comprise an electrode piece.

The right inclined parallelogram electrode piece and the left inclination parallelogram electrode piece may be alternately arranged up and down.

The height of the electrode piece of the first subpixel electrode may be higher than the height of the electrode piece positioned above or below the first subpixel electrode among the electrode pieces of the second subpixel electrode.

An area of the second subpixel electrode may be larger than an area of the first subpixel electrode.

Voltages of the first subpixel electrode and the second subpixel electrode may be different from each other.

A first thin film transistor connected to the first subpixel electrode, a second thin film transistor connected to the second subpixel electrode, a first gate line connected to the first thin film transistor, and the second thin film transistor And a second gate line connected to the second gate line.

The first and second thin film transistors may be turned on according to the signals of the first and second gate lines, respectively, to transmit a signal from the data line.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of two subpixels of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of signal lines G _1a -G _nb , D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G _1a -G _nb , D ₁ -D _m , and arranged in a substantially matrix form. Include. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G _1a -G _nb and D ₁ -D _m are a plurality of gate lines G _1a -G _nb transmitting a gate signal (also called a "scanning signal") and a plurality of data lines transferring a data signal ( D ₁ -D _m ). The gate lines G _1a -G _nb extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX includes a pair of subpixels, and each subpixel includes liquid crystal capacitors Clca and Clcb. At least one of the two subpixels includes a switching element (not shown) connected to the gate line, the data line, and the liquid crystal capacitors Clca and Clcb.

The liquid crystal capacitor Clca / Clcb has two terminals of the subpixel electrode PEa / PEb of the lower panel 100 and the common electrode CE of the upper panel 200, and the subpixel electrodes PEa / PEb and the common electrode. The liquid crystal layer 3 between (CE) functions as a dielectric. The pair of subpixel electrodes PEa and PEb are separated from each other and form one pixel electrode PE. The common electrode CE is formed on the entire surface of the upper panel 200 and receives the common voltage Vcom. The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 may be aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. 2 illustrates that each pixel PX includes a color filter CF representing one of the primary colors in an area of the upper panel 200 as an example of spatial division. Unlike FIG. 2, the color filter CF may be formed above or below the subpixel electrodes PEa and PEb of the lower panel 100.

Polarizers (not shown) are provided on the outer surfaces of the display panels 100 and 200, and polarization axes of the two polarizers may be orthogonal to each other. In the case of a reflective liquid crystal display, one of the two polarizers 12 and 22 may be omitted. In the case of the orthogonal polarizer, incident light entering the liquid crystal layer 3 having no electric field is blocked.

Referring back to FIG. 1, the gray voltage generator 800 generates a plurality of gray voltages (or reference gray voltages) related to the transmittance of the pixel PX.

The gate driver 400 is connected to the gate line of the liquid crystal panel assembly 300 to apply a gate signal Vg formed by a combination of the gate on voltage Von and the gate off voltage Voff to the gate line.

The data driver 500 is connected to the data line of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and applies it to the data line as a data signal. However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, an example of the structure of the liquid crystal panel assembly will be described in detail with reference to FIGS. 3 to 8 and FIGS. 1 and 2 described above.

3 is an equivalent circuit diagram of one pixel of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the liquid crystal panel assembly according to the present exemplary embodiment includes a signal line including a plurality of pairs of gate lines GLa and GLb, a plurality of data lines DL, and a plurality of storage electrode lines SL, and a plurality of connected signal lines. The pixel PX is included.

Each pixel PX includes a pair of subpixels PXa and PXb, and each subpixel PXa / PXb is a switching element connected to a corresponding gate line GLa / GLb and a data line DL, respectively. Qa / Qb, a liquid crystal capacitor Clca / Clcb connected thereto, and a storage capacitor Csta / Cstb connected to the switching element Qa / Qb and the storage electrode line SL.

Each switching element Qa / Qb is a three-terminal element such as a thin film transistor provided in the lower panel 100, and a control terminal thereof is a gate line GLa / GLb. ), An input terminal is connected to a data line DL, and an output terminal is connected to a liquid crystal capacitor Clca / Clcb and a storage capacitor Csta / Cstb.

The storage capacitor Csta / Cstb, which serves as an auxiliary role of the liquid crystal capacitor Clca / Clcb, is formed by overlapping the storage electrode line SL and the pixel electrode PE provided in the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the storage electrode line SL. However, the storage capacitors Csta and Cstb may be formed such that the subpixel electrodes PEa and PEb overlap the front gate line directly above the insulator.

Since the liquid crystal capacitors Clca and Clcb have been described above, detailed descriptions thereof will be omitted.

In the liquid crystal display including the liquid crystal panel assembly, the signal controller 600 receives the input image signals R, G, and B for one pixel PX and outputs the two subpixels PXa and PXb. The image signal DAT may be converted and transmitted to the data driver 500. Alternatively, the gray voltage generator 800 separately sets the gray voltage sets for the two subpixels PXa and PXb and alternately provides them to the data driver 500, or alternately selects them in the data driver 500. Different voltages may be applied to the subpixels PXa and PXb. In this case, however, it is preferable to correct the image signal or to generate a set of gray voltages so that the synthesized gamma curves of the two subpixels PXa and PXb are close to the reference gamma curve at the front. For example, the composite gamma curve at the front side matches the reference gamma curve at the front side determined to be most suitable for this liquid crystal panel assembly, and the composite gamma curve at the side side is closest to the reference gamma curve at the front side.

Next, an example of the liquid crystal panel assembly illustrated in FIG. 3 will be described in detail with reference to FIGS. 4 to 6C and FIGS. 1 and 2 described above.

A plurality of pairs of first and second gate lines 121a and 121b and a plurality of pairs of first and second storage electrode lines 131a on an insulating substrate 110 made of transparent glass or plastic. , A plurality of gate conductors including 131b are formed.

The first and second gate lines 121a and 121b transmit gate signals and extend mainly in the horizontal direction, and are positioned above and below, respectively.

The first gate line 121a includes a plurality of first gate electrodes 124a protruding downward and a wide end portion 129a for connection with another layer or the gate driver 400. The second gate line 121b includes a plurality of second gate electrodes 124b protruding upward and a wide end portion 129b for connection with another layer or the gate driver 400. When the gate driver 400 is integrated on the substrate 110, the gate lines 121a and 121b may extend to be directly connected to the gate driver 400.

The storage electrode lines 131a and 131b receive a predetermined voltage such as the common voltage Vcom and mainly extend in the horizontal direction. The first and second storage electrode lines 131a and 131b are disposed below the first gate line 121a and the second gate line 121b, respectively. Each storage electrode line 131a and 131b includes storage electrodes 137a and 137b extending up and down. However, the shape and arrangement of the storage electrode lines 131a and 131b including the storage electrodes 137a and 137b may be modified in various forms.

The gate conductors 121a, 121b, 131a, and 131b include aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper-based metals such as copper (Cu) and copper alloys, and molybdenum It may be made of molybdenum-based metal such as (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta), and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having low resistivity, such as aluminum-based metal, silver-based metal, or copper-based metal, so as to reduce signal delay or voltage drop. In contrast, other conductive films are made of other materials, particularly materials having excellent physical, chemical and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, tantalum, and titanium. Good examples of such a combination include a chromium bottom film, an aluminum (alloy) top film, and an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate conductors 121a, 121b, 131a, and 131b may be made of various other metals or conductors.

Side surfaces of the gate conductors 121a, 121b, 131a, and 131b are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate conductors 121a, 121b, 131a, and 131b.

On the gate insulating layer 140, a plurality of first and second island-like semiconductors 154a and 154b made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si), polycrystalline silicon, or the like are formed. It is. The first and second semiconductors 154a and 154b are positioned on the first and second gate electrodes 124a and 124b, respectively.

A pair of island-like ohmic contacts (not shown) are formed on each of the first semiconductors 154a, and a pair of island-like ohmic contacts 163b and 165b are formed on each of the second semiconductors 154b. ) Is formed. The ohmic contacts 163b and 165b may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are heavily doped, or may be made of silicide.

Side surfaces of the semiconductors 154a and 154b and the ohmic contacts 163b and 165b are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

Data including a plurality of data lines 171 and a plurality of pairs of first and second drain electrodes 175a and 175b on the ohmic contacts 163b and 165b and the gate insulating layer 140. A conductor is formed.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate lines 121a and 121b and the storage electrode lines 131a and 131b. The distance between each data line 171 is not the same but different. Each data line 171 may have a different layer or data driver 500 than the plurality of pairs of first and second source electrodes 173a and 173b extending toward the first and second gate electrodes 124a and 124b, respectively. It includes a wide end portion 179 for the connection with the). When the data driver 500 is integrated on the substrate 110, the data line 171 may extend to be directly connected to the data driver 500.

The first and second drain electrodes 175a and 175b are separated from each other and also separated from the data line 171. The first and second drain electrodes 175a and 175b face the first and second source electrodes 173a and 173b with respect to the first and second gate electrodes 124a and 124b, and have one wide end portion ( 177a / 177b) and the other end that is rod-shaped. The wide end portion 177b of the second drain electrode 175b has a larger area than the wide end portion 177a of the first drain electrode 175a. The wide ends 177a and 177b overlap the sustain electrode 137, and the rod-shaped ends are partially surrounded by the bent first and second source electrodes 173a and 173b.

The first and second gate electrodes 124a and 124b, the first and second source electrodes 173a and 173b, and the first and second drain electrodes 175a and 175b are formed of the first and second semiconductors 154a and 154b. Together with the first and second thin film transistors (Qa / Qb), the channels of the first and second thin film transistors (Qa / Qb) are formed of the first and second source electrodes ( The first and second semiconductors 154a and 154b are formed between 173a and 173b and the first and second drain electrodes 175a and 175b. The first and second thin film transistors Qa and Qb are positioned on the left and right sides of the data line 171, respectively.

The data conductors 171, 175a, and 175b are preferably made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof, and include a refractory metal film (not shown) and a low resistance conductive film ( It may have a multi-layer structure (not shown). Examples of the multilayer structure include a double layer of chromium or molybdenum (alloy) lower layer and an aluminum (alloy) upper layer, and a triple layer of molybdenum (alloy) lower layer and aluminum (alloy) interlayer and molybdenum (alloy) upper layer. However, the data conductors 171, 175a, and 175b may be made of various other metals or conductors.

The data conductors 171, 175a, and 175b also preferably have their side surfaces inclined at an inclination angle of about 30 ° to 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 163b and 165b exist only between the semiconductors 154a and 154b below and the data conductors 171, 175a and 175b above and lower the contact resistance therebetween. In the semiconductors 154a and 154b, there are portions exposed between the source electrodes 173a and 173b and the drain electrodes 175a and 175b and not covered by the data conductors 171, 175a and 175b.

A passivation layer 180 is formed on the data conductors 171, 175a, and 175b and the exposed semiconductors 154a and 154b. The passivation layer 180 may be made of an inorganic insulator or an organic insulator, and may have a flat surface. The organic insulator preferably has a dielectric constant of 4.0 or less, and may have photosensitivity. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portions of the semiconductors 154a and 154b while maintaining excellent insulating properties of the organic layer.

The passivation layer 180 includes a plurality of contact holes that expose the end portions 179 of the data lines 171 and the wide end portions 177a and 177b of the first and second drain electrodes 175a and 175b, respectively. 182, 185a, and 185b are formed, and the plurality of contact holes 181a and 181b exposing the end portions 129a and 129b of the gate lines 121a and 121b, respectively, in the passivation layer 180 and the gate insulating layer 140. Formed.

A plurality of pixel electrodes 191R, 191G, and 191B and a plurality of contact assistants 81a, 81b, and 82 are formed on the passivation layer 180. They may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver, chromium or an alloy thereof.

The pixel electrodes 191R, 191G, and 191B are formed on the upper panel 200, respectively, and display color filters (eg, one of three primary colors of red (R), green (G), and blue (B)). CF), respectively. Each pixel electrode 191R, 191G, and 191B includes a pair of first and second subpixel electrodes 191Ra, 191Rb, 191Ga, 191Gb, 191Ba, and 191Bb, which are separated from each other, and the subpixel electrodes 191Ra, 191Rb. , 191Ga, 191Ba, and 191Bb have cutouts 91a and 91b, and the subpixel electrode 191Gb has a cutout 92. In addition, the common electrode 270 facing the pixel electrode 191 has a plurality of cutouts 71Ra, 71Rb1.71Rb2, 71Ga, 71Gb, 71Ba, 71Bb1, and 71Bb2.

Each of the first and second subpixel electrodes 191Ra, 191Rb, 191Ga, 191Gb, 191Ba, and 191Bb each includes at least one parallelogram electrode piece 196 shown in FIG. 7A and a parallelogram electrode piece shown in FIG. 197) one. When the electrode pieces 196 and 197 shown in FIGS. 7A and 7B are connected up and down, the basic electrodes 198 shown in FIG. 7C are formed, and each of the subpixel electrodes 191Ra, 191Rb, 191Ga, 191Gb, 191Ba, and 191Bb. Has a structure based on the basic electrode 198.

As shown in FIGS. 7A and 7B, each of the electrode pieces 196 and 197 has a pair of oblique edges 196o and 197o and a pair of transverse edges 196t and 197t and is approximately Parallelogram. Each of the oblique sides 196o and 197o forms an oblique angle with respect to the horizontal sides 196t and 197t, and the size of the oblique angle is preferably about 45 degrees to 135 degrees. For convenience, it is divided according to the inclined direction ("inclination direction") in a vertical state with respect to the bases 196t and 197t forward, and the case inclined to the right as shown in FIG. 7A is called "right inclination" and left as shown in FIG. 7B. The case of tilting is called "left slope".

The lengths of the horizontal edges 196t and 197t of the electrode pieces 196 and 197, that is, the distance between the width W and the horizontal edges 196t and 197t, that is, the height H, are free depending on the size of the display panel assembly 300. Can be decided. In addition, the horizontal edges 196t and 197t of each of the electrode pieces 196 and 197 may be deformed or bent in consideration of a relationship with other portions, and will be referred to as a parallelogram in the future.

The common electrodes 270 are formed with cutouts 61 and 62 facing the electrode pieces 196 and 197, and the electrode pieces 196 and 197 have two subregions (centered around the cutouts 61 and 62). S1, S2). The incisions 61 and 62 form obtuse angles with the oblique portions 61o and 62o and the oblique portions 61o and 62o parallel to the hypotenuses 196o and 197o of the electrode pieces 196 and 197, respectively. And horizontal portions 61t and 62t overlapping the horizontal sides 196t and 197t of.

Each of the subregions S1 and S2 has two primary edges defined by the oblique portions 61o and 62o of the incisions 61 and 62 and the hypotenuses 196t and 197t of the electrode pieces 196 and 197. )

The basic electrode 198 shown in FIG. 7C is formed by combining the right inclined electrode piece 196 and the left inclined electrode piece 197. The angle formed by the right inclined electrode piece 196 and the left inclined electrode piece 197 is preferably approximately right angle, and the connection between the two electrode pieces 196 and 197 is made only in part. The unconnected portion forms the incision 90 and is located on the recessed side. However, the cutout 90 may be omitted.

The outer horizontal sides 196t and 197 of the two electrode pieces 196 and 197 form a horizontal side 198t of the basic electrode 198, and the corresponding hypotenuse sides 196o and 197o of the two electrode pieces 196 are connected to each other. Curved edges 198o1 and 198o2 of the basic electrode 198 are formed.

Curved edges 198o1 and 198o2 meet convex edges 198o1 and transverse sides 198t and obtuse angles such as about 135 ° and acute angles, for example about 45 °. And a concave edge 198o2. The curved sides 198o1 and 198o2 are formed by a pair of hypotenuse sides 196o and 197o at approximately right angles, and thus the angle of bending is approximately right angles.

The cutout 60 extends from the concave vertex CV on the concave side 198o2 to the center of the base electrode 198 toward the convex vertex VV on the convex side 198o1.

In addition, the cutouts 61 and 62 of the common electrode 270 are connected to each other to form one cutout 60. At this time, the horizontal portions 61t and 62t overlapped by the cutouts 61 and 62 are combined to form one horizontal portion 60t1. This new form of incision 60 can be described again as follows.

The cutout 60 is connected to both ends of the bent part 60o having the bend point CP, the central horizontal portion 60t1 connected to the bend point CP of the bent part 60o, and the bent part 60o. And a pair of terminal cross sections 60t2. The bent portion 60o of the incision 60 consists of a pair of oblique portions that meet at right angles, and is substantially parallel to the bend sides 198o1 and 198o2 of the base electrode 198, and the base electrode 198 is left-right and right-sided. Divide into wealth The central horizontal portion 60t1 of the incision 60 forms an obtuse angle, for example about 135 °, with the bend 60o and extends toward the convex vertex VV of the basic electrode 198. The terminal horizontal portion 60t2 is aligned with the horizontal side 198t of the base electrode 198 and forms an obtuse angle with the bend portion 60o, for example, about 135 °.

The base electrode 198 and the incision 60 are approximately inverted symmetric with respect to an imaginary straight line (referred to as a "horizontal center line" forward) connecting the convex vertex (VV) and the concave vertex (CV) of the base electrode 198.

As shown in FIGS. 4 to 6, the first subpixel electrodes 191Ra, 191Ga, and 191Ba consist of a left inclined electrode piece 197 and a right inclined electrode piece 196, and the basic electrode shown in FIG. 7C. It has a structure substantially the same as (198).

The second subpixel electrodes 191Rb and 191Bb include first and second unit electrodes 191Rb1, 191Rb2, 191Bb1, and 191Bb2 having substantially the same structure as the base electrode 198, and the first and second unit electrodes. The 191Rb1, 191Rb2, 191Bb1, and 191Bb2 are connected up and down by the connecting portions 192R and 192B. The heights of the first unit electrodes 191Rb1 and 191Bb1 are higher than the heights of the second unit electrodes 191Rb2 and 191Bb2 and are preferably about 1.1 to 2 times higher. In addition, when the heights of the first subpixel electrodes 191Ra and 191Ba are the same as the heights of the first unit electrodes 191Rb1 and 191Bb1, the first subpixel electrodes 191Ra and 191Ba and the second subpixel electrodes 191Rb and 191Bb may be formed. The area ratio is approximately 1: 1.5 to 1: 2. As described above, a desired area ratio can be obtained by adjusting the width and height of the first subpixel electrodes 191Ra and 191Ba and the first and second unit electrodes 191Rb1, 191Rb2, 191Bb1, and 191Bb2 of the second subpixel electrode.

The second subpixel electrode 191RG has three structures substantially the same as the base electrode 198 and includes three unit electrodes connected from the bottom and the top. The two cutouts 92 divide the second subpixel electrode 191Gb into three parts and each include a bent portion parallel to a curved side of the second subpixel electrode 191Gb and a horizontal portion connected thereto. The width of the second subpixel electrode 191Gb is wider than the width of the first subpixel electrode 191Ga, for example, approximately three times. In addition, the height of the second subpixel electrode 191Gb may be about 1/2 to 1 times the height of the first subpixel electrode 191Ga. Similarly, the area ratio may be adjusted by adjusting the width and height of the first and second subpixel electrodes 191Ga and 191Gb.

The widths and heights of the subpixel electrodes 191Ra, 191Rb, 191Ga, 191Gb, 191Ba, and 191Bb may be adjusted to substantially equal the areas of the pixel electrodes 191R, 191G, and 191B.

In this way, when the pixel electrodes 191R, 191G, and 191B representing the three primary colors form one pixel electrode set, the pixel electrodes 191R, 191G, and 191B representing the same color of the neighboring pixel electrode sets are formed. The shape is repeated the same, and the shape of the neighboring pixel electrode set itself is also repeated. Accordingly, the vertical line expression is better and it is easy to apply a data voltage to the first and second subpixel electrodes 191Ra, 191Rb, 191Ga, 191Gb, 191Ba, and 191Bb separately.

In addition, since the width and height of the subpixel electrodes 191Ra, 191Rb, 191Ga, 191Gb, 191Ba, and 191Bb can be easily adjusted in one pixel electrode set, the area between each pixel electrode 191R, 191G, and 191B can be easily adjusted.

The first subpixel electrodes 191Ra, 191Ga, and 191Ba are connected to the respective first drain electrodes 175a through the contact holes 185a, respectively, and the second subpixel electrode 191Gb and the second subpixel electrode ( The connecting portions 192R and 192B of the 191Rb and the 191Bb are connected to the respective second drain electrodes 175b through the contact holes 185b, respectively.

Each pixel electrode 191 overlaps the data line 171 with the passivation layer 180 interposed therebetween. The areas where two neighboring data lines 171 overlap with the first subpixel electrodes 191Ra, 191Ga, and 191Ba of each pixel electrode 191 are the same. That is, in the pixel electrodes 191R / 191G / 191B corresponding to the red / green / blue color filter 270, the first subpixel electrode 191Ra / 191Ga / 191Ba is connected to the data line 171R1 / 171G / 171B. The area overlapping with is the same as the area overlapping with the neighboring data lines 171G / 171B / 171R2.

The distance between the plurality of data lines 171 is different. That is, the distance between the data line 171R1 connected to the pixel electrode 191R corresponding to the red color filter 270 and the data line 171G connected to the pixel electrode 191G corresponding to the green color filter 270 is green. The distance between the data line 171G connected to the pixel electrode 191G corresponding to the color filter 270 and the data line 171B connected to the pixel electrode 191B corresponding to the blue color filter 270 is shorter. In addition, the distance between the data line 171G connected to the pixel electrode 191G corresponding to the green color filter 270 and the data line 171B connected to the pixel electrode 191B corresponding to the blue color filter 270 is blue. The distance between the data line 171B connected to the pixel electrode 191B corresponding to the color filter 270 and the data line 171R2 connected to the pixel electrode 191R corresponding to the red color filter 270 is longer. By thus adjusting the distances between the data lines 171R1, 171G, 171B, and 171R2 differently, the overlapping area of the pixel electrode 191 and the data line 171 can be freely adjusted.

A parasitic capacitance is generated between the data line 171 and the pixel electrode 191, and the parasitic capacitance affects the pixel electrode voltage, resulting in vertical crosstalk. In particular, when low gray voltage is applied, vertical crosstalk is likely to occur due to parasitic capacitances of the first subpixel electrodes 191Ra / 191Ga / 191Ba and the data line 171 to which a relatively high voltage is applied. As described above, when the first subpixel electrodes 191Ra / 191Ga / 191Ba are arranged to overlap the same area simultaneously with two adjacent data lines 171 to which data voltages are applied with opposite polarities, the data lines 171 and the first subpixel electrodes 191Ra / 191Ga / 191Ba are arranged. The parasitic capacitance between the one subpixel electrodes 191Ra / 191Ga / 191Ba is canceled to prevent the occurrence of vertical crosstalk.

The wide end portions 177a and 177b and the contact holes 185a and 185b of the storage electrode line 131, the first and second drain electrodes 175a and 175b are formed of the first subpixel electrodes 191Ra, 191Ga, and 191Ba. The two subpixel electrodes 191Rb and 191Bb are positioned near the boundary with the second unit electrodes 191Rb2 and 191Bb2 or the second subpixel electrode 191Gb. In this vicinity, the arrangement of the liquid crystal molecules may be disturbed, resulting in texture. When arranged in this way, the aperture ratio may be improved while covering up the texture. Also, the second gate line 121b may also have a second unit electrode 191Rb2, 191Bb2 or a second subpixel electrode 191Gb of the first subpixel electrodes 191Ra, 191Ga, and 191Ba and the second subpixel electrodes 191Rb and 191Bb. It is located near the border with).

The first / second subpixel electrodes 191Ra, 191Ga, and 191Ba) / (191Rb, 191Gb, and 191Bb) and the common electrode 270 of the upper panel 200 are each of the first and second liquid crystal layers 3 therebetween. The second liquid crystal capacitor Clca / Clcb is formed to maintain the applied voltage even after the thin film transistors Qa / Qb are turned off.

The first subpixel electrodes 191Ra, 191Ga, and 191Ba and the first drain electrode 175a connected thereto overlap the first and second storage capacitors Csta with the gate insulating layer 140 interposed therebetween. / Cstb, and the first / second storage capacitors Csta / Cstb enhance the voltage holding capability of the first / second liquid crystal capacitors Clca / Clcb.

The contact auxiliary members 81a, 81b, and 82 are end portions 129a and 129b of the gate lines 121a and 121b and end portions 179 of the data line 171 through the contact holes 181a, 181b, and 182, respectively. Connected with The contact auxiliary members 81a, 81b, and 82 compensate for and protect the adhesion between the end portions 129a and 129b of the gate lines 121a and 121b and the end portions 179 of the data line 171 and the external device. do.

Next, the upper panel 200 will be described with reference to FIGS. 5 to 7.

A light blocking member 220 is formed on an insulating substrate 210 made of transparent glass, plastic, or the like. The light blocking member 220 includes a bent portion corresponding to the curved side of the pixel electrodes 191R, 191G, and 191B and a quadrangle portion corresponding to the thin film transistor, and prevents light leakage between the pixel electrodes 191R, 191G, and 191B, and prevents the pixel electrode. An opening region facing 191R, 191G, 191B is defined.

A plurality of color filters 230R and 230G are further formed on the substrate 210 and the light blocking member 220. The color filters 230R and 230G are mostly present in an area surrounded by the light blocking member 230, and may extend long along the columns of the pixel electrodes 191R, 191G, and 191B. The color filter 230R displays red (R), the color filter 230G displays green (G), and includes a color filter 230 (not shown) that represents blue (B). The color filter may display one of the primary colors other than the three primary colors of red, green, and blue.

An overcoat 250 is formed on the color filters 230R and 230G and the light blocking member 220. The overcoat 250 may be made of an (organic) insulator, which prevents the color filter 230 from being exposed and provides a flat surface. The overcoat 250 may be omitted.

The common electrode 270 is formed on the overcoat 250. The common electrode 270 is made of a transparent conductor such as ITO or IZO, and has a plurality of cutouts 71Ra, 71Rb1.71Rb2, 71Ga, 71Gb, 71Ba, 71Bb1, 71Bb2.

Since the shapes of the cutouts 71Ra, 71Rb1.71Rb2, 71Ga, 71Gb, 71Ba, 71Bb1, 71Bb2 of the common electrode 270 are as described above, detailed descriptions thereof will be omitted.

The number of cutouts 71Ra, 71Rb1.71Rb2, 71Ga, 71Gb, 71Ba, 71Bb1, 71Bb2 may vary depending on the design element, and the light blocking member 220 may be cut out 71Ra, 71Rb1.71Rb2, 71Ga, 71Gb, 71Ba. , 71Bb1, 71Bb2), and can block light leakage near the cutouts 71Ra, 71Rb1. 71Rb2, 71Ga, 71Gb, 71Ba, 71Bb1, 71Bb2.

Alignment layers 11 and 21 are formed on inner surfaces of the display panels 100 and 200, and they may be vertical alignment layers.

Polarizers 12 and 22 are provided on the outer surfaces of the display panels 100 and 200, and the polarization axes of the two polarizers 12 and 22 are orthogonal to each other and the curved sides of the subpixel electrodes 191a and 191b are approximately equal to each other. It is desirable to achieve an angle of 45 degrees. In the case of a reflective liquid crystal display, one of the two polarizers 12 and 22 may be omitted.

The liquid crystal display may include a polarizer 12 and 22, a phase retardation film, display panels 100 and 200, and a backlight unit (not shown) for supplying light to the liquid crystal layer 3.

The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 are aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field.

The cutouts 71Ra, 71Rb1. 71Rb2, 71Ga, 71Gb, 71Ba, 71Bb1, 71Bb2 may be replaced by protrusions (not shown) or depressions (not shown). The protrusions may be made of organic or inorganic materials and may be disposed above or below the field generating electrodes 191R, 191G, 191B, and 270.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). The input image signals R, G, and B contain luminance information of each pixel PX, and the luminance is a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ), or 64 (= 2 ⁶ ) It has gray. Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 applies the input image signals R, G, and B to the operating conditions of the liquid crystal panel assembly 300 and the data driver 500 based on the input image signals R, G, and B and the input control signal. After appropriately processing and generating the gate control signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are processed. ) Is output to the data driver 500. The output video signal DAT has a predetermined number (or gradation) as a digital signal.

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 includes a horizontal synchronization start signal STH indicating the start of transmission of image data to a group of subpixels, a load signal LOAD and a data clock signal for applying a data signal to the liquid crystal panel assembly 300. (HCLK). The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " RVS) may be further included.

In response to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for a group of subpixels, and the gray level corresponding to each digital image signal DAT. By selecting the voltage, the digital image signal DAT is converted into an analog data signal and then applied to the corresponding data line 171.

The gate driver 400 applies the gate-on voltage Von to the gate lines 121a and 121b according to the gate control signal CONT1 from the signal controller 600 to connect the switching elements connected to the gate lines 121a and 121b. Turn on (Qa, Qb). Then, the data signal applied to the data line 171 is applied to the corresponding subpixels 191Ra, 191Rb, 191Ga, 191Gb, 191Ba, and 191Bb through the turned-on switching elements Qa and Qb.

When a potential difference occurs between both ends of the first or second liquid crystal capacitors Clca and Clcb, a primary electric field substantially perpendicular to the surfaces of the display panels 100 and 200 is generated in the liquid crystal layer 3. do. [In the following, the pixel electrodes 191R, 191G, and 191B and the common electrode 270 are also referred to as "field generating electrodes.") The liquid crystal molecules of the liquid crystal layer 3 have their long axes in response to the electric field. The angle of inclination is perpendicular to the direction of the electric field, and the degree of change in polarization of incident light in the liquid crystal layer 3 varies according to the degree of inclination of the liquid crystal molecules. This change in polarization is represented by a change in transmittance by the polarizer, through which the liquid crystal display displays an image.

The angle at which the liquid crystal molecules are inclined depends on the intensity of the electric field. Since the voltages of the two liquid crystal capacitors Clca and Clcb are different from each other, the angles at which the liquid crystal molecules are inclined are different and thus the luminance of the two subpixels is different. Therefore, if the voltage of the first liquid crystal capacitor Clca and the voltage of the second liquid crystal capacitor Clcb are properly adjusted, the image viewed from the side may be as close as possible to the image viewed from the front, that is, the side gamma curve may be front gamma curve. As close as possible to this, side visibility can be improved.

In addition, when the area of the first subpixel electrodes 191Ra, 191Ga, and 191Ba to which a high voltage is applied is smaller than the area of the second subpixel electrodes 191Rb, 191Gb, and 191Bb, the side gamma curve may be closer to the front gamma curve. have. In particular, since the area ratio of the first subpixel electrodes 191Ra, 191Ga, and 191Ba and the second subpixel electrodes 191Rb, 191Gb, and 191Bb is approximately 1: 2, the side gamma curve becomes closer to the front gamma curve, so that side visibility is better. Lose. In particular, in the present invention, since the width and height of the subpixel electrodes 191Ra, 191Rb, 191Ga, 191Gb, 191Ba, and 191Bb are freely adjusted in one pixel electrode set, the first subpixel electrodes 191Ra, 191Ga, 191Ba, and the second subunit are free. The area ratio control of the pixel electrodes 191Rb, 191Gb, and 191Bb is also free and easy to adjust to 1: 2.

The direction in which the liquid crystal molecules are inclined is primarily the incisions 71Ra, 71Rb1.71Rb2, 71Ga, 71Gb, 71Ba, 71Bb1, 71Bb2, 91a, 91b, 92 and subpixels of the field generating electrodes 191R, 191G, 191B, and 270. The sides of the electrodes 191Ra, 191Ga, 191Ba, 191Rb, 191Gb, and 191Bb are determined by the horizontal component produced by distorting the main electric field. The horizontal components of the main electric field are the sides of the cutouts 71Ra, 71Rb1, 71Rb2, 71Ga, 71Gb, 71Ba, 71Bb1, 71Bb2, 91a, 91b, 92 and the subpixel electrodes 191Ra, 191Rb, 191Ga, 191Gb, 191Ba, 191Bb. Is almost perpendicular to the sides.

The subpixel electrodes 191Ra, 191Rb, 191Ga, 191Gb, 191Ba, and 191Bb are divided into four sub-areas by the incisions 71Ra, 71Rb1, 71Rb2, 71Ga, 71Gb, 71Ba, 71Bb1, and 71Bb2. Each subregion is defined by the bent portions of the cutouts 71Ra, 71Rb1, 71Rb2, 71Ga, 71Gb, 71Ba, 71Bb1, 71Bb2 and the bent sides of the subpixel electrodes 191Ra, 191Rb, 191Ga, 191Gb, 191Ba, and 191Bb. Has major edges. Most of the liquid crystal molecules on each subregion are inclined in a direction perpendicular to the periphery thereof, and thus, the inclination directions are approximately four directions. As described above, when the liquid crystal molecules are inclined in various directions, the reference viewing angle of the liquid crystal display is increased.

On the other hand, the direction of the secondary electric field generated by the voltage difference between the subpixel electrodes 191Ra, 191Rb, 191Ga, 191Gb, 191Ba, 191Bb is perpendicular to the periphery of the subregion. Thus, the direction of the negative electric field coincides with the direction of the horizontal component of the main electric field. As a result, the negative electric field between the subpixel electrodes 191Ra, 191Rb, 191Ga, 191Gb, 191Ba, and 191Bb acts to strengthen the crystal in the oblique direction of the liquid crystal molecules.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby allocating data signals to all the pixels PX. Is applied to display an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarities of the data signals flowing through one data line are changed (eg, row inversion and point inversion) according to the characteristics of the inversion signal RVS within one frame, or the polarities of the data signals applied to a group of pixels are also different from each other. Can be different (eg invert columns, invert points).

When the polarity of the data signal is thermally reversed, when a positive data voltage is applied to one data line 171, a negative data voltage is applied to the neighboring data line 171. In this case, as described above, when two data lines to which data voltages having different polarities are applied overlap with one first subpixel electrode 191a, parasitic capacitance between the data line 171 and the pixel electrode 191 may be canceled. Can be.

Next, another example of the liquid crystal panel assembly illustrated in FIG. 3 will be described in detail with reference to FIGS. 8 and 9, and FIGS. 1 and 2 described above.

FIG. 8 is a layout view illustrating a liquid crystal panel assembly according to another exemplary embodiment. FIG. 9 is a layout view illustrating pixel electrodes of the liquid crystal panel of FIG. 8.

Referring to FIG. 8, the liquid crystal panel assembly according to the present exemplary embodiment includes a lower panel (not shown), an upper panel (not shown), and a liquid crystal layer (not shown) therebetween.

The layered structure of the liquid crystal panel assembly according to the present embodiment is usually the same as the layered structure of the liquid crystal panel assembly shown in FIGS. 4 to 6.

Referring to the lower panel, a gate including a plurality of pairs of first and second gate lines 121a and 121b and a plurality of pairs of first and second storage electrode lines 131a and 131b is disposed on an insulating substrate (not shown). A conductor is formed. The first and second gate lines 121a and 121b include first and second gate electrodes 124a and 124b and end portions 129a and 129b, respectively, and the first and second storage electrode lines 131a and 131b. Includes first and second sustain electrodes 137a and 137b, respectively. A gate insulating film (not shown) is formed on the gate conductors 121a, 121b, 131a, and 131b. A plurality of semiconductors 154a and 154b are formed on the gate insulating film, and a plurality of ohmic contacts (not shown) are formed thereon. A data conductor including a plurality of data lines 171 and a plurality of first and second drain electrodes 175a and 175b is formed on the ohmic contact member. The data line 171 includes a plurality of first and second source electrodes 173a and 173b and end portions 179, and the drain electrodes 175a and 175b include wide end portions 177a and 177b. A protective film (not shown) is formed on the data conductors 171, 175a, and 175b and the exposed portions of the semiconductors 154a and 154b, and the plurality of contact holes 181a, 181b, 182, and 185a, 185b) is formed. A plurality of pixel electrodes 191 including the first and second subpixel electrodes 191a and 191b and a plurality of contact auxiliary members 81a, 81b, and 82 are formed on the passivation layer. The areas where the neighboring data lines 171 overlap with the first subpixel electrode 191a are the same. An alignment layer (not shown) is formed on the pixel electrode 191, the contact auxiliary members 81a, 81b, and 82, and the passivation layer.

Referring to the upper panel, a light blocking member, a plurality of color filters, an overcoat, a common electrode having a cutout, and an alignment layer are formed on an insulating substrate.

However, the liquid crystal panel assembly according to the present embodiment has a shape different from that of the liquid crystal panel assembly illustrated in FIGS. 4 to 8. Hereinafter, the pixel electrode 191 of the liquid crystal panel assembly according to the present exemplary embodiment will be described in detail with reference to FIG. 11.

9 is a layout view of a pixel electrode and a common electrode of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

9, the size of the first subpixel electrode 191a of the pixel electrode 191 is smaller than that of the second subpixel electrode 191b. In particular, the height of the second subpixel electrode 191b is higher than the height of the first subpixel electrode 191a, and the widths of the two subpixel electrodes 191b are substantially the same. The number of electrode pieces of the second subpixel electrode 191b is larger than the number of electrode pieces of the first subpixel electrode 191b.

The first subpixel electrode 191a includes a left inclined electrode piece 197 and a right inclined electrode piece 196 and has a structure substantially the same as that of the basic electrode 198 shown in FIG. 7C.

The second subpixel electrode 191b is formed of a combination of two or more left inclined electrode pieces 197 and two or more right inclined electrode pieces 196, and is coupled to the basic electrode 198 illustrated in FIG. 7C. Left and right inclined electrode pieces 196 and 197 are included.

The second subpixel electrode 191b is made up of six electrode pieces 191b1-191b6, and two of the electrode pieces 191b5 and 191b6 are disposed above and below the first subpixel electrode 191a. The pixel electrode 191b has a structure that is bent three times, and has a better vertical line expression than the structure that is curved once. In addition, the cutout portion 61 of the common electrode 270 where the electrode pieces 191a1 and 191a2 of the first subpixel electrode 191a and the electrode pieces 191b5 and 191b6 of the second subpixel electrode 191b are adjacent to each other. Since the horizontal portions 61t and 62t of 62 are combined to form one horizontal portion, the aperture ratio is further increased.

The heights of the intermediate electrode pieces 191a1, 191a2, 191b1, and 191b2 and the electrode pieces 191b3-191b6 disposed above and below are different from each other. For example, the heights of the upper and lower electrode pieces 191b3-191b6 are about 1/2 of the intermediate electrode pieces 191a1, 191a2, 191b1, and 191b2, and thus, the first subpixel electrode 191a and the second subpixel electrode. The area ratio of 191b is approximately 1: 2. Thus, by adjusting the height of the upper and lower electrode pieces 191b3-191b6, a desired area ratio can be obtained.

In FIG. 9, the positional relationship and the bending directions of the first and second subpixel electrodes 191a and 191b may be changed, and the pixel electrode 191 may be deformed by inverting, flipping, rotating, and rotating the pixel electrode 191.

Many features of the liquid crystal panel assembly illustrated in FIGS. 4 to 6 may also be applied to the liquid crystal panel assembly illustrated in FIG. 8.

Next, another example of the liquid crystal panel assembly illustrated in FIG. 3 will be described in detail with reference to FIG. 10 and FIGS. 1 and 2 described above.

FIG. 10 is a layout view illustrating a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

Referring to FIG. 10, the liquid crystal panel assembly according to the present exemplary embodiment includes a lower panel (not shown), an upper panel (not shown), and a liquid crystal layer (not shown) therebetween.

The layered structure of the liquid crystal panel assembly according to the present embodiment is usually the same as the layered structure of the liquid crystal panel assembly shown in FIGS. 4 to 6.

Referring to the lower panel, a gate including a plurality of pairs of first and second gate lines 121a and 121b and a plurality of pairs of first and second storage electrode lines 131a and 131b is disposed on an insulating substrate (not shown). A conductor is formed. The first and second gate lines 121a and 121b include first and second gate electrodes 124a and 124b and end portions 129a and 129b, respectively, and the first and second storage electrode lines 131a and 131b. Includes first and second sustain electrodes 137a and 137b, respectively. A gate insulating film (not shown) is formed on the gate conductors 121a, 121b, 131a, and 131b. A plurality of semiconductors 154a and 154b are formed on the gate insulating film, and a plurality of ohmic contacts (not shown) are formed thereon. A data conductor including a plurality of data lines 171 and a plurality of first and second drain electrodes 175a and 175b is formed on the ohmic contact member. The data line 171 includes a plurality of first and second source electrodes 173a and 173b and end portions 179, and the drain electrodes 175a and 175b include wide end portions 177a and 177b. . A protective film (not shown) is formed on the data conductors 171, 175a, and 175b and the exposed portions of the semiconductors 154a and 154b, and the plurality of contact holes 181a, 181b, 182, and 185a, 185b) is formed. A plurality of pixel electrodes 191 including the first and second subpixel electrodes 191a and 191b and a plurality of contact auxiliary members 81a, 81b, and 82 are formed on the passivation layer. The areas where the neighboring data lines 171 overlap with the first subpixel electrode 191a are the same. An alignment layer (not shown) is formed on the pixel electrode 191, the contact auxiliary members 81a, 81b, and 82, and the passivation layer.

Referring to the upper panel, a light blocking member, a plurality of color filters, an overcoat, a common electrode having a cutout, and an alignment layer are formed on an insulating substrate.

However, the liquid crystal panel according to the present exemplary embodiment further includes a plurality of branch parts 171a connected to the data lines 171, unlike the liquid crystal panel shown in FIGS. 4 to 6. Each branch portion 171a extends to the left with respect to the data line 171 and overlaps the first subpixel electrode 191a of the neighboring pixel electrode 191. That is, although the data line 171 itself extending in a straight line does not overlap sufficiently with the neighboring pixel electrode 191, the branch portion to which the voltage of the same polarity is applied sufficiently overlaps with the neighboring pixel electrode 191 so that the neighboring data line ( The total areas 171 overlapping with the first subpixel electrode 191a are equal to each other. Therefore, the parasitic capacitance between the data line 171 and the first subpixel electrode 191 can be more easily canceled without excessively disparing the distance between the data lines 171.

Many features of the liquid crystal panel assembly illustrated in FIGS. 4 to 6 may also be applied to the liquid crystal panel assembly illustrated in FIG. 10.

Next, another example of the liquid crystal panel assembly illustrated in FIG. 3 will be described in detail with reference to FIG. 11 and FIGS. 1 and 2 described above.

11 is a layout view illustrating a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

Referring to FIG. 11, the liquid crystal panel assembly according to the present exemplary embodiment includes a lower panel (not shown), an upper panel (not shown), and a liquid crystal layer (not shown) therebetween.

The layered structure of the liquid crystal panel assembly according to the present embodiment is usually the same as the layered structure of the liquid crystal panel assembly shown in FIGS. 4 to 6.

Referring to the lower panel, a gate including a plurality of pairs of first and second gate lines 121a and 121b and a plurality of pairs of first and second storage electrode lines 131a and 131b is disposed on an insulating substrate (not shown). A conductor is formed. The first and second gate lines 121a and 121b include first and second gate electrodes 124a and 124b and end portions 129a and 129b, respectively, and the first and second storage electrode lines 131a and 131b. Includes first and second sustain electrodes 137a and 137b, respectively. A gate insulating film (not shown) is formed on the gate conductors 121a, 121b, 131a, and 131b. A plurality of semiconductors 154a and 154b are formed on the gate insulating film, and a plurality of ohmic contacts (not shown) are formed thereon. A data conductor including a plurality of data lines 171 and a plurality of first and second drain electrodes 175a and 175b is formed on the ohmic contact member. The data line 171 includes a plurality of first and second source electrodes 173a and 173b and end portions 179, and the drain electrodes 175a and 175b include wide end portions 177a and 177b. A protective film (not shown) is formed on the data conductors 171, 175a, and 175b and the exposed portions of the semiconductors 154a and 154b, and the plurality of contact holes 181a, 181b, 182, and 185a, 185b) is formed. A plurality of pixel electrodes 191 including the first and second subpixel electrodes 191a and 191b and a plurality of contact auxiliary members 81a, 81b, and 82 are formed on the passivation layer. The areas where the neighboring data lines 171 overlap with the first subpixel electrode 191a are the same. An alignment layer (not shown) is formed on the pixel electrode 191, the contact auxiliary members 81a, 81b, and 82, and the passivation layer.

Referring to the upper panel, a light blocking member, a plurality of color filters, an overcoat, a common electrode having a cutout, and an alignment layer are formed on an insulating substrate.

The shape of the pixel electrode 191 according to the present exemplary embodiment is the same as the pixel electrode 191 of the liquid crystal panel assembly illustrated in FIGS. 8 and 9. In addition, the liquid crystal panel according to the present exemplary embodiment further includes a plurality of branch parts 171a connected to each data line 171, similarly to the liquid crystal panel shown in FIG. 12.

Each branch portion 171a extends to the left with respect to the data line 171 and overlaps the first subpixel electrode 191a of the neighboring pixel electrode 191. At this time, a portion of the branch portion 171a may be bent several times along the cutout 71 of the common electrode 270 formed in the region of the first subpixel electrode 191a (171b) to reduce the aperture ratio. It can be minimized.

Many features of the liquid crystal panel assembly illustrated in FIGS. 4 to 6 may also be applied to the liquid crystal panel assembly illustrated in FIG. 11.

As described above, according to the present invention, generation of vertical crosstalk of the display device can be prevented to improve display quality.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (22)

Board, A plurality of pixel electrodes formed on the substrate, each pixel electrode including first and second subpixel electrodes, and A plurality of data lines overlapping the pixel electrode and extending in a straight line Including; And an area where two neighboring data lines of the data lines overlap each other with the first subpixel electrode. In claim 1, A liquid crystal display device of which the distance between neighboring data lines among the plurality of data lines is different. In claim 1, The pixel electrode includes first, second and third pixel electrodes adjacent to each other, The data line includes first, second and third data lines connected to the first to third pixel electrodes, respectively. And a distance between the first data line and the second data line is shorter than a distance between the second data line and the third data line. In claim 3, A fourth data line adjacent to the third data line; And a distance between the second data line and the third data line is longer than a distance between the third data line and the fourth data line. In claim 1, And a plurality of branch parts connected to each of the data lines and overlapping the pixel electrode. In claim 5, The pixel electrode includes first and second pixel electrodes adjacent to each other. The data line includes first and second data lines connected to the first and second pixel electrodes, respectively. An area where the first data line overlaps the first subpixel electrode of the first pixel electrode is equal to an area where a branch portion of the second data line overlaps the first subpixel electrode of the first pixel electrode. Liquid crystal display. In claim 1, And an organic layer formed between the pixel electrode and the data line. In claim 1, Each of the pixel electrodes includes at least two first and at least one second electrodes adjacent to each other up and down; Each of the first and second electrodes includes at least two parallelogram electrodes having different inclination directions, The first subpixel electrode includes the first electrode, and the second subpixel electrode includes at least one of the first electrode and the second electrode. Liquid crystal display. In claim 8, The height of the first electrode and the height of the second electrode are different from each other. In claim 8, The first electrode of the first subpixel electrode is adjacent to the left and right of the first electrode of the second subpixel electrode. In claim 8, The electrode piece includes a pair of hypotenuses parallel to each other, The hypotenuse of the electrode piece of the said 1st electrode is arrange | positioned and staggered with the hypotenuse of the electrode piece of a said 2nd electrode. In claim 1, Each of the pixel electrodes includes at least one first electrode and at least one second electrode adjacent to each other up and down; Each of the first and second electrodes includes at least two parallelogram electrodes having different inclination directions, The height of the first electrode and the height of the second electrode are different from each other Liquid crystal display. In claim 12, The first subpixel electrode includes the first electrode, and the second subpixel electrode includes two or more second electrodes. Liquid crystal display. In claim 13, The second subpixel electrode includes three second electrodes which are adjacent to each other and connected to each other, The first subpixel electrode is aligned with a second electrode located in the middle of the second electrodes. Liquid crystal display. In claim 1, Each of the first and second subpixel electrodes includes at least two parallelogram electrodes having different inclination directions, At least one of the electrode pieces of the second subpixel electrode is positioned above or below the first subpixel electrode. Liquid crystal display. The method of claim 15, The first subpixel electrode includes one right inclined parallelogram electrode piece and one left inclined parallelogram electrode piece, The second subpixel electrode includes three right inclined parallelogram electrodes and three left inclined parallelogram electrodes. Liquid crystal display. The method of claim 16, And the right inclined parallelogram electrode piece and the left inclination parallelogram electrode piece are alternately arranged up and down. The method of claim 15, And a height of an electrode piece of the first subpixel electrode is higher than a height of an electrode piece positioned above or below the first subpixel electrode among the electrode pieces of the second subpixel electrode. The method according to any one of claims 8, 12 or 15, The area of the second subpixel electrode is larger than the area of the first subpixel electrode. The method according to any one of claims 8, 12 or 15, The liquid crystal display of claim 1, wherein the voltages of the first subpixel electrode and the second subpixel electrode are different from each other. The method of claim 20, A first thin film transistor connected to the first subpixel electrode, A second thin film transistor connected to the second subpixel electrode, A first gate line connected to the first thin film transistor, and A second gate line connected to the second thin film transistor Liquid crystal display further comprising. The method of claim 19, And the first and second thin film transistors are turned on according to the signals of the first and second gate lines, respectively, to transfer the signals from the data lines.

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