KR20080053710A - Thin film transistor array panel - Google Patents

Abstract

A TFT(Thin Film Transistor) array panel is provided to stably display a screen and offer a high-quality LCD by minimizing the luminance variation due to a change in parasitic capacitance. A TFT array panel comprises a substrate, the first and second gate lines(121a,121b), the first and second data lines(171s,171n), the first and second TFTs, and a pixel electrode(191). The first and second gate lines are formed on the substrate. The first data line, crossing the first and second gate lines, comprises a plurality of curved portions which are formed as plural vertical line parts and plural diagonal line parts are repeatedly connected. The second data line, neighboring with the first data line, is parallel to the first data line. The first TFT is connected with the first gate line and the first data line. The second TFT is connected with the second gate line and the first data line. The pixel electrode comprises the first sub pixel electrode connected to the first TFT and the second sub pixel electrode connected to the second TFT. The second sub pixel electrode is superposed with the first and second data lines. The first area where a vertical line part crossing the second gate line is superposed with the second sub pixel electrode is narrower than the second area where a curved portion adjacent to the first gate line is superposed with the second sub pixel electrode.

Description

Thin Film Transistor Display Panels {THIN FILM TRANSISTOR ARRAY PANEL}

1 and 2 are schematic equivalent circuit diagrams of two subpixels of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a layout view of one pixel of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

FIG. 4 is a layout view of a thin film transistor array panel for the liquid crystal panel assembly of FIG. 3.

FIG. 5 is a layout view of a common electrode panel for the liquid crystal panel assembly of FIG. 3.

6 is a cross-sectional view of the liquid crystal panel assembly of FIG. 3 taken along the line V-V.

FIG. 7 is a cross-sectional view of the liquid crystal panel assembly of FIG. 3 taken along the line VII-VII. FIG.

8 is a cross-sectional view of the liquid crystal panel assembly of FIG. 3 taken along the line VIII-VIII.

9 is a schematic layout view of one pixel electrode in a liquid crystal panel assembly according to various embodiments of the present disclosure.

10-12 is a top view of the electrode piece used as the basis of each subpixel electrode shown in FIG.

13 is a graph illustrating a luminance difference of the liquid crystal display according to the present invention and the prior art.

FIG. 14 is a diagram for explaining FIG. 13.

<Description of Drawing>

12, 22: polarizing plates 11, 21: alignment film

71, 71a, 71b: common electrode incision

81a, 81b, 82s, 82n: contact auxiliary member

91a and 92a: pixel electrode cutouts 110 and 210: substrate

121a, 121b, 129a, 129b: gate line

124a and 124b: gate electrode

131: sustain electrode line 137: sustain electrode

140: gate insulating film 154a, 154b: semiconductor

161s, 161n, 163a, 165a, 163b, 165b: resistive contact member

171s, 171n, 179s, 179n: data line

173a and 173b: source electrode 175a and 175b: drain electrode

180: shield

181a, 181b, 182s, 182n, 185a, 185b: contact hole

191, 191a, and 191b: pixel electrode 220: light blocking member

230: color filter 250: overcoat

270 common electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistor array panels, and more particularly, to thin film transistor array panels for liquid crystal displays.

The liquid crystal display is one of the flat panel display devices most widely used. The liquid crystal display includes two display panels on which field generating electrodes, such as a pixel electrode and a common electrode, are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of the liquid crystal molecules of the liquid crystal layer and controlling the polarization of incident light to display an image.

The liquid crystal display also includes a switching element connected to each pixel electrode and a plurality of signal lines such as a gate line and a data line for controlling the switching element and applying a voltage to the pixel electrode.

Among such liquid crystal display devices, a liquid crystal display device having a vertically aligned mode in which the long axis of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels without an electric field applied to the liquid crystal display device is gaining attention due to its large contrast ratio and wide reference viewing angle. . Here, the reference viewing angle refers to a viewing angle having a contrast ratio of 1:10 or a luminance inversion limit angle between gray levels.

In order to increase the aperture ratio in a liquid crystal display, a super-opening ratio structure in which a pixel electrode is widened is proposed.

However, in the ultra-opening ratio structure, the shape of the pixel electrode is changed so that the pixel electrode and the data line overlap, and thus the parasitic capacitance increases. In addition, the parasitic capacitance increases when the thickness of the insulating film formed between the pixel electrode and the data line is thin and the distance between the two metals is small.

The value of the parasitic capacitance varies depending on the overlapping position of the data line and the pixel electrode, and the difference in capacitance causes a difference in luminance.

Therefore, the technical problem to be achieved by the present invention is to minimize the luminance change caused by the parasitic capacitance difference.

In accordance with an aspect of the present invention, a thin film transistor array panel includes a substrate, a first gate line and a second gate line, a first gate line, and a second gate line formed on the substrate, and a plurality of vertical portions and diagonal portions are repeated. A first data line including a plurality of bent portions connected to the first data line, a first thin film transistor adjacent to the first data line and connected with the first data line, the first gate line, and the first data line; A pixel electrode including a second thin film transistor connected to a second gate line and a first data line, a first subpixel electrode connected to a first thin film transistor, and a second subpixel electrode connected to a second thin film transistor; And the second subpixel electrode overlaps the first data line and the second data line, and the vertical portion and the second portion of the data line intersect the second gate line. The first region is smaller than that of the second region overlapping the bent portion and the second sub-pixel electrode adjacent to the gate line and the first pixel electrode overlap.

The area ratio of the first region and the second region may be 1: 0.2 to 0.45.

When the width of the pixel electrode is 150 to 200 μm, an area ratio of the first region to the second region may be 1: 0.3 to 0.45.

When the width of the pixel electrode is 200 to 250 μm, an area ratio of the first region to the second region may be 1: 0.2 to 0.3.

The first and second subpixel electrodes may include at least two parallelogram electrodes having different inclination directions.

The first subpixel electrode includes one right inclination parallelogram electrode piece and one left inclination parallelogram electrode piece, and the second subpixel electrode is three right inclination parallelogram electrode piece and three left inclination parallelogram electrode pieces It may include.

An area of the second subpixel electrode may be larger than an area of the first subpixel electrode.

The second subpixel electrode may partially surround the first subpixel electrode.

A light blocking layer formed on the substrate and overlapping the data line and separated from the gate line may be further included.

Voltages of the first subpixel electrode and the second subpixel electrode may be different from each other.

The first and second thin film transistors may be turned on according to signals from the first and second gate lines, respectively, to transmit signals from the first data line.

The organic layer may further include an organic layer formed between the data line and the drain electrode and the pixel electrode.

The data voltage polarity applied to the first data line and the data voltage polarity applied to the second data line may be opposite to each other.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display of the present invention will now be described in detail with reference to the accompanying drawings.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 and 2 are schematic equivalent circuit diagrams of two subpixels of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention. to be.

In the structure shown in FIG. 1, the liquid crystal display includes lower and upper display panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

Referring to FIG. 1, a signal line includes a plurality of gate lines (not shown) that transmit gate signals (also referred to as “scan signals”) and a plurality of data lines that transmit data signals. The gate lines extend substantially in the row direction and are substantially parallel to each other, and the data lines extend substantially in the column direction to intersect the gate lines and are substantially parallel to each other.

Each pixel includes a pair of subpixels PXa and PXb, and each subpixel PXa and PXb includes liquid crystal capacitors Clca and Clcb. At least one of the two subpixels PXa and PXb includes a switching element (not shown) connected to the gate line, the data line, and the liquid crystal capacitors Clca and Clcb.

The liquid crystal capacitors Clca and Clcb have the subpixel electrodes PEa and PEb of the lower panel 100 and the common electrode CE of the upper panel 200 as two terminals, and the subpixel electrodes PEa and PEb and the common electrode. The liquid crystal layer 3 between (CE) functions as a dielectric. The pair of subpixel electrodes PEa and PEb are separated from each other and form one pixel electrode PE. The common electrode CE is formed on the entire surface of the upper panel 200 and receives the common voltage Vcom.

The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 may be aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field.

On the other hand, in order to implement color display, each pixel may display one of the primary colors uniquely (spatial division) or each pixel may display the primary colors alternately (time division) according to time. In this way, the desired color can be recognized in time. Examples of the primary colors include three primary colors such as red, green, and blue.

1 illustrates that each pixel includes a color filter CF representing one of the primary colors in an area of the upper panel 200 as an example of spatial division. Unlike FIG. 1, the color filter CF may be formed above or below the subpixel electrodes PEa and PEb of the lower panel 100.

Polarizers (not shown) are provided on the outer surfaces of the display panels 100 and 200, and polarization axes of the two polarizers may be orthogonal to each other. In the case of a reflective liquid crystal display, one of two polarizers may be omitted. In the case of the orthogonal polarizer, incident light entering the liquid crystal layer 3 having no electric field is blocked.

The liquid crystal display may include a phase delay film (not shown) and a backlight unit (not shown) for supplying light to the liquid crystal layer 3.

Referring to FIG. 2, the liquid crystal panel assembly according to the present exemplary embodiment includes a signal line including a plurality of pairs of gate lines GLa and GLb, a plurality of data lines DL, and a plurality of storage electrode lines SL, and a plurality of connected signal lines. The pixel PX is included.

Each pixel PX includes a pair of subpixels PXa and PXb, and each subpixel PXa / PXb is a switching element connected to corresponding gate lines GLa and GLb and data lines DL, respectively. Qa and Qb, liquid crystal capacitors Clca and Clcb connected thereto, and storage capacitors Csta and Cstb connected to the switching elements Qa and Qb and the storage electrode line SL.

Each of the switching elements Qa and Qb is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate lines GLa and GLb and the input terminal of the data line DL. ) And the output terminals are connected to the liquid crystal capacitors Clca and Clcb and the storage capacitors Csta and Cstb.

The storage capacitors Csta and Cstb, which serve as an auxiliary role of the liquid crystal capacitors Clca and Clcb, are formed by overlapping the storage electrode line SL and the pixel electrode PE provided in the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the storage electrode line SL. However, the storage capacitors Csta and Cstb may be formed such that the subpixel electrodes PEa and PEb overlap the front gate line directly above the insulator.

Since the liquid crystal capacitors Clca and Clcb have been described above, detailed descriptions thereof will be omitted.

In the liquid crystal display device including the liquid crystal panel assembly as described above, by separately generating a set of gradation voltages for the two subpixels PXa and PXb, alternately providing them to a data driver (not shown), or alternately selecting them in the data driver, Different voltages may be applied to the two subpixels PXa and PXb. However, at this time, it is preferable to correct the image signal or to create a set of gray voltages so that the composite gamma curve of the two subpixels PXa and PXb is close to the reference gamma curve at the front. For example, the composite gamma curve at the front side matches the reference gamma curve at the front side determined to be most suitable for this liquid crystal panel assembly, and the composite gamma curve at the side side is closest to the reference gamma curve at the front side.

An example of the liquid crystal panel assembly illustrated in FIGS. 1 and 2 will be described in detail with reference to FIGS. 3 to 8.

3 is a layout view of one pixel of a liquid crystal panel assembly according to an exemplary embodiment of the present invention, FIG. 4 is a layout view of a thin film transistor array panel for the liquid crystal panel assembly of FIG. 3, and FIG. 5 is for the liquid crystal panel assembly of FIG. 3. 6 is a cross-sectional view illustrating the liquid crystal panel assembly of FIG. 3 taken along the line VV, and FIG. 7 is a cross-sectional view illustrating the liquid crystal panel assembly of FIG. 3 taken along the line VII-VII. 8 is a cross-sectional view of the liquid crystal panel assembly of FIG. 3 taken along the line VIII-VIII.

3 to 8, the liquid crystal panel assembly according to the present exemplary embodiment includes a lower panel 100 and an upper panel 200 facing each other, and a liquid crystal layer 3 interposed between the two display panels 100 and 200. It includes.

First, the lower panel 100 will be described.

Referring to FIGS. 3, 4, 6 and 8, a plurality of pairs of first and second gate lines 121a and 121b and a plurality of insulating layers 110 are formed on an insulating substrate 110 made of transparent glass or plastic. A plurality of gate conductors including storage electrode lines 131 and a plurality of light blocking films 120s and 120n are formed.

The first and second gate lines 121a and 121b transmit gate signals and mainly extend in the horizontal direction.

The first gate line 121a includes a plurality of first gate electrodes 124a protruding downward and a wide end portion 129a for connection with another layer or a gate driver (not shown). The second gate line 121b includes a wide end portion 129b for connecting the plurality of second gate electrodes 124b protruding upward from another layer or the gate driver. When the gate driver is integrated on the substrate 110, the gate lines 121a and 121b may extend to be directly connected to the gate driver.

The storage electrode line 131 receives a predetermined voltage such as the common voltage Vcom, and mainly extends in the horizontal direction. The storage electrode line 131 is positioned between the first gate line 121a and the second gate line 121b, respectively, and is positioned at substantially the same distance from the first gate line 121a and the second gate line 121b. Each storage electrode line 131 includes a plurality of storage electrodes 137 extending up and down. However, the shape and arrangement of the storage electrode line 131 including the storage electrode 137 may be modified in various forms.

The light blocking films 120s and 120n mainly extend in the vertical direction and include a plurality of small blocking films spaced apart from each other. The light blocking layers 120n and 120s are divided into various parts so as not to be shorted with the first and second gate lines 121a and 121b and the storage electrode line 131.

The gate conductors 120s, 120n, 121a, 121b, and 131 are aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, and copper-based metals such as copper (Cu) and copper alloys. , Molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, and may be made of chromium (Cr), tantalum (Ta) and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having low resistivity, such as aluminum-based metal, silver-based metal, or copper-based metal, so as to reduce signal delay or voltage drop. In contrast, other conductive films are made of other materials, particularly materials having excellent physical, chemical, and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, tantalum, and titanium. Good examples of such a combination include a chromium bottom film and an aluminum (alloy) top film, and an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate conductors 120s, 120n, 121a, 121b, and 131 may be made of various metals or conductors.

Side surfaces of the gate conductors 120s, 120n, 121a, 121b, and 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate conductors 120s, 120n, 121a, 121b, and 131.

On the gate insulating layer 140, a plurality of linear semiconductors 151s and 151n made of hydrogenated amorphous silicon (amorphous silicon is abbreviated as a-Si), polysilicon, or the like are formed. The linear semiconductors 151s and 151n mainly extend in the longitudinal direction and include a plurality of first and second projections 154a and 154b extending toward the first and second gate electrodes 124a and 124b. .

On the semiconductors 151s and 151n, a plurality of linear ohmic contacts 161s and 161n, a first island-type ohmic contact 165a and a second island-type ohmic contact 165b165b are formed. The ohmic contacts 161s, 161n, 165a, and 165b may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are heavily doped, or may be made of silicide. The linear ohmic contacts 161s and 161n have a plurality of first protrusions 163a and second protrusions 163b, and the first and second protrusions 163a and the first and second island-type ohmic contacts ( The 165a and 165b are paired and disposed on the first and second protrusions 154a and 154b of the semiconductors 151s and 151n.

Side surfaces of the semiconductors 151s and 151n and the ohmic contacts 161s, 161n, 165a, and 165b are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

On the ohmic contacts 161s, 161n, 165a, and 165b and the gate insulating layer 140, a plurality of data lines 171s and 171n and a plurality of pairs of first and second drain electrodes 175a, A data conductor comprising 175b) is formed.

The data lines 171s and 171n transmit data signals and mainly extend in the vertical direction to intersect the gate lines 121a and 121b and the storage electrode line 131.

Each data line 171s, 171n is not in a straight line throughout, and is bent at least twice. That is, the data lines 171s and 171n include a plurality of vertical portions perpendicular to the gate lines 121s and 121n and diagonal portions inclined with respect to the vertical portions. The vertical portion and the diagonal portion are repeatedly connected, and the vertical portion and the diagonal portion are connected to form a plurality of curved portions Cs1 to Cs8 and Cn1 to Cn8. The data lines 171s and 171n overlap the light blocking films 120s and 120n, and the light blocking films 120s and 120n have curved portions according to the shapes of the data lines 171s and 171n, and the data lines 171s and 171n. Each of the data lines 171s and 171n may have a plurality of pairs of first and second source electrodes 173a and 172 extending toward the first and second gate electrodes 124a and 124b, respectively. 173b) and wide end portions 179s and 179n for connection with other layers or data drivers (not shown). When the data driver is integrated on the substrate 110, the data lines 171s and 171n may extend to be directly connected to the data driver.

The first and second drain electrodes 175a and 175b are separated from each other and also separated from the data lines 171s and 171n.

The first and second drain electrodes 175a and 175b face the first and second source electrodes 173a and 173b with respect to the first and second gate electrodes 124a and 124b, and the rod-shaped end portion thereof It is bent in the direction of the electrodes 173a and 173b and partially surrounded by the source electrodes 173a and 173b.

The first and second gate electrodes 124a and 124b, the first and second source electrodes 173a and 173b, and the first and second drain electrodes 175a and 175b are formed of the first and second semiconductors 154a and 154b. And first and second thin film transistors TFTs Qa and Qb, respectively, and channels of the first and second thin film transistors Qa and Qb are formed of first and second source electrodes, respectively. It is formed in the first and second semiconductors 154a and 154b between the 173a and 173b and the first and second drain electrodes 175a and 175b.

The data conductors 171s, 171n, 175a, and 175b are preferably made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof, and include a refractory metal film (not shown) and a low resistance conductive material. It may have a multilayer structure including a film (not shown). Examples of the multilayer structure include a double layer of chromium or molybdenum (alloy) lower layer and an aluminum (alloy) upper layer, and a triple layer of molybdenum (alloy) lower layer and aluminum (alloy) interlayer and molybdenum (alloy) upper layer. However, the data conductors 171, 175a, and 175b may be made of various other metals or conductors.

The data conductors 171s, 171n, 175a, and 175b also preferably have their side surfaces inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 161s, 161n, 165a, and 165b exist only between the semiconductors 154a and 154b below and the data conductors 171s, 171n, 175a, and 175b thereon, and lower the contact resistance therebetween. . The semiconductors 154a and 154b have portions exposed between the data electrodes 171s, 171n, 175a, and 175b as well as between the source electrodes 173a and 173b and the drain electrodes 175a and 175b.

On the other hand, it has substantially the same planar shape as the linear semiconductors 151s and 151n, the data conductors 171s, 171n, 175a and 175b, and the ohmic contacts 161s, 161n, 165a and 165b thereunder.

A passivation layer 180 is formed on the data conductors 171s, 171n, 175a, and 175b and the exposed semiconductors 154a and 154b. The passivation layer 180 may be made of an inorganic insulator or an organic insulator, and may have a flat surface. The organic insulator preferably has a dielectric constant of 4.0 or less, and may have photosensitivity. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portions of the semiconductors 154a and 154b while maintaining excellent insulating properties of the organic layer.

The passivation layer 180 has a plurality of contact holes 182s respectively exposing end portions 179s and 179n of the data lines 171s and 171n and one portions of the first and second drain electrodes 175a and 175b, respectively. , 182n, 185a, and 185b, and a plurality of contact holes 181a and 181b exposing end portions 129a and 129b of the gate lines 121a and 121b in the passivation layer 180 and the gate insulating layer 140, respectively. Is formed.

A plurality of pixel electrodes 191 and a plurality of contact assistants 81a, 81b, 82s, and 82n are formed on the passivation layer 180. They may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver, chromium or an alloy thereof.

Each pixel electrode 191 includes a pair of first and second subpixel electrodes 191a and 191b separated from each other.

The first subpixel electrode 191a is connected to each of the first drain electrodes 175a through the contact hole 185a, respectively, and the second subpixel electrode 191b is formed through the contact hole 185b. It is connected to the 2 drain electrode 175b.

The pixel electrode 191 overlaps the data lines 171s and 171n with the passivation layer 180 interposed therebetween. One data line 171s and 171n overlaps the neighboring pixel electrode 191. The data lines 171s and 171n are adjacent to the magnetic pixel electrode 191 and the magnetic pixel electrode 191 connected through the first and second thin film transistors Qa and Qb due to the bent pixel electrode 191. Both of the pixel electrodes 191 overlap with each other.

Next, a detailed structure of the pixel electrode of the liquid crystal panel assembly will be described with reference to FIGS. 9 through 12.

FIG. 9 is a schematic layout view of one pixel electrode in a liquid crystal panel assembly according to various embodiments of the present disclosure, and FIGS. 10 to 12 are plan views of electrode pieces that are the basis of each subpixel electrode illustrated in FIG. 9.

As shown in FIG. 9, each pixel electrode 191 of the liquid crystal panel assembly according to the exemplary embodiment of the present invention is a pair of first and second subpixel electrodes 191a and 191b separated from each other. It includes. The first subpixel electrode 191a and the second subpixel electrode 191b are adjacent in the row direction and have cutouts 91a and 91b. The common electrode 270 has cutouts 71a and 71b facing the first and second subpixel electrodes 191a and 191b.

Each of the first and second subpixel electrodes 191a and 191b includes at least one parallelogram electrode piece 196 shown in FIG. 10 and one parallelogram electrode piece 197 shown in FIG. 11. When the electrode pieces 196 and 197 shown in FIGS. 10 and 11 are connected up and down, the base electrode 198 shown in FIG. 12 becomes a subpixel electrode 191a and 191b. It has a structure based on.

10 and 11, each of the electrode pieces 196, 197 has a pair of oblique edges 196o, 197o and a pair of transverse edges 196t, 197t and is approximately Parallelogram. Each of the oblique sides 196o and 197o forms an oblique angle with respect to the transverse sides 196t and 197t, and the size of the oblique angle is preferably about 45 ° to 135 °. For convenience, it is divided according to the inclined direction ("inclination direction") in the vertical state with respect to the bases 196t and 197t forward, and the case inclined to the right as shown in FIG. 10 is called "right inclination" and left as shown in FIG. The case of tilting is called "left slope".

The lengths of the horizontal sides 196t and 197t of the electrode pieces 196 and 197, that is, the distance between the width W and the horizontal sides 196t and 197t, that is, the height H may be freely determined according to the size of the display panel assembly. In addition, the horizontal edges 196t and 197t of each of the electrode pieces 196 and 197 may be deformed or bent in consideration of a relationship with other portions, and will be referred to as a parallelogram in the future.

The common electrodes 270 are formed with cutouts 61 and 62 facing the electrode pieces 196 and 197, and the electrode pieces 196 and 197 have two subregions (centered around the cutouts 61 and 62). S1, S2). At least one concave or convex notch is formed in the cutouts 61 and 62. The incisions 61 and 62 form obtuse angles with the oblique portions 61o and 62o and the oblique portions 61o and 62o parallel to the hypotenuses 196o and 197o of the electrode pieces 196 and 197, respectively. And horizontal portions 61t and 62t overlapping the horizontal sides 196t and 197t of.

Each of the subregions S1 and S2 has two primary edges defined by the oblique portions 61o and 62o of the incisions 61 and 62 and the hypotenuses 196t and 197t of the electrode pieces 196 and 197. ) The distance between the periphery, i.e. the width of the subregion, is preferably about 25-40 mu m.

The basic electrode 198 illustrated in FIG. 12 is formed by combining the right inclined electrode piece 196 and the left inclined electrode piece 197. The angle formed by the right inclined electrode piece 196 and the left inclined electrode piece 197 is preferably approximately right angle, and the connection between the two electrode pieces 196 and 197 is made only in part. The unconnected portion forms the incision 90 and is located on the recessed side. However, the cutout 90 may be omitted.

Outer horizontal sides 196t and 197t of the two electrode pieces 196 and 197 form a side 198t of the base electrode 198, and corresponding hypotenuses 196o and 197o of the two electrode pieces 196 are connected to each other. To form curved edges 198o1 and 198o2 of the basic electrode 198.

Curved edges 198o1 and 198o2 meet convex edges 198o1 and transverse sides 198t and obtuse angles such as about 135 ° and acute angles, for example about 45 °. And a concave edge 198o2. The curved sides 198o1 and 198o2 are formed by a pair of hypotenuse sides 196o and 197o at approximately right angles, and thus the angle of bending is approximately right angles.

The cutout 60 extends from the concave vertex CV on the concave side 198o2 to the center of the base electrode 198 toward the convex vertex VV on the convex side 198o1.

In addition, the cutouts 61 and 62 of the common electrode 270 are connected to each other to form one cutout 60. At this time, the horizontal portions 61t and 62t overlapped by the cutouts 61 and 62 are combined to form one horizontal portion 60t1. This new form of incision 60 can be described again as follows.

The cutout 60 is connected to both ends of the bent part 60o having the bend point CP, the central horizontal portion 60t1 connected to the bend point CP of the bent part 60o, and the bent part 60o. And a pair of terminal cross sections 60t2. The bent portion 60o of the incision 60 consists of a pair of oblique portions that meet at right angles, and is substantially parallel to the bend sides 198o1 and 198o2 of the base electrode 198, and the base electrode 198 is left-right and right-sided. Divide into wealth The central horizontal portion 60t1 of the incision 60 forms an obtuse angle, for example about 135 °, with the bend 60o and extends toward the convex vertex VV of the basic electrode 198. The terminal horizontal portion 60t2 is aligned with the horizontal side 198t of the base electrode 198 and forms an obtuse angle with the bend portion 60o, for example, about 135 °.

The base electrode 198 and the incision 60 are approximately inverted symmetric with respect to an imaginary straight line (referred to as a "horizontal center line" forward) connecting the convex vertex (VV) and the concave vertex (CV) of the base electrode 198.

In each pixel electrode 191 illustrated in FIG. 9, the size of the first subpixel electrode 191a is smaller than that of the second subpixel electrode 191b. In particular, the height of the second subpixel electrode 191b is higher than the height of the first subpixel electrode 191a, and the widths of the two subpixel electrodes 191a and 191b are substantially the same. The number of electrode pieces of the second subpixel electrode 191b is larger than the number of electrode pieces of the first subpixel electrode 191b.

The first subpixel electrode 191a includes a left inclined electrode piece 197 and a right inclined electrode piece 196, and has a structure substantially the same as that of the basic electrode 198 illustrated in FIG. 12. Part of the two electrode pieces 196 and 197 is connected, and the unconnected portion forms the cutout 91a and is located at the recessed side.

The second subpixel electrode 191b is formed of a combination of two or more left inclined electrode pieces 197 and two or more right inclined electrode pieces 196, and is coupled to the basic electrode 198 illustrated in FIG. 12. Left and right inclined electrode pieces 196 and 197 are included.

The second subpixel electrode 191b shown in FIG. 9 includes six electrode pieces 191b1-191b6, and two of the electrode pieces 191b5 and 191b6 are disposed above and below the first subpixel electrode 191a. It is arranged. Part of the lower electrode pieces 191b3 and 191b5 is connected to a portion of the hypotenuse 196o, and the unconnected portion forms a cutout, and becomes a lower diagonal cutout 91b1 of the cutout 91a of the pixel electrode 191. . The upper two electrode pieces 191b4 and 191b6 are connected to a portion of the hypotenuse 197o and the unconnected portion forms an incision, and becomes an upper oblique incision 91b2 of the incision 91a of the pixel electrode 191. .

The intermediate electrode pieces 191b1 and 191b2 of the first subpixel electrode 191a and the second subpixel electrode 191b are separated by the gaps 91b3 and 91b4, and the gaps 91b3 and 91b4 are the pixel electrodes 191. The lower oblique cutout portion 91b1 and the upper oblique cutout portion 91b2 of each of the upper and lower diagonal cutouts 91b2 are connected to form the cutout 91a of the pixel electrode 191. The cutout 91a may be connected to the cutout 91b of the bent portion. A gap formed between the electrode pieces 191b5 and 191b6 of the second subpixel electrode 191b adjacent to the upper and lower portions of the first subpixel electrode 191a is connected to the cutout 91a of the pixel electrode 191. .

At least one concave or convex notch is formed in the cutout 91a of the pixel electrode 191.

The pixel electrode 191b has a structure that is bent three times, and has a better vertical line expression than the structure that is curved once. In addition, the cutout portion 61 of the common electrode 270 where the electrode pieces 191a1 and 191a2 of the first subpixel electrode 191a and the electrode pieces 191b5 and 191b6 of the second subpixel electrode 191b are adjacent to each other. Since the horizontal portions 61t and 62t of 62 are combined to form one horizontal portion, the aperture ratio is further increased.

The heights of the intermediate electrode pieces 191a1, 191a2, 191b1, and 191b2 and the electrode pieces 191b3-191b6 disposed above and below are different from each other. For example, the heights of the upper and lower electrode pieces 191b3-191b6 are about 1/2 of the intermediate electrode pieces 191a1, 191a2, 191b1, and 191b2, and thus, the first subpixel electrode 191a and the second subpixel electrode. The area ratio of 191b is approximately 1: 2. Thus, by adjusting the height of the upper and lower electrode pieces 191b3-191b6, a desired area ratio can be obtained.

In FIG. 9, the positional relationship and the bending directions of the first and second subpixel electrodes 191a and 191b may be changed, and the pixel electrode 191 of FIG. 9 may be deformed by inverting symmetry or rotating in the vertical direction. .

Referring to FIGS. 3 to 8 again, the first and second subpixel electrodes 191a and 191b and the common electrode 270 of the upper panel 200 are respectively formed together with portions of the liquid crystal layer 3 therebetween. And the second liquid crystal capacitors Clca and Clcb to maintain the applied voltage even after the thin film transistors Qa and Qb are turned off.

The first and second subpixel electrodes 191a and 191b overlap the storage electrode 137 with the gate insulating layer 140 interposed therebetween to form first and second storage capacitors Csta and Cstb, respectively. The second storage capacitors Csta and Cstb enhance the voltage holding capability of the first and second liquid crystal capacitors Clca and Clcb.

The pixel electrode 191 overlaps the data line 171 with the passivation layer 180 interposed therebetween. In this case, the pixel electrode 191 is not only connected to the data line 171s (hereinafter referred to as a "magnetic data line") connected through the thin film transistor, but also is not connected to the pixel electrode 191 and is adjacent to the magnetic data line 171s. The line 171n (hereinafter referred to as "neighbor data line") also overlaps.

Based on one data line 171, the data line 171 is connected to the pixel electrode 191 bent several times and overlaps the two neighboring pixel electrodes 191.

The light blocking films 120s and 120n are formed under the linear semiconductors 151s and 151n and the data lines 171 along the portions of the linear semiconductors 151s and 151n and the data lines 171s and 171n. At this time, the width of the light blocking film 120s formed under the data line 171s overlapping the second subpixel electrode 191b is larger than the width of the linear semiconductor 151s in consideration of the aperture ratio and a process placement error. Formed. However, in order to prevent the opening ratio from being excessively reduced due to the light blocking films 120s and 120n, the width of the light blocking film 120 may be the same as that of the linear semiconductors 151s and 151n.

The contact auxiliary members 81a, 81b, 82s, and 82n respectively have end portions 129a and 129b and data lines 171s and 171n of the gate lines 121a and 121b through the contact holes 181a, 181b, 182s, and 182n, respectively. Is connected to the end portions 179s and 179n. The contact auxiliary members 81a, 81b, 82a, and 82b adhere to the end portions 129a and 129b of the gate lines 121a and 121b and the end portions 179a and 179b of the data lines 171s and 171n and the external device. Complement and protect them.

Next, the upper panel 200 will be described.

3 and 5 to 8, a light blocking member 220 is formed on an insulating substrate 210 made of transparent glass, plastic, or the like. The light blocking member 220 includes a linear portion corresponding to the gate lines 121a and 121b and a planar portion corresponding to the thin film transistor. The light blocking member 220 may correspond to a gap between the pixel electrode 191 and the pixel electrode 191. The light blocking member 220 prevents light leakage between the pixel electrodes 191 and defines an opening area facing the pixel electrode 191.

A plurality of color filters 230 is also formed on the substrate 210 and the light blocking member 220. The color filter 230 is mostly present in an opening area surrounded by the light blocking member 220, and may extend long along the column of pixel electrodes 191. Each color filter 230 may display one of primary colors such as three primary colors of red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light blocking member 220. The overcoat 250 may be made of an (organic) insulator, which prevents the color filter 230 from being exposed and provides a flat surface. The overcoat 250 may be omitted.

The common electrode 270 is formed on the overcoat 250.

A plurality of cutouts 71a and 71b are formed in the common electrode 270. The cutouts 71a and 71b have been described above and thus will be omitted.

Alignment layers 11 and 21 are formed on inner surfaces of the display panels 100 and 200, and they may be vertical alignment layers.

Next, the operation of the liquid crystal display will be described in detail.

1 and 2, the input image signals R, G, and B applied to the liquid crystal display assembly contain luminance information of each pixel PX, and luminance is determined by a predetermined number, for example, 1024 ( = 2 ¹⁰ ), 256 (= 2 ⁸ ) or 64 (= 2 ⁶ ) grays. The input image signal is properly processed by a signal controller (not shown) according to operating conditions, and then input to the data line and the gate line through the data driver and the gate driver of the liquid crystal panel assembly.

When the gate-on voltage Von is applied to the gate line, the switching element connected to the gate line is turned on. Then, the data signal applied to the data line is applied to the corresponding subpixel through the turned-on switching element.

In this case, the first subpixel electrode 191a and the second subpixel electrode 191b constituting the pixel electrode 191 are connected to separate switching elements, so that the two subpixels are connected to each other through the same data line at different times. A separate data voltage is applied. The voltage of the first subpixel electrode 191a having a relatively small area is higher than the voltage of the second subpixel electrode 191b having a relatively large area.

When a potential difference occurs between both ends of the first or second liquid crystal capacitors Clca and Clcb, a primary electric field substantially perpendicular to the surfaces of the display panels 100 and 200 is generated in the liquid crystal layer 3. . [Hereinafter, the pixel electrode 191 and the common electrode 270 will be referred to as "field generating electrodes." Then, the liquid crystal molecules of the liquid crystal layer 3 respond to the electric field, and its long axis is in the direction of the electric field. The angle of inclination is perpendicular, and the degree of change in polarization of incident light in the liquid crystal layer 3 varies according to the degree of inclination of the liquid crystal molecules. This change in polarization is represented by a change in transmittance by the polarizer, through which the liquid crystal display displays an image.

The angle at which the liquid crystal molecules are inclined depends on the intensity of the electric field. Since the voltages of the two liquid crystal capacitors Clca and Clcb are different from each other, the angles at which the liquid crystal molecules are inclined are different and thus the luminance of the two subpixels is different. Therefore, if the voltage of the first liquid crystal capacitor Clca and the voltage of the second liquid crystal capacitor Clcb are properly adjusted, the image viewed from the side can be as close as possible to the image viewed from the front, that is, the side gamma curve is front- gamma. As close as possible to the curve, this improves side visibility.

In addition, when the area of the first subpixel electrode 191a to which a high voltage is applied is smaller than the area of the second subpixel electrode 191b, the side gamma curve may be closer to the front gamma curve. In particular, when the area ratios of the first and second subpixel electrodes 191a and 191b are approximately 1: 2 to 1: 3, the side gamma curve becomes closer to the front gamma curve, thereby improving side visibility.

The direction in which the liquid crystal molecules are inclined is determined primarily by the horizontal component generated by distorting the main electric field between the cutouts 71a, 71b and 91a of the field generating electrodes 191 and 270 and the subpixel electrodes 191a and 191b. do. The horizontal component of the main electric field is substantially perpendicular to the sides of the cutouts 71a, 71b, 91a and the sides of the subpixel electrodes 191a, 191b.

Referring to FIG. 9, since the liquid crystal molecules on each of the subregions divided by the cutouts 71a and 71b are inclined in a direction perpendicular to the periphery, the four directions are approximately four directions. As described above, when the liquid crystal molecules are inclined in various directions, the reference viewing angle of the liquid crystal display is increased.

On the other hand, the direction of the secondary electric field generated by the voltage difference between the subpixel electrodes 191a, 191b is perpendicular to the periphery of the subregion. Thus, the direction of the negative electric field coincides with the direction of the horizontal component of the main electric field. As a result, the negative electric field between the subpixel electrodes 191a and 191b acts to strengthen the crystal in the oblique direction of the liquid crystal molecules.

Meanwhile, referring to FIG. 4, the second subpixel electrode 191b overlaps the magnetic data line 171s and the neighboring data line 171n, and the first and second parasitic capacitances C1 and C2 are respectively disposed therebetween. The voltages of the magnetic data line 171s and the neighboring data line 171n fluctuate. The pixel electrode voltage swings up and down in accordance with the voltage change of the magnetic data line 171s and the neighboring data line 171n. Here, when a positive voltage is applied to the magnetic data line 171s and a negative voltage is applied to the neighboring data line 171n, the fluctuation phases of the voltages of the two data lines 171s and 171n are changed. Since it is the reverse, the fluctuation of the pixel electrode voltage may be canceled out.

In particular, when the area where the magnetic data line 171s and the second subpixel electrode 191b overlap is the same as the area where the neighboring data line 171n and the second subpixel electrode 191b overlap, the two parasitic capacitances C1 And C2 are the same so that the voltage fluctuations of the magnetic data line 171s and the voltage fluctuations of the neighboring data line 171n are completely canceled out so that the pixel electrode voltage remains unchanged.

In an exemplary embodiment of the present invention, the curved portion Cn1 of the data line 171n neighboring the second subpixel electrode 191b is positioned to position the data line 171n neighboring the second subpixel electrode 191b. ) And overlapping area of each other, the second subpixel electrode 191b and the magnetic data line 171s are minimized. Therefore, the area of the second subpixel electrode 191b overlapping the two data lines 171s and 171n is similar to minimize the voltage change of the two data lines 171s and 171n due to the parasitic capacitance difference.

Therefore, in the exemplary embodiment of the present invention, an area ratio where the second subpixel electrode 191b and the magnetic data line 171s overlap and an area ratio where the second subpixel electrode 191b and the neighbor data line 171s overlap 1: 0.2 to 0.45. When the width of the pixel electrode 191 is 200 to 250 μm, the area ratio may be 1: 0.2 to 0.3, and when the width of the pixel electrode 191 is 150 to 200 μm, the area ratio may be 1: 0.35 to 0.45.

FIG. 13 is a graph illustrating a luminance difference of the liquid crystal display according to the present invention and the prior art, FIG. 14 is a diagram for explaining FIG. 13, and Table 1 is a graph showing the maximum and minimum voltages of the graph shown in FIG. 13. This table shows the difference.

The graph of FIG. 13 is a graph showing the voltage difference between the B area and the C area according to the gray level change of the A area when the background of FIG. 14 is 171 (gray) gray level.

13 and 14, when the gray level of the A region is changed from 0 to 253 gray level, the voltage difference (yellow and red line) of the liquid crystal display according to the present invention is the voltage difference according to the prior art (blue line). You can see that it is smaller. That is, since the voltage difference of the liquid crystal display device according to the present invention is small, the luminance change according to the present invention may be small, thereby displaying a stable screen.

Here, the horizontal axis represents the gray level change in the A region, and the vertical axis represents the voltage difference in the B region and the C region.

Referring to Table 1 below, it can be seen that the voltage difference average of the liquid crystal display according to the present invention is 14.7mV and the voltage difference average according to the prior art is 34mV, and the voltage difference is reduced by 1/2 or more as compared with the related art.

Table 1

According to the present invention, it is possible to minimize the luminance change caused by the parasitic capacitance change due to the superposition of the data line and the pixel electrode, thereby stably displaying the screen and providing a high quality liquid crystal display device.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (13)

Board, A first gate line and a second gate line formed on the substrate; A first data line intersecting the first gate line and the second gate line, the first data line including a plurality of bent portions formed by repeatedly connecting a plurality of vertical portions and diagonal portions; A second data line adjacent to the first data line and parallel to the first data line, A first thin film transistor connected to the first gate line and the first data line, A second thin film transistor connected to the second gate line and the first data line, A pixel electrode including a first subpixel electrode connected to the first thin film transistor and a second subpixel electrode connected to the second thin film transistor; Including, The second subpixel electrode overlaps the first data line and the second data line; The first region where the vertical portion of the data line crossing the second gate line and the second subpixel electrode overlap is narrower than the second region where the bent portion adjacent to the first gate line and the second subpixel electrode overlap. Thin film transistor display panel. In claim 1, The area ratio of the first region and the second region is 1: 0.2 to 0.45. In claim 2, The area ratio of the first region and the second region when the width of the pixel electrode is 150 to 200 μm, wherein the area ratio is 1: 0.3 to 0.45. In claim 2, The area ratio of the first region and the second region when the width of the pixel electrode is 200 to 250㎛, the thin film transistor array panel. In claim 1, The first and second subpixel electrodes include at least two parallelogram electrodes having different oblique directions. In claim 5, The first subpixel electrode includes one right inclined parallelogram electrode piece and one left inclined parallelogram electrode piece, And the second subpixel electrode includes three right tilted parallelogram electrodes and three left tilted rectangular electrodes. In claim 6, The area of the second subpixel electrode is wider than the area of the first subpixel electrode. In claim 7, The second subpixel electrode partially surrounds the first subpixel electrode. In claim 1, And a light blocking layer formed on the substrate and overlapping the first and second data lines and separated from the gate line. In claim 1, The thin film transistor array panel of which the voltages of the first subpixel electrode and the second subpixel electrode are different from each other. In claim 10, And the first and second thin film transistors are turned on according to the signals from the first and second gate lines, respectively, to transfer the signals from the first data line. In claim 1, The thin film transistor array panel of claim 1, further comprising an organic layer formed between the first and second data lines and the drain electrode and the pixel electrode. In claim 1, And a data voltage polarity applied to the first data line and a data voltage polarity applied to the second data line are opposite to each other.

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