KR101232044B1 - Array substrate, method of manufacturing the same and display panel having the same - Google Patents

Abstract

An array substrate for improving a viewing angle and an aperture ratio, and a display panel having the same are disclosed. The array substrate includes a switching element, a storage capacitor, and a voltage distribution capacitor. The switching element is formed in a pixel region defined by adjacent gate lines and adjacent data lines. The storage capacitor is formed on the storage common line across the data line and is electrically connected to the switching element. The voltage distribution capacitor is formed between the storage capacitor and the gate wiring and is electrically connected to the storage capacitor. As a result, the viewing angle and the aperture ratio of the pixel region can be improved.

Storage Capacitor, PAV, Opening Ratio, Viewing Angle

Description

ARRAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND DISPLAY PANEL HAVING THE SAME}

1 is a plan view illustrating a pixel unit of a display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

3 to 10 are process diagrams for describing a manufacturing process of the array substrate illustrated in FIG. 1.

11 is a conceptual diagram illustrating an inclination angle of liquid crystal molecules according to an exemplary embodiment of the present invention.

12 is a plan view illustrating a pixel unit of an array substrate according to another exemplary embodiment of the present invention.

FIG. 13 is a conceptual diagram illustrating an inclination angle of liquid crystal molecules according to another exemplary embodiment shown in FIG. 12.

<Description of the symbols for the main parts of the drawings>

110 switching element 111 gate electrode

113: source electrode 114: drain electrode

131: main pixel electrode 132: first sub pixel electrode

133: second sub-pixel electrode 150: storage capacitor

160: first voltage-distributing capacitor í ° ° 170: second voltage-distributing capacitor

The present invention relates to an array substrate and a display panel having the same, and more particularly, to an array substrate for improving a viewing angle and an aperture ratio, and a display panel having the same.

In general, a liquid crystal display device has a disadvantage in that it has a narrower viewing angle than a CRT display device. In order to further extend the viewing angle of an image generated in the liquid crystal display device, recently, a liquid crystal display device having a patterned vertical alignment (PVA) mode, a multi-domain vertical alignment (MVA) mode, and an in-plane switching (IPS) mode has been developed. There is a bar.

The PVA mode liquid crystal display includes liquid crystal molecules vertically aligned with respect to the upper and lower substrates, and a constant opening pattern is formed on the pixel electrode and the common electrode opposite thereto. The viewing angle of the image generated in the PVA mode liquid crystal display is extended by a fringe field formed by the pixel electrode and the common electrode.

The technical problem of the present invention has been devised in this respect, and an object of the present invention is to provide an array substrate for improving the viewing angle and aperture ratio. Another object of the present invention is to provide a method of manufacturing the array substrate. Another object of the present invention is to provide a display panel having the array substrate.

An array substrate according to an embodiment for realizing the above object of the present invention includes a switching element, a storage capacitor and a voltage distribution capacitor. The switching element is formed in a pixel region defined by adjacent gate lines and adjacent data lines. The storage capacitor is formed on the storage common line across the data line and is electrically connected to the switching element. The voltage distribution capacitor is formed between the storage capacitor and the gate line and is electrically connected to the storage capacitor.

Preferably, the size of the storage capacitor is formed larger than the size of the voltage distribution capacitor.

In addition, the storage capacitor is defined by the storage common wiring and the storage electrode disposed on the storage common wiring extending from the drain electrode of the switching element.

In addition, the voltage distribution capacitor includes a floating electrode formed in an island shape in the pixel area separated from the storage common line.

In more detail, the voltage divider capacitor is defined by the voltage divider capacitor electrode and the floating electrode which extends from the storage electrode and is disposed on the floating electrode.

The array substrate may further include a main pixel electrode electrically connected to the storage electrode through a first contact hole, and a sub pixel electrode electrically connected to the floating electrode through a second contact hole.

An array substrate according to another embodiment of the present invention includes a switching element, a storage capacitor, a first voltage sharing capacitor, and a second voltage sharing capacitor. The switching element is formed in the pixel region. The storage capacitor includes a storage common line dividing the pixel area into a first area and a second area, and a storage electrode extending from the drain electrode of the switching element and disposed on the storage common line. The first voltage divider capacitor includes a first floating electrode formed in the first region, and a first voltage divider capacitor electrode extending from the storage electrode and formed on the first floating electrode. The second voltage divider capacitor includes a second floating electrode formed in the second region, and a second voltage divider capacitor electrode extending from the storage electrode and formed on the second floating electrode.

Preferably, the array substrate includes a main pixel electrode electrically connected to a storage electrode of the storage capacitor and a first sub pixel electrode electrically connected to a first floating electrode of the first voltage distribution capacitor and formed at one side of the main pixel electrode. And a second sub pixel electrode electrically connected to the second floating electrode of the second voltage distribution capacitor and formed on the other side of the main pixel electrode.

For example, an opening pattern in which a predetermined region is opened is formed in the main pixel electrode and the first and second sub pixel electrodes.

For example, the first and second voltage distribution capacitors may be formed in the same size, and optionally, the first and second voltage distribution capacitors may be formed in different sizes.

The display panel according to an exemplary embodiment of the present invention includes a liquid crystal layer, a first substrate, and a second substrate. The first substrate includes a common electrode. The second substrate receives the liquid crystal layer through coalescence with the first substrate. The second substrate includes a storage capacitor and a first voltage sharing capacitor. The storage capacitor includes a storage common wiring and a storage electrode formed on the storage common wiring, and the first voltage distribution capacitor is formed on a first floating electrode and the first floating electrode and is electrically connected to the storage electrode. And a voltage-sharing capacitor electrode.

The first floating electrode of the voltage distribution capacitor is formed spaced apart from the storage common line.

The second substrate further includes a main pixel electrode electrically connected to the storage electrode of the storage capacitor, and a first sub pixel electrode electrically connected to the first floating electrode of the first voltage distribution capacitor. The first sub pixel electrode has a first opening pattern in which a predetermined region is opened.

Preferably, the common electrode includes a second opening pattern in which a predetermined region that is shifted from the region in which the first opening pattern is formed is opened.

For example, the storage capacitor and the first voltage distribution capacitor are formed in different sizes. Therefore, the liquid crystal layer interposed between the main pixel electrode and the liquid crystal common electrode is driven at a first inclination angle, and the liquid crystal layer interposed between the sub pixel electrode and the liquid crystal common electrode has a second inclination angle different from the first inclination angle. Is driven.

Preferably, the second substrate further includes a second voltage dividing capacitor further comprising a second floating electrode and a second voltage dividing capacitor electrode formed on the second floating electrode and electrically connected to the storage electrode. The first and second voltage bonsai capacitors are disposed opposite each other based on the storage common wiring.

The first voltage divider capacitor and the second voltage divider capacitor may have different sizes.

The liquid crystal display according to the exemplary embodiment of the present invention includes a main liquid crystal capacitor, a first sub liquid crystal capacitor, a storage capacitor, and a first voltage distribution capacitor. The main liquid crystal capacitor is applied with a pixel voltage from the switching element. The first sub liquid crystal capacitor is formed adjacent to the main liquid crystal capacitor. The storage capacitor maintains the pixel voltage applied to the main liquid crystal capacitor for a predetermined time. The pixel voltage is applied to the first voltage sharing capacitor, and a voltage smaller than the applied pixel voltage is applied to the first sub liquid crystal capacitor.

For example, the first sub liquid crystal capacitor and the storage capacitor are connected in parallel, and the first sub liquid crystal capacitor and the first voltage division capacitor are connected in series to distribute the applied pixel voltage to the first sub liquid crystal capacitor. To apply.

The main liquid crystal capacitor may include a common electrode formed on a second substrate, a main pixel electrode formed on a first substrate, and a liquid crystal layer formed between the common electrode and the main pixel electrode, and the storage capacitor may include the main pixel electrode; The storage electrode may be electrically connected to the switching element, and may include a storage electrode to which the pixel voltage is applied, and a storage common wiring spaced apart from the storage electrode.

The first sub liquid crystal capacitor may include a common electrode formed on the second substrate, a first sub pixel electrode formed on the first substrate, and a liquid crystal layer formed between the common electrode and the first sub pixel electrode. The first voltage-sharing capacitor is electrically connected to the first metal pattern to be spaced apart from the first voltage-sharing capacitor electrode and the first voltage-sharing capacitor electrode to which the pixel voltage is applied, and faces the second metal pattern. And a first floating electrode electrically connected to the subpixel electrode.

Preferably, a second sub liquid crystal capacitor adjacent to the storage capacitor and the pixel voltage are applied and connected in series with the second sub liquid crystal capacitor to distribute the applied pixel voltage to the second sub liquid crystal capacitor. It further comprises a two voltage distribution capacitor.

For example, the first and second liquid crystal capacitors are located in opposite directions with respect to the main liquid crystal capacitor.

For example, the capacity of the first liquid crystal capacitor is the same as that of the second liquid crystal capacitor, but may be formed differently.

According to an embodiment of the present invention, an array substrate manufacturing method includes forming a first metal layer on a base substrate, patterning the first metal layer to form a gate electrode, a storage common wiring, and a first floating electrode spaced apart from the storage common wiring. Forming a gate insulating film on a base substrate on which the gate electrode, the storage common wiring, and the first floating electrode are formed; and exposing a portion of the gate insulating film to expose the first floating electrode. Forming a second metal layer on the gate insulating layer; etching the second metal layer to form a drain electrode on the gate electrode; a source electrode spaced apart from the drain electrode; and electrically connected to the drain electrode. The storage electrode disposed on the storage common wiring, the first metal pattern and the electrical Forming a first voltage division capacitor electrode connected to the first floating electrode and disposed on the first floating electrode; exposing the first floating electrode by removing a portion of the first voltage division capacitor electrode; Forming a transparent conductive layer electrically connected to the first floating electrode and the storage electrode, and patterning the transparent conductive layer to form a first subpixel electrode electrically connected to the first floating electrode; And forming a main pixel electrode insulated from the first sub pixel electrode and electrically connected to the first metal pattern. According to the array substrate and the display panel having the same, a floating of the common electrode and the sub capacitor of the storage capacitor is performed. Reduced overlapping area between electrodes and data lines, improving viewing angle and It can improve guyul.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view illustrating a pixel unit of a display panel according to an exemplary embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

1 and 2, the display panel includes an array substrate 100, an opposing substrate 200, and a liquid crystal layer 300.

The array substrate 100 includes a plurality of gate lines GL extending in a first direction on the base substrate 101 and a plurality of data (or source) lines extending in a second direction crossing the first direction. DLs and a plurality of pixel parts defined by the gate lines GL and data lines DL.

Each pixel unit includes a main liquid crystal capacitor to which a pixel voltage is applied from a switching element, a first sub liquid crystal capacitor formed adjacent to the main liquid crystal capacitor, and a pixel voltage applied to the main liquid crystal capacitor in parallel with the main liquid crystal capacitor. The storage capacitor and the pixel voltage is applied to maintain a predetermined time, the first voltage distribution capacitor is connected in series with the first sub liquid crystal capacitor to distribute the applied pixel voltage to the first sub liquid crystal capacitor Include.

In more detail, the pixel unit 110 includes a switching element 110, a main pixel electrode 131, a first sub pixel electrode 132, a second sub pixel electrode 133, a storage capacitor 150, and a first voltage distribution capacitor. 160 and a second voltage divider capacitor 170.

The switching element 110 includes a gate electrode 111 connected to the gate line GL, a source electrode 113 and a drain electrode 114 connected to the data line DL. The semiconductor layer 112 is formed between the gate electrode 111 and the source and drain electrodes 113 and 114. The semiconductor layer 112 includes an active layer 112a and an ohmic contact layer 112b. The switching element 110 shown in FIG. 2 illustrates a general reverse staggered structure.

The main pixel electrode 131 is electrically connected to the drain electrode 114 through the first contact hole 153. The first sub pixel electrode 132 and the second sub pixel electrode 133 are formed symmetrically with respect to the main pixel electrode 131.

V-shaped first opening patterns 135 are formed on the main pixel electrodes and the first to second sub pixel electrodes 131, 132, and 133. The main pixel electrode and the first to second subpixel electrodes 131, 132, and 133 are spaced apart from each other and electrically insulated from each other.

The storage capacitor 150 includes a storage common wiring 151 and a storage electrode 152. The storage common line 151 is formed in parallel with the gate line GL, and bisects the pixel portion into a first region P1 and a second region P2. The storage capacitor 150 is connected in parallel with the liquid crystal capacitor formed of the main pixel electrode 131, the liquid crystal layer 300, and the common electrode 230. Thus, the storage capacitor 150 assists the liquid crystal capacitor so that the voltage applied to the liquid crystal capacitor is maintained for one frame.

In detail, the storage common wiring 151 having the first size disposed in the pixel portion is a first electrode of the storage capacitor 150, and the storage electrode 152 extending from the drain electrode 114 is the storage. It is the second electrode of the capacitor 150. In addition, a first contact hole 153 is formed in the insulating layer 104 positioned on the storage electrode 152 to electrically connect the drain electrode 114 and the main pixel electrode 131. . The gate insulating layer 102 formed between the storage electrode 152 and the storage common wiring 151 spaces the storage electrode 152 from the storage common wiring 151.

The storage electrode 152 is electrically connected to the drain electrode 114 of the switching element 110 to receive a pixel voltage output from the switching element, and the pixel voltage is a main pixel electrode electrically connected to the storage electrode 152. 131).

Therefore, since the storage electrode 152 and the main pixel electrode 131 to which the same voltage (pixel voltage) is applied are electrically connected, the storage capacitor 150 and the main pixel electrode (including the storage electrode 152) are electrically connected. The connection relationship of the liquid crystal capacitor including 131 corresponds to the parallel connection electrically. The first voltage division capacitor 160 includes a first floating electrode 161 and a first voltage division capacitor electrode 162.

The first floating electrode 161 has a second size smaller than the first size of the storage common line. A first voltage distribution capacitor electrode 162 extending from the storage electrode 152 is formed on the first floating electrode 161. The first floating electrode 161 is electrically connected to the first sub pixel electrode 132 through a second contact hole 163. The first voltage distribution capacitor electrode 162 is electrically connected to the storage electrode 152 so that a pixel voltage output from the drain electrode 114 of the switching element 110 is applied through the storage electrode 152. .

Accordingly, since the first sub pixel electrode is electrically connected to the first floating electrode 161 facing the first voltage division capacitor, the first sub liquid crystal capacitor including the first sub pixel electrode and the first sub pixel electrode are electrically connected. The connection relationship of the first voltage sharing capacitor including the floating electrode 161 corresponds to the series connection. Therefore, since the pixel voltage applied to the first voltage division capacitor electrode 162 is divided by the first voltage division capacitor and the first sub liquid crystal capacitor, a voltage smaller than the pixel voltage is applied to the first sub liquid crystal capacitor. .

The second sub capacitor 170 includes a second floating electrode 171, a second voltage distribution capacitor electrode 172, a third contact hole 173, a second sub pixel electrode 133, and the floating electrode. 230.

The second floating electrode 171 is formed to have the same size as the second size of the first floating electrode 161. That is, the first and second floating electrodes 161 and 171 are formed symmetrically with respect to the storage common wiring 151.

A second voltage distribution capacitor electrode 172 extending from the storage electrode 152 is formed on the second floating electrode 171. The second floating electrode 171 is electrically connected to the second sub pixel electrode 133 through a third contact hole 173 to become a first electrode of the second sub capacitor 170. The second electrode of the second subcapacitor 170 is the liquid crystal common electrode.

 The opposing substrate 200 forms a light blocking layer 210, a color filter layer 220, and a common electrode 230 on the base substrate 201.

The light blocking layer 210 is patterned to define an internal space corresponding to the pixel portion on the base substrate 201 and block leakage light.

The color filter layer 220 is formed in the internal space defined by the light blocking layer 210. The color filter layer 220 includes red (R), green (G), and blue (B) colors, and expresses a unique color in response to incident light.

The common electrode 230 is formed on the color filter layer 220 and is a liquid crystal common electrode facing the pixel electrode 130 of the array substrate 100. A second opening pattern 235 is formed in the common electrode 230 to deviate from the first opening pattern 135 of the first to second sub pixel electrodes 131, 132, and 133. That is, the second opening pattern 235 is formed to correspond to an area where the first opening pattern 135 is not formed.

A planarization layer may be formed on the light blocking layer 210 and the color filter layer 220 to serve as a planarization layer and a protective layer.

The liquid crystal layer 300 is interposed between the array substrate 100 and the counter substrate 200, and is disposed by the potential difference between the pixel electrodes 131, 132, 133, and the common electrode 230 of the counter substrate 200. The arrangement angle of the liquid crystal molecules is changed.

3 to 10 are process diagrams for describing a manufacturing process of the array substrate illustrated in FIG. 1.

3 and 4, a gate metal layer is formed on the base substrate 101. The gate metal layer is patterned by photolithography using a first mask 410. The gate wiring GL, the storage common wiring 151, the first floating electrode 161, the second floating electrode 171, and the gate electrode 111 are formed on the base substrate 101.

As shown in FIG. 4, the storage common line 151 is formed between two adjacent gate lines GLn-1 and GLn. The storage common line 151 bisects the pixel portion defined by the two adjacent gate lines GLn-1 and GLn into a first region P1 and a second region P2.

The first and second floating electrodes 161 and 171 are formed in island shapes in the first and second regions P1 and P2, respectively. Preferably it is formed to be symmetrical with respect to the storage common wiring 151.

As the first and second floating electrodes 161 and 171 are formed in an island shape in the pixel portion, an area overlapping with a data line DL formed later is reduced.

This structure improves the aperture ratio of the pixel portion and reduces the RC delay of the data line DL. In addition, the possibility of generating an electrical short between the storage common line (or gate line) and the data line is reduced.

5 to 8, a gate insulating layer 102 is formed on the gate metal layer. The gate insulating layer 102 is formed of an insulating material such as silicon nitride and silicon oxide to a thickness of approximately 4500 angstroms.

The semiconductor layer 112 is formed on the gate insulating layer 102.

Specifically, an amorphous silicon film and an in-situ doped n + amorphous silicon film are sequentially stacked on the gate insulating layer 102 by a plasma chemical vapor deposition method. The stacked amorphous silicon film and the n + amorphous silicon film are patterned to form a semiconductor layer 112 including an active layer 112a and an ohmic contact layer 112b on an upper portion of the gate electrode 111.

The data metal layer is formed on the resultant product on which the semiconductor layer 112 is formed.

The data metal layer is patterned by a photolithography process using a second mask 420 on the base substrate 101 on which the data metal layer is formed. The patterned data metal layer may include the data line DL, the storage electrode 152, the first voltage-sharing capacitor electrode 162, the second voltage-sharing capacitor electrode 172, the source electrode 113, and the drain electrode 114. Include. Second and third contact holes 163 and 173 are formed in the second and second voltage distribution capacitor electrodes 162 and 172, respectively.

As illustrated in FIG. 8, the data line DL is formed to be arranged in a direction crossing the gate line GL. The storage electrode 152 is formed on the storage common line 151, and the first and second voltage distribution capacitor electrodes 162 and 172 are formed on the first and second floating electrodes 161 and 171, respectively.

The first voltage division capacitor electrode 162 extends from the storage electrode 152 and is formed on the first floating electrode 161, and the second voltage division capacitor electrode 172 is formed from the storage electrode 152. It extends and is formed on the second floating electrode 171. Second and third contact holes 163 and 173 are formed in the first and first voltage distribution capacitor electrodes 162 and 172, respectively.

The source and drain electrodes 113 and 114 are formed to be overlaid on a portion of the semiconductor layer 112, and by removing the ohmic contact layer 112b by using the source and drain electrodes 113 and 114 as masks. The channel region 110.

6 and 7, a passivation layer 103 is formed on the patterned data metal layer. The passivation layer 103 is formed of an inorganic protective film to a thickness of about 4000 angstroms or less.

An organic insulating layer 104 is formed by applying a photosensitive organic resist on the passivation layer 103 to a thickness of about 2 μm to 4 μm by a spin coating method. The organic insulating layer 104 may not be formed.

The organic insulating layer 104 and the gate insulating layer 102 formed in the first to third contact holes 153, 163, and 173 are removed by a photolithography process using the third mask 430. Specifically, an organic insulating layer formed on the second and third contact holes 163 and 173 is formed by forming a first contact hole 153 exposing a portion of the storage electrode 152 extending from the drain electrode 114. The layer 104, the passivation layer 103, and the gate insulating layer 102 are removed. Although not shown, the passivation layer 103 formed in the first to third contact holes 153, 163, and 173 may be etched first, and then the organic insulating layer 104 may be etched.

As illustrated in FIG. 8, the only area where the data line DL overlaps the gate metal layer is an area where the storage common line 151 and the data line DL cross each other. That is, since the first and second floating electrodes 161 and 171 extend from the storage common line 151 to form an island shape, the first and second floating electrodes 161 and 171 do not overlap with the data line DL.

As a result, the overlapping area between the gate wiring, that is, the storage common wiring 151 and the data wiring DL is reduced, so that the aperture ratio of the pixel portion is improved, and the RC delay of the data wiring is reduced.

In addition, the possibility of an electrical short between the storage common line 151 and the data line DL can be reduced.

9 and 10, a pixel electrode ¸ µ 130 is formed on the base substrate 101 on which the organic insulating layer 104 is formed. The pixel electrode layer 130 is an indium-tin-oxide (ITO), indium-zinc-oxide (IZO), or indium-tin-zinc oxide (ITO) as the transparent conductive material. Indium-Tin-Zinc-Oxide).

The pixel electrode layer 130 is patterned by a photolithography process using a fourth mask 440 to form first to second sub pixel electrodes 131, 132, and 133. In addition, a V-shaped first opening pattern 135 is formed in each of the first to second sub pixel electrodes 131, 132, and 133.

As illustrated in FIG. 10, a main pixel electrode 131, a first sub pixel electrode 132, and a second sub pixel electrode 133 are formed in the pixel portion. The main pixel electrode 131 is formed to correspond to the storage capacitor 150, and the first sub pixel electrode 132 is formed to correspond to the first voltage distribution capacitor 160 and the second sub pixel. The electrode 133 is formed to correspond to the second subcapacitor 170.

That is, a first voltage charged in the storage capacitor 150 is applied to the main pixel electrode 131, and a second voltage charged in the first voltage distribution capacitor 160 is applied to the first sub pixel electrode 132. A voltage is applied, and a third voltage charged in the second sub capacitor 170 is applied to the second sub pixel electrode 133.

As the first and second voltage distribution capacitors 160 and 170 are formed to have the same size, the same voltage is charged, thereby applying the same voltage to the first and second sub pixel electrodes 132 and 133.

FIG. 11 is a conceptual diagram illustrating an inclination angle of liquid crystal molecules included in the liquid crystal display panel illustrated in FIG. 1. For convenience of explanation, the tilt angle of the liquid crystal molecules arranged with respect to the plane parallel to the array substrate is shown.

1 and 11, the liquid crystal molecules are arranged at an angle of inclination of 90 degrees from the reference plane in the electroless state.

As a predetermined electric field is applied for the display operation, the storage capacitor 150 and the first and second voltage distribution capacitors 160 and 170 are charged with different levels of voltage, whereby the inclination angle θ of the liquid crystal molecules is mutually different. Adjusted to be different.

In detail, the storage capacitor is charged with a first voltage V1, and the liquid crystal molecules arranged on the main pixel electrode 131 corresponding to the storage capacitor 150 have a relatively small first inclination angle θ1. Arranged to have. The first and second voltage division capacitors 160 and 170 are charged with a second voltage V2 which is lower than the first voltage V1 and correspond to the first and second voltage division capacitors 160 and 170. The liquid crystal molecules arranged on the second sub pixel electrodes 132 and 133 are arranged to have a relatively high inclination angle θ2 of the second angle (where 0 <θ1, θ2 <90 and θ1 <θ2).

As described above, one pixel unit has an effect of widening the viewing angle as the liquid crystal layer is driven differently by two storage capacitors having different charge capacities.

12 is a plan view illustrating a pixel unit of an array substrate according to another exemplary embodiment of the present invention.

Referring to FIG. 12, the array substrate includes a plurality of gate lines GL extending in a first direction and a plurality of data (or source) lines DL extending in a second direction crossing the first direction. And a plurality of pixel parts defined by the gate line GL and the data line DL.

The pixel unit includes a switching element 510, a main pixel electrode 531, a first sub pixel electrode 532, a second sub pixel electrode 533, a storage capacitor 550, a first voltage distribution capacitor 560, and a first voltage division capacitor 560. Two voltage distribution capacitors 570.

The switching element 510 includes a gate electrode 511 connected to the gate line GL, a source electrode 513 and a drain electrode 514 connected to the data line DL. A semiconductor layer is formed between the gate electrode 511 and the source and drain electrodes 513 and 514.

The main pixel electrode 531 is electrically connected to the drain electrode 514 through the first contact hole 553. The first sub pixel electrode 532 and the second sub pixel electrode 533 are symmetrically formed with respect to the main pixel electrode 131.

V-shaped first opening patterns 535 are formed in the first to second sub pixel electrodes 531, 532, 533. In this case, the first and second sub pixel electrodes 532 and 533 are separated.

The storage capacitor 550 includes a storage common wiring 551 and a storage electrode 552. The storage common line 551 is formed parallel to the gate line GL, and bisects the pixel portion into a first region P1 and a second region P2.

In detail, the storage common wiring 551 having the first size disposed in the pixel unit is a first electrode of the storage capacitor 550, and the storage electrode 552 extending from the drain electrode 514 is the storage. It is the second electrode of the capacitor 550. In addition, a first contact hole 553 is formed in the storage electrode 552 to electrically connect the drain electrode 114 and the main pixel electrode 531.

The first voltage division capacitor 560 includes a first floating electrode 561 and a first voltage division capacitor electrode 562.

The first floating electrode 561 is formed to have a second size smaller than the first size of the storage common line. A first voltage distribution capacitor electrode 562 extending from the storage electrode 552 is formed on the first floating electrode 561. The first floating electrode 561 is electrically connected to the first sub pixel electrode 532 through a second contact hole 563.

The second voltage division capacitor 570 includes a second floating electrode 571 and a second voltage division capacitor electrode 572.

The second floating electrode 571 is formed to have a third size smaller than the second size of the first floating electrode. That is, the first and second floating electrodes 561 and 571 may be formed to be symmetrical with respect to the storage common wiring 551, and may have different sizes.

A second voltage distribution capacitor electrode 572 extending from the storage electrode 552 is formed on the first floating electrode 561. The second floating electrode 571 is electrically connected to the second sub pixel electrode 533 through a third contact hole 573.

Although not shown, the display panel including the array substrate includes an opposite substrate on which a common electrode layer having a second opening pattern is formed, as shown in FIGS. 1 and 2.

FIG. 13 is a conceptual diagram illustrating an inclination angle of liquid crystal molecules included in the display panel illustrated in FIG. 12.

1 and 13, the liquid crystal molecules are arranged at an inclination angle of 90 degrees from the reference plane in the electroless state.

As a predetermined electric field is applied for the display operation, the storage capacitor 550, the first voltage divider capacitor 560, and the second voltage divider capacitor 570 are charged with different levels of voltage, and thus, the liquid crystal molecules may be charged. The inclination angle θ is adjusted to be different from each other.

In detail, the storage capacitor 550 is charged with a first voltage V1, and the liquid crystal molecules arranged in the main pixel electrode 531 corresponding to the storage capacitor 550 are inclined at a relatively small first angle. arranged to have [theta] 1).

The first voltage division capacitor 560 is charged with a second voltage V2 which is lower than the first voltage V1 and charged to the first sub pixel electrode 532 corresponding to the first voltage division capacitor 560. The arranged liquid crystal molecules are arranged to have a relatively high inclination angle θ2 of the second angle.

The second voltage division capacitor 570 is charged with a third voltage V3 which is lower than the second voltage V2, and is charged to the second sub pixel electrode 533 corresponding to the second voltage division capacitor 570. The arranged liquid crystal molecules are arranged to have a relatively high inclination angle θ3 of the third angle. (Where V1> V2> V3, 0 <θ1 <θ2 <θ3 <90)

As described above, one pixel unit has an effect of wider viewing angle as the liquid crystal layer is driven differently by three storage capacitors having different charge capacities.

As described above, according to the present invention, first, the floating electrode of the voltage distribution capacitor formed in the unit pixel region is formed in the pixel region in an island shape, thereby reducing the data wiring and the overlap region. As a result, the RC delay of the data wiring can be reduced, and the aperture ratio of the pixel region can be improved. In addition, the possibility of short generation with the data wiring can be reduced.

Second, by implementing two different voltage distribution capacitors, the viewing angle can be further improved.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. You will understand.

Claims (28)

An array substrate including a switching element formed in a pixel region, a main pixel electrode connected to a drain electrode of the switching element, and a first sub pixel electrode and a second sub pixel electrode spaced apart from the main pixel electrode; An opposing substrate facing the array substrate; And A liquid crystal layer disposed between the array substrate and the opposing substrate, The first liquid crystal molecules corresponding to the main pixel electrode, the second liquid crystal molecules corresponding to the first sub pixel electrode, and the third liquid crystal molecules corresponding to the second sub pixel electrode each have different inclination angles, The array substrate A storage capacitor connected to the main pixel electrode and to which a first voltage is applied; A first voltage division capacitor connected to the first sub pixel electrode and to which a second voltage different from the first voltage is applied; And A second voltage distribution capacitor connected to the second sub pixel electrode and to which a third voltage different from the first and second voltages is applied; The first voltage division capacitor includes a first floating electrode connected to the first sub pixel electrode, and the second voltage division capacitor includes a second floating electrode connected to the second sub pixel electrode. Display panel. delete The storage capacitor of claim 1, wherein the storage capacitor includes a storage common line for dividing the pixel area into a first area and a second area, and a storage electrode extending from the drain electrode of the switching element and facing the storage common line. , The first voltage division capacitor further includes a first voltage division capacitor electrode extending from the storage electrode and facing the first floating electrode. The second voltage division capacitor further includes a second voltage division capacitor electrode extending from the storage electrode and facing the second floating electrode, And the first floating electrode is disposed in the first area, and the second floating electrode is disposed in the second area. The display panel of claim 1, wherein the first and second floating electrodes are formed from the same metal layer as the plurality of gate lines. The display panel of claim 3, wherein the first and second voltage distribution capacitor electrodes are formed from the same metal layer as the plurality of data lines. The display device of claim 3, wherein the main pixel electrode is disposed in the first region and the second region. The main pixel electrode is larger than the first sub pixel electrode and the second sub pixel electrode. The method of claim 3, wherein the main pixel electrode is electrically connected to the storage electrode of the storage capacitor, The first sub pixel electrode is disposed in the first region, and is electrically connected to the first floating electrode of the first voltage distribution capacitor. And the second sub pixel electrode is disposed in the second region and is electrically connected to the second floating electrode of the second voltage distribution capacitor. The display panel of claim 1, wherein the first floating electrode is larger than the second floating electrode. The method of claim 1, wherein the first voltage is greater than the second voltage, And the second voltage is greater than the third voltage. The method of claim 9, wherein the capacitance of the storage capacitor is greater than that of the first voltage distribution capacitor. And a capacitance of the first voltage division capacitor is greater than a capacitance of the second voltage division capacitor. The display panel of claim 1, wherein the main pixel electrode, the first sub pixel electrode, and the second sub pixel electrode comprise an opening pattern. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete

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