KR101126344B1 - Fabricating method of fringe field switch type thin film transistor substrate - Google Patents

Abstract

The present invention relates to a method of manufacturing a fringe field switching thin film transistor substrate, comprising: forming a double conductive layer including a transparent conductive layer on the substrate and a metal layer stacked on the transparent conductive layer; Patterning the double conductive layer using a first mask to form a gate line formed of the double conductive layer, a gate electrode of a thin film transistor connected to the gate line, a common electrode plate separated from the gate line, and the gate electrode, and the Forming a common line integrated with the common electrode plate; A photolithography process using a second mask includes a first photoresist pattern covering side surfaces and top surfaces of the gate line and the gate electrode, and a second photoresist formed on the transparent conductive layer of the common line along the common line. Forming a pattern; Etching the metal layer covered by the first and second photoresist patterns to maintain the gate line and the gate electrode respectively covered by the first photoresist pattern as the double conductive layer; Removing the metal layer on the common electrode plate exposed around the photoresist pattern; And removing the first and second photoresist patterns.

Description

Fringe field switching type thin film transistor substrate manufacturing method {FABRICATING METHOD OF FRINGE FIELD SWITCH TYPE THIN FILM TRANSISTOR SUBSTRATE}

1 is a cross-sectional view showing a conventional FFS type thin film transistor substrate.

2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 1.

3 is a plan view showing a thin film transistor substrate of the FFS type according to an embodiment of the present invention.

4 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 3 taken along the line II-II ′.

5A and 5B are a plan view and a cross-sectional view for explaining a first and a second mask process in the method of manufacturing a thin film transistor substrate of the FFS type according to the embodiment of the present invention.

6A to 6D are cross-sectional views illustrating in detail the first and second mask processes of the present invention.

7A and 7B are a plan view and a sectional view for describing a third mask process in the method of manufacturing the FFS type thin film transistor substrate according to the embodiment of the present invention.                 

8A and 8B are a plan view and a cross-sectional view for describing a fourth mask process in the method of manufacturing the FFS type thin film transistor substrate according to the embodiment of the present invention.

9A to 9B are plan and cross-sectional views illustrating a fifth mask process in the method of manufacturing the FFS type thin film transistor substrate according to the embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

102: gate line 4, 104: data line

TFT: thin film transistor 6, 106: gate electrode

8, 108: source electrode 10, 110: drain electrode

12, 112: contact hole 14, 114: common electrode plate

16, 116: common line 18, 118: pixel electrode

20, 120: substrate 25, 125: semiconductor pattern

22, 122: gate insulating film 24, 124: active layer

26, 126: ohmic contact layer 28, 128: protective film

101: transparent conductive layer 103: gate metal layer

130: photoresist pattern

The present invention relates to a fringe field switch type liquid crystal display device, and more particularly, to a fringe field switch type thin film transistor substrate and a method of manufacturing the same.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. Such liquid crystal displays are roughly classified into a vertical electric field application type and a horizontal electric field application type according to the direction of the electric field for driving the liquid crystal.

In the vertical field applying liquid crystal display, a liquid crystal of TN (Twisted Nemastic) mode is driven by a vertical electric field formed between a pixel electrode and a common electrode disposed to face the upper and lower substrates. The vertical field application type liquid crystal display device has an advantage of having a large aperture ratio while having a narrow viewing angle of about 90 degrees.

In the horizontal field application type liquid crystal display, a liquid crystal in an in-plane switch (hereinafter referred to as IPS) mode is driven by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on a lower substrate. Such a horizontal field application type liquid crystal display device has a wide viewing angle of about 160 degrees, but has a disadvantage of low aperture ratio and low transmittance.

In order to improve the disadvantage of the horizontal field-applied liquid crystal display device, a fringe field switching (FFS) type liquid crystal display device operated by a fringe field has been proposed. A FFS type liquid crystal display device includes a common electrode plate and a pixel electrode having an insulating film interposed therebetween in each pixel region, and forms a fringe field by forming a gap between the common electrode plate and the pixel electrode narrower than a gap between upper and lower substrates. . The liquid crystal molecules filled between the upper and lower substrates by the fringe field are all operated to improve the aperture ratio and transmittance.

1 is a cross-sectional view illustrating a thin film transistor substrate included in a conventional FFS type liquid crystal display device.

1 and 2 include a gate line (not shown) and a data line 4 formed to intersect a gate insulating layer 22 therebetween on a lower substrate 20, and a thin film formed at each intersection thereof. The common electrode plate 14 and the pixel electrode slit 18 which are formed with the gate insulating film 22 and the protective film 28 interposed therebetween so as to form a fringe field in the pixel region provided with the transistor TFT and the intersection structure, The common line 16 connected with the electrode plate 14 is provided.

The common electrode plate 14 is formed in each pixel area and is supplied with a reference voltage (hereinafter, common voltage) for driving the liquid crystal through the common line 16 formed and connected to the common electrode plate 14. The common electrode plate 14 is a transparent conductive layer, and the common line 16 is formed of a gate metal layer together with the gate line 2.

The thin film transistor TFT keeps the pixel signal of the data line 4 charged and maintained in the pixel electrode slit 18 in response to the gate signal of the gate line (not shown). For this purpose, the TFT may include a gate electrode 6 connected to a gate line, a source electrode 8 connected to a data line 4, a drain electrode 10 connected to a pixel electrode slit 18, and a gate. An active layer 24, a source electrode 8, and a drain electrode 10 that overlap with the electrode 6 and the gate insulating layer 22 therebetween to form a channel between the source electrode 8 and the drain electrode 10. A semiconductor pattern 25 including an ohmic contact layer 26 for ohmic contact with the active layer 24 is provided.

The pixel electrode slit 18 is connected to the drain electrode 10 of the thin film transistor TFT through a contact hole penetrating through the passivation layer 28 to overlap the common electrode plate 14. ) Forms a fringe field with the common electrode plate 14 such that liquid crystal molecules arranged in a horizontal direction between the thin film transistor substrate and the color filter substrate are rotated by dielectric anisotropy. In addition, light transmittance through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

In the overlapping portion of the common electrode plate 14 and the pixel electrode slit 18, a storage capacitor for stably holding the video signal supplied to the pixel electrode slit 18 is formed.

A thin film transistor substrate of the FFS type having such a configuration is formed in a five mask process as follows.

Referring to FIG. 2A, a common electrode plate 14 is formed in each pixel area of the substrate 20 by a first mask process. The common electrode plate 14 is formed in each pixel area by forming a transparent conductive layer on the substrate 20 and then patterning the same by a photolithography process and an etching process using a first mask.

Referring to FIG. 2B, a gate metal pattern including a gate line, a gate electrode 6, and a common line 16 is formed on the substrate 20 on which the common electrode plate 14 is formed in the second mask process. The gate metal pattern is formed by forming a gate metal layer on the substrate 20 on which the common electrode plate 14 is formed, and then patterning the same by a photolithography process and an etching process using a second mask.

Referring to FIG. 2C, a gate insulating layer 22 is formed on a substrate 20 on which a gate metal pattern is formed, and an active layer 24 and an ohmic contact layer 26 are formed on the gate insulating layer 22 by a third mask process. A semiconductor pattern 25; A source / drain metal pattern including a data line 4, a source electrode 8, and a drain electrode 10 is formed.

In detail, the gate insulating layer 22, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower substrate 20 on which the gate metal pattern is formed. Next, a photoresist pattern having a step is formed on the source / drain metal layer by a photolithography process using a third mask, which is a diffraction exposure mask. The stepped photoresist pattern has a relatively low height in the channel portion of the thin film transistor. In the etching process using the photoresist pattern, a source / drain metal pattern and a semiconductor pattern are formed thereunder. In this case, the source electrode 8 and the drain electrode 10 included in the source / drain metal pattern are integrally formed. The source electrode 8 and the drain electrode 10 are then separated by ashing the photoresist pattern and removing the exposed source / drain metal pattern along with the ohmic contact layer 26 thereunder.

Referring to FIG. 2D, a passivation layer 28 including a contact hole is formed on the gate insulating layer 22 on which the source / drain metal pattern is formed by a fourth mask process. The passivation layer 28 is entirely formed on the gate insulating layer 22 on which the source / drain metal pattern is formed, and is patterned by a photolithography process and an etching process using a fourth mask to form a contact hole exposing the drain electrode 10.

Referring to FIG. 2E, the pixel electrode slit 18 is formed on the passivation layer 28 by a fifth mask process. The pixel electrode slit 18 is formed by forming a transparent conductive layer on the protective film 28 and then patterning the photolithography process and etching process using a fifth mask.

As such, the conventional FFS type thin film transistor substrate and its manufacturing method are formed through a five mask process. Here, each mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, an inspection process, and the like. Therefore, there is a problem that the conventional FFS type thin film transistor substrate and its manufacturing method are complicated.

The present invention provides a method for manufacturing a thin film transistor substrate of the FFS type that can simplify the process.

A method of manufacturing a thin film transistor substrate of the FFS type of the present invention comprises the steps of forming a double conductive layer including a transparent conductive layer on the substrate and a metal layer laminated on the transparent conductive layer; Patterning the double conductive layer using a first mask to form a gate line formed of the double conductive layer, a gate electrode of a thin film transistor connected to the gate line, a common electrode plate separated from the gate line and the gate electrode, and the Forming a common line integrated with the common electrode plate; A photolithography process using a second mask includes a first photoresist pattern covering side surfaces and top surfaces of the gate line and the gate electrode, and a second photoresist formed on the transparent conductive layer of the common line along the common line. Forming a pattern; Etching the metal layer covered by the first and second photoresist patterns to maintain the gate line and the gate electrode respectively covered by the first photoresist pattern as the double conductive layer; Removing the metal layer on the common electrode plate exposed around the photoresist pattern; And removing the first and second photoresist patterns.
The transparent conductive layer is formed of any one of ITO, TO, and IZO, and the metal layer is formed of any one metal of Mo, Ti, Cu, and Al (Nd).
The manufacturing method includes sequentially forming a gate insulating layer, an active layer including an amorphous silicon layer, an ohmic contact layer including an amorphous silicon layer doped with impurities (n + or p +), and a source / drain metal layer on the substrate; Forming a thin photoresist pattern in the channel portion of the thin film transistor by applying a photoresist on the source / drain metal layer and exposing and developing the photoresist in a photolithography process using a third mask selected as a diffraction exposure mask. step; Forming a source / drain metal pattern and a semiconductor pattern thereunder by collectively patterning the source / drain metal layer from the source / drain metal layer to the amorphous silicon layer by an etching process using a thin photoresist pattern in the channel portion; Removing the photoresist pattern remaining in the channel portion by ashing the thin photoresist pattern in the channel portion by an ashing process using an oxygen (O ₂ ) plasma; The source and drain metal patterns exposed by the etching process using the photoresist pattern remaining after the ashing process and the ohmic contact layer below are removed to separate the source electrode and the drain electrode of the thin film transistor, and in the channel part, Exposing the active layer; Removing the photoresist pattern remaining on the source / drain metal pattern; Forming a contact layer on the source / drain metal pattern and the gate insulating layer and forming a contact hole exposing the drain electrode of the thin film transistor in the passivation layer by a photolithography process using a fourth mask; And forming a transparent conductive layer on the passivation layer, and patterning the transparent conductive layer formed on the passivation layer by a photolithography process using a fifth mask to form pixel electrode slits on the passivation layer.
Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

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Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 9B.                     

3 is a plan view illustrating a FFS type thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 3 taken along the line II-II ′.

3 and 4 include a gate line 102 and a data line 104 formed to intersect a gate insulating layer 122 therebetween on a lower substrate 120, and a thin film transistor formed at each intersection thereof. The common electrode plate 114 and the pixel electrode slit 118 formed with the gate insulating film 122 and the passivation film 128 interposed therebetween so as to form a fringe field in the pixel region provided with the TFT and the cross structure. The common line 116 connected with the board 114 is provided.

The gate line 102 for supplying the gate signal and the data line 104 for supplying the data signal are formed in a cross structure to define a pixel area. Here, the gate line 102 has a double structure in which the transparent conductive layer 101 and the metal layer 103 are stacked together with the gate electrode 106. In this case, the metal layer 103 may be a metal layer having a single / double / triple structure.

The common electrode plate 114 is formed in each pixel area, and receives a reference voltage (hereinafter, common voltage) for driving the liquid crystal through the common line 116 connected to the common electrode plate 114. Here, the common electrode plate 114 is formed on the same layer as the transparent conductive layer 101 included in the gate line 101, and the common line 116 has the same double structure as the gate line 102. In this case, in the overlapping portion of the common line 116 and the common electrode plate 114, the transparent conductive layer 103 of the common line 116 becomes a part of the common electrode plate 114.

The common electrode plate 114 is formed on the same layer as the transparent conductive layer 101 included in the gate line 101, and the common line 116 is the same layer as the metal layer 103 constituting the gate line 102. Is formed.

The thin film transistor TFT keeps the pixel signal of the data line 104 charged in the pixel electrode slit 18 in response to the gate signal of the gate line 102. For this purpose, the TFT may include a gate electrode 106 connected to the gate line 102, a source electrode 108 connected to the data line 104, and a drain electrode 110 connected to the pixel electrode slit 118. In addition, the active layer 124, the source electrode 108, and the drain electrode 110 overlapping each other with the gate electrode 106 and the gate insulating layer 122 interposed therebetween to form a channel between the source electrode 108 and the drain electrode 110. ) And a semiconductor pattern 125 including an ohmic contact layer 126 for ohmic contact between the active layer 124 and the active layer 124.

The semiconductor pattern 125 including the active layer 124 and the ohmic contact layer 126 is formed to overlap the data line 104.

The pixel electrode slit 118 is connected to the drain electrode 110 of the thin film transistor TFT through a contact hole 112 passing through the passivation layer 128 so as to overlap the common electrode plate 114. The pixel electrode slit 114 is formed of a transparent conductive layer, and includes a plurality of first slits symmetrically formed with respect to the common line 116, and a second slit commonly connecting the plurality of first slits. The pixel electrode slit 118 forms a fringe field with the common electrode plate 114 such that liquid crystal molecules arranged in a horizontal direction between the thin film transistor substrate and the color filter substrate rotate by dielectric anisotropy. In addition, light transmittance through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

In the overlapping portion of the common electrode plate 114 and the pixel electrode slit 118, a storage capacitor for stably maintaining the video signal supplied to the pixel electrode slit 18 is formed.

A thin film transistor substrate of the FFS type having such a configuration is formed in a five mask process as follows.

5A and 5B, the gate line 102, the gate electrode 106 and the common line 116 having a dual structure, and the common electrode having a single structure are formed on the substrate 120 in the first and second mask processes. Plate 114 is formed. The first and second mask processes will be described in detail with reference to FIGS. 6A to 6D.

Referring to FIG. 6A, the transparent conductive layer 101 and the metal layer 103 are continuously deposited on the substrate 120 through a deposition method such as sputtering. Here, the transparent conductive material of any one of ITO, TO, and IZO is used for the transparent conductive layer 101, and the metal of any one of Mo, Ti, Cu, and Al (Nd) is used for the metal layer 103.

Referring to FIG. 6B, the transparent conductive layer 101 and the metal layer 103 are patterned by a photolithography process and an etching process using a first mask to form a gate line 102, a gate electrode 106, and a common line having a dual structure. 116, and a common electrode plate 114 covered with the metal layer 103 is formed.

Referring to FIG. 6C, the photoresist pattern 130 is formed on the gate line 102, the gate electrode 106, and the common line 116 by a photolithography process using a second mask, and the photoresist pattern 130. The common electrode plate 114 is exposed by etching the exposed metal layer 103 by using a method. At this time, the photoresist pattern 130 is formed to surround side and top surfaces of each of the gate line 102 and the gate electrode 106 so that the gate line 102 and the gate electrode 106 are not etched in the etching process. Protect it. The metal layer 103 on the common electrode plate 114 is patterned along the photoresist pattern 130 formed thereon to form a common line 116 having a dual structure. In this case, the transparent conductive layer 101 of the common line 116 is included as part of the overlapping portion with the common electrode plate 114. In other words, the transparent conductive layer 101 of the common line 116 is formed integrally with the common electrode plate 114 on the same layer. 6D, the photoresist pattern 130 is removed.

As such, since the transparent conductive layer 101 and the metal layer 103 to be used in the first and second mask processes are continuously deposited through one sputtering process, that is, one sputtering equipment, one sputtering process and cleaning in comparison with the conventional one The process can be shortened.

7A and 7B, a gate insulating layer 122 is formed on the substrate 120, and an active layer 124 and an ohmic contact layer 126 are formed on the gate insulating layer 122 by a third mask process. A source / drain metal pattern including the semiconductor pattern 125 and the data line 104, the source electrode 108, and the drain electrode 110 is formed. The semiconductor pattern 125 and the source / drain metal pattern are formed by one mask process using a diffraction exposure mask or a halftone mask.

In detail, a gate insulating layer 122, an amorphous silicon layer, an amorphous silicon layer doped with an impurity (n + or p +), and a source / drain metal layer are sequentially formed on the substrate 120. For example, the gate insulating layer 122, the amorphous silicon layer, and the amorphous silicon layer doped with impurities are formed by PECVD, and the source / drain metal layer is formed by sputtering. An inorganic insulating material such as SiOx, SiNx, etc. is used as the gate insulating layer 122, and Cr, Mo, MoW, Al / Cr, Cu, Al (Nd), Al / Mo, Al (Nd) are used as the source / drain metal layer 109. ) / Al, Al (Nd) / Cr, Mo / Al (Nd) / Mo, Cu / Mo, Ti / Al (Nd) / Ti and the like. Then, a photoresist is applied on the source / drain metal layer, and then the photoresist is exposed and developed by a photolithography process using a diffraction exposure mask to form a relatively thin photoresist pattern.

Subsequently, the source / drain metal pattern and the semiconductor pattern 125 below are formed by collectively patterning the source / drain metal layer to the amorphous silicon layer by an etching process using a photoresist pattern. In this case, the source electrode 108 and the drain electrode 110 of the source / drain metal pattern have an integrated structure.

Next, the photoresist pattern of the channel portion is removed by ashing the photoresist pattern by an ashing process using an oxygen (O ₂ ) plasma. In addition, the source / drain metal pattern exposed by the etching process using the ashed photoresist pattern and the ohmic contact layer 126 thereunder are removed to separate the source electrode 108 and the drain electrode 110 and the active layer 124. ) Is exposed.

Then, the photoresist pattern remaining on the source / drain metal pattern is removed by the strip process.

8A and 8B, a passivation layer 128 including a contact hole 112 is formed on the source / drain metal pattern and the gate insulating layer 122 by a fourth mask process.

Specifically, the passivation layer 128 is formed on the gate insulating layer 122 on which the source / drain metal pattern is formed by a method such as PECVD, spin coating, or spinless coating. As the passivation layer 128, an inorganic insulating material such as the gate insulating film 122, or an organic insulating material is used. Subsequently, the contact hole 112 exposing the drain electrode 110 is formed by patterning the passivation layer 128 in a photolithography process and an etching process using a fourth mask.
9A and 9B, the pixel electrode slit 118 is formed on the passivation layer 128 by a fifth mask process. The pixel electrode slit 118 is formed by forming a transparent conductive layer on the passivation layer 128 and then patterning the photolithography and etching processes using a fifth mask.

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As described above, in the FFS type thin film transistor substrate and the method of manufacturing the same, the transparent conductive layer and the metal layer to be patterned in the first and second mask processes are continuously deposited through one sputtering process, that is, one sputtering equipment. As a result, one sputtering process can be shortened with the next cleaning process in comparison with the conventional one. Accordingly, the number of manufacturing steps of the FFS type thin film transistor substrate according to the present invention can be reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

delete delete delete Forming a double conductive layer including a transparent conductive layer on the substrate and a metal layer stacked on the transparent conductive layer; Patterning the double conductive layer using a first mask to form a gate line formed of the double conductive layer, a gate electrode of a thin film transistor connected to the gate line, a common electrode plate separated from the gate line, and the gate electrode, and the Forming a common line integrated with the common electrode plate; A photolithography process using a second mask includes a first photoresist pattern covering side surfaces and top surfaces of the gate line and the gate electrode, and a second photoresist formed on the transparent conductive layer of the common line along the common line. Forming a pattern; Etching the metal layer covered by the first and second photoresist patterns to maintain the gate line and the gate electrode respectively covered by the first photoresist pattern as the double conductive layer; Removing the metal layer on the common electrode plate exposed around the photoresist pattern; And Removing the first and second photoresist patterns; The transparent conductive layer is formed of any one of ITO, TO, IZO, The metal layer is a method of manufacturing a fringe field switching type thin film transistor substrate, characterized in that formed of any one of Mo, Ti, Cu, Al (Nd) metal. delete delete The method of claim 4, wherein Sequentially forming a gate insulating layer, an active layer including an amorphous silicon layer, an ohmic contact layer including an amorphous silicon layer doped with impurities (n + or p +), and a source / drain metal layer on the substrate; Forming a thin photoresist pattern in the channel portion of the thin film transistor by applying a photoresist on the source / drain metal layer and exposing and developing the photoresist in a photolithography process using a third mask selected as a diffraction exposure mask. step; Forming a source / drain metal pattern and a semiconductor pattern thereunder by collectively patterning the source / drain metal layer from the source / drain metal layer to the amorphous silicon layer by an etching process using a thin photoresist pattern in the channel portion; Removing the photoresist pattern remaining in the channel portion by ashing the thin photoresist pattern in the channel portion by an ashing process using an oxygen (O ₂ ) plasma; The source and drain metal patterns exposed by the etching process using the photoresist pattern remaining after the ashing process and the ohmic contact layer below are removed to separate the source electrode and the drain electrode of the thin film transistor, and in the channel part, Exposing the active layer; Removing the photoresist pattern remaining on the source / drain metal pattern; Forming a contact layer on the source / drain metal pattern and the gate insulating layer and forming a contact hole exposing the drain electrode of the thin film transistor in the passivation layer by a photolithography process using a fourth mask; And Forming a transparent electrode layer on the passivation layer, and forming a pixel electrode slit on the passivation layer by patterning the transparent conduction layer formed on the passivation layer by a photolithography process using a fifth mask. Method for producing a thin film transistor substrate of fringe field switching type.

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