KR101227461B1 - Gate driver device for driving moter - Google Patents

Abstract

PURPOSE: A gate driver device for driving a motor is provided to stably and efficiently drive a high side driving transistor. CONSTITUTION: A level shifter(161) shifts the level of a pulse-width modulating signal inputted from a control unit(110). RS flip-flop outputs an electric signal according to a set signal or a reset signal which is inputted from the level shifter. A gate driver(163) outputs a high driving signal or a low driving signal according to a high signal or a low signal inputted from the RS flip-flop. A first transistor(Q1) and a second transistor(Q2) are serially connected to each other. The gate electrode of a high side driving transistor(M1) is connected to the connecting point of the first transistor and second transistor.

Description

Gate driver device for motor drive {GATE DRIVER DEVICE FOR DRIVING MOTER}

One embodiment of the present invention relates to a gate driver device for driving a motor.

Recently, three-phase brushless DC motors (BLDC motors) controlled by inverters are increasingly used in home appliances (air conditioners, washing machines, refrigerators, etc.) to increase energy efficiency. Brushless DC motors, also called commutatorless motors, are currents that flow through the stator windings by switching electronic circuits using power switching semiconductor elements such as transistors, MOSFETs, and IGBTs, instead of brushes and commutators, which are usually important parts of DC motors. It is a motor that drives by generating torque by switching.

Therefore, brushless DC motors have a current-to-torque and speed-to-voltage characteristic similar to that of DC motors in the structure of synchronous motors.As a result, the field of application is expanding from home appliances to industrial equipment due to high efficiency and high power density. to be. The three-phase brushless DC motor is easier to control torque than a single phase, has high efficiency and advantageous in terms of noise, and large capacity is driven in three phases. The motor drive used to drive such a brushless DC motor is a voltage inverter using six power switching elements such as a field effect transistor (FET) or an insulated gate bipolar transistor (IGBT). It is controlled by the pulse width modulation (PWM) driving method.

Japanese Patent Laid-Open No. 2004-261275 (2004.09.24.)
Japanese Laid-Open Patent Publication No. 2004-336921 (2004.11.25.)

One embodiment of the present invention provides a motor driver gate driver apparatus capable of stable and efficient operation with a simple structure.

An embodiment of the present invention includes a high side drive transistor and a low side drive transistor connected in series, and a high side of a motor driving device for supplying current to a motor from a connection point of the high side drive transistor and the low side drive transistor. A motor driving gate driver apparatus for driving a driving transistor, comprising: a level shifter for shifting and outputting a level of a pulse width modulation signal input from a control unit of a three-phase brushless DC motor; An RS flip-flop for outputting an electrical signal according to a set signal or a reset signal input from the level shifter; A gate driver configured to output a high driving signal or a low driving signal according to a high signal or a low signal input from the RS flip-flop; And a first transistor and a second transistor connected to the gate driver and connected in series with each other, wherein a gate electrode of the high side driving transistor is electrically connected to a connection point of the first transistor and the second transistor. And a bootstrap capacitor connected between the source electrode of the first transistor and the source electrode of the high side driving transistor.

An internal power source may be connected to the source electrode of the first transistor, and an under voltage lock out (UVLO) may be connected between the internal power source and the RS flip-flop.

An external power supply may be connected to the drain electrode of the high side driving transistor, and the level shifter may shift the output pulse width modulation signal to a voltage level of the external power supply.

The bootstrap capacitor may be charged up to a voltage level of the internal power source or a combined voltage level of the internal power source and the external power source.

An embodiment of the present invention provides a motor driving gate driver apparatus capable of operating a stable and efficient high side driving transistor by a simple configuration consisting of a level shifter, an RS flip-flop, a gate driver, first and second transistors, and UVLO. do.

In addition, an embodiment of the present invention provides a motor driving gate driver apparatus capable of stably driving a high side driving transistor due to a bootstrap capacitor.

1 is a block diagram illustrating a gate driver device for driving a motor according to an exemplary embodiment of the present invention.
2 is a partial detailed view of FIG. 1.
3 is a graph illustrating an input waveform and an output waveform by the motor driving gate driver apparatus according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

Here, parts having similar configurations and operations throughout the specification are denoted by the same reference numerals. In addition, when a part is electrically connected to another part, it includes not only a direct connection but also a case where the other part is connected to the other part in between.

FIG. 1 is a block diagram illustrating a gate driver apparatus 100 for driving a motor according to an exemplary embodiment of the present invention, and FIG. 2 is a partial detailed view of FIG. 1.

As shown in FIG. 1, the gate driver apparatus 100 for driving a motor according to an embodiment of the present invention includes a control unit 110, an input buffer 120, a logic and delay unit 130 of a three-phase brushless DC motor. ), U, V, and W phase drivers 141, 142, 143, high side drive transistors M1, low side drive transistors M2, and bootstrap capacitors connected to the U, V, and W phase drivers 141, 142, 143, respectively. C1) and resistors R2 and R3. Of course, the coil (load 165) of the motor is electrically connected to the connection point of each of the high side driving transistor M1 and the low side driving transistor M2.

Here, the U, V and W phase drivers 141, 142, 143, and the high side driving transistor M1, the low side driving transistor M2, the bootstrap capacitor C1, and the resistors R2 and R3 are all the same. Since it has a circuit configuration, only one driver 141 and a circuit configuration connected thereto will be described in detail with reference to FIG. 2. In addition, for convenience of description, the input buffer 120, the logic and delay unit 130, and the U, V, and W phase drivers 141, 142, and 143 are considered to be formed in one IC chip 150.

As shown in FIG. 2, the IC chip 150 includes a HIN terminal, a LIN terminal, a BS terminal, a HO terminal, a VS terminal, a VCC terminal, a LO terminal, and a GND terminal. In addition, the IC chip 150 includes an input buffer 120, a logic and delay unit 130 between the HIN terminal, the BS terminal, the HO terminal, and the VS terminal, and also has a level shifter 161 and an RS flip. The flop 162, the gate driver 163, the first transistor Q1, the second transistor Q2, the UVLO 164, the internal power supply VCC, the resistor R1, and the diode D1 are provided. Here, the RS flip-flop 162, the gate driver 163, the first transistor Q1, the second transistor Q2, and the UVLO 164 are high voltage regions.

In addition, an input buffer 120 is connected to the HIN terminal, a logic and delay unit 130 is connected to the input buffer 120, and a level shifter 161 is connected to the logic and delay unit 130. . In addition, the level shifter 161 is connected to the diode D1, the UVLO 164, the source electrode of the first transistor Q1, the BS terminal, and the RS flip-flop 162. A source electrode of the UVLO 164, the gate driver 163, and the second transistor Q2 is connected to the RS flip-flop 162. The gate electrode of the first transistor Q1 and the gate electrode of the second transistor Q2 are connected to the gate driver 163. The drain electrode of the first transistor Q1 and the drain electrode of the second transistor Q2 are both connected to the HO terminal, and the VS terminal is electrically connected to the source electrode of the second transistor Q2. In addition, a bootstrap capacitor C1 is connected between the BS terminal and the VS terminal, and a gate electrode of the high side driving transistor M1 is connected to the HO terminal through a resistor R1. A resistor R1 is also connected between the gate electrode and the source electrode of the high side driving transistor M1, and an external power source (for example, 450 V) is connected to the drain electrode of the high side driving transistor M1. In addition, a body diode is connected from the source electrode to the drain electrode of the high side driving transistor M1.

In addition, an input buffer 120, a logic and a delay unit 130 are provided between the LIN terminal, the VCC terminal, the LO terminal, and the GND terminal, and also includes a reference power supply (Vref), a gate driver 163 ', and a first transistor. Q1 'and a second transistor Q2' are provided. Here, an input buffer 120 is connected to the LIN terminal, a logic and delay unit 130 is connected to the input buffer 120, and a gate driver 163 ′ is connected to the logic and delay unit 130. do. As described above, the gate electrodes of the first transistor Q1 'and the second transistor Q2' are connected to the gate driver 163 '. The source electrode of the first transistor Q1 'is connected to the VCC terminal, and the LO terminal is connected to the drain electrode of the first transistor Q1' and the second transistor Q2 '. In addition, the source electrode of the second transistor Q2 'is connected to the GND terminal. A reference power supply Vref and a UVLO 164 'are connected to the VCC terminal and the GND terminal of the first transistor Q1'. Here, VCC is an internal power supply, for example, 15V is supplied. In addition, a gate electrode of the low side driving transistor M2 is connected to the LO terminal through a resistor R2 ', and a resistor R3' is also disposed between the gate electrode and the source electrode of the low side driving transistor M2. Connected. In addition, the drain electrode of the low side driving transistor M2 is electrically connected to the source electrode of the high side driving transistor M1, and the source electrode is electrically connected to the GND terminal. That is, the source electrode of the low side driving transistor M2 is grounded.

Of course, the load 165 of the motor, that is, the coil, is electrically connected to the source electrode of the high side driving transistor M1 and the drain electrode of the low side driving transistor M2. In addition, the first transistors Q1 and Q1 'may be P-channel MOSFETs, and the second transistors Q2 and Q2' may be N-channel MOSFETs. In addition, both the high side driving transistor M1 and the low side driving transistor M2 may be N channel driving transistors having body diodes.

3 is a graph illustrating input waveforms and output waveforms by the gate driver apparatus 100 for driving a motor according to an exemplary embodiment of the present invention. Here, X axis is time and Y axis is voltage. See also FIG. 2 together.

First, a PWM signal is input to the HIN terminal and the LIN terminal through the control unit 110 of the three-phase brushless DC motor. For example, a 5 V square wave voltage is applied to the HIN terminal, and a 5 V square wave voltage is applied to the LIN terminal. Here, the square wave voltage input to the HIN terminal and the square wave voltage input to the LIN terminal have a phase difference of approximately 180 degrees.

The 5V square wave signal applied to the HIN terminal is input to the level shifter 161 through the input buffer 120, the logic and the delay unit 130. The level shifter 161 shifts and outputs the input square wave signal to a level similar to that of an external power source. That is, the level shifter 161 up-levels the square wave signal and outputs the square wave signal to the RS flip-flop 162. For example, the level shifter 161 inputs a high signal to the R terminal of the RS flip-flop 162, a low signal to the S terminal, or a low signal to the R terminal and a high signal to the S terminal. Accordingly, the RS flip-flop 162 outputs a high signal or a low signal to the gate driver 163 through the Q terminal. The driver 163 also outputs a high signal or a low signal to the gate electrode of the first transistor Q1 and the gate electrode of the second transistor Q2.

For example, when the gate driver 163 outputs a high signal, the first transistor Q1 is turned off because it is a P-channel MOSFET, and the second transistor Q2 is turned on because it is an N-channel MOSFET. Therefore, the low signal is output through the HO terminal, so that the high side driving transistor M1 maintains the turn-off state. Substantially, since the low side driving transistor M2 is controlled to be turned on, the HO terminal is in a grounded state. In addition, since the low side driving transistor M2 is turned on, the internal power supply Vcc, the resistor R1, the diode D1, the BS terminal, the bootstrap capacitor C1, the low side driving transistor M2, A current flows through the GND terminal (ground), so that the bootstrap capacitor C1 is charged with the voltage of the internal power supply Vcc (for example, 15V). Here, as is well known, when the high side driving transistor M1 is turned off, the low side driving transistor M2 is turned on, and when the high side driving transistor M1 is turned on, the low side driving transistor M2 is turned on. It is well known that each gate driver 163, 163 'operates to be off.

In addition, when the gate driver 163 outputs a low signal, the first transistor Q1 is turned on because it is a P-channel MOSFET, and the second transistor Q2 is turned off because it is an N-channel MOSFET. Accordingly, since the voltage charged to the bootstrap capacitor C1 is applied to the gate electrode of the high side driving transistor M1 through the HO terminal, the high side driving transistor M1 is turned on, and thus the load 165 is applied to the gate electrode. The voltage of an external power supply (for example, 450V) is applied. Here, since the bootstrap capacitor C1 is connected between the BS terminal and the VS terminal, even though the voltage of the source electrode of the high side driving transistor M1 is 450V, the BS and HO terminals are connected through the BS terminal and the HO terminal. Since a higher voltage (for example, approximately 465 V when an internal voltage is 15 V) is applied, the high side driving transistor M1 is not turned off and remains turned on.

By this operation, as shown in Fig. 3, the output voltage through the LO terminal is approximately 465V. In addition, it can be seen that the voltage output to the load is approximately 450V.

Here, when the bootstrap capacitor C1 is charged through the internal power supply Vcc, a large current flows due to a certain cause to cause a ripple in the output voltage of the internal power supply Vcc. Therefore, at this time, other control circuits that are receiving power from the internal power supply Vcc may operate incorrectly. Therefore, as in the present invention, the resistor R1 and the diode D1 are connected between the internal power supply Vcc and the bootstrap capacitor C1, thereby preventing ripple on the output voltage of the internal power supply Vcc. .

Meanwhile, the operation of the low side driving transistor M2 and the peripheral structure of the driver 163 'are the same as in the related art. That is, the internal power supply Vcc is input through the VCC terminal, and a voltage of approximately 15 V is output through the LO terminal to turn on the low side driving transistor M2, or the ground voltage is output to output the low side driving transistor M2. Is turned off.

In addition, UVLOs 164 and 164 'are connected to the gate driver 163 for driving the high side driving transistor M1 and the gate driver 163' for driving the low side driving transistor M2, respectively. When Vcc is equal to or less than a predetermined voltage, the operation of the gate drivers 163 and 163 'is immediately stopped. Thus, driving safety of the motor is further improved.

What has been described above is only one embodiment for implementing the motor driving gate driver apparatus according to the present invention, and the present invention is not limited to the above-described embodiment, and as claimed in the following claims, the present invention Without departing from the gist of the present invention, those skilled in the art to which the present invention pertains to the technical spirit of the present invention to the extent that various modifications can be made.

100; Gate driver device for motor drive
110; A controller 120; Input buffer,
130; Logic and delay units 141, 142, 143; U, V, and W phase drivers
150; IC chip 161; Level shifter
162; RS flip-flop 163; driver
164; UVLO 165; Load
Q1, Q2; 1st transistor, 2nd transistor
M1, M2; High Side Drive Transistors, Low Side Drive Transistors
R1, R2, R3; Resistance D1; diode
C1; Bootstrap capacitor

Claims (3)

A motor for driving a high side drive transistor of a motor drive device having a high side drive transistor and a low side drive transistor connected in series and supplying current to the motor from a connection point of the high side drive transistor and the low side drive transistor. In a gate driver device for driving,
A level shifter for shifting and outputting a level of a pulse width modulation signal input from a control unit of a three-phase brushless DC motor;
An RS flip-flop for outputting an electrical signal according to a set signal or a reset signal input from the level shifter;
A gate driver configured to output a high driving signal or a low driving signal according to a high signal or a low signal input from the RS flip-flop; And
A gate electrode connected to the gate driver and including a first transistor and a second transistor connected in series with each other;
A gate electrode of the high side driving transistor is electrically connected to a connection point of the first transistor and the second transistor,
A bootstrap capacitor connected between the source electrode of the first transistor and the source electrode of the high side driving transistor;
An internal power source is connected to the source electrode of the first transistor,
Motor drive gate driver device characterized in that the Under Voltage Lock Out (UVLO) is connected between the internal power supply and the RS flip-flop. delete The method of claim 1,
An external power source is connected to the drain electrode of the high side driving transistor,
And the level shifter outputs the input pulse width modulation signal by shifting it to a voltage level of the external power supply.

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