KR101205413B1 - A power-saving circuit of liquid crystal display device - Google Patents

Abstract

The present invention relates to a technology for reducing power consumption by supplying a common voltage supplied to a pixel of a liquid crystal panel by swinging in a direction opposite to a data voltage when driving the liquid crystal panel in an inversion method.
To this end, the present invention provides a liquid crystal display device of an inversion drive method, comprising: a plurality of common voltage lines arranged to correspond to gate lines of the liquid crystal panel and connected to common voltage terminals of respective pixels; When the common voltage is supplied to each of the plurality of common voltage lines, the common voltage supply unit is configured to supply a voltage at a level opposite to the data voltage output in an inversion manner from the source driver.

Description

 Power-saving circuit of liquid crystal display device {A POWER-SAVING CIRCUIT OF LIQUID CRYSTAL DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for reducing power consumption of a liquid crystal display device, and more particularly, to a power saving circuit of a liquid crystal display device capable of reducing power consumption by reducing a data voltage swing width of a source driver.

Recently, flat panel display devices such as liquid crystal displays (LCDs), PDDPs, organic light emitting diodes (OLEDs), and the like have been widely used, and the spread of liquid crystal displays is more prominent.

In general, a liquid crystal display device includes a liquid crystal display panel (hereinafter, referred to as a 'liquid crystal panel') having a plurality of gate lines and data lines arranged in a direction perpendicular to each other and having a matrix-shaped pixel region, and a driving signal and And a backlight for providing a light source to the liquid crystal panel.

1 is a block diagram of a liquid crystal display device including a liquid crystal panel and a driving circuit unit according to the prior art, and as shown therein, the image data is processed to drive the liquid crystal panel 14 displaying the received image data. A timing controller 11 for generating a timing control signal; A gate driver 13 supplying a scan signal to the gate line GL of the liquid crystal panel 14 under the control of the timing controller 11; A source driver 12 for supplying a data voltage to the data line DL of the liquid crystal panel 14 under the control of the timing controller 11; A common voltage supply unit 15 is provided to supply a common voltage to each pixel arranged on the liquid crystal panel 14.

The liquid crystal panel 14 includes a plurality of pixels P arranged in a matrix at an intersection of the data lines DL1 to DLm and the gate lines GL1 to GLn. Each transistor T formed in the pixel P transfers a data voltage input from the data line DL to the liquid crystal cell C _lc in response to a scan signal supplied from the corresponding gate line GL. Further, the liquid crystal cell (C _lc) each of which is formed a storage capacitor (Cst), which serves to keep constant the voltage of the liquid crystal cell (C _lc). Thus, an image is displayed on the liquid crystal panel 14.

The timing controller 11 generates a gate control signal for controlling the gate drivers 13 and a data control signal for controlling the source driver 12 using a vertical / horizontal synchronization signal and a clock signal supplied from the system. In addition, the timing controller 11 rearranges and supplies the digital video data RGB input from the system to the source driver 12.

The source driver 12 converts the digital video data RGB into a data voltage corresponding to the gray scale value in response to a data control signal supplied from the timing controller 11 to convert the data line DL1 of the liquid crystal panel 14. ~ DLm).

The gate driver 13 sequentially supplies scan pulses (gate pulses) to the gate lines GL1 to GLn in response to the gate control signal supplied from the timing controller 11 to supply the data. Selectively drive horizontal lines.

The common voltage supply unit 15 supplies a common voltage VCOM to each pixel arranged on the liquid crystal panel 14. In general, the common voltage supply unit 15 is included in a DC / DC converter (not shown in the drawing). The DC / DC converter, in addition to the common voltage VCOM, requires a DC voltage V _DD , V _GH , V _GL ).

However, in the liquid crystal layer of the liquid crystal display device, when a constant electric field is continuously applied, the liquid crystal deteriorates, resulting in afterimages generated by the DC voltage component. Accordingly, in order to prevent such deterioration of the liquid crystal and to remove the DC voltage component, the data voltage (voltage of the image information) is applied to the data voltage (voltage of the image information) repeatedly based on the common voltage. This driving method is called an inversion method. .

The inversion driving method includes a frame inversion method in which the polarity of the data voltage is inverted by one frame unit of the image, a line inversion method in which the polarity of the data voltage is inverted by the gate line unit, and a polarity of the data voltage. There is a dot inversion method that is inverted and supplied for each adjacent pixel and inverted in a frame unit.

The common voltage VCOM is a DC voltage having the same level in every horizontal period and is supplied to each pixel P through the common voltage lines VL1 to VLn. As such, since the level of the common voltage VCOM (eg, VDD / 2) is fixed, the voltage difference between the common voltage VCOM and the data voltage can be adjusted only by adjusting the data voltage.

For example, in order to set the voltage difference between the data voltage Vdata and the common voltage VCOM to VDD / 2 as shown in FIG. 2, when the source driver 12 outputs the data voltage Vdata, the common voltage is once. The voltage is increased by VDD / 2 based on (VCOM) and outputted at the level of the power supply terminal voltage (VDD). Then, the voltage is decreased by VDD / 2 and outputted alternately by outputting at the level of the ground terminal voltage (GND). .

The alternate output period is determined according to the inversion scheme. For example, in the frame inversion method, the common voltage VCOM is increased by VDD / 2 or decreased by VDD / 2 in a frame period as shown in FIG. 2. As another example, in the line inversion method, the common voltage VCOM is increased by VDD / 2 or output by decreasing VDD / 2 in a horizontal period. As a result, regardless of the inversion scheme, the overall swing width of the data voltage is from the ground terminal voltage GND to the power terminal voltage VDD.

As described above, in the inversion method of the conventional liquid crystal display device, when outputting the data voltage to the liquid crystal panel, the data voltage is increased by one time based on the fixed common voltage and then output by the data voltage based on the common voltage. Since the operation of lowering and outputting alternately, the overall swing width of the data voltage has a large width ranging from the ground terminal voltage to the power terminal voltage, which causes a lot of power consumption.

Therefore, the problem to be solved by the present invention is to reduce the power voltage swing width of the source driver in the liquid crystal display device.

Problems to be solved by the present invention are not limited to the aforementioned problems. Other objects and advantages of the invention will be more clearly understood by the following description.

The present invention for achieving the above object,

A timing controller which processes image data and generates various timing control signals to drive the liquid crystal panel;

A gate driver supplying a scan signal to a gate line of the liquid crystal panel;

A source driver supplying a data voltage to a data line of the liquid crystal panel;

A plurality of common voltage lines arranged to correspond to gate lines of the liquid crystal panel and connected to common voltage terminals of each pixel;

When the common voltage is supplied to each of the plurality of common voltage lines, the common voltage supply unit is configured to supply a voltage at a level opposite to the data voltage output from the source driver in an inversion manner.

Preferably, the common voltage supply unit

A polarity signal output unit configured to alternately output first and second polar signals having phases opposite to each other using a frame start pulse in a frame period;

A shift register for sequentially shifting the frame start pulse using a gate line start pulse;

A common voltage output unit configured to alternately output a ground terminal voltage and a common voltage having a VCC level using first and second polar signals output from the polarity signal output unit and a clock signal as an output signal of the shift register;

A level shifter for converting the common voltage of the VCC level output from the common voltage output unit into a common voltage of the VDD / 2 level, and outputting the common voltage of the VDD / 2 level;

An output driver unit converting the common voltage of the VDD / 2 level output from the level shifter into a stable form and alternately outputting the common voltage and the ground terminal voltage to the common voltage line on the liquid crystal panel every frame; It is composed.

In the present invention, when the liquid crystal panel is driven in an inversion method, the swing of the data voltage is performed without reducing the driving voltage level of the liquid crystal panel by supplying the common voltage in the opposite direction to the data voltage rather than supplying the common voltage in a fixed form. The width is reduced by half compared to the normal case, the power consumption is reduced.

1 is a block diagram of a liquid crystal display device according to the prior art.
Figure 2 is a waveform diagram showing a common voltage supply principle according to the prior art.
3 is a block diagram of a power saving circuit of a liquid crystal display device according to the present invention;
Figure 4 is a waveform diagram showing a common voltage supply principle according to the present invention.
5 is a detailed block diagram of a common voltage supply unit according to the present invention;
(A)-(q) is a waveform diagram of each part of FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is an overall block diagram of a power saving circuit of a liquid crystal display according to the present invention. As shown therein, a timing controller 31, a source driver 32, a gate driver 33, a liquid crystal panel 34, and a common voltage It comprises a supply part 35. The operation of the remaining components except for the common voltage supply unit 35 among the components is the same as in the prior art.

The liquid crystal panel 34 includes a plurality of pixels P arranged in a matrix at the intersection of the data lines DL1 to DLm and the gate lines GL1 to GLn. Each transistor T formed in the pixel P transfers a data voltage input from the data line DL to the liquid crystal cell C _lc in response to a scan signal supplied from the corresponding gate line GL. Further, the liquid crystal cell (C _lc) each of which is formed a storage capacitor (Cst), which serves to keep constant the voltage of the liquid crystal cell (C _lc). Thus, an image is displayed on the liquid crystal panel 34.

The timing controller 31 generates a gate control signal for controlling the gate drivers 33 and a data control signal for controlling the source driver 32 using a vertical / horizontal synchronization signal and a clock signal supplied from the system. In addition, the timing controller 31 rearranges the digital video data RGB input from the system and supplies the digital video data RGB to the source driver 32.

 The source driver 32 converts the digital video data RGB into a data voltage corresponding to a gray scale value in response to a data control signal supplied from the timing controller 31 to convert the data line DL1 of the liquid crystal panel 34. ~ DLm).

The gate driver 33 sequentially supplies scan pulses (gate pulses) to the gate lines GL1 to GLn in response to the gate control signal supplied from the timing controller 31 to supply the data to the liquid crystal panel 34. Selectively drive horizontal lines.

Meanwhile, when the common voltage supply unit 35 supplies the common voltage VCOM to the plurality of common voltage lines VL1 -VLn arranged along the gate lines (or horizontal lines) on the liquid crystal panel 34, the common voltage supply unit 35 is fixed. Instead of supplying the signal at the level (eg, VDD / 2 level), the source driver 32 alternately supplies the voltage at a level opposite to the data voltage output in the inversion manner.

For example, when the inversion type data voltage Vdata is output at the VDD / 2 level from the source driver 32 as shown in FIG. 4, the common voltage supply unit 35 is connected to a ground terminal at a corresponding common voltage line. The common voltage VCOM of the voltage GND level is output. On the contrary, when the inversion type data voltage Vdata is output at the ground terminal voltage GND level from the source driver 32, the common voltage supply unit 35 has a VDD / 2 level on the common voltage line. Output the common voltage (VCOM).

FIG. 5 is a detailed block diagram of the common voltage supply unit 35. As shown therein, the polarity signal output unit 51, the shift register 52, the common voltage output unit 53, the level shifter 54 and And, having an output driver 55, the operation thereof will be described in detail with reference to FIG.

The polarity signal output unit 51 includes an inverter I and a D flip-flop DFF to output polarity signals POL1 and POL2 as shown in FIGS. 6D and 6E.

To this end, the frame start pulse VSP is directly input to the clock terminal ck of the D flip-flop DFF, and the inverted clock terminal of the D flip-flop DFF is passed through the inverter I. ckb). The inverted output terminal QB of the D flip-flop DFF is connected to the data terminal D of the D flip-flop DFF.

Accordingly, the first polarity signal POL1 as shown in FIG. 6D is output from the output terminal Q of the D-type flip-flop DFF, and the inverted output terminal QB is connected to FIG. The same second polarity signal POL2 is output.

In other words, the first frame start pulse VSP as shown in FIG. 6C is input to the clock terminal ck of the D-type flip-flop DFF in the first frame, so that the first polarity signal ( POL1) is continuously output as 'low' in the initial state as shown in FIG. 6 (d), and the second polarity signal POL2 is continuously output as 'high' in the initial state as shown in 6e. In the second frame, the second frame start pulse VSP is input to the clock terminal ck of the D flip-flop DFF, and the first polarity signal POL1 is output during the second frame as shown in FIG. 'High' is output, and the second polarity signal POL2 is output 'low' as shown in (e) of FIG. 6. Thereafter, the first polarity signal POL1 and the second polarity signal POL2 are output in the same pattern according to the odd frame or even frame.

The shift register 52 includes a plurality of D-type flip-flops DFF ₁₁ -DFF _1n connected in series, and the frame start pulse VSP and the gate line start pulse shown in FIG. 6A. Pulse (VSC) is used to generate clock signals CK ₁ to CK _n such as (g), (i), (k), (m), (o) and (q) of FIG.

To this end, the frame start pulse VSP is supplied to the input terminal D of the shift register 52, and the gate line start pulse VSC is provided with a plurality of D-type flip flops constituting the shift register 52. Commonly supplied to the clock terminal CK of the DFF.

Accordingly, the plurality of D-type flip-flops DFF _{11 to} DFF _1n constituting the shift register 52 detect an input signal at the rising edge of the gate line start pulse VSC input to the clock terminal CK. As shown in (f), (h), (j), (l), (n), and (p) of FIG. 6, clock signals CK ₁ to CK _n having a pulse width of 1 gsc (Gate Shift Clock) )

For example, the first D flip-flop DFF ₁₁ of the shift register 52 detects the 'high' of the frame start pulse VSP at the rising edge of the gate line start pulse VSC. Outputs the clock signal CK ₁ as shown in (f).

As another example, the second D flip-flop (DFF ₁₂ ) of the shift register 52 is a 'D' of the signal input from the first D flip-flop (DFF ₁₁ ) at the rising edge of the gate line start pulse (VSC). High 'is detected and the clock signal CK _{2 as} shown in FIG.

As another example, the n-th D-type flip-flop (DFF _1n ) of the shift register 52 may be moved from the n-th D-type flip-flop (DFF _1n-1 ) at the rising edge of the gate line start pulse (VSC). It detects the 'high' of the input signal and outputs the clock signal CK _{n as} shown in FIG.

The common voltage output unit 53 includes the number of D-type flip-flops DFF ₂₁ -DFF _2n corresponding to the D-type flip-flops DFF ₁₁ -DFF _1n of the shift register 52. 6 (g), (i), (k), (m), using the bipolar signals POL1 and POL2 and the clock signals CK ₁ to CK _n output from the shift register 52. As shown in (o) and (q), the ground terminal voltage GND and the common voltages X ₁ to X _n of the VCC level are output.

To this end, the output terminals of the plurality of D-type flip-flops DFF ₁₁ -DFF _1n constituting the shift register 52 are the clock terminals CK ₁ to CK of the plurality of D-type flip-flops DFF ₂₁ -DFF _2n . _n ), respectively, and the first polar signal terminal POL1 is connected to an input terminal D of odd-type D flip-flops DFF ₂₁ , DFF ₂₃ ,..., and DFF _2n-1 , respectively, The polarity signal terminal POL2 is connected to the input terminal D of even D type flip-flops DFF ₂₂ , DFF ₂₂ ,..., DFF _2n .

Accordingly, in the first frame, the common voltage of the ground terminal voltage (GND) level of the D-type flip-flops DFF ₂₁ , DFF ₂₃ ,..., DFF _2n-1 constituting the common voltage output unit 53 is obtained. Outputs X ₁ , X ₃ , ..., X _n-1 , and the excellent D-type flip-flops (DFF ₂₂ , DFF ₂₄ , ..., DFF _2n ) have a common voltage (X ₂ , X ₄ , ..., X _n ) In the second frame, in contrast to the above, the common voltages (X ₁ , X ₃ , ..., X _n-1 ) of the VCC level are applied to the odd-type D flip-flops DFF ₂₁ , DFF ₂₃ ,..., And DFF _2n-1 . In the excellent D-type flip-flops DFF ₂₂ , DFF ₂₄ ,..., And DFF _2n , the common voltages X ₂ , X ₄ ,..., _N of the ground terminal voltage GND level are output. In the subsequent frame, the common voltage output unit 53 outputs the common voltage in the same manner as described above.

The level shifter 54 includes the number of level shifters LS ₃₁ -LS _3n corresponding to the D-type flip-flops DFF ₂₁ -DFF _2n of the common voltage output unit 53 to provide the common voltage output unit ( 53) outputs the common voltage (X ₁ ~ X _n ) of the ground terminal voltage (GND) level output from the common terminal of the ground terminal voltage (GND) level and outputs the common voltage (X ₁ ~ X _n ) of the VCC level. The output voltage is converted to the common voltage of VDD / 2 level.

The output driver unit 55 includes a plurality of output drivers 55A to 55N, and the VDD / 2 level common voltages X ₁ to X _n output from the level shifter 54 are stabilized. 2 levels are converted to common voltages V1 to Vn and output to the common voltage lines VL1 to VLn on the liquid crystal panel 34.

For example, in the first frame, the ground terminal voltage (VL1, VL3, ..., VLn-1) from the output drivers 55A, 55C, ..., 55N-1 to the odd common voltage lines VL1, VL3, ..., VLn-1 of the liquid crystal panel 34. The common voltages V1, V3, ..., Vn-1 of the GND) level are supplied respectively. At this time, the common voltage lines VL2, VL4, ..., VLn of the liquid crystal panel 34 from the output drivers 55B, 55D, ..., 55N are connected to the common voltages V2, V4, ..., Vn) supplied separately.

In the second frame, VDD / 2 levels are common to the odd common voltage lines VL1, VL3, ..., VLn-1 of the liquid crystal panel 34 from the output drivers 55A, 55C, ..., 55N-1. Voltages V1, V3, ..., Vn-1 are supplied respectively. At this time, the common voltages V2 and V4 of the ground terminal voltage GND level are output from the output drivers 55B, 55D, ..., 55N to the even common voltage lines VL2, VL4, ..., VLn of the liquid crystal panel 34. , ..., Vn) are supplied, respectively.

As an example, a common voltage is supplied from the common voltage supply unit 35 to an arbitrary common voltage line among a plurality of common voltage lines VL1 -VLn arranged along the gate lines of the liquid crystal panel 34. As shown in FIG. 4, it can be seen that the ground terminal voltage GND and VDD / 2 are alternately supplied in units of frames when referring to one gate line. Of course, at this time, the source driver 32 alternately supplies VDD / 2 and the ground terminal voltage GND through the corresponding data line to correspond to the common voltage supplied as described above.

In the above description, when the common voltage supply unit 35 supplies a common voltage to the plurality of common voltage lines VL1 -VLn arranged along the gate lines of the liquid crystal panel 34, the ground terminal voltage GND at a frame period, Although alternately supplying VDD / 2 has been described as an example, the present invention is not limited thereto and may be supplied at various periods (eg, horizontal line periods).

For reference, FIG. 6 (b) shows the reset signal FRS for determining the polarity of the common voltage VCOM at start. Immediately after the power is turned on, the first frame start pulse VSP is input. This signal is input once before.

Although the preferred embodiment of the present invention has been described in detail above, the scope of the present invention is not limited thereto, and may be implemented in various embodiments based on the basic concept of the present invention defined in the following claims. Such embodiments are also within the scope of the present invention.

31: timing controller
32: source driver
33: gate driver
34 liquid crystal channel
35: common voltage supply unit
51: polarity signal output unit
52: shift register
53: common voltage output unit
54: level shifter
55: output driver

Claims (6)

A timing controller for processing image data and generating various timing control signals for driving the liquid crystal panel, a gate driver for supplying a scan signal to a gate line of the liquid crystal panel, and a source driver for supplying a data voltage to a data line of the liquid crystal panel. In the power saving circuit of the liquid crystal display device provided with,
A plurality of common voltage lines arranged to correspond to gate lines of the liquid crystal panel and connected to common voltage terminals of each pixel;
When supplying a common voltage for each of the plurality of common voltage lines, comprising a common voltage supply for supplying a voltage of a level opposite to the data voltage output in the inversion method from the source driver,
The common voltage supply unit
A polarity signal output unit configured to alternately output first and second polar signals having phases opposite to each other using a frame start pulse in a frame period;
A shift register for sequentially shifting the frame start pulse using a gate line start pulse;
A common voltage output unit configured to alternately output a ground terminal voltage and a common voltage having a VCC level using first and second polarity signals output from the polarity signal output unit and a clock signal output from the shift register;
A level shifter for converting the common voltage of the VCC level output from the common voltage output unit into a common voltage of VDD / 2 level and outputting the common voltage; And,
An output driver unit converting the common voltage of the VDD / 2 level output from the level shifter into a stable form and alternately outputting the common voltage and the ground terminal voltage to the common voltage line on the liquid crystal panel every frame; A power saving circuit of a liquid crystal display device, characterized in that configured.
delete 2. The polarity signal output unit of claim 1, wherein the polarity signal output unit directly connects a frame start pulse terminal to the clock terminal ck of the D flip-flop DFF, and inverts the D flip-flop DFF through the inverter I. And an inverting output terminal QB of the D-type flip-flop DFF to a data terminal D of the D-type flip-flop DFF. Power saving circuit.
The shift register of claim 1, wherein the shift register includes a plurality of D-type flip-flops (DFF ₁₁ -DFF _1n ) connected in series, and a gate line start pulse is used as a clock signal of the D-type flip-flops (DFF ₁₁ -DFF _1n ). A power saving circuit of a liquid crystal display device, characterized by shifting the frame start pulse sequentially.
The common voltage output unit includes a plurality of D-type flip-flops (DFF ₂₁ -DFF _2n ), and outputs the output signal of the shift register to a clock signal of the D-type flip-flops (DFF ₂₁ -DFF _2n ). CK ₁ to CK _n ), the first polar signal is supplied as data of odd D flip-flops (DFF ₂₁ , DFF ₂₃ ,..., DFF _2n-1 ), and the second polar signal is excellent. A power saving circuit of a liquid crystal display device, characterized in that configured to be supplied with data of D-type flip-flops (DFF ₂₂ , DFF ₂₂ ,..., DFF _2n ).
2. The level shifter of claim 1, wherein the level shifter includes a plurality of level shifters LS ₃₁ -LS _3n to share the common voltages X ₁ to X _n of the VCC level output from the common voltage output unit. A power saving circuit of a liquid crystal display device, characterized in that the output is converted to a voltage.

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