KR101186682B1 - Light emitting chips arrayed and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a light emitting device. The light emitting device according to the present invention includes a substrate, an N-type semiconductor layer formed on the substrate, and a P-type semiconductor layer formed on a portion of the N-type semiconductor layer, and a short circuit formed on an exposed portion of the N-type semiconductor layer. It characterized in that it comprises a prevention unit. As described above, the present invention may provide a light emitting cell and a light emitting device that are reliable by preventing a short circuit by forming a short circuit prevention unit in the N-type semiconductor layer.

Light emitting element, short circuit prevention part, wiring, N type semiconductor layer, short circuit

Description

LIGHT EMITTING CHIPS ARRAYED AND METHOD FOR MANUFACTURING THE SAME}

1 is a cross-sectional view of a conventional light emitting device.

2 and 3 are cross-sectional views of the light emitting device according to the first embodiment of the present invention.

4A to 4D are views for explaining a manufacturing process of the light emitting device according to the first embodiment of the present invention.

5 is a cross-sectional view of a light emitting device according to a second embodiment of the present invention.

6 is a view for explaining a manufacturing process of the light emitting device according to the second embodiment of the present invention.

<Description of the symbols of the main parts of the drawings>

100: substrate 200: N-type semiconductor layer

220: N-type electrode 240: short circuit prevention portion

300: active layer 400: P-type semiconductor layer

420: P-type electrode 600: wiring

The present invention relates to a light emitting device in which a plurality of light emitting cells are arrayed, and more particularly, to a light emitting device in which a plurality of light emitting cells are provided with a short circuit prevention means on an exposed semiconductor of each unit cell of the plurality of light emitting devices. will be.

1 is a cross-sectional view of a conventional light emitting device.

Referring to FIG. 1, a conventional light emitting device includes a substrate 10, an N-type semiconductor layer 20 grown on the substrate 10, and an active layer sequentially grown on a portion of the N-type semiconductor layer 20. 40 and a plurality of light emitting cells each having a P-type semiconductor layer 60, and an N-type electrode 42 and a P-type electrode 62 formed on the N-type semiconductor layer 40 and the P-type semiconductor layer 60, respectively. It includes. At this time, the N-type electrode 42 and the P-type electrode 62 are electrically connected by the wiring 80.

In the conventional horizontal light emitting device as described above, the N-type semiconductor layer 40 is exposed in a mesa shape, and the N-type electrode 42 is formed on the exposed N-type semiconductor layer 40 to form a wiring ( 80).

However, in the manufacturing process of the light emitting device and the manufacturing process using a plurality of light emitting devices on the N-type electrode on the N-type semiconductor layer 40 exposed in the mesa form, the wiring 80 contacts the P-type semiconductor layer 60 to emit light. There is a problem that the light emitting device does not work due to a short circuit between the cells.

In order to solve the above problems, an object of the present invention is to provide a light emitting cell and a light emitting device which are reliable by preventing a short circuit by forming a short circuit prevention unit in the N-type semiconductor layer.

In order to achieve the above object, the present invention includes a first semiconductor layer and a second semiconductor layer formed on a part of the first semiconductor layer, and a short circuit prevention part formed on an exposed portion of the first semiconductor layer. It provides a light emitting device characterized in that.

In this case, the short circuit prevention unit may include a stepped shape or a short circuit prevention protrusion protruding from an intermediate portion of the exposed portion of the first semiconductor layer.

The present invention also includes a plurality of light emitting cells comprising a substrate, a first semiconductor layer formed on the substrate, and a second semiconductor layer formed on a portion of the first semiconductor layer, wherein the first semiconductor of the one light emitting cell is provided. A second semiconductor layer of another light emitting cell adjacent to the layer is electrically connected, and a short circuit prevention part is formed on an exposed upper surface of the first semiconductor layer.

In this case, the short circuit prevention unit may include a stepped shape having at least one end, or a short circuit prevention protrusion protruding from an exposed portion of the first semiconductor layer.

The display device may further include an electrode formed at a portion of the short-circuit prevention part of the one light emitting cell, wherein the electrode is formed in the short-circuit prevention part located farthest from the second semiconductor layer of the one light-emitting cell.

Moreover, the present invention comprises the steps of preparing a substrate; Forming a first semiconductor layer and a second semiconductor layer on the substrate; Exposing a portion of the substrate to form a plurality of light emitting cells; Exposing a portion of the first semiconductor layer; Etching a portion of the exposed first semiconductor layer to form a step shape; Electrically connecting a second semiconductor layer of the one light emitting cell and a first semiconductor layer located far from the second semiconductor layer of another light emitting cell adjacent to the one light emitting cell. To provide.

In addition, the present invention comprises the steps of preparing a substrate; Forming a first semiconductor layer and a second semiconductor layer on the substrate; Etching a portion of the first semiconductor layer and the second semiconductor layer to expose a substrate to form a plurality of light emitting cells; Exposing a portion of the first semiconductor layer; Etching a portion of the exposed first semiconductor layer to form a short circuit bump formed in the middle of the exposed portion of the first semiconductor layer; Electrically connecting a second semiconductor layer of the one light emitting cell and a first semiconductor layer located far from the second semiconductor layer of another light emitting cell adjacent to the one light emitting cell. To provide.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like reference numerals refer to like elements throughout. Meanwhile, in the following embodiments, the above-described first semiconductor layer is implemented as an N-type semiconductor layer and the second semiconductor layer is implemented as a P-type semiconductor layer, but is not limited thereto.

As a method of depositing and growing a semiconductor to form a semiconductor layer on a substrate, metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (Plasma-enhanced Chemical Vapor Deposition) , PCVD), Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), and the like, but various methods are used. The organometallic chemical vapor deposition method is a thin film formation method using an organometallic raw material and forming a metal oxide film on a substrate using a chemical reaction. The organic compound vapor of a high vapor pressure metal is sent to a heated substrate in a vacuum chamber. The metal oxide film is grown on a substrate. Under certain conditions, crystals of the compound semiconductor can be grown into an epitaxial layer.

2 to 3 are views for explaining a light emitting device according to the first embodiment of the present invention.

Referring to FIG. 2, the light emitting device according to the first exemplary embodiment of the present invention may include a substrate 100, an N-type semiconductor layer 200a formed on the substrate 100, and a short circuit prevention unit 240 formed thereon. A light emitting cell having an active layer 300 and a P-type semiconductor layer 400 sequentially stacked on the N-type semiconductor layer 200a, and an N-type electrode 220 formed in an exposed region on the N-type semiconductor layer 200a. ), A P-type electrode 420 formed on the P-type semiconductor layer 400, and a wiring 600 for electrically connecting adjacent N-type electrodes and P-type electrodes.

The N-type semiconductor layer 200a is a layer in which electrons are generated, and is formed of an N-type compound semiconductor layer and an N-type cladding layer. The N-type compound semiconductor layer uses, for example, gallium nitride (GaN) doped with N-type impurities.

When an external power source is applied to the conventional light emitting device, current flows through the N-type semiconductor layer, the active layer, and the P-type semiconductor layer. In this case, when the wiring connected to the N-type electrode is pressed during the assembly process of the light emitting device and other assembly processes thereafter, and is in contact with the P-type semiconductor layer or the active layer, the light emitting device does not operate. In order to solve this problem, as shown in FIG. 2, the first embodiment of the present invention, when the short circuit prevention unit 240 is formed in the N-type semiconductor layer 200, the P-type semiconductor layer 400 may be pressed even if the wiring 600 is pressed. Contact with the short circuit prevention part 240 which is a part of the N-type semiconductor layer 200a, thereby preventing the wiring 600 and the P-type semiconductor layer 400 from being short-circuited.

As described above, the N-type semiconductor layer 200 in which the short circuit prevention unit 240 is formed is formed in a mesa shape, and a side cross section is formed in a step shape. In this case, the wiring 600 is connected to the N-type electrode 220 formed at the lowermost end. That is, as shown in FIG. 3, a stepped short circuit prevention unit having two ends in the N-type semiconductor layer 200b, an N-type electrode 220 formed at the lowermost end, and a wiring connected to the N-type electrode 220. May have 600. Therefore, the short circuit can be prevented by the end formed on the side of the N-type electrode 220, that is, the short circuit prevention unit.

The short circuit prevention unit 240 is formed by etching the N-type semiconductor layer 200a in a step shape to include a first short circuit prevention region 240a and a second short circuit prevention region 240b having different heights. That is, the first short circuit prevention region 240a is formed higher than the second short circuit prevention region 240b. At this time, the region adjacent to the P-type semiconductor layer 400 is referred to as the first short circuit prevention region 240a, and the region formed relatively to the P-type semiconductor layer 400 is referred to as the second short circuit prevention region 240b. The wiring 600 connected to the lowermost end of the N-type semiconductor layer 200a on which the short circuit prevention unit 240 is formed, that is, the N-type electrode 220 of the second short circuit prevention region 240b, is also connected to a conventional light emitting device. As such, it may be in contact with a surface adjacent to the wiring 600 during the manufacturing process. However, even when the wiring 600 is in contact with the short circuit prevention unit 240, that is, the first short circuit prevention region 240a, the first short circuit prevention region 240a is formed by etching the N-type semiconductor layer 200a, so that N is eventually formed. Since the same type as the semiconductor layer 200a, a short circuit does not affect the operation of the light emitting device.

Meanwhile, the P-type semiconductor layer 180 is a layer in which holes are formed, and is formed of a P-type cladding layer and a P-type compound semiconductor layer. In this case, the P-type compound semiconductor layer uses a P-type semiconductor doped with P-type impurities, for example, aluminum gallium nitride (AlGaN).

The active layer 160 is a region where a predetermined bandgap and a quantum well are made to recombine electrons and holes, and includes indium gallium nitride (InGaN). In addition, the emission wavelength generated by the combination of electrons and holes is changed according to the type of material constituting the active layer 160. Therefore, it is preferable to use the semiconductor material whose composition was controlled according to the target wavelength as the active layer 160.

The N-type electrode 220 and the P-type electrode 420 are for electrically connecting the light emitting cells with the external wiring 600. The N-type electrode 220 formed on the N-type semiconductor layer 200a is an ohmic metal, and is formed by coating germanium (Ge), nickel (Ni), gold (Au), or an alloy thereof. In this case, the N-type electrode 220 is formed at the lower end of the stepped short circuit prevention unit formed in the N-type semiconductor layer 200.

Meanwhile, the P-type electrode 420 formed on the P-type semiconductor 400 serves to uniformly transfer power input through the wiring 600 to the P-type semiconductor layer 400. Indium tin oxide (ITO) or a transparent metal electrode such as is formed. In this case, chromium (Cr) and gold (Au) or an alloy thereof may be coated at a predetermined position on the transparent conductive thin film to form an electrode material for a bonding pad.

4A to 4D are views for explaining a manufacturing process of the light emitting device according to the first embodiment of the present invention.

Hereinafter, referring to FIGS. 4A to 4D, a method of manufacturing the above-described light emitting device will be described. First, an undoped gallium nitride (GaN) layer (not shown) is grown on a substrate 100 as a buffer layer. Thereafter, the N-type semiconductor layer 200a, the active layer 300, and the P-type semiconductor layer 400 are sequentially grown on the buffer layer (FIG. 4A). In this case, a transparent electrode layer (not shown) may be further formed on the P-type semiconductor layer 400. Each layer is formed through various deposition methods for depositing the materials described above.

Subsequently, a photolithography process using a first mask is performed to expose the substrate 100 so that each cell is electrically separated to perform first etching. In other words, a portion of the P-type semiconductor layer 400, the active layer 300, and the N-type semiconductor layer 200 is removed through an etching process using the first mask as an etching mask to expose the substrate 100 (FIG. 4B). ). In this case, the first mask is formed using a photosensitive film. The etching process may be performed by a wet or dry etching process, and in this embodiment, it is preferable to perform dry etching using plasma.

After performing the above process, a second etching is performed to etch the P-type semiconductor layer 400 and the active layer 300 using the second mask to expose the N-type semiconductor layer 200a of each cell (FIG. 4C). .

Thereafter, a part of the N-type semiconductor layer 220a is removed again using a third mask on the exposed N-type semiconductor layer 200a to prevent the first and second short circuit prevention regions 240a and 240b. The third etching is performed to form a light emitting cell (figure 4d).

After removing the mask, an N-type electrode 220 is formed on the second short-circuit prevention region 240b of the exposed N-type semiconductor layer 200a and the P-type electrode 420 on the P-type semiconductor layer 400. ).

Thereafter, the N-type electrode 220 on the second short-circuit prevention region 240b of the N-type semiconductor layer 200 is connected to the P-type electrode on the adjacent P-type semiconductor layer by a predetermined bridge process or step cover. The light emitting device as shown in FIG. 3 is manufactured by electrically connecting the same. In this case, when the P-type electrode 420 is formed as a transparent electrode on the P-type semiconductor layer 400, a portion of the transparent electrode is etched by a photo process to expose the P-type semiconductor layer 400, (not shown). A P-type bonding pad may be formed.

Next, another form of the short circuit prevention unit of the present invention will be described. In the second embodiment of the present invention described below, since the same as the first embodiment except for the short circuit prevention portion, it will be omitted.

As shown in FIG. 5, in the light emitting device according to the second embodiment of the present invention, the N-type semiconductor layer 200c having the substrate 100 and the short circuit preventing portion 240 formed on the substrate 100 is formed. And a light emitting cell having an active layer 300 and a P-type semiconductor layer 400 sequentially grown on a portion of the N-type semiconductor layer 200c, and the N-type semiconductor layer 200c and the P-type semiconductor layer 400. And an N-type electrode 220 and a P-type electrode 420 formed therein. In this case, a wire 600 is connected to the N-type electrode 220.

The short circuit prevention portion 240 formed on the N-type semiconductor layer 200c includes a short circuit prevention line 240c protruding from an intermediate portion of the exposed region of the N-type semiconductor layer 200c. That is, the short circuit prevention unit 240 is relatively far from the P-type semiconductor layer 400 and the first short circuit prevention region 240a adjacent to the P-type semiconductor layer 400 on the N-type semiconductor layer 200c. And a short circuit prevention jaw 240c protruding from a second short circuit prevention region 240b and an intermediate portion of the first short circuit prevention region 240a and the second short circuit prevention region 240b. In this case, an N-type electrode 220 is formed on the second short circuit prevention region 240b which is relatively unlikely to short-circuit with the P-type semiconductor layer 400 or the active layer 300, and the wiring 600 is N-type. It is connected to the electrode 220. In addition, the first short circuit prevention region 240a and the second short circuit prevention region 240b of the short circuit prevention unit 240 according to the second embodiment of the present invention have the same height, unlike the short circuit prevention unit of the first embodiment. The short circuit is prevented by the short circuit prevention step 240c.

However, the present invention is not limited thereto, and heights of the first short circuit prevention region 240a and the second short circuit prevention region 240b may be different. In addition, one short circuit prevention barrier 240c may be formed as illustrated in FIG. 5, but a plurality of short circuit prevention barriers 240c may be formed. At this time, the N-type electrode 220 is formed on the short circuit prevention region that is formed farthest from the P-type semiconductor layer 400 among the short circuit prevention regions divided by the plurality of protruding short circuit bumps to be connected to the wiring 600. .

Hereinafter, a manufacturing process of the light emitting device according to the second embodiment of the present invention will be briefly described with reference to the accompanying drawings.

5 and 6, the method of manufacturing the light emitting device according to the second embodiment of the present invention may be sequentially grown on the substrate 100 in the same manner as the manufacturing process of the light emitting device according to the first embodiment. A portion of the N-type semiconductor layer 200c, the active layer 300, and the P-type semiconductor layer 400 may be first etched to expose the substrate 100 using a first mask.

Subsequently, in order to expose the N-type semiconductor layer 200c, a second etching is performed to etch a portion of the active layer 300 and the P-type semiconductor layer 400 using a second mask. After performing the second etching, the first short circuit prevention region 240a and the second short circuit prevention region 240b and the first short circuit prevention region are formed on the exposed upper surface of the N-type semiconductor layer 200c by using a third mask. A third etching is performed to form a short circuit prevention jaw 240c protruding from an intermediate portion of the 240a and the second short circuit prevention region 240b. At this time, the first short-circuit prevention region 240a and the second short-circuit prevention region 240b are formed by etching deeper than the second etching of the first embodiment, and the short-circuit prevention jaw 240c having the same height as the second etching of the first embodiment is formed. ) To form a light emitting cell (FIG. 6).

After removing the mask, the N-type electrode 220 is formed on the exposed second short circuit prevention region of the N-type semiconductor layer 200c and the P-type electrode 420 is formed on the P-type semiconductor layer 400. do. Thereafter, when the wire 600 is connected to the N-type electrode 220 and the P-type electrode 420, the light emitting device as illustrated in FIG. 5 is completed.

It is to be understood that the invention is not limited to the disclosed embodiments, but is capable of many modifications and alterations, all of which are within the scope of the appended claims. It is self-evident.

As described above, the present invention can provide a reliable light emitting cell and a light emitting device by preventing a short circuit by forming a short circuit prevention unit in the N-type semiconductor layer.

Claims (8)

A substrate; A plurality of light emitting cells including a first semiconductor layer formed on the substrate and a second semiconductor layer formed on a portion of the first semiconductor layer; A second semiconductor layer of another light emitting cell adjacent to the first semiconductor layer of the one light emitting cell is electrically connected by wiring; The exposed upper surface of the first semiconductor layer includes a first region and a second region having different heights by a step, The first region is located outward of the second region and has a height lower than that of the second region, One end of the wiring is connected to the first region. The method of claim 1, wherein the exposed upper surface comprises a stepped shape including a plurality of stages, characterized in that the first region and the second region is divided based on the side of one of the plurality of stages. Light emitting element. The light emitting device of claim 1, wherein the exposed upper surface includes a protruding jaw at an intermediate portion, and the first region and the second region are divided based on one side of the jaw. The light emitting device according to any one of claims 1 to 3, wherein an electrode is formed in the first region so that one end of the wiring is connected to the first region by the electrode. Preparing a substrate; Forming a first semiconductor layer and a second semiconductor layer on the substrate; Exposing a portion of the substrate to form a plurality of light emitting cells; Exposing a portion of the first semiconductor layer to form an exposed top surface of the first semiconductor layer; A stepped shape including a plurality of stages is formed on the exposed upper surface by etching, so that the first region on the outside and the second region on the inside of the second region are located on the side of one of the stages. Providing on the surface; A wire connection step of electrically connecting a first semiconductor layer of one light emitting cell and a second semiconductor layer of another light emitting cell adjacent to the one light emitting cell among the plurality of light emitting cells; Light emitting device, characterized in that in the wiring connection step, one end of the wiring is connected to the first area of the one light emitting cell. Preparing a substrate; Forming a first semiconductor layer and a second semiconductor layer on the substrate; Etching a portion of the first semiconductor layer and the second semiconductor layer to expose a substrate to form a plurality of light emitting cells; Exposing a portion of the first semiconductor layer to form an exposed top surface of the first semiconductor layer; Forming a jaw protruding from an intermediate portion of the exposed upper surface by etching to provide an exposed first surface with an outer first region and an inner second region with respect to one side of the jaw; A wire connection step of electrically connecting a first semiconductor layer of one light emitting cell and a second semiconductor layer of another light emitting cell adjacent to the one light emitting cell among the plurality of light emitting cells; Light emitting device, characterized in that in the wiring connection step, one end of the wiring is connected to the first area of the one light emitting cell. A substrate; At least one light emitting cell having a first semiconductor layer formed on the substrate and a second semiconductor layer formed on a portion of the first semiconductor layer; The first semiconductor layer includes an exposed top surface, The exposed upper surface includes a first region and a second region having different heights by steps; The first region is located outward of the second region and has a height lower than that of the second region, A light emitting device, characterized in that one end of the wiring is connected to the first region. The light emitting device of claim 7, further comprising a bonding pad formed on the first region, wherein the wiring is bonded to the bonding pad.

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