TW202013766A - Semiconductor devices and manufacturing methods thereof - Google Patents

Abstract

A semiconductor device includes a substrate; a semiconductor stack, formed on the substrate, including a light emitting surface and a sidewall surrounding and connecting the light emitting surface; an isolation layer, formed on the semiconductor stack and covering the light emitting surface and the sidewall, the isolation layer including a first opening and a second opening on the light emitting surface; and an metal electrode layer, formed on the isolation layer, including a pad electrode and an extension electrode, wherein the pad electrode and the extension electrode electrically connects to the semiconductor stack through the first opening and the second opening, respectively. From a top view, the first opening and the second opening respectively includes a first opening outer edge and a second opening outer edge, and the pad electrode and the extension electrode includes a first electrode outer edge and a second electrode outer edge respectively corresponding to the first opening outer edge and the second opening outer edge. The first electrode outer edge and the second electrode outer edge respectively surround the first opening outer edge and the second opening outer edge so as to the metal electrode layer completely cover the first opening and the second opening.

Description

Semiconductor element and related manufacturing method

This specification relates to a semiconductor device and its manufacturing method, in particular to a light emitting diode and its related manufacturing method.

Light-Emitting Diode (LED) has good characteristics such as low energy consumption, low heat generation, long operating life, shock resistance, small size, and fast response speed, so it is suitable for various lighting and display applications.

In addition to the need for good luminous efficiency, LEDs also need to have good reliability. An LED often needs to pass many rigorous reliability tests to prove that it can be durable to a certain life. For example, the LED will pass the reliability test of high temperature and high humidity. However, during the test, water vapor may enter the LED and react with the epitaxial material in the LED, such as an oxidation reaction, thereby rendering the LED ineffective. How to make LEDs have better reliability is the goal of the industry.

A semiconductor element, comprising a substrate; a semiconductor stack, arranged on the substrate, having a light emitting surface and a side wall surrounding and connecting the light emitting surface; an insulating layer formed on the semiconductor stack and covering the light emitting surface and the side wall, The insulating layer has a first opening and a second opening on the light exit surface; and, a metal electrode layer, including a pad electrode and an extension electrode, is formed on the insulating layer, and the pad electrode and the extension electrode respectively pass through the first The opening and the second opening are electrically connected to the semiconductor stack. From a top view, the first opening and the second opening each have a first opening outer edge and a second opening outer edge, and the pad electrode and the extension electrode each have a first electrode outer edge and a second electrode outer edge , Corresponding to the first opening outer edge and the second opening outer edge, respectively, the first electrode outer edge and the second electrode outer edge respectively surround the first opening outer edge and the second opening outer edge, so that the metal electrode layer completely covers the first Opening and second opening.

A method for manufacturing a semiconductor device includes: providing a substrate; forming a semiconductor stack on the substrate, wherein the semiconductor stack has a second conductive semiconductor layer, an active layer, and a semiconductor layer in sequence from the substrate The semiconductor layer has a surface far away from the substrate; a mask layer is formed on the surface of the semiconductor layer; the mask layer has an upper surface on the opposite side of the surface; the upper surface of the mask layer is etched to form a patterned mask layer It has a surface with a pattern; and, the patterned mask layer and the semiconductor layer are etched and thinned to transfer the pattern to the semiconductor layer.

A method for manufacturing a semiconductor device includes: forming a semiconductor stack on a growth substrate, the semiconductor stack includes a first portion and a second portion outward from the growth substrate, wherein the first portion includes an undoped layer, the first The two parts include a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; the growth substrate and the semiconductor stack are bonded to a conductive substrate, wherein the semiconductor stack is sandwiched between the growth substrate and the conductive substrate Remove the growth substrate so that the semiconductor stack exposes a surface of the undoped layer; form a mask layer on the surface of the undoped layer, the mask layer has an upper surface on the opposite side of the surface; etching mask A patterned mask layer is formed on the upper surface of the mask layer, which has a surface with a pattern; the thinned patterned mask layer and the undoped layer are etched to make the pattern transferred to the second of the semiconductor stack Forming a light emitting surface with this pattern on part of the first conductive semiconductor layer; etching the second part of the semiconductor stack to form a scribe line and exposing a side wall of the second part of the semiconductor stack, the side wall surrounding And connect to the light emitting surface; forming an insulating layer to cover the light emitting surface and the side walls; patterning the insulating layer to form a patterned insulating layer, which includes an insulating layer opening on the light emitting surface; and, forming a metal electrode layer on the patterned insulating layer On the top, the metal electrode layer corresponds to and is electrically connected to the first conductive semiconductor layer through the opening of the insulating layer, wherein, from a top view, the opening of the insulating layer has an outer edge of the opening, and the metal electrode layer has an outer edge of the electrode The outer edge of the opening of the insulating layer, so that the metal electrode layer completely covers the opening.

A method for manufacturing a semiconductor device includes: providing a substrate; forming a semiconductor stack on the substrate, wherein the semiconductor stack has a second conductive semiconductor layer, an active layer, and a semiconductor layer in sequence from the substrate The semiconductor layer has a surface far away from the substrate; a first mask layer is formed on the surface of the semiconductor layer, the first mask layer has a flat upper surface on the opposite side of the surface; the first mask layer is thinned by etching A semiconductor layer, so that the flat upper surface is transferred to the semiconductor layer so that the semiconductor layer has a flat surface; a second mask layer is formed on the flat surface of the semiconductor layer, and the second mask layer has opposite sides on the flat surface An upper surface; etching the upper surface of the second mask layer to form a patterned mask layer having a surface with a pattern; and etching to thin the patterned mask layer and the semiconductor layer to turn the pattern Print to the semiconductor layer.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings, which has enabled those skilled in the art of the present disclosure to fully understand the spirit of the present disclosure. The disclosure is not limited to the following embodiments, but can be implemented in other forms. In this specification, there are some same symbols, which represent elements with the same or similar structure, function, and principle, and those with general knowledge in the industry can infer according to the teaching of this specification. For the sake of brevity of the manual, elements with the same symbol will not be restated. Furthermore, when a first material layer is located on or above a second material layer, it includes the case where the first material layer and the second material layer are in direct contact. Alternatively, there may be a situation where one or more other material layers are spaced apart, in which case, the first material layer and the second material layer may not be in direct contact. In addition, the terms "layer" and "layer type" usually mean a material with a specific thickness in an area, which can be composed of a single layer or a plurality of sublayers, as long as the composition provides the same function.

FIG. 1 shows a schematic cross-sectional view of a light emitting diode 300 according to an embodiment of the present disclosure, which can be CX-CX, CX'-CX' or CX"-CX along the line segment in Figs. 6A, 6B or 6C "The resulting schematic cross-section, the details of which will be detailed below. In this embodiment, the light emitting diode 300 is an ultraviolet (UV) LED, but the disclosure is not limited to UV LEDs. In other embodiments, the light emitting diode 300 may be a white LED, a blue LED, or a red LED.

The LED 300 includes a conductive substrate 102, a bonding layer 104, a barrier layer 106, a reflective layer 108, a current blocking layer 110, a semiconductor stack 111, a sidewall protection layer 118, a main protection layer 320 And a metal electrode layer 322, wherein the semiconductor stack 111 includes a p-type semiconductor layer 112, a light-emitting layer 114, and an n-type semiconductor layer 116. The semiconductor stack 111 has a mesa (not shown), the platform has a light exit surface LO and a side wall SW surrounding and connecting the light exit surface LO, and has a land width WRFL, wherein the light exit surface LO has a rough structure RGH. The sidewall SW is covered with a sidewall protection layer 118, and the sidewall protection layer 118 can be selectively extended to cover a part of the light exit surface LO. The main protection layer 320 covers the sidewall protection layer 118 and the light emitting surface LO of the semiconductor stack 111. In another embodiment, the light emitting diode 300 may not include the sidewall protection layer 118, and the main protection layer 320 directly covers the light exit surface LO and the sidewall SW of the semiconductor stack 111. As shown in the schematic cross-sectional view of FIG. 1, on the light exit surface LO, the main protective layer 320 has an opening VA, which has an opening width WNPD. The metal electrode layer 322 has an electrode width WML and is formed in the opening VA of the main protective layer 320 and extends over a part of the main protective layer 320 to completely cover the opening VA, in other words, at the edge of the metal electrode layer 322, The main protective layer 320 extends under the metal electrode layer 322 and is sandwiched between the metal electrode layer 322 and the n-type semiconductor layer 116. In an embodiment, from a top view, the edge of the metal electrode layer 322 surrounds the edge of the opening VA of the main protective layer 320. In one embodiment, the edge of the metal electrode layer 322 is larger than the edge of the opening VA of the main protective layer 320 by more than 1 μm, that is, from a cross-sectional view, the edge of the metal electrode layer 322 extends to cover the upper surface of the main protective layer 320 Part of it is more than 1μm. The metal electrode layer 322 forms a low-resistance contact, such as an ohmic contact, with the n-type semiconductor layer 116 in the semiconductor stack 111 through the opening VA to serve as an upper electrode for electrically connecting the semiconductor stack 111 to the outside. The reflective layer 108 forms a low-resistance contact with the p-type semiconductor layer 112 in the semiconductor stack 111, such as an ohmic contact, to serve as a lower electrode for electrically connecting the semiconductor stack 111 to the outside world. When an appropriate trans-voltage is applied to the semiconductor stack 111 via the upper electrode and the lower electrode, carriers, such as electrons and holes, will recombination of the light emitting layer 114 to emit light, and radiate to the light exit surface LO to outside world.

As previously mentioned, the edge of the metal electrode layer 322 is located outside the edge of the opening VA, so the electrode width WML of the metal electrode layer 322 is larger than the opening width WNPD of the opening VA of the main protective layer 320, so that the metal electrode layer 322 can completely cover the main The opening VA of the protective layer 320. In addition, referring to FIG. 1, the current blocking layer 110 has a blocking layer width WCB, which is larger than the opening width WNPD of the opening VA of the main protective layer 320, so the light emitting efficiency of the light emitting diode 300 can be improved. Because the metal electrode layer 322 is electrically connected to the semiconductor stack 111 through the opening VA of the main protective layer 320, when a suitable trans-voltage is applied to the light emitting diode 300 through the metal electrode layer 322 and the reflective layer 108 to make it emit light, it is To prevent the carrier current from the metal electrode layer 322 through the opening VA of the main protective layer 320 from being excessively concentrated in the local area of the light-emitting layer 114 between the metal electrode layer 322 and the reflective layer 108 directly below it, so the corresponding main protective layer A current blocking layer 110 is provided below the opening VA of 320, so that the carrier flow (eg, electron flow and/or hole flow) from the metal electrode layer 322 or the reflective layer 108 can diffuse laterally through more light-emitting layers The region 114 allows a larger area of the light-emitting layer 114 to emit light, thereby improving the light-emitting efficiency of the light-emitting diode 300. In other words, when the width WCB of the current blocking layer 110 is designed to be larger than the opening width WNPD of the opening VA of the main protective layer 320, the carrier flow from the metal electrode layer 322 and the reflective layer 108 can be laterally diffused to more The area of the light-emitting layer 114 allows a large area of the light-emitting layer 114 to emit light; Layer 322 absorbs. In one embodiment, the edge of the current blocking layer 110 is larger than the edge of the opening VA of the main protective layer 320 by 15 μm˜65 μm.

Fig. 2 and Fig. 3 respectively show schematic cross-sectional views of light-emitting diodes of other comparative examples. The same or similarities between the light-emitting diode 100 of FIG. 2 or the light-emitting diode 200 of FIG. 3 and the light-emitting diode 300 of FIG. 1 will not be repeated. The difference between the light-emitting diode 100 of FIG. 2 and the light-emitting diode 300 of FIG. 1 is that the metal electrode layer 122 of the light-emitting diode 100 is located in the opening (not shown) of the main protective layer 120 on the light-emitting surface, It does not extend to cover the main protective layer 120. In one embodiment, since the opening of the main protective layer 120 and the metal electrode layer 122 belong to the same lithography etching process, the opening of the main protective layer 120 may cause an undercut during etching, resulting in subsequent formation There is a gap SB between the metal electrode layer 122 and the main protective layer 120. The difference between the light-emitting diode 200 of FIG. 3 and the light-emitting diode 300 of FIG. 1 is that the main protective layer 220 of the light-emitting diode 200 extends to cover the side (not shown) and part of the metal electrode layer 222 Surface (not shown), wherein the main protective layer 220 has an opening 224 to expose the upper surface of the metal electrode layer 222. In one embodiment, the light-emitting diode 100 fails in the reliability test of high temperature and high humidity. The reason is that water vapor will pass through the gap SB and enter the semiconductor stack 111, causing the material in the n-type semiconductor layer 116 to oxidize and deteriorate. As a result, the light emitting diode 100 fails. In addition, compared with the light-emitting diode 100, the light-emitting diode 200 and the light-emitting diode 300 have better performance in the reliability test of high temperature and high humidity. However, when a rough structure RGH is formed on the upper surface of the semiconductor stack 111 of the light emitting diode 200 and the brightness of the light emitting diode 200 is to be improved by the rough structure RGH, the rough structure RGH formed on the semiconductor stack 111 The adjacent CR between the edge of the metal electrode layer 222 and the semiconductor stack 111 will cause a sink structure (not shown) due to the rough structure RGH, and such a sink structure will make it difficult to cover the main protective layer 220 formed later And protect the adjacent CR between the edge of the metal electrode layer 222 and the semiconductor stack 111, so that moisture easily enters from here. Therefore, the reliability of the light emitting diode 200 still needs to be improved. In the light-emitting diode 300 of FIG. 1, since the main protective layer 320 extends below the metal electrode layer 322 and is located between the metal electrode layer 322 and the n-type semiconductor layer 116, the main protective layer 320 can cover the n compliantly and completely The type semiconductor layer 116 and the metal electrode layer 322 overlap and adjoin, and the metal electrode layer 322 formed later covers the main protective layer 320 so that the opening VA of the main protective layer 320 is completely covered by the metal electrode layer 322. In such a layered structure, no gap or dent is formed between the metal electrode layer 322 and the main protective layer 320, which impairs reliability. The light-emitting diode 300 is at a higher temperature than the light-emitting diode 100 or the light-emitting diode 200. The high humidity reliability test has better performance.

4A to 4E show schematic cross-sectional views of the light emitting diode 300 at different stages of the manufacturing process. Referring to FIG. 4A, a stacked structure composed of a semiconductor stack 111, a current blocking layer 110, and a reflective layer 108 is first formed on a growth substrate (not shown); then, the stacked structure on the growth substrate is bonded to a conductive substrate 102; After removing the growth substrate and performing subsequent processes, a schematic cross-sectional view as shown in FIG. 4A is obtained. The conductive substrate 102 is used as a carrier supporting the stacked structure above it, which may be a molybdenum (Mo) substrate, a copper-tungsten alloy (CuW) substrate, a nickel-gold alloy (NiAu) substrate, or a silicon (Si) substrate , But not limited to this. The bonding layer 104 may have a single-layer or multi-layer structure. The stacked structure of the semiconductor stack 111, the current blocking layer 110, and the reflective layer 108 on the growth substrate is bonded to the conductive substrate 102 through the bonding layer 104. The bonding layer 104 includes a single layer of indium (In), gold (Au), or titanium (Ti), a stack, or a stack of alloys thereof, but is not limited thereto. The barrier layer 106 can prevent the material of the bonding layer 104 from diffusing to the reflective layer 108 during the bonding process and reduce the reflectivity of the reflective layer 108. The barrier layer 106 includes a titanium tungsten (TiW) alloy, or a single layer of platinum (Pt), a stack, or a stack of alloys thereof, but is not limited thereto. The light generated by the light-emitting layer 114 and directed toward the conductive substrate 102 is reflected back to the semiconductor stack 111 through the reflective layer 108 and then emitted from the light-emitting surface LO, thereby improving the light-emitting efficiency of the light-emitting diode 300. A low resistance contact, such as an ohmic contact, is formed between the reflective layer 108 and the p-type semiconductor layer 112. The material of the reflective layer 108 may be, for example, silver (Ag), aluminum (Al), titanium tungsten (TiW), or platinum (Pt), but is not limited thereto. The partial area of the current blocking layer 110 between the reflective layer 108 and the p-type semiconductor layer 112 can regionally block the metal reflective layer 108 from contacting the p-type semiconductor layer 112, so that the carriers can effectively diffuse laterally through the semiconductor stack Layer 111 to increase the luminous efficiency of the semi-luminescent diode 300. In one embodiment, the current blocking layer 110 is not covered by the reflective layer 108, and is interleaved with the reflective layer 108 between the barrier layer 106 and the p-type semiconductor layer 112. The current blocking layer 110 may be a single-layer structure such as titanium dioxide (TiO2) or silicon dioxide (SiO2), or a structure such as TiO2 and SiO2 alternately stacked, but it is not limited thereto.

The semiconductor stack 111 includes a group III-V semiconductor material, such as AlxInyGa(1-x-y)N or AlxInyGa(1-x-y)P, where 0≤x, y≤1, and (x+y)≤1. For example, the materials of the p-type semiconductor layer 112 and the n-type semiconductor layer 116 may include a gallium nitride (GaN) layer or an aluminum gallium nitride (AlGaN) layer. The material of the light emitting layer 114 may be AlGaInP material, InGaN material, AlGaN material or AlGaInN material. The material of the light-emitting layer 114 may be an undoped, p-type impurity doped, or n-type impurity doped semiconductor material. The light emitting layer 114 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum-well structure structure, MQW). Taking the MQW light emitting layer 114 as an example, the MQW light emitting layer 114 includes one or more sets of barrier layers and well layers alternately stacked. Taking the UV LED in this embodiment as an example, the semiconductor material of the barrier layer includes aluminum gallium nitride, and the semiconductor material of the well layer includes aluminum (indium) gallium nitride, wherein the aluminum concentration in the barrier layer is greater than the aluminum concentration in the well layer In order to effectively limit the recombination of electrons and holes in the quantum well, photons are released.

Next, a roughening process is used to roughen the upper surface (not shown) of the semiconductor stack 111 exposed after the growth substrate is removed to form a light emitting surface LO with a rough structure RGH. The details of the roughening process will be Details are below. The rough structure RGH can reduce the reflection of the light emitted from the light emitting layer 114 by the light emitting surface LO, so as to improve the light extraction efficiency of the light emitting diode 300. Then, the semiconductor stack 111 is patterned to form a mesa through a mesa forming process. In one embodiment, at wafer level, the semiconductor stack 111 on the wafer can be defined by a platform forming process to form a plurality of platforms, and there are a plurality of grooves between the platforms to separate each platform Separated. After the platform formation process, the semiconductor stack 111 has sidewalls SW. In another embodiment, the semiconductor stack 111 may be subjected to a platform formation process and then a roughening process to form the structure shown in FIG. 4A.

The sidewall protection layer 118 can protect the light-emitting layer 114 exposed from the sidewall SW due to the platform formation process. The material of the sidewall protection layer 118 may be silicon nitride (SiN), which has an excellent ability to block moisture, and can protect the light-emitting layer 114 from the external environment. In one embodiment, since the energy gap of the SiN material is about 5 eV, when the light emitted by the light-emitting layer 114 is in the UV band, the SiN material absorbs the light emitted by the light-emitting layer 114, thereby reducing the luminous efficiency of the light-emitting diode 300. Therefore, as shown in FIG. 4A, the sidewall protection layer 118 covers only a part of the light exit surface LO.

In FIG. 4A, the main protective layer 320 is deposited on the sidewall protective layer 118 and the semiconductor stack 111 in a comprehensive manner. In one embodiment, the light-emitting diode 300 may not include the sidewall protection layer 118, but is deposited on the light exit surface LO and the sidewall SW of the semiconductor stack 111 only through the main protection layer 320. The material of the main protective layer 320 may be an insulating material such as silicon dioxide (SiO2) or SiN. In an embodiment, when the light emitted from the light emitting layer 114 of the light emitting diode 300 is in the UV band, the material of the main protective layer 320 is preferably SiO2. Because the energy gap of SiO2 is about 9 eV, compared with SiN, SiO2 does not absorb UV light, so it can be used as the material of the main protective layer 320 on the light-emitting surface LO.

Referring to FIGS. 4B-4C, following the process of FIG. 4A, a mask layer is formed on the main protective layer 320, and then exposed and developed to form a patterned mask layer PR_1 on the main protective layer 320, which has an opening VA_1 is used to expose part of the main protective layer 320.

FIG. 4C shows a schematic cross-sectional view of the structure of the main protective layer 320 after the etching process and the process of removing the patterned mask layer. For example, the etching process may use buffer oxide etcher (BOE) to remove the main protective layer 320 that is not protected by the patterned mask layer PR_1 in FIG. 4B, that is, the portion in the position of the mask layer opening VA_1 Part of the main protective layer 320 so that the main protective layer 320 has an opening VA. After that, the patterned mask layer PR_1 is removed to obtain the structure as shown in FIG. 4C. The opening width WNPD of the opening VA of the main protective layer 320 will be smaller than the blocking layer width WCB of the current blocking layer 110 directly below, as can be understood from the sectional view of FIG. 4C, in a relative top view, the opening VA is completely located in the current Within the barrier layer 110.

Continuing with FIG. 4C, FIG. 4D shows a schematic cross-sectional view of another mask layer after exposure and development to form a patterned mask layer PR_2 on the main protective layer 320. The patterned mask layer PR_2 has an opening VA_2 to expose A part of the main protective layer 320 and the opening VA of the main protective layer 320 are provided.

Continuing with FIG. 4D, FIG. 4E shows a schematic cross-sectional view of depositing a metal material layer 321 on the patterned mask layer PR_2 and filling the opening VA_2. The metal material layer 321 deposited in the opening VA of the main protective layer 320 and the metal material layer 321 on the main protective layer 320 around the opening VA will constitute the metal electrode layer 322. The metal material layer 321 may be formed by stacking several metal layers. For example, the metal material layer 321 may be a stack of aluminum (Al), titanium (Ti), platinum (Pt), chromium (Cr), or gold (Au). Layer or its alloy stack, but not limited to this.

Then, a photoresist removal process may be used to remove the patterned mask layer PR_2 and lift off the metal material layer 321 on the patterned mask layer PR_2, leaving the metal material layer 321 in the opening VA_2, To become the metal electrode layer 322. In the wafer-level process, a dicing process can be used to cut through the grooves (cutting lanes) between the above-mentioned platforms by a dicing knife or laser beam, as shown in Figure 1 Light-emitting diode 300.

FIGS. 5A to 5C respectively show a top view of the metal electrode layer 322 and the main protective layer 320 and a perspective view of the current blocking layer 110 in the light emitting diode 300 viewed from the semiconductor stack 111 side. In the cross-sectional view of FIG. 1, the semiconductor stack 111 has a mesa width WRFL. In FIGS. 5A and 5C, the dashed area indicates the area of the semiconductor stack 111, which has a width, that is, the mesa width WRFL. FIG. 5A shows a top view of the metal electrode layer 322. The metal electrode layer 322 has a pad electrode 3221 and an extension electrode 3222. The pad electrode 3221 and the extension electrode 3222 each have a first electrode outer edge 3221e and a second electrode outer edge 3222e. FIG. 5B shows a top view of the main protective layer 320. The main protective layer 320 has a first opening 3201 and a second opening 3202, wherein the first opening 3201 and the second opening 3202 can be separated or connected. In this embodiment, the first opening 3201 and the second opening 3202 are connected as an example. The first opening 3201 and the second opening 3202 each have a first opening outer edge 3201e and a second opening outer edge 3202e. FIG. 5C shows a perspective view of the current blocking layer 110 viewed from the side of the semiconductor stack 111. The current blocking layer 110 has a pad blocking layer 1101 and an extension blocking layer 1102, and the pad blocking layer 1101 and the extension blocking layer 1102 each have a A first barrier layer outer edge 1101e and a second barrier layer outer edge 1102e.

Figures 6A to 6C show that after overlaying Figures 5A to 5C, a pad electrode area 400, an extended electrode intersection area 402, and an extended electrode area 404 marked in Figures 5A to 5C are shown. Enlarged schematic at the location. FIG. 6A shows the relative positions of the pad electrode 3221, the first opening 3201 of the main protective layer 320 and the pad barrier layer 1101 in the pad electrode area 400. As shown in FIG. 6A, the pad electrode 3221, the first opening 3201 and the pad barrier layer 1101 are correspondingly provided with each other, and the first electrode outer edge 3221e of the pad electrode 3221 is interposed between the first opening of the first opening 3201 Between the outer edge 3201e and the outer edge 1101e of the first barrier layer of the pad barrier layer 1101, that is, the outer edge 1101e of the first barrier layer of the pad barrier layer 1101 surrounds the first electrode outer edge 3221e of the pad electrode 3221 The first electrode outer edge 3221e of the pad electrode 3221 surrounds the first opening outer edge 3201e of the first opening 3201. In another embodiment, the outer edge 1101e of the first barrier layer of the pad barrier layer 1101 may be between the outer edge 3221e of the first electrode of the pad electrode 3221 and the outer edge 3201e of the first opening of the first opening 3201, in other words , The first electrode outer edge 3221e of the pad electrode 3221 surrounds the first barrier layer outer edge 1101e of the pad barrier layer 1101, and the first barrier layer outer edge 1101e of the pad barrier layer 1101 surrounds the first opening of the first opening 3201 The outer edge 3201e. Similarly, FIGS. 6B and 6C show the relative positions of the extended electrode 3222, the second opening 3202 of the main protective layer 320, and the extended barrier layer 1102 in the extended electrode intersection region 402 and the extended electrode region 404, respectively, The relative positional relationship between the second electrode outer edge 3222e of the extended electrode 3222, the second opening outer edge 3202e of the second opening 3202, and the second barrier outer edge 1102e of the extended barrier layer 1102 will be as described above, Repeat.

In addition, in FIG. 6A, the cross-sectional view along the line segment CX-CX can be obtained to obtain a schematic cross-sectional view of the light emitting diode 300 shown in FIG. 1, along the line segment CX in FIG. 6B or 6C. The cross-sectional view generated by'-CX' and the line segment CX "-CX" can also obtain a schematic cross-sectional view of the light emitting diode 300 shown in Fig. 1. The relative positions between the layer structures of the cross-sectional schematic diagrams are the same. The main difference is that the widths of the pad electrode 3221 and the extension electrode 3222 cause the corresponding first opening 3201, second opening 3202, pad barrier layer 1101, and The width of the extension barrier layer 1102 is different.

7A to 7H show a roughening process for roughening the light emitting surface LO of the light emitting diode 300.

FIG. 7A provides a growth substrate 600. The growth substrate 600 may be a patterned sapphire substrate (PSS), which has a preset convex pattern on its upper surface, but is not limited thereto, and the upper surface of the patterned sapphire substrate may also be provided with a concave pattern or a convex pattern Combined pattern of raised/recessed. On the growth substrate 600, an undoped semiconductor layer 602, an n-type semiconductor layer 116, a light-emitting layer 114, and a p-type semiconductor layer 112 are sequentially grown and stacked. The n-type semiconductor layer 116, the light-emitting layer 114, and the p-type semiconductor layer 112 constitute a semiconductor stack 111. The semiconductor stack 111 and the undoped semiconductor layer 602 thereunder constitute a semiconductor stack 604. The undoped semiconductor layer 602 serves as a buffer layer to reduce the stress generated in the n-type semiconductor layer 116 due to lattice mismatch between the n-type semiconductor layer 116 and the growth substrate 600 Or dislocation defect. A nucleation layer (not shown) composed of one or more sub-layers may also be included between the buffer layer 602 and the substrate 600. The lattice constant of the nucleation layer material is similar to that of the substrate 600. For example, the nucleation layer may be composed of aluminum nitride (AlN), and its thickness is about 50 nm to 500 nm. In a preferred embodiment, the nucleation layer may be formed by stacking a low temperature epitaxially grown AlN sublayer (thickness about 40 nm) and a high temperature epitaxially grown AlN sublayer (thickness about 150 nm). A patterned current blocking layer 110 and a reflective layer 108 are formed on the p-type semiconductor layer 112. Next, a barrier layer 106 is formed on the current blocking layer 110 and the reflective layer 108.

FIG. 7B shows bonding the structure of FIG. 7A to the conductive substrate 102. At this time, the growth substrate 600, the semiconductor stack 604, the current blocking layer 110, the reflective layer 108, and the barrier layer 106 are bonded to the conductive substrate 102 through the bonding layer 104, as shown in FIG. 7B, the semiconductor stack 604 is sandwiched Between the growth substrate 600 and the conductive substrate 102.

FIG. 7C continues from FIG. 7B, showing the removal of the growth substrate 600. For example, the growth substrate 600 is removed by laser lift off or etching to expose the undoped semiconductor layer in the semiconductor stack 604 A surface of 602 (not shown in the figure). Because of the convex pattern on the growth substrate 600, there is a corresponding concave pattern on the surface of the undoped semiconductor layer 602. The result is as shown in FIG. 7D. In another embodiment, if a recessed pattern is provided on the upper surface of the growth substrate 600, after the growth substrate 600 is removed, a corresponding convex pattern remains on the surface of the undoped semiconductor layer 602.

FIG. 7E continues from FIG. 7D, and a mask layer PRRGH is formed on the undoped semiconductor layer 602. The mask layer PRRGH fills the depression pattern created by the growth substrate 600 on the undoped semiconductor layer 602 to provide a flat upper surface TS. The mask layer PRRGH may be an organic material layer or an inorganic material layer.

Next, the structure shown in FIG. 7E may be placed in an inductively coupled plasma reactive ion etcher (ICP etcher) to perform a coking step on the upper surface TS of the mask layer PRRGH. For example, using the thermal energy generated by ICP bombardment, the upper surface TS of the mask layer PRRGH is coked to form a patterned surface RGH1. The result is as shown in FIG. 7F. The patterned surface RGH1 has a pattern.

Next, in the same ICP machine, continue ICP bombardment to etch and thin the mask layer PRRGH to expose a portion of the undoped semiconductor layer 602. At this time, the mask layer PRRGH and the undoped semiconductor layer 602 are simultaneously etched, and the The pattern of the patterned surface RGH1 is transferred to the undoped semiconductor layer 602, and then, by continuous ICP bombardment, the pattern is transferred to the n-type semiconductor layer 116 to form the light-emitting surface LO1, and the results are similar to the 7G Figure and Figure 7H. In this step, by selecting the material of the mask layer PRRGH, the ICP etching selectivity ratio of the mask layer PRRGH and the undoped semiconductor layer 602 is close to 1. In this way, under the ICP bombardment, the pattern of the patterned surface RGH1 of the mask layer PRRGH can be transferred to the undoped semiconductor layer 602, and then transferred to the n-type semiconductor layer 116.

In another embodiment, the recess pattern of the undoped semiconductor layer 602 may be smoothed first, and then the subsequent roughening step may be performed. For details, refer to FIG. 7E, FIG. 7E_1, FIG. 7E_2, and 7G_1 Figure and Figure 7H_1 are described as follows.

Following Figure 7E, the structure in Figure 7E is placed in an inductively coupled plasma ion etching machine. The difference from the previous embodiment is that the upper surface TS of the mask layer PRRGH is not subjected to a coking step. In other words, by adjusting the ICP parameters and the characteristics of the mask layer PRRGH, the mask layer PRRGH will be etched and thinned under ICP bombardment. But no patterned surface is formed. In this way, the flat upper surface TS features of the mask layer PRRGH can be transferred to the undoped semiconductor layer 602, thereby eliminating the concave pattern on the surface of the undoped semiconductor layer 602. The result is shown in FIG. 7E_1. A flat surface TS1 is formed on the doped semiconductor layer 602. Next, a mask layer PRRGH2 is formed on the surface TS1 of the undoped semiconductor layer 602, and then, the upper surface of the mask layer PRRGH2 is subjected to a coking step by ICP bombardment, so that the upper surface of the mask layer PRRGH2 is coked. A patterned surface RGH2 is formed. The patterned surface RGH2 has a pattern, and the result is as shown in FIG. 7E_2. Continue to Figure 7E_2, continue to bombard the patterned surface RGH2 with ICP, transfer the pattern of the patterned surface RGH2 to the undoped semiconductor layer 602, and then transfer to the n-type semiconductor layer 116, the results are as shown in Figure 7G_1 And shown in Figure 7H_1.

Steps from Figure 7E, Figure 7F, Figure 7G to Figure 7H, or steps from Figure 7E, Figure 7E_1, Figure 7E_2, Figure 7G_1 to Figure 7H_1, can be in the same ICP machine To save the transportation and machine preparation time required for the operation of different process machines. But not limited to this, the steps from Figure 7E, Figure 7F, Figure 7G to Figure 7H, or the steps from Figure 7E, Figure 7E_1, Figure 7E_2, Figure 7G_1 to Figure 7H_1 can also be Performed in different ICP machines.

8A to 8C show another roughening process for roughening the light emitting surface LO of the light emitting diode 300. The following is only a brief explanation of the manufacturing method of FIGS. 8A to 8C. For more details, please refer to the previous disclosure.

As shown in FIG. 8A, the difference from the previous embodiment is that since there is no undoped semiconductor layer 602 on the n-type semiconductor layer 116, after the growth substrate 600 is removed, a recess pattern is formed on the n-type semiconductor layer 116 . Next, a photoresist layer PRRGH3 is formed on the n-type semiconductor layer 116. The mask layer PRRGH3 fills the recessed pattern created by the growth substrate 600 on the n-type semiconductor layer 116 to provide a smooth upper surface TS2. Next, the structure in Figure 8A can be placed in the ICP machine, and the upper surface TS2 of the mask layer PRRGH3 is subjected to a coking step, and the upper surface of the mask layer PRRGH3 is formed into a patterned surface RGH3, and the result is as shown in Figure 8B As shown.

Next, the ICP bombardment is continued to etch and thin the mask layer PRRGH3 to expose the n-type semiconductor layer 116, and at the same time transfer the pattern of the patterned surface RGH3 to the n-type semiconductor layer 116 to form the light emitting surface LO2, the result is as As shown in Figure 8C.

In one embodiment, the roughening process in the manufacturing process of the light-emitting diode 300 can be replaced with the above embodiments of the roughening process according to the process requirements or product design. After the above roughening process is completed, it will be carried out The manufacturing process or the platform forming process of the metal electrode layer 322 can be referred to the above, and is not repeated here.

The above is only the preferred embodiment of the disclosure, and any changes and modifications made according to the patent application scope of the disclosure shall fall within the scope of the disclosure.

100, 200, 300: light emitting diode 102: conductive substrate 104: bonding layer 106: barrier layer 108: reflective layer 110: current blocking layer 1101: pad barrier layer 1101e: outer edge of the first barrier layer 1102: extended barrier Layer 1102e: second barrier layer outer edge 111: semiconductor stack 112: p-type semiconductor layer 114: light-emitting layer 116: n-type semiconductor layer 118: sidewall protection layers 120, 220, 320: main protection layer 3201: first opening 3201e : First opening outer edge 3202: Second opening 3202e: Second opening outer edge 321: Metal material layers 122, 222, 322: Metal electrode layer 3221: Pad electrode 3221e: First electrode outer edge 3222: Extension electrode 3222e: Second electrode outer edge 224: opening 400: bonding pad area 402: extended electrode intersection area 404: extended electrode area 600: growth substrate 602: undoped semiconductor layer 604: semiconductor stack CR: adjacent CX-CX, CX' -CX', CX”-CX”: line segments LO, LO1, LO2: light emitting surfaces PR_1, PR_2, PRRGH, PRRGH2, PRRGH3: mask layer RGH, RGH1, RGH2, RGH3: rough structure SB: slit SW: sidewall TS, TS1, TS2: upper surface VA, VA_1, VA_2: opening WCB: barrier width WML: electrode width WNPD: opening width WRFL: platform width

FIG. 1 shows a schematic cross-sectional view of a light-emitting diode according to an embodiment of the present disclosure.

FIG. 2 shows a schematic cross-sectional view of the light-emitting diode of Comparative Example 1. FIG.

FIG. 3 shows a schematic cross-sectional view of the light-emitting diode of Comparative Example 2. FIG.

FIGS. 4A to 4E show schematic cross-sectional views of the light-emitting diode of FIG. 1 at different stages of the manufacturing process.

FIGS. 5A to 5C respectively show the top view of the metal electrode layer above the semiconductor stack and the main protective layer in the light emitting diode of FIG. 1, and the current blocking layer below the semiconductor stack as viewed from the semiconductor stack side Perspective view.

FIGS. 6A to 6C show enlarged perspective views of the pad electrode area, the extended electrode intersection area, and the extended electrode area after superposition of FIGS. 5A to 5C.

Figures 7A to 7D, 7E, 7F, 7G, and 7H show a roughening process for roughening the light-emitting surface of the light-emitting diode.

Figures 7A to 7D, 7E, 7E_1, 7E_2, 7G_1, and 7H_1 show a roughening process for roughening the light-emitting surface of the light-emitting diode.

8A to 8C show a roughening process for roughening the light emitting surface of the light emitting diode.

300: light emitting diode

102: conductive substrate

104: junction layer

106: barrier layer

108: reflective layer

110: current blocking layer

111: Semiconductor stack

112: p-type semiconductor layer

114: light emitting layer

116: n-type semiconductor layer

118: sidewall protection layer

320: Main protective layer

322: Metal electrode layer

LO: light side

RGH: rough structure

SW: Side wall

VA: opening

WCB: barrier width

WML: electrode width

WNPD: opening width

WRFL: platform width

Claims (17)

A semiconductor device, comprising: a substrate; a semiconductor stack, disposed on the substrate, having a light exit surface and a side wall, the side wall surrounding and connecting the light exit surface; an insulating layer formed on and covering the semiconductor stack The light emitting surface and the side wall, the insulating layer has a first opening and a second opening on the light emitting surface; and a metal electrode layer, including a pad electrode and an extension electrode, formed on the insulating layer, the The pad electrode and the extension electrode are electrically connected to the semiconductor stack through the first opening and the second opening, respectively; wherein, from a top view, the first opening and the second opening each have a first opening Edge and a second opening outer edge, the pad electrode and the extension electrode each have a first electrode outer edge and a second electrode outer edge, respectively corresponding to the first opening outer edge and the second opening outer edge, The outer edge of the first electrode and the outer edge of the second electrode respectively surround the outer edge of the first opening and the outer edge of the second opening, so that the metal electrode layer completely covers the first opening and the second opening. The semiconductor device according to item 1 of the patent application scope further includes: a current blocking layer is formed between the semiconductor stack and the substrate, and has a pad blocking layer and an extension blocking layer, respectively corresponding to the pad electrodes And the extended electrode is provided. The semiconductor device as claimed in item 2 of the patent application, wherein, from the top view, the pad barrier layer and the extension barrier layer each have a first barrier layer outer edge and a second barrier layer outer edge, and the The outer edge of the first barrier layer and the outer edge of the second barrier layer respectively surround the outer edge of the first opening and the outer edge of the second opening. The semiconductor device of claim 3, wherein the outer edge of the first barrier layer and the outer edge of the second barrier layer respectively surround the outer edge of the first electrode and the outer edge of the second electrode, or the first barrier The outer edge of the layer is located between the outer edge of the first electrode and the outer edge of the first opening, and the outer edge of the second barrier layer is located between the outer edge of the second electrode and the outer edge of the second opening. As in the semiconductor device of claim 1, the light-emitting surface includes a roughened structure. As in the semiconductor device of claim 1, the insulating layer includes a silicon dioxide layer. For example, the semiconductor device according to item 1 of the patent application scope further includes a reflective layer formed between the semiconductor stack and the substrate. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming a semiconductor stack on the substrate, wherein the semiconductor stack sequentially has a second conductive semiconductor layer, an active layer, and an A semiconductor layer, wherein the semiconductor layer has a surface away from the substrate; a mask layer is formed on the surface of the semiconductor layer, the mask layer has an upper surface on the opposite side of the surface; the mask layer is etched On the upper surface, a patterned mask layer is formed with a surface having a pattern; and the patterned mask layer and the semiconductor layer are thinned by etching to transfer the pattern to the semiconductor layer. For example, in the manufacturing method of claim 8, the step of etching the mask layer uses inductively coupled plasma reactive ion etching (ICP). As in the manufacturing method of claim 8, the step of forming the semiconductor stack on the substrate includes: providing a growth substrate, the growth substrate including an upper surface; and sequentially on the upper surface of the growth substrate Forming the semiconductor layer, the active layer, and the second conductivity type semiconductor layer to form the semiconductor stack; joining the semiconductor stack and the substrate; and removing the growth substrate, and exposing the surface of the semiconductor layer. As in the manufacturing method of claim 10, the upper surface of the growth substrate has a plurality of protrusions or depressions, and the surface of the semiconductor layer corresponds to the plurality of protrusions or depressions having a plurality of Depression or protrusion. As in the manufacturing method of claim 11 of the patent application scope, wherein the mask layer covers the plurality of recesses or protrusions that fill the semiconductor layer. As in the manufacturing method of claim 8, the semiconductor layer includes an undoped layer or a first conductivity type semiconductor layer. For example, the manufacturing method of claim 13 further includes a doped semiconductor layer located between the undoped layer and the active layer, wherein the doped semiconductor layer has a conductivity. For example, in the manufacturing method of claim 8, the step of etching to thin the patterned mask layer and the semiconductor layer uses inductively coupled plasma reactive ion etching (ICP). A method for manufacturing a semiconductor device, comprising: forming a semiconductor stack on a growth substrate, the semiconductor stack including a first portion and a second portion outward from the growth substrate, wherein the first portion includes an undoped layer, The second part includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; the growth substrate and the semiconductor stack are bonded to a conductive substrate, wherein the semiconductor stack is sandwiched by the growth Between the substrate and the conductive substrate; removing the growth substrate so that the semiconductor stack exposes a surface of the undoped layer; forming a mask layer on the surface of the undoped layer, the mask layer Having an upper surface located on the opposite side of the surface; etching the upper surface of the mask layer to form a patterned mask layer with a surface having a pattern; etching to thin the patterned mask layer and the An undoped layer, the pattern is transferred to the first conductive type semiconductor layer of the second portion of the semiconductor stack to form a light exit surface with the pattern; etching the second portion of the semiconductor stack, Forming a scribe line and exposing a side wall of the second part of the semiconductor stack, the side wall surrounding and connecting to the light exit surface; forming an insulating layer covering the light exit surface and the side wall; patterning the insulation layer to form a pattern An insulating layer, the patterned insulating layer includes an insulating layer opening on the light exit surface; and forming a metal electrode layer on the patterned insulating layer, wherein the metal electrode layer corresponds to the insulating layer opening and penetrates through the insulating The layer opening is electrically connected to the first conductivity type semiconductor layer; wherein, from a top view, the insulating layer opening has an opening outer edge, and the metal electrode layer has an electrode outer edge surrounding the opening outer edge, so that the metal The electrode layer completely covers the insulating layer opening. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming a semiconductor stack on the substrate, wherein the semiconductor stack sequentially has a second conductive semiconductor layer, an active layer, and an A semiconductor layer, wherein the semiconductor layer has a surface away from the substrate; a first mask layer is formed on the surface of the semiconductor layer, the first mask layer has a flat upper surface on the opposite side of the surface; the etching is thin Transforming the first mask layer and the semiconductor layer to transfer the flat upper surface to the semiconductor layer so that the semiconductor layer has a flat surface; forming a second mask layer on the flat surface of the semiconductor layer The second mask layer has an upper surface on the opposite side of the flat surface; the upper surface of the second mask layer is etched to form a patterned mask layer with a surface having a pattern; and Etching and thinning the patterned mask layer and the semiconductor layer to transfer the pattern to the semiconductor layer.

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